CN115204076A - Logic optimization method and device of integrated circuit, electronic equipment and readable medium - Google Patents
Logic optimization method and device of integrated circuit, electronic equipment and readable medium Download PDFInfo
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Abstract
The disclosure relates to a logic optimization method and device for an integrated circuit, an electronic device and a computer readable medium. The method comprises the following steps: acquiring a multi-level logic network of an integrated circuit, wherein the multi-level logic network comprises nodes and directed edges; generating an adjacency matrix for the integrated circuit based on nodes and directed edges in the multi-level logical network; performing logic optimization on the integrated circuit based on the adjacency matrix and matrix operation. The logic optimization method, the logic optimization device, the electronic equipment and the computer readable medium of the integrated circuit can update the relation between the nodes in the logic network of the integrated circuit from the original link type to the matrix form, and quickly and accurately optimize the integrated circuit through the matrix calculation mode.
Description
Technical Field
The present disclosure relates to the field of integrated circuit design, and in particular, to a method and an apparatus for logic optimization of an integrated circuit, an electronic device, and a computer-readable medium.
Background
Generally, after a circuit specification and a design requirement are given, a circuit design engineer designs the behavior of the circuit by using a Hardware Description Language (HDL). HDL can describe the logical functionality of a digital circuit so that a circuit design engineer can devote more energy to the design of the functionality while avoiding the initial study of potentially extremely complex circuit connections. Through the HDL, the logic circuit function can be converted into a circuit structure description, and the circuit structure is generally represented and saved through a netlist (netlist), and the netlist is essentially the description of the circuit wiring relation. Today, circuits with functional logic are often represented using multi-level logic networks (multi-level logic networks).
The complexity of an integrated circuit that determines functionality may vary greatly, since the code written during the writing process may correspond to different actual circuits. For this reason, in the actual design stage, the corresponding logic network of the integrated circuit is often optimized to reduce the complexity of the actual circuit. At this stage, computer technology irrelevant to the specific semiconductor device process can be adopted to simplify the corresponding logic function of the integrated circuit, thereby reducing the number of logic gates and meeting certain requirements on time sequence, area and power consumption.
The optimized logic gate netlist is further subjected to various verifications to ensure that the functions of the logic gate netlist conform to the expectation of a designer. The netlist is then sent to an integrated circuit hardware vendor, where a technician will fabricate actual circuits, such as application specific integrated circuits, from the logic gate netlist using device-specific device technology.
The above information disclosed in this background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
In view of this, the present application provides a logic optimization method and apparatus for an integrated circuit, an electronic device, and a computer readable medium, which can update the relationship between nodes in a logic network of the integrated circuit from an original link type to a matrix type, and quickly and accurately optimize the integrated circuit through a matrix calculation method.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.
According to an aspect of the present application, a method for logic optimization of an integrated circuit is provided, the method comprising: acquiring a multi-level logic network of an integrated circuit, wherein the multi-level logic network comprises nodes and directed edges; generating an adjacency matrix for the integrated circuit based on nodes and directed edges in the multi-level logical network; performing logic optimization on the integrated circuit based on the adjacency matrix and matrix operation.
In an exemplary embodiment of the present application, generating an adjacency matrix for the integrated circuit based on node-directed edges in the multi-level logical network includes: and generating an adjacency matrix of the integrated circuit based on linked list relations or code data corresponding to the nodes and the directed edges in the multi-level logic network.
In an exemplary embodiment of the present application, logic optimization of the integrated circuit based on the adjacency matrix and matrix operations includes: performing a matrix calculation on the adjacency matrix to generate a plurality of largest independent fan-out cones of the integrated circuit; performing logic optimization on the integrated circuit based on the plurality of largest independent fan-out cones.
In an exemplary embodiment of the present application, matrix computing the adjacency matrix to generate a plurality of largest independent fan-out cones of the integrated circuit includes: extracting input nodes and output nodes of the integrated circuit from the multi-level logic network; starting, by the input node, a progressive advance to an output node based on a forward wave; performing matrix calculation on the adjacent matrix in each level of forward waves to update the subordination relation between the node in the forward wave of the current level and the parent node of the node; after forward wave advancement to an output node, generating the plurality of largest independent fan-out cones of the integrated circuit according to a membership between each node and its parent node.
In an exemplary embodiment of the present application, performing a matrix calculation on the adjacency matrix in each stage of the forward wave to update the membership between a node in the forward wave of the current stage and its parent node includes: performing vector multiplication calculation on nodes in the forward wave of the current level in parallel based on the adjacency matrix in each level of forward wave; in each level of vector multiplication calculation of the forward wave, when the root node of the node to be calculated is the same as the root node corresponding to the forward wave of the current level, the root node mark of the node to be calculated is maintained to keep the dependency relationship.
In an exemplary embodiment of the present application, performing a matrix calculation on the adjacency matrix in each stage of the forward wave to update the membership between a node in the forward wave of the current stage and its parent node, further includes: and when the root node of the node to be calculated is different from the root node corresponding to the forward wave of the current level, canceling the root node mark of the node to be calculated so as to treat the node to be calculated as an isolated node.
In one exemplary embodiment of the present application, generating the plurality of largest independent fan-out cones of the integrated circuit from dependencies between each node and its parent node after a forward wave advances to an output node comprises: after the forward wave advances to an output node, the largest independent fan-out cone for the root node is generated by nodes belonging to the same root node only.
In an exemplary embodiment of the present application, logically optimizing the integrated circuit based on the plurality of largest independent fan-out cones includes: generating a plurality of sliced sets of each of the plurality of largest independent fan-out cones; and carrying out logic simplification based on a plurality of segmentation sets corresponding to the plurality of maximum independent fan-out cones.
In an exemplary embodiment of the present application, performing logic simplification based on a plurality of slicing sets corresponding to the plurality of largest independent fan-out cones includes: extracting a target segmentation set from a plurality of segmentation sets corresponding to the plurality of maximum independent fan-out cones; and rewriting the nodes in the target segmentation set.
According to an aspect of the present application, an apparatus for logic optimization of an integrated circuit is provided, the apparatus comprising: the network module is used for acquiring a multistage logic network of the integrated circuit, wherein edges among nodes in the multistage logic network are directed edges; a matrix module to generate an adjacency matrix for the integrated circuit based on nodes in the multi-level logical network and their corresponding directed edges; an optimization module to perform logic optimization on the integrated circuit based on the adjacency matrix and matrix operations.
According to an aspect of the present application, an electronic device is provided, the electronic device including: one or more processors; storage means for storing one or more programs; when executed by one or more processors, cause the one or more processors to implement a method as above.
According to an aspect of the application, a computer-readable medium is proposed, on which a computer program is stored, which program, when being executed by a processor, carries out the method as above.
According to the logic optimization method, the logic optimization device, the electronic equipment and the computer readable medium of the integrated circuit, a multi-level logic network of the integrated circuit is obtained, wherein the multi-level logic network comprises nodes and directed edges; generating an adjacency matrix for the integrated circuit based on nodes and directed edges in the multi-level logical network; the method for carrying out logic optimization on the integrated circuit based on the adjacency matrix and the matrix operation can update the relation between the nodes in the logic network of the integrated circuit from the original link formula to a matrix form, and quickly and accurately optimize the integrated circuit through a matrix calculation mode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. The drawings described below are only some embodiments of the present application, and other drawings may be derived from those drawings by those skilled in the art without inventive effort.
FIG. 1 is a schematic diagram of a multi-level logic network of an integrated circuit.
FIG. 2 is a flow chart illustrating a method of logic optimization of an integrated circuit, according to an example embodiment.
Fig. 3 is a schematic diagram illustrating matrix operations in a method for logic optimization of an integrated circuit according to an example embodiment.
FIG. 4 is a schematic diagram illustrating a largest independent fan-out cone in a method for logic optimization of an integrated circuit, according to an example embodiment.
FIG. 5 is a flow chart illustrating a method of logic optimization of an integrated circuit according to another exemplary embodiment.
FIG. 6 is a schematic diagram illustrating a method of logic optimization of an integrated circuit according to another exemplary embodiment.
FIG. 7 is a flow chart illustrating a method of logic optimization of an integrated circuit according to another exemplary embodiment.
FIG. 8 is a block diagram illustrating an apparatus for logic optimization of an integrated circuit in accordance with an exemplary embodiment.
FIG. 9 is a block diagram illustrating an electronic device in accordance with an example embodiment.
FIG. 10 is a block diagram illustrating a computer-readable medium in accordance with an example embodiment.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.
The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. I.e. these functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor means and/or microcontroller means.
The flowcharts shown in the figures are illustrative only and do not necessarily include all of the contents and operations/steps, nor do they necessarily have to be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present concepts. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be appreciated by those skilled in the art that the drawings are merely schematic representations of exemplary embodiments, and that the blocks or processes shown in the drawings are not necessarily required to practice the present application and are, therefore, not intended to limit the scope of the present application.
The technical abbreviations referred to in this application are explained as follows:
HDL (Hardware Description Language), which is a Language used to describe the functions and behaviors of digital circuits, can describe digital circuit systems at the register transfer level, behavior level, logic gate level, etc. With the development of automated logic synthesis tools, hardware description languages can be identified by these tools and automatically converted to logic gate level netlists, so that the hardware description languages can be used to design circuit systems and verify circuit functions through the form of logic simulation. After the design is complete, logic synthesis tools may be used to generate a netlist (i.e., netlist) at a low level of abstraction (gate level).
EDA (Electronic Design Automation) refers to a Design method for completing the processes of functional Design, integration, verification, physical Design (including layout, wiring, layout, design rule check, etc.) of a very large scale integrated circuit (VLSI) chip by using Computer Aided Design (CAD) industrial Automation software.
In digital circuit design, RTL (Register transfer Level) is an abstract model of a synchronous digital circuit, and is determined according to the flow of digital signals among logic units such as hardware registers, memories, combinational logic devices and buses, and the logic algebraic operation mode of the logic units. Register transfer level abstraction models are used in hardware description languages such as Verilog and VHDL to create a high-level description of the actual circuit, while low-level descriptions may even be derived from the high-level description. In modern digital design, the design at the register transfer level is the most typical workflow. The logic synthesis tool may build lower level circuit descriptions from the register transfer level descriptions.
BFS (Breadth First Search algorithm), which is also translated into Breadth-First Search or horizontal-First Search, is a Search algorithm based on graph structure. In brief, BFS is a traversal of the nodes of the tree down the width of the tree, starting from the root node (root). If all nodes are visited, or the target node is searched, the algorithm terminates. Implementations of breadth-first searches generally employ an open-closed table to record nodes that have been processed (labeled closed) or are already waiting in a queue (labeled open).
DP (Dynamic Programming), a method for solving complex problems by decomposing an original problem into relatively simple sub-problems. Often many sub-problems are very similar, for which dynamic programming attempts to solve each sub-problem only once, thereby reducing the amount of computation: once the solution for a given sub-problem has been calculated, it is memorised and stored for direct lookup next time the same sub-problem solution is required. This is particularly useful when the number of repeated sub-problems is long in relation to the size of the input, which means .
PI (Primary Input), an Input terminal at the outermost layer of the circuit logic network, and all nodes without fanin are PI.
PO (Primary Output), the Output of the outermost layer of a circuit logic network, and all nodes without fanout are PO.
AIG (And-Inverter Graph, NOT-AND).
MFFC (Maximum Fanout-Free Cone) refers to the Maximum number of subordinate modules in the system architecture that a module can directly call.
FIG. 1 is a schematic diagram of a multi-level logic network of an integrated circuit. At present, a common logic optimization algorithm of an integrated circuit is algebraic rewriting (algebra rewriting) of circuit nodes, a corresponding circuit netlist or a corresponding multi-level logic network of the circuit for optimization is a directed Graph built through an AIG (add-inverse Graph), and a storage data structure of the AIG directed Graph is formed through a linked list. In a multi-level logical network, each node represents a logical gate, and the nodes are connected by directed edges. The directed edges are represented in the AIG by using linked lists, and have different attributes according to different corresponding physical meanings. As shown in FIG. 1, the o1 and o2 nodes are input nodes, a, b, c, d and e are output nodes, and the node 1,2,3,4,5,6,7,8 can be called a node in the website.
FIG. 2 is a flow chart illustrating a method for logic optimization of an integrated circuit according to an example embodiment. The logic optimization method 20 of the integrated circuit includes at least steps S202 to S206.
As shown in fig. 2, in S202, a multi-level logical network of the integrated circuit is obtained, where the multi-level logical network includes nodes and directed edges. Logic network related data of an integrated circuit to be optimized is obtained.
In S204, an adjacency matrix for the integrated circuit is generated based on nodes and directed edges in the multi-level logical network. As described above, in the prior art, the data structure of the AIG itself is constructed by a linked list, and the modification of the structure requires complex linked list pointer operation, which is inefficient. Therefore, in the present application, the data in the form of the linked list is converted into the data in the form of the matrix for subsequent calculation.
In one embodiment, an adjacency matrix for the integrated circuit may be generated based on linked list relationships or code data corresponding to nodes and directed edges in the multi-level logical network.
More specifically, the nodes in the multi-level logic network can be read one by one, and the adjacency matrix of the integrated circuit to be optimized is generated according to the correspondence between the nodes and the directed edges.
In S206, the integrated circuit is logically optimized based on the adjacency matrix and matrix operations.
In the application, each operation processing in the graph algorithm is abstracted into linear algebraic operation (matrix operation), and the efficiency of each operation processing in the graph algorithm is improved through the matrix operation, so that the efficiency of logic optimization of the integrated circuit is improved.
Fig. 3 is a schematic diagram illustrating matrix operations in a logic optimization method for an integrated circuit according to an exemplary embodiment. As shown in FIG. 3, taking the dynamic programming DP as an example, the message passing from a node to its children node is expressed as operations of an adjacency matrix (adjacency matrix) and a distance vector (distance vector) through linear algebra, and the analogy matrix and the vector multiplication are performed by the analogy matrix and the vector multiplication C i,j =∑ k A i,k ×B k,j Can be used to convert sigma k (.) replace min k (.), "x" operation is replaced by "+", so new formula C i,j =min k (A i,k + B k,j ) Isomorphism, the new formula is equivalent to that the node i transmits own value to all nodes k with connection relation in the next layer in the dynamic programming DP operation, and then each nodeAnd calculating the distance (+) from the node k to the node i by the node k, and selecting the minimum value (min) from all the results by the node j to update the distance value from the node j to the node i.
Corresponding to the network structure in fig. 1, it can be further abstracted into a matrix expression of
OP1 performs a phase wise operation (interval wise operation) and OP2 is a condensation (reduction), simulating a matrix multiplication. Then the step of dynamically planning the DP can be expressed as
. By combining the graph algorithm and the sparse matrix operation and applying the combination to the optimization of the logic synthesis algorithm, the calculation efficiency of the algorithm can be improved and unnecessary expenses can be reduced.
In one embodiment, a matrix calculation may be performed on the adjacency matrix to generate a plurality of maximum independent fan-out cones (MFFCs) of the integrated circuit; performing logic optimization on the integrated circuit based on the plurality of largest independent fan-out cones.
FIG. 4 is a schematic diagram illustrating a largest independent fan-out cone in a method for logic optimization of an integrated circuit, according to an example embodiment. MFFC is used to compute or search data streams transmitted by other nodes (logic gates) associated with a node n (or a logic gate in a circuit network) in a directed graph structure, and only affects or changes the output result of the node n. Fig. 4 shows the result of the MFFC operation performed on the network shown in fig. 1. Where the MFFC of node 8 is contained in the shaded portion, the MFFC of node 5 is shaded only itself.
In one embodiment, matrix computing the adjacency matrix to generate a plurality of largest independent fan-out cones of the integrated circuit comprises: extracting input nodes and output nodes of the integrated circuit from the multi-level logic network; starting, by the input node, a progressive advance to an output node based on a forward wave; performing matrix calculation on the adjacent matrix in each level of forward waves to update the subordination relation between the node in the forward wave of the current level and the parent node of the node; after forward wave advancement to an output node, generating the plurality of largest independent fan-out cones of the integrated circuit according to a membership between each node and its parent node.
The details of "performing a matrix calculation on the adjacency matrix to generate a plurality of largest independent fan-out cones of the integrated circuit" will be described in detail later.
According to the logic optimization method of the integrated circuit, a multi-level logic network of the integrated circuit is obtained, wherein the multi-level logic network comprises nodes and directed edges; generating an adjacency matrix for the integrated circuit based on nodes and directed edges in the multi-level logical network; the logic optimization method for the integrated circuit based on the adjacency matrix and the matrix operation can update the relation between the nodes in the logic network of the integrated circuit from the original link form to the matrix form, and quickly and accurately optimize the integrated circuit through the matrix calculation mode.
It should be clearly understood that this application describes how to make and use particular examples, but the principles of this application are not limited to any details of these examples. Rather, these principles can be applied to many other embodiments based on the teachings of the present disclosure.
FIG. 5 is a flow chart illustrating a method of logic optimization of an integrated circuit according to another exemplary embodiment. The flow 50 shown in FIG. 5 is a detailed description of S206 "matrix compute the adjacency matrix to generate the multiple largest independent fan-out cones of the integrated circuit" in the flow shown in FIG. 2.
As shown in fig. 5, in S502, the input node and the output node of the integrated circuit are extracted from the multi-stage logic network.
In S504, the input node starts to advance to the output node stage by stage based on the forward wave.
In S506, a matrix calculation is performed on the adjacency matrix in each level of the forward wave to update the membership between the node in the current level of the forward wave and its parent node. Vector multiplication calculation can be carried out on nodes in the forward wave of the current level in parallel based on the adjacency matrix in each level of forward wave; in each level of vector multiplication calculation of the forward wave, when the root node of the node to be calculated is the same as the root node corresponding to the forward wave of the current level, the root node mark of the node to be calculated is maintained to keep the dependency relationship.
In one embodiment, when the root node of the node to be calculated is different from the root node corresponding to the forward wave of the current level, the root node mark of the node to be calculated is cancelled to treat the node to be calculated as an isolated node.
In S508, after the forward wave advances to the output node, the plurality of largest independent fan-out cones of the integrated circuit are generated according to the membership between each node and its parent node. After the forward wave advances to an output node, the largest independent fan-out cone for the root node is generated by nodes belonging to the same root node only.
FIG. 6 is a schematic diagram illustrating a method of logic optimization of an integrated circuit according to another exemplary embodiment. The flow described in fig. 5 can be explained in detail with the aid of the contents of fig. 6. As shown in fig. 6, a level is the most forward wave (shown by a dotted line in the graph) in the directed graph structure, the mark of the root node (root) (in a small square beside each node) is pushed to the node of the next layer, the computation of all nodes in the forward wave (root) of each layer can be processed in parallel, when the marked node is encountered and the value of the marked root node is different from the current value, the node provides signals for a plurality of parent nodes, so that the node cannot belong to an independent MFFC, namely, the corresponding parent node is marked off. Finally, all nodes that record only one root node (root) information belong to the MFFC (multi-factor flow chart) of the root node.
The above-described MFFC calculation may be implemented using execution of the following code examples:
in the actual calculation process, each wavefront is equivalent to traversing one layer in the graph algorithm BFS, and corresponds to linear algebraic linear matrix operation, namely A & lt +1.Get _root () ñ v.
In the prior art, the data structure of the AIG directed graph is formed by a linked list, the data structure of the linked list can only be calculated one by one according to the sequence of the linked list, and the graph data calculation efficiency of the linked list structure is extremely low for a complex integrated circuit. Due to the low computational efficiency, most of the current integrated circuit logic optimization based on the graph data in the form of a linked list is local, and the global exploration of a graph data network cannot be performed.
According to the logic optimization method of the integrated circuit, the original link table type integrated circuit network data are converted into the matrix type data, the original link table type data calculation mode one by one is changed into the matrix parallel calculation mode, and the logic optimization efficiency of the integrated circuit can be greatly improved.
FIG. 7 is a flow chart illustrating a method of logic optimization of an integrated circuit according to another exemplary embodiment. The flow 70 shown in FIG. 7 is a detailed description of S206 "logically optimizing the integrated circuit based on the plurality of largest independent fan-out cones" in the flow shown in FIG. 2.
As shown in fig. 7, in S702, a plurality of sliced sets of each of the plurality of largest independent fan-out cones is generated.
The cut set (cutengeneration) is a logical synthesis in which the cost (cost) of nodes (or logic gates) to be replaced and the surplus (gain) after replacement are calculated. A split set is a set of boundary points (or called leaves leaf nodes) of a logical cone (logiccone) with a node (or logical gate) as a root, which makes every path (path) from the PI to the root node root must pass through at least one node in the split set. The segmentation is a possible segmentation set for finding out each node of the circuit logic network as a root node root of the region, and the segmentation set is not unique for one node.
In S704, a target segmentation set is extracted from a plurality of segmentation sets corresponding to the maximum independent fan-out cones. The number of optimized nodes can be determined according to the optimization goal of the integrated circuit; and extracting a target segmentation set according to the number of the optimized nodes.
In a specific embodiment, it may be specified according to the optimization goal of the integrated circuit that the sliced set including 4 nodes is to be optimized into a sliced set including 3 nodes, i.e., each sliced set including 4 nodes is attempted to be reduced into 3 nodes. All the segmentation sets including 4 nodes may be used as a target set, and of course, other optimization targets may also be set, for example, the segmentation sets including the most nodes are optimized, and the like, which is not limited in this application.
In S706, node rewriting is performed on the nodes in the target segmentation set. Multi-level logic network data of the integrated circuit can be obtained; generating an adjacency matrix for the integrated circuit based on nodes in the multi-level logical network data and their corresponding directed edges; generating segmentation matrixes corresponding to the plurality of segmentation sets based on the adjacency matrixes; and rewriting the nodes based on a plurality of segmentation matrixes and matrix calculation.
In the prior art, in the graph data based on the chain table form, when node optimization is performed on diversity combining, complex chain table pointer operation needs to be performed, and according to the logic optimization method of the integrated circuit in the application, a matrix calculation mode is adopted, so that the operation efficiency can be greatly improved.
Those skilled in the art will appreciate that all or part of the steps implementing the above embodiments are implemented as computer programs executed by a CPU. When executed by the CPU, performs the functions defined by the methods provided herein. The program may be stored in a computer readable storage medium, which may be a read-only memory, a magnetic or optical disk, or the like.
Furthermore, it should be noted that the above-mentioned figures are only schematic illustrations of the processes involved in the method according to exemplary embodiments of the present application and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.
The following are embodiments of the apparatus of the present application that may be used to perform embodiments of the method of the present application. For details which are not disclosed in the embodiments of the apparatus of the present application, reference is made to the embodiments of the method of the present application.
FIG. 8 is a block diagram illustrating an apparatus for logic optimization of an integrated circuit in accordance with an exemplary embodiment. As shown in fig. 8, the logic optimization apparatus 80 of the integrated circuit includes: a network module 802, a matrix module 804, and an optimization module 806.
The network module 802 is configured to obtain a multi-level logic network of an integrated circuit, where edges between nodes in the multi-level logic network are directed edges;
a matrix module 804 for generating an adjacency matrix for the integrated circuit based on nodes in the multi-level logical network and their corresponding directed edges; the matrix module 804 is further configured to generate an adjacency matrix of the integrated circuit based on linked list relationships or code data corresponding to nodes and directed edges in the multi-level logical network.
An optimization module 806 is used to logically optimize the integrated circuit based on the adjacency matrix and matrix operations. The optimization module 806 is further configured to perform a matrix calculation on the adjacency matrix to generate a plurality of largest independent fan-out cones of the integrated circuit; performing logic optimization on the integrated circuit based on the plurality of largest independent fan-out cones.
According to the logic optimization device of the integrated circuit, a multi-level logic network of the integrated circuit is obtained, wherein the multi-level logic network comprises nodes and directed edges; generating an adjacency matrix for the integrated circuit based on nodes and directed edges in the multi-level logical network; the method for carrying out logic optimization on the integrated circuit based on the adjacency matrix and the matrix operation can update the relation between the nodes in the logic network of the integrated circuit from the original link formula to a matrix form, and quickly and accurately optimize the integrated circuit through a matrix calculation mode.
FIG. 9 is a block diagram illustrating an electronic device in accordance with an example embodiment.
An electronic device 900 according to this embodiment of the application is described below with reference to fig. 9. The electronic device 900 shown in fig. 9 is only an example and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.
As shown in fig. 9, the electronic device 900 is embodied in the form of a general purpose computing device. Components of electronic device 900 may include, but are not limited to: at least one processing unit 910, at least one storage unit 920, a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910), a display unit 940, and the like.
Wherein the storage unit stores program code that can be executed by the processing unit 910 such that the processing unit 910 performs the steps according to various exemplary embodiments of the present application described in the present specification. For example, the processing unit 910 may perform the steps shown in fig. 2, 5, and 7.
The storage unit 920 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 9201 and/or a cache memory unit 9202, and may further include a read only memory unit (ROM) 9203.
The memory unit 920 may also include a program/utility 9204 having a set (at least one) of program modules 9205, such program modules 9205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.
The electronic device 900 may also communicate with one or more external devices 900' (e.g., keyboard, pointing device, bluetooth device, etc.), such that a user can communicate with devices with which the electronic device 900 interacts, and/or any device (e.g., router, modem, etc.) with which the electronic device 900 can communicate with one or more other computing devices. Such communication may occur via input/output (I/O) interfaces 950. Also, the electronic device 900 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet) via the network adapter 960. The network adapter 960 may communicate with other modules of the electronic device 900 via the bus 930. It should be appreciated that although not shown, other hardware and/or software modules may be used in conjunction with the electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, and may also be implemented by software in combination with necessary hardware. Therefore, as shown in fig. 10, the technical solution according to the embodiment of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, or a network device, etc.) to execute the above method according to the embodiment of the present application.
The software product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable storage medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable storage medium may be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).
The computer readable medium carries one or more programs which, when executed by a device, cause the computer readable medium to perform the functions of: acquiring a multi-level logic network of an integrated circuit, wherein the multi-level logic network comprises nodes and directed edges; generating an adjacency matrix for the integrated circuit based on nodes and directed edges in the multi-level logical network; performing logic optimization on the integrated circuit based on the adjacency matrix and matrix operation.
Those skilled in the art will appreciate that the modules described above may be distributed in the apparatus as described in the embodiments, and that corresponding changes may be made in one or more apparatus that are unique from the embodiments. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiment of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiment of the present application.
Exemplary embodiments of the present application are specifically illustrated and described above. It is to be understood that the application is not limited to the details of construction, arrangement, or method of implementation described herein; on the contrary, the intention is to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (12)
1. A method of logic optimization of an integrated circuit, comprising:
acquiring a multi-level logic network of an integrated circuit, wherein the multi-level logic network comprises nodes and directed edges;
generating an adjacency matrix for the integrated circuit based on nodes and directed edges in the multi-level logical network;
performing logic optimization on the integrated circuit based on the adjacency matrix and matrix operation.
2. The method of claim 1, wherein generating the adjacency matrix for the integrated circuit based on node-directed edges in the multi-level logical network comprises:
and generating an adjacency matrix of the integrated circuit based on linked list relations or code data corresponding to the nodes and the directed edges in the multi-level logic network.
3. The method of claim 1, wherein logically optimizing the integrated circuit based on the adjacency matrix and matrix operations comprises:
performing a matrix calculation on the adjacency matrix to generate a plurality of largest independent fan-out cones of the integrated circuit;
performing logic optimization on the integrated circuit based on the plurality of largest independent fan-out cones.
4. The method of claim 3, wherein matrix computing the adjacency matrix to generate a plurality of largest independent fan-out cones of the integrated circuit comprises:
extracting input nodes and output nodes of the integrated circuit from the multi-level logic network;
starting, by the input node, a progressive advance to an output node based on a forward wave;
performing matrix calculation on the adjacent matrix in each level of forward waves to update the subordination relation between the node in the forward wave of the current level and the parent node of the node;
after forward wave advancement to an output node, generating the plurality of largest independent fan-out cones of the integrated circuit according to a membership between each node and its parent node.
5. The method of claim 4, wherein performing a matrix computation on the adjacency matrix in each level of the forward wave to update the membership between a node in the current level of the forward wave and its parent node comprises:
performing vector multiplication calculation on nodes in the forward wave of the current level in parallel based on the adjacency matrix in each level of forward wave;
in each level of vector multiplication calculation of the forward wave, when the root node of the node to be calculated is the same as the root node corresponding to the forward wave of the current level, the root node mark of the node to be calculated is maintained to keep the dependency relationship.
6. The method of claim 5, wherein the adjacency matrix is matrix-computed in each level of the forward wave to update the membership between a node and its parent node in the current level of the forward wave, further comprising:
and when the root node of the node to be calculated is different from the root node corresponding to the forward wave of the current level, canceling the root node mark of the node to be calculated so as to regard the node to be calculated as an isolated node.
7. The method of claim 4, wherein generating the plurality of largest independent fan-out cones of the integrated circuit from dependencies between each node and its parent node after a forward wave advances to an output node comprises:
after the forward wave advances to an output node, the largest independent fan-out cone for the root node is generated by nodes belonging to the same root node only.
8. The method of claim 3, wherein logically optimizing the integrated circuit based on the plurality of largest independent fan-out cones comprises:
generating a plurality of sliced sets of each of the plurality of largest independent fan-out cones;
and carrying out logic simplification based on a plurality of segmentation sets corresponding to the plurality of maximum independent fan-out cones.
9. The method of claim 8, wherein performing a logical reduction based on a plurality of sliced sets corresponding to the plurality of largest independent fan-out cones comprises:
extracting a target segmentation set from a plurality of segmentation sets corresponding to the plurality of maximum independent fan-out cones;
and rewriting the nodes in the target segmentation set.
10. An apparatus for logic optimization of an integrated circuit, comprising:
the network module is used for acquiring a multistage logic network of the integrated circuit, wherein edges among nodes in the multistage logic network are directed edges;
a matrix module to generate an adjacency matrix for the integrated circuit based on nodes in the multi-level logical network and their corresponding directed edges;
an optimization module to perform logic optimization on the integrated circuit based on the adjacency matrix and matrix operations.
11. An electronic device, comprising:
one or more processors;
storage means for storing one or more programs;
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method recited in any of claims 1-9.
12. A computer-readable medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1-9.
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