CN117540670A - Global truth table generation method and device for digital circuit - Google Patents

Abstract

The present disclosure relates to a global truth table generation method and apparatus for digital circuits. The method comprises the following steps: acquiring one or more corresponding Boolean functions of a target digital circuit; generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions; determining a target value for a root node of the global expression tree; traversing the global expression tree based on the target value; calculating signal combinations of a plurality of leaf nodes in a global expression tree based on a logic relation in the process of traversing the global expression tree; a global truth table for the target digital circuit is generated by signal combining of the plurality of leaf nodes. The global truth table generation method and the global truth table generation device for the digital circuit can quickly and accurately acquire the global truth table of the corresponding plurality of Boolean functions of the digital circuit, so that the calculation efficiency of the Boolean functions in the digital circuit is improved, the simulation speed is improved, and system resources are saved.

Description

Global truth table generation method and device for digital circuit

Technical Field

The present disclosure relates to the field of digital circuits, and in particular, to a global truth table generating method and apparatus for a digital circuit.

Background

A digital circuit is a circuit that performs arithmetic operations and logical operations on digital quantities using digital signals, and is called a digital circuit, or a digital system. It is also called a digital logic circuit because it has logic operation and logic processing functions. Logic gates are the basic units of digital logic circuits. Digital circuits can be divided into two main categories, combinational logic circuits and sequential logic circuits.

Digital circuits are based on binary digital logic, the operating signals of which are discrete digital signals, so that there are a large number of boolean functions in boolean logic in one digital circuit, which are particularly important components in digital circuits.

The EDA simulator can simulate the functional behaviour of a circuit without the need to build an actual circuit (which can be cumbersome and expensive) and is therefore a very valuable tool. Before the actual circuit is constructed, simulation verification is carried out on the design, so that the design efficiency can be greatly improved. This is because the designer can observe and study the behavior of the circuit in advance before constructing the circuit without having to pay time and economic costs for the physical implementation of the circuit. Particularly, integrated circuits are physically expensive to implement in terms of electronic processes such as photomasks, which are required for the circuits, and the high complexity of the integrated circuits is difficult to implement on bread boards. Therefore, almost all integrated circuit designs are relatively dependent on simulations. The most well known analog simulation is SPICE, while the most well known digital circuit simulators are either Verilog or VHDL based.

It is obvious that a large number of boolean functions need to be calculated for simulation of a digital circuit, and if the values of the boolean functions are obtained by means of a truth table, a large number of boolean functions need to be calculated, and the calculation amount is also relatively large.

The above information disclosed in the background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

In view of this, the present application provides a global truth table generating method and apparatus for a digital circuit, which can quickly and accurately obtain a global truth table of a plurality of boolean functions corresponding to the digital circuit, thereby accelerating the calculation efficiency of the boolean functions in the digital circuit, improving the simulation speed, and saving the system resources.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.

According to an aspect of the present application, a global truth table generation method for a digital circuit is presented, the method comprising: acquiring one or more corresponding Boolean functions of a target digital circuit; generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions; determining a target value for a root node of the global expression tree; traversing the global expression tree based on the target value; calculating signal combinations of a plurality of leaf nodes in a global expression tree based on a logic relation in the process of traversing the global expression tree; a global truth table for the target digital circuit is generated by signal combining of the plurality of leaf nodes.

In an exemplary embodiment of the present application, further comprising: acquiring signal values of a plurality of input signals; inputting the plurality of input signals to ports corresponding to the target digital circuit; and obtaining simulation output results of the digital circuit through the plurality of input signals and the global truth table.

In an exemplary embodiment of the present application, generating, by the one or more boolean functions, a global expression tree corresponding to the target digital circuit includes: parsing the one or more boolean functions to generate one or more expression trees; and correlating the one or more expression trees to generate the global expression tree corresponding to the target digital circuit.

In an exemplary embodiment of the present application, associating the one or more expression trees to generate the global expression tree corresponding to the target digital circuit includes: extracting heel and leaf nodes of the one or more expression trees; associating the one or more expression trees based on correspondence of root nodes and leaf nodes; and generating the global expression tree corresponding to the target digital circuit according to the association result.

In one exemplary embodiment of the present application, traversing the global expression tree based on the target value includes: taking the target value as a numerical value corresponding to a root node of the global expression tree; traversing the global expression tree by a breadth-first search algorithm.

In one exemplary embodiment of the present application, calculating a signal combination of a plurality of leaf nodes in a global expression tree based on a logical relationship in traversing the global expression tree includes: acquiring the numerical value of a root node in the process of traversing the global expression tree; calculating the signal combination of the lower node according to the numerical value of the root node and the corresponding operation type; the signal combinations of the lower nodes are traversed one by one until the signal combinations of the lower leaf nodes are generated.

In an exemplary embodiment of the present application, traversing the signal combinations of the lower nodes one by one until the signal combinations of the lower leaf nodes are generated includes: acquiring current nodes in the process of traversing the lower nodes one by one; when the current node is not a leaf node, extracting numerical values in signal combinations corresponding to the current node one by one; and calculating the signal combination of the lower node according to the numerical value of the current node and the corresponding operation type.

In one exemplary embodiment of the present application, generating a global truth table for the target digital circuit from a combination of signals of the plurality of leaf nodes includes: extracting signal combinations corresponding to leaf nodes at the bottom layer in the global expression tree; expanding the signal combination corresponding to the non-bottom leaf node; and generating a global truth table of the target digital circuit through signal combination corresponding to the bottom-layer leaf nodes and the expanded non-bottom-layer leaf nodes.

In an exemplary embodiment of the present application, expanding signal combinations corresponding to non-underlying leaf nodes includes: and expanding each number value in the signal combination corresponding to the non-bottom leaf node one by one according to the number of layers corresponding to the non-bottom leaf node.

In an exemplary embodiment of the present application, generating a global truth table of the target digital circuit by combining signals corresponding to the bottom leaf node and the extended non-bottom leaf node includes: generating an index value table through signal combination corresponding to the bottom-layer leaf nodes and the expanded non-bottom-layer leaf nodes; and eliminating repeated sequences in the index value table to generate a global truth table of the target digital circuit.

According to an aspect of the present application, there is provided a global truth table generating apparatus for a digital circuit, the apparatus comprising: the function module is used for acquiring one or more corresponding Boolean functions of the target digital circuit; the expression tree module is used for generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions; a target value module for determining a target value of a root node of the global expression tree; a traversing module for traversing the global expression tree based on the target value; the calculation module is used for calculating the numerical values of a plurality of leaf nodes in the global expression tree based on the logic relation in the process of traversing the global expression tree; and the truth table module is used for generating a global truth table of the target digital circuit through the numerical values of the plurality of leaf nodes.

According to an aspect of the present application, there is provided an electronic device including: one or more processors; a storage means for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the methods as described above.

According to an aspect of the present application, a computer-readable medium is presented, on which a computer program is stored, which program, when being executed by a processor, implements a method as described above.

According to the global truth table generation method and device for the digital circuit, one or more Boolean functions corresponding to the target digital circuit are obtained; generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions; determining a target value for a root node of the global expression tree; traversing the global expression tree based on the target value; calculating signal combinations of a plurality of leaf nodes in a global expression tree based on a logic relation in the process of traversing the global expression tree; the global truth table of the target digital circuit is generated by combining the signals of the plurality of leaf nodes, so that the global truth table of a plurality of corresponding Boolean functions of the digital circuit can be quickly and accurately obtained, the calculation efficiency of the Boolean functions in the digital circuit is improved, the simulation speed is improved, and the system resources are saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. The drawings described below are only some embodiments of the present application and other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a flow chart illustrating a global truth table generation method for a digital circuit according to an exemplary embodiment.

FIG. 2 is a flow chart illustrating a global truth table generation method for a digital circuit according to an exemplary embodiment.

Fig. 3 is a flow chart illustrating a global truth table generation method for a digital circuit according to another exemplary embodiment.

Fig. 4 is a schematic diagram illustrating a global truth table generation method for a digital circuit according to another exemplary embodiment.

Fig. 5 is a flow chart illustrating a global truth table generation method for a digital circuit according to another exemplary embodiment.

Fig. 6 is a schematic diagram illustrating a global truth table generation method for a digital circuit according to another exemplary embodiment.

Fig. 7 is a schematic diagram illustrating a global truth table generation method for a digital circuit according to another exemplary embodiment.

FIG. 8 is a block diagram illustrating a global truth table generating apparatus for a digital circuit according to an exemplary embodiment.

Fig. 9 is a block diagram of an electronic device, according to an example embodiment.

Fig. 10 is a block diagram of a computer-readable medium shown according to an example embodiment.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present application concept. As used herein, the term "and/or" includes any one of the associated listed items and all combinations of one or more.

Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments, and that the modules or flows in the drawings are not necessarily required to practice the present application, and therefore, should not be taken to limit the scope of the present application.

The technical abbreviations involved in this application are explained as follows:

boolean function (Boolean function): describing how to determine the boolean output based on some logical calculation of the boolean input, they play a fundamental role in the problem of complexity theory and the chip design of digital computers.

Boolean logic: boolean logic is an algebraic system of a set of logics, and is named by George Boolean of UK mathematician, and the Boolean logic operators mainly comprise four types of logical AND (and), logical OR (or), logical NOT (not) and logical XOR (xor).

Truth table: a table characterizing all possible states between logical event inputs and outputs.

Binary tree: is a set of n finite elements, either null or composed of one element called root and two disjoint binary trees, called left and right subtrees, respectively, which are ordered trees. When the set is empty, the binary tree is referred to as an empty binary tree. In a binary tree, an element is also called a node.

Expression tree: leaf nodes of the expression tree are operands and other nodes are operators. Assuming that all operators are binocular operators, just one binary tree is formed. We can derive the values of the entire expression tree by recursively computing the values of the left and right subtrees.

Breadth-first search algorithms (also known as breadth-first search) are one of the simplest graph search algorithms, the alias of which is also known as BFS, belonging to a blind search method, with the aim of systematically developing and examining all nodes in a graph to find results. In other words, it does not take into account the possible locations of the results, searching through the entire graph until the results are found.

Traversal (Traversal) refers to sequentially accessing each node in a tree (or graph) along a search route.

Verilog HDL: the language is a language for describing the structure and the behavior of digital system hardware in text form, and can be used for representing logic circuit diagrams, logic expressions and logic functions completed by a digital logic system. Verilog HDL and VHDL are the two most popular hardware description languages in the world.

BITs (BIT), computer terminology, is a unit of information content and is transliterated from English BIT. And the bit in the binary digit is also the measurement unit of the information quantity, which is the minimum unit of the information quantity.

The truth table is the basis of simulation calculation of a digital circuit, and for calculation of the truth table, a set of permutation and combination can be obtained according to input, and output can be obtained by putting the combination into the truth table. But it increases exponentially with the number of permutation and combination according to the permutation and combination algorithm. The calculation amount is also large by calculation combination.

The inventors have studied and found that in a digital circuit, assuming n input signals, in the case where only the input value of each input signal of the boolean function is considered to be 0 or 1, there are 2n combinations of all permutations in the truth table, and in the case where the signal values of the input signals are four possibilities of 0,1, x, z, there are 4n permutations of the truth table. The size of the truth table and the number of the combinations of the inputs are exponentially increased, and in the prior art, the operation amount of the truth table simulation is relatively large in a manner of obtaining the truth table through permutation and combination.

In view of the technical bottleneck in the prior art, the application provides a global truth table generating method for a digital circuit, which can accelerate the calculation time of the truth table. The following describes the content of the present application in detail with reference to specific examples.

FIG. 1 is a flow chart illustrating a global truth table generation method for a digital circuit according to an exemplary embodiment. The global truth table generating method 10 for a digital circuit includes at least steps S102 to S108.

As shown in fig. 1, in S102, a corresponding boolean function or functions of the target digital circuit are acquired. The circuit information of the target digital circuit can be read in, the Boolean function to be simulated is obtained in the circuit information, and the mapping relation between the input and the output of each Boolean function is not changed in the simulation.

In S104, a global expression tree corresponding to the target digital circuit is generated by the one or more boolean functions. Parsing the one or more boolean functions to generate one or more expression trees; and correlating the one or more expression trees to generate the global expression tree corresponding to the target digital circuit.

More specifically, the heel and leaf nodes of the one or more expression trees may be extracted; associating the one or more expression trees based on correspondence of root nodes and leaf nodes; and generating the global expression tree corresponding to the target digital circuit according to the association result.

In one example, the Boolean function corresponding to a digital circuit is as follows:

f＝((a&b)|c)&d。

the corresponding expression tree for the boolean function may be as shown in fig. 2.

In S106, a target value of a root node of the global expression tree is determined. The root node is the output value f of the boolean function, and there may be two possibilities for taking on f, for example: 1 or 0. The truth table of the boolean function when f=1 and the truth table of the boolean function when f=0 can be established according to the steps hereinafter, respectively.

In S108, traversing the global expression tree based on the target value. The target value can be used as a numerical value corresponding to a root node of the global expression tree; traversing the global expression tree by a breadth-first search algorithm.

F=0 can be set first, traversing the global expression tree based on the root node being 0.

In S110, signal combinations of a plurality of leaf nodes in a global expression tree are deduced based on logical relationships in traversing the global expression tree. The numerical value of the root node can be obtained in the process of traversing the global expression tree; calculating the signal combination of the lower node according to the numerical value of the root node and the corresponding operation type; the signal combinations of the lower nodes are traversed one by one until the signal combinations of the lower leaf nodes are generated.

The content of "deriving a signal combination of a plurality of leaf nodes in a global expression tree based on logical relationships in traversing the global expression tree" will be described in detail in the corresponding embodiment of fig. 3.

In S112, a global truth table for the target digital circuit is generated by signal combining of the plurality of leaf nodes. Extracting signal combinations corresponding to leaf nodes at the bottom layer in the global expression tree; expanding the signal combination corresponding to the non-bottom leaf node; and generating a global truth table of the target digital circuit through signal combination corresponding to the bottom-layer leaf nodes and the expanded non-bottom-layer leaf nodes.

The content of the global truth table for generating the target digital circuit by signal combining of the plurality of leaf nodes will be described in detail in the corresponding embodiment of fig. 4.

According to the global truth table generation method for the digital circuit, corresponding one or more Boolean functions of a target digital circuit are obtained; generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions; determining a target value for a root node of the global expression tree; traversing the global expression tree based on the target value; calculating signal combinations of a plurality of leaf nodes in a global expression tree based on a logic relation in the process of traversing the global expression tree; the global truth table of the target digital circuit is generated by combining the signals of the plurality of leaf nodes, so that the global truth table of a plurality of corresponding Boolean functions of the digital circuit can be quickly and accurately obtained, the calculation efficiency of the Boolean functions in the digital circuit is improved, the simulation speed is improved, and the system resources are saved.

It should be clearly understood that this application describes how to make and use particular examples, but the principles of this application are not limited to any details of these examples. Rather, these principles can be applied to many other embodiments based on the teachings of the present disclosure.

Fig. 3 is a flow chart illustrating a global truth table generation method for a digital circuit according to another exemplary embodiment. The flow 30 shown in fig. 3 is a detailed description of S110 "signal combination of a plurality of leaf nodes in the global expression tree is calculated based on logical relationships in traversing the global expression tree" in the flow shown in fig. 1.

As shown in fig. 3, in S302, the value of the root node is acquired in traversing the global expression tree. The root node may be assumed to be 0.

In S304, signal combinations of the lower nodes are calculated according to the numerical values of the root nodes and the corresponding operation types.

The truth table of the basic logic gate is derived from IEEE Standard forHardware Description Language, the truth table corresponding to the boolean function can be generated by the truth table of the basic logic gates. The truth table for the basic logic gate may be as shown in fig. 4.

According to the logic gate truth table of fig. 4, however, the combinations of inputs are all listed by way of a backward push, and then the signal combinations that generate the lower nodes are arranged.

For a truth table with a target output of 0, i.e. a root node of 0, its input combination is determined in case of a logical operation determination, e.g. if the output of an and gate is 0, then its likelihood is 3. The method can be, for example, as follows:

0＝0&0；

0＝1&0；

0＝0&1；

the combination of inputs is the possible 0,1,0 of one input and the possible 0,1 of the other input. Or the gate is reversed in a similar manner.

The above is the backward signal combination under the two conditions that the output value of the root node is 1,0 and the value range of the input value is also 0,1. It will be appreciated that the method of the present application may also be used in digital circuit calculations where the range of values of the input signal is four, 0,1, x, z. In the range of the input signal with four values of 0,1, x and z, the possibility of the combination obtained by reverse pushing is more.

In S306, the current node is acquired in the process of traversing the lower nodes one by one.

In S308, when the current node is not a leaf node, the values in the signal combinations corresponding to the current node are extracted one by one.

In the layer-by-layer traversing process, the nodes encountered each time are used as new root nodes, for example, the signal combination of the current node is 0,1 and 0, then 0 can be firstly extracted as the target output value of the current calculated node, and the possible combination of the values of the lower nodes is calculated by backward pushing; then extracting 1 as a target output value of the node currently calculated, and reversely pushing and calculating possible combination of values of the lower nodes; and finally, extracting 0 as a target output value of the currently calculated node, and reversely pushing and calculating the possible combination of the values of the lower nodes.

In S310, signal combinations of lower nodes are calculated according to the numerical value of the current node and the corresponding operation type. And obtaining all possible combination arrangements of the lower nodes through three times of calculation. The calculation result may be as shown in fig. 5.

A set of corresponding input combinations, which are the output values of its child nodes, can be obtained based on the values to be obtained and the type of operation of the node, and sequentially traverses down until the leaf nodes, all of which are the inputs to the Boolean function.

Fig. 6 is a flow chart illustrating a global truth table generation method for a digital circuit according to another exemplary embodiment. The process 60 shown in fig. 6 is a detailed description of the process S112 "generating a global truth table for the target digital circuit by signal combination of the plurality of leaf nodes" shown in fig. 2.

As shown in fig. 6, in S602, signal combinations corresponding to leaf nodes at the bottom layer in the global expression tree are extracted. As in the previous embodiments, all of the back-pushed signal combinations in the leaf nodes may be extracted. The specific signal combinations are shown in fig. 5.

In S604, signal combinations corresponding to non-bottom leaf nodes are extended. And each numerical value in the signal combination corresponding to the non-bottom layer leaf node can be expanded one by one according to the layer number corresponding to the non-bottom layer leaf node.

To generate a global truth table in the following, the combinations of all leaf nodes may be padded to the same value, and for example, the number of elements in the upper layer may be padded with the number of elements in the lowest layer, the padding is very simple, each value is repeated to the power of 3 by the offset, and the offset is the difference of the hierarchy.

In one embodiment, the tree has all values of its inputs at each level of 3 (n-1) th order elements, 3 at the second level, 9 at the third level, and 27 at the fourth level, as the boolean function shown above. Each value in each of the remaining leaf nodes of the layers, except the fourth layer of leaf nodes, is repeated 3 (n-1) times.

The value of each leaf node after expansion is shown in fig. 7.

In S606, a global truth table of the target digital circuit is generated by combining signals corresponding to the bottom leaf nodes and the expanded non-bottom leaf nodes. Generating an index value table through signal combination corresponding to the bottom-layer leaf nodes and the expanded non-bottom-layer leaf nodes; and eliminating repeated sequences in the index value table to generate a global truth table of the target digital circuit.

The index value table obtained in fig. 8 is subjected to a deduplication operation, so that a global truth table corresponding to the digital circuit can be obtained.

In one embodiment, signal values for a plurality of input signals may be obtained; inputting the plurality of input signals to ports corresponding to the target digital circuit; and obtaining simulation output results of the digital circuit through the plurality of input signals and the global truth table. In the actual use process, the simulation output value of the digital circuit can be obtained through searching through the global truth table.

Those skilled in the art will appreciate that all or part of the steps implementing the above described embodiments are implemented as a computer program executed by a CPU. When executed by a CPU, performs the functions defined by the above methods provided herein. The program may be stored in a computer readable storage medium, which may be a read-only memory, a magnetic disk or an optical disk, etc.

Furthermore, it should be noted that the above-described figures are merely illustrative of the processes involved in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.

The following are device embodiments of the present application, which may be used to perform method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

FIG. 8 is a block diagram illustrating a global truth table generating apparatus for a digital circuit according to an exemplary embodiment. As shown in fig. 8, the global truth table generating means 80 for a digital circuit includes: function module 802, expression tree module 804, target value module 806, traversal module 808, dead reckoning module 810, truth table module 812.

The function module 802 is configured to obtain one or more boolean functions corresponding to the target digital circuit;

the expression tree module 804 is configured to generate a global expression tree corresponding to the target digital circuit through the one or more boolean functions; the expression tree module 804 is further configured to parse the one or more boolean functions to generate one or more expression trees; and correlating the one or more expression trees to generate the global expression tree corresponding to the target digital circuit.

The target value module 806 is configured to determine a target value for a root node of the global expression tree;

a traversing module 808 is configured to traverse the global expression tree based on the target value; the traversing module 808 is further configured to take the target value as a numerical value corresponding to a root node of the global expression tree; traversing the global expression tree by a breadth-first search algorithm.

The calculating module 810 is configured to calculate a signal combination of a plurality of leaf nodes in the global expression tree based on a logical relationship in a process of traversing the global expression tree; the calculation module 810 is further configured to obtain a value of the root node during traversing the global expression tree; calculating the signal combination of the lower node according to the numerical value of the root node and the corresponding operation type; the signal combinations of the lower nodes are traversed one by one until the signal combinations of the lower leaf nodes are generated.

Truth table module 812 is configured to generate a global truth table for the target digital circuit from a combination of signals of the plurality of leaf nodes. The truth table module 812 is further configured to extract a signal combination corresponding to a leaf node at the bottom layer in the global expression tree; expanding the signal combination corresponding to the non-bottom leaf node; and generating a global truth table of the target digital circuit through signal combination corresponding to the bottom-layer leaf nodes and the expanded non-bottom-layer leaf nodes.

According to the global truth table generating device for the digital circuit, corresponding one or more Boolean functions of the target digital circuit are obtained; generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions; determining a target value for a root node of the global expression tree; traversing the global expression tree based on the target value; calculating signal combinations of a plurality of leaf nodes in a global expression tree based on a logic relation in the process of traversing the global expression tree; the global truth table of the target digital circuit is generated by combining the signals of the plurality of leaf nodes, so that the global truth table of a plurality of corresponding Boolean functions of the digital circuit can be quickly and accurately obtained, the calculation efficiency of the Boolean functions in the digital circuit is improved, the simulation speed is improved, and the system resources are saved.

Fig. 9 is a block diagram of an electronic device, according to an example embodiment.

An electronic device 900 according to this embodiment of the present application is described below with reference to fig. 9. The electronic device 900 shown in fig. 9 is merely an example, and should not be construed as limiting the functionality and scope of use of the embodiments herein.

As shown in fig. 9, the electronic device 900 is embodied in the form of a general purpose computing device. Components of electronic device 900 may include, but are not limited to: at least one processing unit 910, at least one storage unit 920, a bus 930 connecting the different system components (including the storage unit 920 and the processing unit 910), a display unit 940, and the like.

Wherein the storage unit stores program code that is executable by the processing unit 910 such that the processing unit 910 performs steps described in the present specification according to various exemplary embodiments of the present application. For example, the processing unit 910 may perform the steps as shown in fig. 1, 2, and 6.

The storage unit 920 may include readable media in the form of volatile storage units, such as Random Access Memory (RAM) 9201 and/or cache memory 9202, and may further include Read Only Memory (ROM) 9203.

The storage unit 920 may also include a program/utility 9204 having a set (at least one) of program modules 9205, such program modules 9205 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

The bus 930 may be one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 900 may also be in communication with one or more external devices 900' (e.g., keyboard, pointing device, bluetooth device, etc.), devices that enable a user to interact with the electronic device 900, and/or any devices (e.g., routers, modems, etc.) that the electronic device 900 can communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 950. Also, electronic device 900 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 960. The network adapter 960 can communicate with other modules of the electronic device 900 via the bus 930. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 900, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, as shown in fig. 10, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a server, or a network device, etc.) to perform the above-described method according to the embodiments of the present application.

The software product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable storage medium may also be any readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

The computer-readable medium carries one or more programs, which when executed by one of the devices, cause the computer-readable medium to perform the functions of: acquiring one or more corresponding Boolean functions of a target digital circuit; generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions; determining a target value for a root node of the global expression tree; traversing the global expression tree based on the target value; calculating signal combinations of a plurality of leaf nodes in a global expression tree based on a logic relation in the process of traversing the global expression tree; a global truth table for the target digital circuit is generated by signal combining of the plurality of leaf nodes.

Those skilled in the art will appreciate that the modules may be distributed throughout several devices as described in the embodiments, and that corresponding variations may be implemented in one or more devices that are unique to the embodiments. The modules of the above embodiments may be combined into one module, or may be further split into a plurality of sub-modules.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or in combination with the necessary hardware. Thus, the technical solutions according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and include several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the methods according to the embodiments of the present application.

Exemplary embodiments of the present application are specifically illustrated and described above. It is to be understood that this application is not limited to the details of construction, arrangement or method of implementation described herein; on the contrary, the application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (11)

1. A global truth table generation method for a digital circuit, comprising:

acquiring one or more corresponding Boolean functions of a target digital circuit;

generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions;

determining a target value for a root node of the global expression tree;

traversing the global expression tree based on the target value;

calculating signal combinations of a plurality of leaf nodes in a global expression tree based on a logic relation in the process of traversing the global expression tree;

a global truth table for the target digital circuit is generated by signal combining of the plurality of leaf nodes.

2. The global truth table generating method of claim 1, further comprising:

acquiring signal values of a plurality of input signals;

inputting the plurality of input signals to ports corresponding to the target digital circuit;

and obtaining simulation output results of the digital circuit through the plurality of input signals and the global truth table.

3. The global truth table generation method of claim 1, wherein generating a global expression tree corresponding to the target digital circuit by the one or more boolean functions comprises:

parsing the one or more boolean functions to generate one or more expression trees;

and correlating the one or more expression trees to generate the global expression tree corresponding to the target digital circuit.

4. A global truth table generation method according to claim 3, wherein associating the one or more expression trees to generate the global expression tree for the target digital circuit comprises:

extracting heel and leaf nodes of the one or more expression trees;

associating the one or more expression trees based on correspondence of root nodes and leaf nodes;

and generating the global expression tree corresponding to the target digital circuit according to the association result.

5. The global truth table generation method of claim 1, wherein traversing the global expression tree based on the target value comprises:

taking the target value as a numerical value corresponding to a root node of the global expression tree;

traversing the global expression tree by a breadth-first search algorithm.

6. The global truth table generating method according to claim 1, wherein calculating a signal combination of a plurality of leaf nodes in a global expression tree based on a logical relationship in traversing the global expression tree comprises:

acquiring the numerical value of a root node in the process of traversing the global expression tree;

calculating the signal combination of the lower node according to the numerical value of the root node and the corresponding operation type;

the signal combinations of the lower nodes are traversed one by one until the signal combinations of the lower leaf nodes are generated.

7. The global truth table generating method of claim 6 wherein traversing signal combinations of lower level nodes one by one until signal combinations of lower level leaf nodes are generated comprises:

acquiring current nodes in the process of traversing the lower nodes one by one;

when the current node is not a leaf node, extracting numerical values in signal combinations corresponding to the current node one by one;

and calculating the signal combination of the lower node according to the numerical value of the current node and the corresponding operation type.

8. The global truth table generating method of claim 1, wherein generating the global truth table of the target digital circuit by signal combining of the plurality of leaf nodes comprises:

extracting signal combinations corresponding to leaf nodes at the bottom layer in the global expression tree;

expanding the signal combination corresponding to the non-bottom leaf node;

and generating a global truth table of the target digital circuit through signal combination corresponding to the bottom-layer leaf nodes and the expanded non-bottom-layer leaf nodes.

9. The global truth table generating method of claim 8 wherein expanding signal combinations corresponding to non-underlying leaf nodes comprises:

and expanding each number value in the signal combination corresponding to the non-bottom leaf node one by one according to the number of layers corresponding to the non-bottom leaf node.

10. The global truth table generating method of claim 8 wherein generating the global truth table of the target digital circuit by combining signals corresponding to the underlying leaf nodes and the extended non-underlying leaf nodes comprises:

generating an index value table through signal combination corresponding to the bottom-layer leaf nodes and the expanded non-bottom-layer leaf nodes;

and eliminating repeated sequences in the index value table to generate a global truth table of the target digital circuit.

11. A global truth table generating apparatus for a digital circuit, comprising:

the function module is used for acquiring one or more corresponding Boolean functions of the target digital circuit;

the expression tree module is used for generating a global expression tree corresponding to the target digital circuit through the one or more Boolean functions;

a target value module for determining a target value of a root node of the global expression tree;

a traversing module for traversing the global expression tree based on the target value;

the calculation module is used for calculating signal combinations of a plurality of leaf nodes in the global expression tree based on a logic relation in the process of traversing the global expression tree;

and the truth table module is used for generating a global truth table of the target digital circuit through signal combination of the plurality of leaf nodes.