CN117540668A

CN117540668A - Simulation method and device for digital circuit

Info

Publication number: CN117540668A
Application number: CN202310454710.0A
Authority: CN
Inventors: 刘治强; 史峰
Original assignee: Beijing Xinsi Technology Co ltd
Current assignee: Beijing Xinsi Technology Co ltd
Priority date: 2023-04-25
Filing date: 2023-04-25
Publication date: 2024-02-09

Abstract

The present disclosure relates to a simulation method and apparatus for a digital circuit. The method comprises the following steps: acquiring an index table of a digital circuit to be simulated; acquiring signal values of a plurality of input signals to be simulated; inputting the plurality of input signals to ports corresponding to the digital circuits; and obtaining simulation output results of the digital circuit through the plurality of input signals and the index table. The simulation method and the simulation device for the digital circuit can improve the speed of Boolean function evaluation in the calculation process of the digital circuit, reduce the simulation time of the digital circuit, improve the overall operation efficiency and solve the system resource.

Description

Simulation method and device for digital circuit

Technical Field

The disclosure relates to the field of digital circuits, and in particular relates to a simulation method and device of a digital circuit.

Background

A digital circuit is a circuit that performs arithmetic operations and logical operations on digital quantities using digital signals, and is called a digital circuit, or a digital system. It is also called a digital logic circuit because it has logic operation and logic processing functions. Logic gates are the basic units of digital logic circuits. Digital circuits can be divided into two main categories, combinational logic circuits and sequential logic circuits.

The EDA simulator can simulate the functional behaviour of a circuit without the need to build an actual circuit (which can be cumbersome and expensive) and is therefore a very valuable tool. Before the actual circuit is constructed, simulation verification is carried out on the design, so that the design efficiency can be greatly improved. This is because the designer can observe and study the behavior of the circuit in advance before constructing the circuit without having to pay time and economic costs for the physical implementation of the circuit. Particularly, integrated circuits are physically expensive to implement in terms of electronic processes such as photomasks, which are required for the circuits, and the high complexity of the integrated circuits is difficult to implement on bread boards. Therefore, almost all integrated circuit designs are relatively dependent on simulations. The most well known analog simulation is SPICE, while the most well known digital circuit simulators are either Verilog or VHDL based.

Digital circuits are based on binary digital logic, the operating signals of which are discrete digital signals, so that there are a large number of boolean functions in boolean logic in one digital circuit, which are particularly important components in digital circuits. A Boolean function has a plurality of inputs, each input representing a conductor in the circuit, and when the voltage on the conductor changes, it represents that the value changes, each time the value changes, the function value may be changed, conventionally, the Boolean function is recalculated each time a value changes, and the output value corresponding to the current state is obtained. A large number of boolean functions need to be calculated during the digital circuit simulation in the prior art.

Disclosure of Invention

In view of this, the present application provides a simulation method and apparatus for a digital circuit, which can improve the speed of boolean function evaluation in the calculation process of the digital circuit, reduce the simulation time of the digital circuit, improve the overall operation efficiency, and solve the system resources.

Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.

According to an aspect of the present application, a simulation method of a digital circuit is provided, the method including: acquiring an index table of a digital circuit to be simulated; acquiring signal values of a plurality of input signals to be simulated; inputting the plurality of input signals to ports corresponding to the digital circuits; and obtaining simulation output results of the digital circuit through the plurality of input signals and the index table.

In an exemplary embodiment of the present application, further comprising: acquiring circuit information of a digital circuit to be simulated; extracting a Boolean function corresponding to the digital circuit based on the circuit information; and establishing the index table based on the Boolean function.

In an exemplary embodiment of the present application, building the index table based on the boolean function includes: generating a truth table of the Boolean function through a truth table of a basic logic gate; representing signal values of a plurality of input signals in the truth table in binary; the index table is built based on binary representations of the plurality of input signals and the values of their corresponding output signals.

In an exemplary embodiment of the present application, generating the truth table of the boolean function by a basic logic gate truth table includes: and comparing the logic relation in the Boolean function with the logic numerical value in the truth table of the basic logic gate to calculate and generate the truth table of the Boolean function, wherein the truth table comprises numerical relation between a plurality of input signals and output signals of the Boolean function.

In one exemplary embodiment of the present application, representing the signal values of the plurality of input signals in the truth table in binary includes: determining a binary conversion rule according to the value range of the signal value of each input signal; and distributing binary identification to each input signal according to the binary conversion rule.

In an exemplary embodiment of the present application, building the index table based on binary representations of the plurality of input signals and values of their corresponding output signals includes: generating a decimal sequence number corresponding to each input signal based on a binary representation of the signal; and establishing the index table according to the corresponding relation between the decimal serial number and the numerical value of the output signal.

In an exemplary embodiment of the present application, obtaining a simulation output result of the digital circuit through the plurality of input signals and the index table includes: allocating an identifier to each input signal according to the signal value of the input signal; arranging the plurality of input signals according to a preset sequence; and extracting simulation output results of the digital circuit from the index table according to the identifiers corresponding to the plurality of input signals based on the arrangement.

In an exemplary embodiment of the present application, assigning an identity to each input signal according to its signal value includes: the signal values are mapped to conversion rules to assign a binary identification to each input signal.

In an exemplary embodiment of the present application, extracting, based on the arrangement, a simulation output result of the digital circuit in the index table according to the identifiers corresponding to the plurality of input signals includes: representing the plurality of signals with their corresponding identities, respectively, based on the arrangement to generate a binary sequence; calculating a decimal serial number corresponding to the binary sequence; extracting a numerical value of an output signal of the digital circuit from the index table based on the decimal sequence number; and generating a simulation output result through the numerical value of the output signal.

According to an aspect of the present application, there is provided an emulation apparatus of a digital circuit, the apparatus comprising: acquiring an index table of a digital circuit to be simulated; acquiring signal values of a plurality of input signals to be simulated; inputting the plurality of input signals to corresponding ports of the digital circuit; and obtaining simulation output results of the digital circuit through the plurality of input signals and the index table.

According to an aspect of the present application, there is provided an electronic device including: one or more processors; a storage means for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors are caused to implement the methods as described above.

According to an aspect of the present application, a computer-readable medium is presented, on which a computer program is stored, which program, when being executed by a processor, implements a method as described above.

According to the simulation method and the simulation device of the digital circuit, an index table of the digital circuit to be simulated is obtained; acquiring signal values of a plurality of input signals to be simulated; inputting the plurality of input signals to ports corresponding to the digital circuits; the simulation output result of the digital circuit is obtained through the plurality of input signals and the index table, so that the Boolean function evaluation speed in the digital circuit calculation process can be improved, the digital circuit simulation time is reduced, the overall operation efficiency is improved, and the system resource is solved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. The drawings described below are only some embodiments of the present application and other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a flow chart illustrating a method of simulating a digital circuit according to an exemplary embodiment.

Fig. 2 is a flow chart illustrating a method of simulating a digital circuit according to an exemplary embodiment.

Fig. 3 is a schematic diagram illustrating a simulation method of a digital circuit according to another exemplary embodiment.

Fig. 4 is a schematic diagram illustrating a simulation method of a digital circuit according to another exemplary embodiment.

Fig. 5 is a schematic diagram illustrating a simulation method of a digital circuit according to another exemplary embodiment.

Fig. 6 is a flow chart illustrating a method of simulating a digital circuit according to another exemplary embodiment.

Fig. 7 is a block diagram illustrating an emulation device of a digital circuit according to an exemplary embodiment.

Fig. 8 is a block diagram of an electronic device, according to an example embodiment.

Fig. 9 is a block diagram of a computer-readable medium shown according to an example embodiment.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the present application. One skilled in the relevant art will recognize, however, that the aspects of the application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the application.

The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present application concept. As used herein, the term "and/or" includes any one of the associated listed items and all combinations of one or more.

Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments, and that the modules or flows in the drawings are not necessarily required to practice the present application, and therefore, should not be taken to limit the scope of the present application.

The technical abbreviations involved in this application are explained as follows:

boolean function (Boolean function): describing how to determine the boolean output based on some logical calculation of the boolean input, they play a fundamental role in the problem of complexity theory and the chip design of digital computers.

Boolean logic: boolean logic is an algebraic system of a set of logics, and is named by George Boolean of UK mathematician, and the Boolean logic operators mainly comprise four types of logical AND (and), logical OR (or), logical NOT (not) and logical XOR (xor).

Truth table: a table characterizing all possible states between logical event inputs and outputs.

Verilog HDL: the language is a language for describing the structure and the behavior of digital system hardware in text form, and can be used for representing logic circuit diagrams, logic expressions and logic functions completed by a digital logic system. Verilog HDL and VHDL are the two most popular hardware description languages in the world.

BITs (BIT), computer terminology, is a unit of information content and is transliterated from English BIT. And the bit in the binary digit is also the measurement unit of the information quantity, which is the minimum unit of the information quantity.

In the prior art, in digital circuit simulation, for a boolean function:

f＝((a&b)|c)&d；

the input signal is a, b, c, d, and each time the input changes, for example a changes, the simulator calculates the value of a & b, assuming media 1, then calculates media 1|c to obtain media 2, then calculates the value of media 2& d to obtain the output result f.

The prior art approach is the priority and binding rate of operations. When a large amount of logic is calculated through simulation, a large amount of Boolean functions are required to be called for calculation, the consumed time is relatively large, and the simulation result needs to be obtained for a long time.

Fig. 1 is a flow chart illustrating a method of simulating a digital circuit according to an exemplary embodiment. The simulation method 10 of the digital circuit at least comprises steps S102 to S108.

As shown in fig. 1, in S102, an index table of a digital circuit to be simulated is acquired. An index table may be created in advance based on the binary representation of the input signal and the values of its corresponding output signal, the contents of which are described in the corresponding embodiment of fig. 2.

The index table may be stored in a predetermined location or may be stored inside the digital circuit related data to be emulated as circuit information of the digital circuit.

In S104, signal values of a plurality of input signals to be simulated are acquired. For example, if the input signal is a, b, c, d, the signal value corresponding to the input signal a, b, c, d in this simulation is obtained, and in general, there are four possibilities of the signal value of the input variable of the digital circuit, i.e., low level or low voltage (generally indicated by 0 in the digital circuit), high level or high voltage (generally indicated by 1 in the digital circuit), and x and z.

In S106, the plurality of input signals are input to ports corresponding to the digital circuits.

In S108, a simulation output result of the digital circuit is obtained through the plurality of input signals and the index table. An identifier can be allocated to each input signal according to the signal value of the input signal; arranging the plurality of input signals according to a preset sequence; and extracting simulation output results of the digital circuit from the index table according to the identifiers corresponding to the plurality of input signals based on the arrangement.

In a specific embodiment, the signal value of the input signal a is high, the signal value of b is low, the signal value of c is low, and the signal value of d is low, and the flag corresponding to a, b, c, d may be arranged to be "1000", for example. The value of the input result f may be extracted from the index table according to 1000.

Details of the "simulation output result of the digital circuit obtained by the plurality of input signals and the index table" will be described in the corresponding embodiments of fig. 3 and 4.

According to the simulation method of the digital circuit, an index table of the digital circuit to be simulated is obtained; acquiring signal values of a plurality of input signals to be simulated; inputting the plurality of input signals to ports corresponding to the digital circuits; the simulation output result of the digital circuit is obtained through the plurality of input signals and the index table, so that the Boolean function evaluation speed in the digital circuit calculation process can be improved, the digital circuit simulation time is reduced, the overall operation efficiency is improved, and the system resource is solved.

It should be clearly understood that this application describes how to make and use particular examples, but the principles of this application are not limited to any details of these examples. Rather, these principles can be applied to many other embodiments based on the teachings of the present disclosure.

Fig. 2 is a flow chart illustrating a method of simulating a digital circuit according to an exemplary embodiment. The simulation method 20 of the digital circuit may further include steps S202 to S210.

As shown in fig. 2, in S202, circuit information of a digital circuit to be simulated is acquired. The expression of the digital circuit is generally expressed by a hardware description language, and the circuit information of the digital circuit can comprise a logic circuit diagram and a logic expression.

In S204, a boolean function corresponding to the digital circuit is extracted based on the circuit information. The EDA can read in circuit information when simulating a circuit, and the Boolean function to be simulated can be obtained in the circuit information, and the mapping relation between the input and the output of each Boolean function is not changed in the simulation, so that the truth table of the Boolean function can be obtained before the simulation.

In one example, the Boolean function corresponding to a digital circuit is as follows:

f＝((a&b)|c)&d。

in S206, a truth table for the boolean function is generated by a basic logic gate truth table. Logic relationships in the boolean function may be compared to logic values in the basic logic gate truth table to calculate a truth table for generating the boolean function, the truth table including numerical relationships between a plurality of input signals and their output signals in the boolean function.

The truth table of the basic logic gate is derived from IEEE Standard forHardware Description Language, the truth table corresponding to the boolean function can be generated by the truth table of the basic logic gates. The truth table for the basic logic gate may be as shown in fig. 3.

A boolean function, once its form is determined, its truth table is fixed and its fields and values are limited, neither large for logical operations, so it is not possible to map the mapping between fields and values at simulation time before the start of the simulation, without removing the repeated computational mapping logic at simulation time. That is, the simulator sees a set of inputs and knows their corresponding outputs, rather than computing the values of those inputs, thereby speeding up.

In S208, the signal values of the plurality of input signals in the truth table are represented in binary. The binary conversion rule can be determined according to the value range of the signal value of each input signal; and distributing binary identification to each input signal according to the binary conversion rule.

For example, if the values of x and z are not considered for the boolean function above, the boolean function: the truth table of f= ((a & b) |c) & d can be shown in fig. 4.

Each input occupies one bit, and if considered as one bit in a binary number, the table may also be represented as a binary number. Therefore, the output value of the Boolean function corresponds to a binary number, a binary number can be saved in simulation, the bit corresponding to the value is updated every time a variable is changed, then the function value corresponding to the new binary number is searched to obtain the output value corresponding to the Boolean function, the function is calculated and converted into a bit operation, and the value of the position corresponding to the array is searched once. The operation speed is improved.

In S210, the index table is built based on the binary representations of the plurality of input signals and the values of their corresponding output signals. A decimal sequence number corresponding to each input signal may be generated based on the binary representation of the signal; and establishing the index table according to the corresponding relation between the decimal serial number and the numerical value of the output signal. The index table established by the method in the present application may be as shown in fig. 5.

In one embodiment, there are four possibilities for logically operating on a variable, 0,1, x, z, respectively. For simplicity, only the case where one variable is 0 or 1 (low level, high level) will be discussed first. I.e. either a low level 0 or a high level 1 for one input variable. So that it is just one bit in the binary system, the four inputs can represent a four-bit binary system, and conversely, the four-bit binary system can represent a combination of four inputs, the binary system and the decimal system are different in form and same in size, as shown in fig. 4 and 5, the column of the decimal system representation of the binary system is shown, and a decimal number represents an input combination of abcd four input signals.

If x and z are considered. The truth table for the boolean function can also be obtained by the above truth table for the basic gate circuit, except that two binary bits are needed to represent one input, and all inputs can be represented in the same way by one binary number (which can be, for example, an integer character), and simulation can be performed in the same way.

In a specific embodiment, the input signal may comprise four possibilities of 0,1, x, z, in which case a two-bit binary number may be used to represent an input, e.g. 00 for a signal value of the input signal to a low level, 01 for a signal value of the input signal to a high level, 11 for a signal value of the input signal to x, and 10 for a signal value of the input signal to z. At this time, since there are four possibilities for each variable, four variables are 4 times as many as possible, i.e., 256. I.e. the array in the truth table has 256 elements. In this case, the binary number of the four-bit input can still be represented in the form of a 32-bit integer, and the corresponding value can be obtained from the array of output values.

In another embodiment, a 32-bit v may also be used to store the values of the four input variables, e.g., a first bit to hold d, a second bit to hold c, a third bit to hold b, and a fourth bit to hold a.

Initially all inputs are 0, v is 0, and if c becomes 1 and c is the second bit, v=2' b 0010=2.

The output values can be placed in the array {0,0,0,1,0,0,0,1,0,0,0,1,0,1,0,1} according to the corresponding relation;

at this time, for 2, it is sufficient to directly obtain the second value in the array, which is the output. If all inputs are 1, then the combination of inputs can be denoted by 15 and it is sufficient to find the index in the array to be a value of 15.

Fig. 6 is a flow chart illustrating a method of simulating a digital circuit according to another exemplary embodiment. The process 60 shown in fig. 6 is a detailed description of S108 "the simulation output result of the digital circuit is obtained through the plurality of input signals and the index table" in the process shown in fig. 1.

As shown in fig. 6, in S602, an identification is assigned to each input signal according to its signal value. The signal values may be mapped to conversion rules to assign a binary identification to each input signal.

For example, the input signal is a, b, c, d, and in this simulation, there are two possible signal values corresponding to the input signal a, b, c, d, i.e., a low level corresponds to 0 and a high level corresponds to 1.

More specifically, the signal value of the input signal a is high level; the signal value of the input signal b is high level; the signal value of the input signal c is high level; the signal value of the input signal d is high.

The binary of the input signal a is denoted as 1; the binary of the input signal b is denoted as 1; the binary of the input signal c is denoted as 1; the binary of the input signal d is denoted 1.

In S604, the plurality of input signals are arranged in a preset order. The input signals a, b, c, d can be arranged in the order of the input signals abcd.

In S606, a simulation output result of the digital circuit is extracted from the index table according to the identifications corresponding to the plurality of input signals based on the arrangement. The arrangement of the input signals a, b, c, d can be as follows: 1111.

the plurality of signals may be represented with their corresponding identities, respectively, based on the arrangement to generate a binary sequence; calculating a decimal serial number corresponding to the binary sequence; extracting a numerical value of an output signal of the digital circuit from the index table based on the decimal sequence number; and generating a simulation output result through the numerical value of the output signal. The decimal number corresponding to the binary data 1111 is denoted by 15, and the output value 1 corresponding to the decimal number 15 can be obtained by looking up the index table shown in fig. 5.

The method for obtaining the output value by the difference can replace the method for determining the output by judging the input values one by one, and the user can know what the output is by only using a group of identifiers corresponding to the input information numbers.

Those skilled in the art will appreciate that all or part of the steps implementing the above described embodiments are implemented as a computer program executed by a CPU. When executed by a CPU, performs the functions defined by the above methods provided herein. The program may be stored in a computer readable storage medium, which may be a read-only memory, a magnetic disk or an optical disk, etc.

Furthermore, it should be noted that the above-described figures are merely illustrative of the processes involved in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It will be readily appreciated that the processes shown in the above figures do not indicate or limit the temporal order of these processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, for example, among a plurality of modules.

The following are device embodiments of the present application, which may be used to perform method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

Fig. 7 is a block diagram illustrating an emulation device of a digital circuit according to an exemplary embodiment. As shown in fig. 7, the simulation apparatus 70 of the digital circuit includes: the acquisition module 702, the signal module 704, the input module 706, the search module 708, and the simulation apparatus 70 for digital circuits may further include: a module 710 is established.

The acquisition module 702 is configured to acquire an index table of a digital circuit to be simulated;

the signal module 704 is configured to obtain signal values of a plurality of input signals to be simulated;

an input module 706 is configured to input the plurality of input signals to corresponding ports of the digital circuit;

the look-up module 708 is configured to obtain a simulation output result of the digital circuit through the plurality of input signals and the index table. The search module 708 is further configured to assign an identifier to each input signal according to a signal value of the input signal; arranging the plurality of input signals according to a preset sequence; and extracting simulation output results of the digital circuit from the index table according to the identifiers corresponding to the plurality of input signals based on the arrangement.

The building module 710 is configured to obtain circuit information of a digital circuit to be simulated; extracting a Boolean function corresponding to the digital circuit based on the circuit information; and establishing the index table based on the Boolean function.

According to the simulation device of the digital circuit, an index table of the digital circuit to be simulated is obtained; acquiring signal values of a plurality of input signals to be simulated; inputting the plurality of input signals to ports corresponding to the digital circuits; the simulation output result of the digital circuit is obtained through the plurality of input signals and the index table, so that the Boolean function evaluation speed in the digital circuit calculation process can be improved, the digital circuit simulation time is reduced, the overall operation efficiency is improved, and the system resource is solved.

An electronic device 800 according to this embodiment of the present application is described below with reference to fig. 8. The electronic device 800 shown in fig. 8 is merely an example and should not be construed as limiting the functionality and scope of use of embodiments of the present application.

As shown in fig. 8, the electronic device 800 is embodied in the form of a general purpose computing device. Components of electronic device 800 may include, but are not limited to: at least one processing unit 810, at least one memory unit 820, a bus 830 that connects the different system components (including memory unit 820 and processing unit 810), a display unit 840, and the like.

Wherein the storage unit stores program code that is executable by the processing unit 810 such that the processing unit 810 performs steps described in the present specification according to various exemplary embodiments of the present application. For example, the processing unit 810 may perform the steps as shown in fig. 1, fig. 2, and fig. 6.

The storage unit 820 may include a readable medium in the form of a volatile memory unit, such as a random access memory unit (RAM) 8201 and/or a cache memory unit 8202, and may further include a read only memory unit (ROM) 8203.

The storage unit 820 may also include a program/utility 8204 having a set (at least one) of program modules 8205, such program modules 8205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

Bus 830 may be one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 800 may also communicate with one or more external devices 800' (e.g., keyboard, pointing device, bluetooth device, etc.), devices that enable a user to interact with the electronic device 800, and/or any devices (e.g., routers, modems, etc.) that the electronic device 800 can communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 850. Also, electronic device 800 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet, through network adapter 860. Network adapter 860 may communicate with other modules of electronic device 800 via bus 830. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 800, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, as shown in fig. 9, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and includes several instructions to cause a computing device (may be a personal computer, a server, or a network device, etc.) to perform the above-described method according to the embodiments of the present application.

The software product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable storage medium may also be any readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

The computer-readable medium carries one or more programs, which when executed by one of the devices, cause the computer-readable medium to perform the functions of: acquiring an index table of a digital circuit to be simulated; acquiring signal values of a plurality of input signals to be simulated; inputting the plurality of input signals to ports corresponding to the digital circuits; and obtaining simulation output results of the digital circuit through the plurality of input signals and the index table.

Those skilled in the art will appreciate that the modules may be distributed throughout several devices as described in the embodiments, and that corresponding variations may be implemented in one or more devices that are unique to the embodiments. The modules of the above embodiments may be combined into one module, or may be further split into a plurality of sub-modules.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or in combination with the necessary hardware. Thus, the technical solutions according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, and include several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the methods according to the embodiments of the present application.

Exemplary embodiments of the present application are specifically illustrated and described above. It is to be understood that this application is not limited to the details of construction, arrangement or method of implementation described herein; on the contrary, the application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method of simulating a digital circuit, comprising:

acquiring an index table of a digital circuit to be simulated;

acquiring signal values of a plurality of input signals to be simulated;

inputting the plurality of input signals to ports corresponding to the digital circuits;

and obtaining simulation output results of the digital circuit through the plurality of input signals and the index table.

2. The simulation method of claim 1, further comprising:

acquiring circuit information of a digital circuit to be simulated;

extracting a Boolean function corresponding to the digital circuit based on the circuit information;

and establishing the index table based on the Boolean function.

3. The simulation method of claim 2, wherein building the index table based on the boolean function comprises:

generating a truth table of the Boolean function through a truth table of a basic logic gate;

representing signal values of a plurality of input signals in the truth table in binary;

the index table is built based on binary representations of the plurality of input signals and the values of their corresponding output signals.

4. A simulation method according to claim 3, wherein generating a truth table for the boolean function from a basic logic gate truth table comprises:

and comparing the logic relation in the Boolean function with the logic numerical value in the truth table of the basic logic gate to calculate and generate the truth table of the Boolean function, wherein the truth table comprises numerical relation between a plurality of input signals and output signals of the Boolean function.

5. A simulation method according to claim 3, wherein representing the signal values of the plurality of input signals in the truth table in binary comprises:

determining a binary conversion rule according to the value range of the signal value of each input signal;

and distributing binary identification to each input signal according to the binary conversion rule.

6. A simulation method according to claim 3, wherein building the index table based on the binary representations of the plurality of input signals and the values of their corresponding output signals comprises:

generating a decimal sequence number corresponding to each input signal based on a binary representation of the signal;

and establishing the index table according to the corresponding relation between the decimal serial number and the numerical value of the output signal.

7. The simulation method of claim 1, wherein obtaining the simulation output result of the digital circuit through the plurality of input signals and the index table comprises:

allocating an identifier to each input signal according to the signal value of the input signal;

arranging the plurality of input signals according to a preset sequence;

and extracting simulation output results of the digital circuit from the index table according to the identifiers corresponding to the plurality of input signals based on the arrangement.

8. The simulation method according to claim 7, wherein assigning an identification to each input signal based on its signal value comprises:

the signal values are mapped to conversion rules to assign a binary identification to each input signal.

9. The simulation method of claim 7, wherein extracting the simulation output result of the digital circuit in the index table according to the identifications corresponding to the plurality of input signals based on the arrangement comprises:

representing the plurality of signals with their corresponding identities, respectively, based on the arrangement to generate a binary sequence;

calculating a decimal serial number corresponding to the binary sequence;

extracting a numerical value of an output signal of the digital circuit from the index table based on the decimal sequence number;

and generating a simulation output result through the numerical value of the output signal.

10. A fast simulation apparatus for a digital circuit, comprising:

the acquisition module is used for acquiring an index table of the digital circuit to be simulated;

the signal module is used for acquiring signal values of a plurality of input signals to be simulated;

an input module for inputting the plurality of input signals to corresponding ports of the digital circuit;

and the searching module is used for obtaining the simulation output result of the digital circuit through the plurality of input signals and the index table.