CN117423725A - High-voltage transverse GaN high-electron mobility transistor - Google Patents

High-voltage transverse GaN high-electron mobility transistor Download PDF

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Publication number
CN117423725A
CN117423725A CN202311636393.0A CN202311636393A CN117423725A CN 117423725 A CN117423725 A CN 117423725A CN 202311636393 A CN202311636393 A CN 202311636393A CN 117423725 A CN117423725 A CN 117423725A
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layer
electric field
algan barrier
barrier layer
electrode
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邓华鲜
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Leshan Jiayang Technology Development Co ltd
LESHAN SHARE ELECTRONIC CO Ltd
Jiangsu Hill Semiconductor Co ltd
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Leshan Jiayang Technology Development Co ltd
LESHAN SHARE ELECTRONIC CO Ltd
Jiangsu Hill Semiconductor Co ltd
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Priority to CN202311636393.0A priority Critical patent/CN117423725A/en
Publication of CN117423725A publication Critical patent/CN117423725A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

The invention discloses a high-voltage transverse GaN high-electron mobility transistor which comprises a substrate layer, a GaN buffer layer, an unintentionally doped GaN channel layer, an AlGaN barrier layer, an electric field optimization auxiliary layer and an insulating medium layer which are sequentially arranged from bottom to top, wherein the left side and the right side of the AlGaN barrier layer are respectively provided with a source electrode and a drain electrode, the source electrode and the drain electrode are in ohmic contact with the AlGaN barrier layer, a groove is etched on the AlGaN barrier layer, and a grid electrode is arranged in the groove through an insulating gate medium. According to the invention, the gate-drain electric field, the transverse electric field distribution and the dynamic resistance degradation phenomenon of the HEMT device are optimized, the breakdown characteristic of the HEMT device is improved, the current collapse effect of the HEMT device is improved, and the high-voltage HEMT device can be realized on the premise of not sacrificing the specific on-resistance, so that the purpose of being applied to a high-voltage high-current scene is achieved.

Description

High-voltage transverse GaN high-electron mobility transistor
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a high-voltage transverse GaN high-electron mobility transistor.
Background
The performance of the traditional silicon-based semiconductor power device reaches the physical limit of silicon, the high-end application scene cannot be met, and the third-generation semiconductor power device represented by gallium nitride GaN has larger forbidden band width, larger critical breakdown electric field and better heat conductivity compared with Si, and meanwhile, the low on-resistance and high breakdown voltage are realized, so that the silicon-based semiconductor power device becomes a hotspot of the industry and the future development direction.
At present, a High Electron Mobility Transistor (HEMT) formed by AlGaN and GaN materials can form free electrons (2 DEG) with high mobility density at a heterojunction interface through polarization effect, and the free electrons have higher electron concentration, higher electron mobility and higher electron saturation velocity, so that the free electrons are suitable for high-frequency and high-power scene applications. However, the GaN high electron mobility transistor has a 2DEG even under zero gate voltage, i.e. the threshold voltage of the device is negative, which makes the design of the gate driving circuit of the HEMT device complex and costly. Meanwhile, because the HEMT device is internally provided with no PN junction structure, electric fields are concentrated at the edge of the gate, and the breakdown voltage intensity of the device depends on the interval between gate and drain, the breakdown voltage of the HEMT device is greatly limited, so that the HEMT device is often applied to the scene below 650V.
In addition, patent document with publication number of CN114725214A discloses a multilayer passivation groove gate MIS-HEMT device and a preparation method thereof, wherein the device comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer from bottom to top in sequence; the left side and the right side of the barrier layer are respectively provided with a source electrode and a drain electrode; a groove gate region is arranged in the middle of the barrier layer and close to one side of the source electrode, and a plurality of passivation layers are arranged on the groove gate region; the multi-layer passivation layer comprises a first passivation layer, a transition layer, a mask layer and a second passivation layer; the first passivation layer selectively grows at the bottom of the groove gate region of the barrier layer and is contacted with the upper surface of the channel layer; the transition layer is positioned on the upper surface of the first passivation layer; the mask layer is positioned on the barrier layers at two sides of the groove gate region; the second passivation layer is located on the transition layer and extends upward to the upper surface of the mask layer. According to the technology, the multilayer passivation structure is combined with the selective growth technology, so that the passivation layer is effectively, accurately and controllably deposited in the gate region, the defect problem of a medium interface is solved, and the device performance is improved. However, the patent only uses the gate-drain spacing to withstand voltage, and when the device is in a voltage-resistant state, an electric field peak value can appear when the bottom of the gate is close to the drain test, so that the device breaks down in advance. In order to increase the breakdown voltage of the device, the gate-drain spacing has to be increased, but this in turn sacrifices the specific on-resistance. Even though this patent compromises breakdown voltage and specific on-resistance, it is still difficult to achieve high voltage high current devices.
Disclosure of Invention
The invention aims to overcome the problems in the prior art and provide a high-voltage transverse GaN high-electron mobility transistor, which optimizes the gate-drain electric field, transverse electric field distribution and dynamic resistance degradation phenomena of an HEMT device, improves the breakdown characteristic of the HEMT device, improves the current collapse effect of the HEMT device, and can realize the high-voltage HEMT device without sacrificing specific on-resistance so as to achieve the purpose of being applied to high-voltage high-current scenes.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a high voltage lateral GaN high electron mobility transistor characterized by: comprises a substrate layer, a GaN buffer layer, an unintentionally doped GaN channel layer, an AlGaN barrier layer, an electric field optimization auxiliary layer and an insulating medium layer which are sequentially arranged from bottom to top, wherein the left side and the right side of the AlGaN barrier layer are respectively provided with a source electrode and a drain electrode, the source electrode and the drain electrode form ohmic contact with the AlGaN barrier layer, a groove is etched on the AlGaN barrier layer near the source electrode, and a grid electrode is arranged in the groove through an insulated gate medium.
The electric field optimization auxiliary layer is a SIPOS material layer or a High-k material layer.
When the electric field optimization auxiliary layer is a SIPOS material layer, a passivation layer covering the AlGaN barrier layer is arranged between the SIPOS material layer and the AlGaN barrier layer.
The trench is etched down from the passivation layer to the AlGaN barrier layer.
The grid electrode is wrapped in an insulated gate medium, the electric field optimization auxiliary layer and the insulated medium layer are both connected between the source electrode and the drain electrode, and the insulated gate medium is located between the electric field optimization auxiliary layer and the groove.
The grid electrode is positioned above the insulated gate dielectric, and the electric field optimization auxiliary layer and the insulated dielectric layer are both connected between the grid electrode and the drain electrode.
The upper end of the left side of the insulated gate dielectric extends horizontally to the left to the source electrode and covers the AlGaN barrier layer.
The upper portion of the gate extends horizontally to the right and partially covers the insulating dielectric layer.
The upper portion of the drain electrode extends horizontally leftwards and is partially covered with an insulating dielectric layer.
The invention has the advantages that:
1. the High-voltage transverse GaN High-electron mobility transistor adopts a recessed gate MIS structure, and a semi-insulating polycrystalline silicon SIPOS material layer/High-k material layer is introduced as an electric field optimization auxiliary layer. Therefore, the gate-drain electric field and the transverse electric field distribution of the HEMT device are optimized, the breakdown characteristic of the HEMT device is improved, the current collapse effect of the HEMT device is improved, the dynamic resistance degradation phenomenon is optimized, the production cost is reduced, the breakdown voltage can be greatly improved (particularly to 650-1400V) on the premise of not sacrificing the specific on-resistance, and the purpose of being applied to a high-voltage high-current scene is achieved. The invention fills the blank of the High-voltage GaN HEMT device, creatively combines the groove gate MIS structure with the SIPOS/High-k structure, greatly improves the forward conduction characteristic and the reverse voltage withstand characteristic of the HEMT device, and has more excellent product performance and reliability compared with the existing product.
2. When the electric field optimization auxiliary layer is the SIPOS material layer, the passivation layer which covers the AlGaN barrier layer is arranged between the SIPOS material layer and the AlGaN barrier layer, and the passivation layer is beneficial to playing roles of protecting an interface and buffering.
3. The invention horizontally extends the upper end of the left side of the insulated gate dielectric to the left to the source electrode and covers the AlGaN barrier layer, which is beneficial to effectively protecting the interface of the device.
4. According to the invention, the upper part of the grid electrode is horizontally extended to the right and is partially covered by the insulating dielectric layer or the upper part of the drain electrode is horizontally extended to the left and is partially covered by the insulating dielectric layer, and the metal field plate can be realized through extension, so that the surface electric field can be relieved.
Drawings
Fig. 1 is a schematic structural view of embodiment 1;
fig. 2 is a schematic structural view of embodiment 2;
fig. 3 is a schematic structural view of embodiment 3;
fig. 4 is a schematic structural view of embodiment 4;
fig. 5 is a schematic structural view of embodiment 5;
fig. 6 is a graph showing the results of the forward conduction simulation test in example 1;
fig. 7 is a graph showing the breakdown voltage test result of example 1;
fig. 8 is a graph showing the results of the forward conduction simulation test in example 2;
fig. 9 is a graph showing the breakdown voltage test result of example 2;
fig. 10 is a graph showing the results of the forward conduction simulation test in example 3;
fig. 11 is a graph showing the breakdown voltage test result of example 3.
The drawing is marked as follows: 1-1 parts of substrate layers, 1-2 parts of GaN buffer layers, 1-3 parts of unintentionally doped GaN channel layers, 1-4 parts of AlGaN barrier layers, 1-5 parts of source electrodes, 1-6 parts of insulated gate dielectrics, 1-7 parts of grid electrodes, 1-8 parts of insulated dielectric layers, 1-9 parts of SIPOS material layers, 1-10 parts of passivation layers, 1-11 parts of drain electrodes, 1-12 parts of High-k material layers.
Detailed Description
Example 1
The present embodiment provides a high-voltage lateral GaN high electron mobility transistor, which comprises a substrate layer 1-1, a GaN buffer layer 1-2, an unintentionally doped GaN channel layer 1-3, an AlGaN barrier layer 1-4, an electric field optimization auxiliary layer, an insulating medium layer 1-8, an insulating gate medium 1-6, a gate electrode 1-7, a source electrode 1-5 and a drain electrode 1-11, as shown in FIG. 1. The substrate layer 1-1 is a Si substrate or a sapphire substrate, the substrate layer 1-1, the GaN buffer layer 1-2, the unintentionally doped GaN channel layer 1-3, the AlGaN barrier layer 1-4, the electric field optimization auxiliary layer and the insulating medium layer 1-8 are sequentially arranged from bottom to top, the source electrode 1-5 and the drain electrode 1-11 are respectively arranged on the left side and the right side of the AlGaN barrier layer 1-4, and the source electrode 1-5 and the drain electrode 1-11 are in ohmic contact with the AlGaN barrier layer 1-4. The AlGaN barrier layer 1-4 is etched with a groove near the source 1-5 (with the middle part left), the insulated gate dielectric 1-6 is arranged in the groove and covers the bottom wall and the side wall of the groove, and the upper end of the left side of the insulated gate dielectric 1-6 also horizontally extends to the left to the source 1-5 and covers the AlGaN barrier layer 1-4. The grid electrode 1-7 is arranged in the groove through the insulated gate dielectric 1-6 and is positioned above the insulated gate dielectric 1-6, the electric field optimization auxiliary layer and the insulated dielectric layer 1-8 are arranged between the grid electrode 1-7 and the drain electrode 1-11, and two ends of the electric field optimization auxiliary layer and two ends of the insulated dielectric layer 1-8 are connected with the grid electrode 1-7 and the drain electrode 1-11.
In this embodiment, the electric field optimization auxiliary layer is preferably a SIPOS material layer 1-9, and when the electric field optimization auxiliary layer is the SIPOS material layer 1-9, in order to play a role of protecting interface and buffering, a passivation layer 1-10 covering the AlGaN barrier layer 1-4 is further disposed between the SIPOS material layer 1-9 and the AlGaN barrier layer 1-4.
When the passivation layer 1-10 is disposed between the SIPOS material layer 1-9 and the AlGaN barrier layer 1-4, the trench is etched from the passivation layer 1-10 down to the AlGaN barrier layer 1-4. In addition, the passivation layer 1-10 is disposed directly above the AlGaN barrier layer 1-4, but the passivation layer 1-10 between the gate electrode 1-7 and the source electrode 1-5 is located below the insulated gate dielectric 1-6 due to the trench isolation.
The working principle of this embodiment is as follows:
in the embodiment, 2DEG conduction is formed through polarization effect, an electron channel from a source electrode 1-5 to a drain electrode 1-11 is formed, a resistance field plate is formed by a SIPOS material layer 1-9 between a grid electrode and a drain electrode, a surface uniform electric field is formed, the electric field distribution of a GaN region between the grid electrode 1-7 and the drain electrode 1-11 is optimized, the breakdown characteristic of the device is further improved, and meanwhile the reliability of the device is improved. The AlGaN barrier layer 1-4 below the grid electrode 1-7 is thinned through the groove, the 2DEG concentration below the grid electrode 1-7 is exhausted, the positive threshold voltage is realized, and the reverse conduction loss is reduced. And the high-concentration 2DEG concentration is ensured by the structure that the rest parts of the AlGaN barrier layers 1-4 are still thicker, so that larger saturation current is obtained. In addition, the MIS trench gate structure can also realize the adjustment of threshold voltage by controlling the etching depth of the trench. When the potential difference between the grid electrode 1-7 and the source electrode 1-5 is smaller than the threshold voltage of the device, the 2DEG below the grid electrode 1-7 is exhausted, the current path is turned off, the device is in a blocking state, and under the blocking voltage of the drain electrode 1-11, SIPOS material layers 1-9 on two sides are connected with the grid electrode 1-7 and the metal drain electrode 1-11, so that a resistance field plate is realized, and a uniform transverse distribution electric field is introduced. In addition, the passivation layer 1-10 deposited by LPCVD is arranged below the SIPOS material layer 1-9 to play a role in protecting an interface and buffering, and the insulating medium layer 1-8 above the SIPOS material layer 1-9 plays a role in protecting a SIPOS film.
The applicant conducted simulation tests on the present example, and FIGS. 6 and 7 respectively simulate the forward conduction curve and the voltage breakdown characteristic curve of the product, and as can be seen from FIGS. 6 and 7, the specific on-resistance is 0.7mΩ cm 2 The breakdown voltage can reach 1440V. In contrast, the present embodiment can greatly improve the breakdown characteristics of the product without sacrificing the specific on-resistance.
Example 2
The present embodiment provides a high-voltage lateral GaN high electron mobility transistor, which includes a substrate layer 1-1, a GaN buffer layer 1-2, an unintentionally doped GaN channel layer 1-3, an AlGaN barrier layer 1-4, an electric field optimization auxiliary layer, an insulating dielectric layer 1-8, an insulating gate dielectric 1-6, a gate electrode 1-7, a source electrode 1-5, and a drain electrode 1-11, as shown in FIG. 2. The substrate layer 1-1 is a Si substrate or a sapphire substrate, the substrate layer 1-1, the GaN buffer layer 1-2, the unintentionally doped GaN channel layer 1-3, the AlGaN barrier layer 1-4, the electric field optimization auxiliary layer and the insulating medium layer 1-8 are sequentially arranged from bottom to top, the source electrode 1-5 and the drain electrode 1-11 are respectively arranged on the left side and the right side of the AlGaN barrier layer 1-4, and the source electrode 1-5 and the drain electrode 1-11 are in ohmic contact with the AlGaN barrier layer 1-4. The AlGaN barrier layer 1-4 is etched with a groove near the source 1-5 (with the middle part left), the insulated gate dielectric 1-6 is arranged in the groove and covers the bottom wall and the side wall of the groove, and the upper end of the left side of the insulated gate dielectric 1-6 also horizontally extends to the left to the source 1-5 and covers the AlGaN barrier layer 1-4. The grid electrode 1-7 is arranged in the groove through the insulated gate dielectric 1-6 and is positioned above the insulated gate dielectric 1-6, and the electric field optimization auxiliary layer and the insulated dielectric layer 1-8 are arranged between the grid electrode 1-7 and the drain electrode 1-11. Preferably, the electric field optimization auxiliary layer is a high.k material layer 1-12, and two ends of the high.k material layer 1-12 and two ends of the insulating medium layer 1-8 are connected with the grid electrode 1-7 and the drain electrode 1-11.
The working principle of this embodiment is as follows:
in the embodiment, 2DEG conduction is formed through polarization effect, an electron channel from a source electrode 1-5 to a drain electrode 1-11 is formed on the surface of an unintentionally doped GaN channel layer 1-3, and a high.k material layer 1-12 between the gate and the drain depletes the 2DEG in the GaN channel layer, so that the breakdown characteristic of the device is optimized, and meanwhile, the reliability of the device is improved. The AlGaN barrier layer 1-4 below the grid electrode 1-7 is thinned through the groove, the concentration of the 2DEG below the grid electrode 1-7 is depleted, positive threshold voltage is realized, reverse conduction loss is reduced, and the rest part is still of a thick barrier layer structure to ensure the concentration of the 2DEG with high concentration, so that larger saturation current is obtained. In addition, the MIS trench gate structure device can also realize the adjustment of threshold voltage by controlling the etching depth of the trench. When the potential difference between the grid electrode 1-7 and the source electrode 1-5 is smaller than the threshold voltage of the device, the 2DEG below the grid electrode 1-7 is exhausted, the current path is turned off, the device is in a blocking state, after the peak reaches a critical breakdown electric field, the device breaks down in advance, after the electric field 2DEG at the tail end of the grid electrode 1-7 is exhausted, the electric field lines emitted by the left fixed polarization positive charges are concentrated to the tail end of the grid electrode 1-7, and the introduction of the high.k material layer 1-12 optimizes the surface electric field, can attract the electric field lines emitted by the fixed polarization positive charges, and relieves the curvature effect at the edge of the grid electrode 1-7.
The applicant conducted simulation test on the present example, and figures 8 and 9 respectively simulate the forward conduction curve and the voltage breakdown characteristic curve of the product, and as can be seen from figures 8 and 9, the specific on-resistance is 0.58mΩ cm 2 The breakdown voltage can reach 1200V. In contrast, the present embodiment can greatly improve the breakdown characteristics of the product without sacrificing the specific on-resistance.
Example 3
The present embodiment provides a high-voltage lateral GaN high electron mobility transistor, which includes a substrate layer 1-1, a GaN buffer layer 1-2, an unintentionally doped GaN channel layer 1-3, an AlGaN barrier layer 1-4, an electric field optimization auxiliary layer, an insulating dielectric layer 1-8, an insulating gate dielectric 1-6, a gate electrode 1-7, a source electrode 1-5, and a drain electrode 1-11, as shown in FIG. 3. The substrate layer 1-1 is a Si substrate or a sapphire substrate, the substrate layer 1-1, the GaN buffer layer 1-2, the unintentionally doped GaN channel layer 1-3, the AlGaN barrier layer 1-4, the electric field optimization auxiliary layer and the insulating medium layer 1-8 are sequentially arranged from bottom to top, the source electrode 1-5 and the drain electrode 1-11 are respectively arranged on the left side and the right side of the AlGaN barrier layer 1-4, and the source electrode 1-5 and the drain electrode 1-11 are in ohmic contact with the AlGaN barrier layer 1-4. A groove is etched on the AlGaN barrier layer 1-4 near the source electrode 1-5 (the middle part is far left), the grid electrode 1-7 is wrapped in the insulated gate medium 1-6, and the insulated gate medium 1-6 is arranged in the groove. The electric field optimization auxiliary layer and the insulating medium layer 1-8 are connected between the source electrode 1-5 and the drain electrode 1-11, and the insulating gate medium 1-6 and the gate electrode 1-7 are positioned between the electric field optimization auxiliary layer and the groove. Preferably, the electric field optimization auxiliary layer is a high.k material layer 1-12, and two ends of the high.k material layer 1-12 and two ends of the insulating medium layer 1-8 are connected with the source electrode 1-5 and the drain electrode 1-11.
The working principle of this embodiment is as follows:
in this embodiment, 2DEG conduction is formed by polarization effect, and electron channels from the source electrode 1-5 to the drain electrode 1-11 are formed on the surface of the unintentionally doped GaN channel layer 1-3. When blocking, as the bias voltage of the drain source increases, after the electric field 2DEG at the tail end of the grid electrode 1-7 is exhausted, the electric field lines emitted by the positive charges with fixed polarization left over are concentrated to the tail end of the grid electrode 1-7, so that the curvature of the electric lines is increased, and the high.k material layer 1-12 between the drain source exhausts the 2DEG in the unintentionally doped GaN channel layer 1-3, so that the curvature effect is optimized, the breakdown characteristic of the device is optimized, and meanwhile, the reliability of the device is improved. The structure reduces the thickness of the AlGaN barrier layer 1-4 below the grid electrode 1-7 through the groove, depletes the concentration of the 2DEG below the grid electrode 1-7, realizes positive threshold voltage, reduces reverse conduction loss, and ensures the concentration of the 2DEG with high concentration by adopting a thick barrier layer structure at the rest part, thereby obtaining larger saturation current. In addition, the MIS trench gate structure device realizes the adjustment of threshold voltage by controlling the etching depth of the trench. When the potential difference between the grid electrode 1-7 and the source electrode 1-5 is smaller than the threshold voltage of the device, the 2DEG below the grid electrode 1-7 is exhausted, the current path is turned off, the device is in a blocking state, the traditional HEMT device has no PN junction structure and cannot bear high avalanche resistance, after the peak reaches a critical breakdown electric field, the device breaks down in advance, and after the electric field 2DEG at the tail end of the grid electrode 1-7 is exhausted, electric field lines emitted by the left fixed polarization positive charges are concentrated to the tail end of the grid electrode 1-7 and the tail end of the drain electrode 1-11. The introduction of the high-k material layers 1-12 optimizes the surface electric field, attracts electric field lines emitted by positive charges of fixed polarization, and relieves curvature effects at the edges of the grid electrodes 1-7.
The applicant conducted simulation tests on the present example, and FIGS. 10 and 11 respectively simulate the forward conduction curve and the voltage breakdown characteristic curve of the product, and as can be seen from FIGS. 10 and 11, the specific on-resistance is 0.59mΩ cm 2 The breakdown voltage can reach 1280V. In contrast, the present embodiment can greatly improve the breakdown characteristics of the product without sacrificing the specific on-resistance.
Example 4
This embodiment provides further improvements in the structure of the gates 1-7 based on embodiments 1 or 2. As shown in fig. 4, in this embodiment, the upper portion of the gate electrode 1-7 extends horizontally rightward and partially covers the insulating dielectric layer 1-8, and the metal field plate structure can be implemented by this extending portion, so that the surface electric field can be relieved.
Example 5
This embodiment provides a further improvement in the structure of the gates 1-7 based on any of embodiments 1-3. Taking the HEMT device in embodiment 1 as an example, as shown in fig. 5, the upper portion of the drain electrode 1-11 extends horizontally to the left and partially covers the insulating dielectric layer 1-8. According to the embodiment, the metal field plate structure can be realized through the extension part, and then the surface electric field can be relieved.
While the invention has been described with reference to certain embodiments, it is understood that any feature disclosed in this specification may be replaced by alternative features serving the equivalent or similar purpose, unless expressly stated otherwise; all of the features disclosed, or all of the steps in a method or process, except for mutually exclusive features and/or steps, may be combined in any manner.

Claims (9)

1. A high voltage lateral GaN high electron mobility transistor characterized by: comprises a substrate layer (1-1), a GaN buffer layer (1-2), an unintentionally doped GaN channel layer (1-3), an AlGaN barrier layer (1-4), an electric field optimization auxiliary layer and an insulating medium layer (1-8) which are sequentially arranged from bottom to top, wherein the left side and the right side of the AlGaN barrier layer (1-4) are respectively provided with a source electrode (1-5) and a drain electrode (1-11), the source electrode (1-5) and the drain electrode (1-11) form ohmic contact with the AlGaN barrier layer (1-4), a groove is etched on the AlGaN barrier layer (1-4) close to the source electrode (1-5), and a grid electrode (1-7) is arranged in the groove through an insulated gate medium (1-6).
2. A high voltage lateral GaN high electron mobility transistor according to claim 1, characterized in that: the electric field optimization auxiliary layer is a SIPOS material layer (1-9) or a high. K material layer (1-12).
3. A high voltage lateral GaN high electron mobility transistor according to claim 2, characterized in that: when the electric field optimization auxiliary layer is a SIPOS material layer (1-9), a passivation layer (1-10) covering the AlGaN barrier layer (1-4) is arranged between the SIPOS material layer (1-9) and the AlGaN barrier layer (1-4).
4. A high voltage lateral GaN high electron mobility transistor according to claim 3, characterized by: the trench is etched down from the passivation layer (1-10) to the AlGaN barrier layer (1-4).
5. A high voltage lateral GaN high electron mobility transistor according to claim 2, characterized in that: the grid electrode (1-7) is wrapped in an insulated gate medium (1-6), the electric field optimization auxiliary layer and the insulated medium layer (1-8) are connected between the source electrode (1-5) and the drain electrode (1-11), and the insulated gate medium (1-6) is located between the electric field optimization auxiliary layer and the groove.
6. A high voltage lateral GaN high electron mobility transistor according to any of claims 1-4, characterized in that: the grid electrode (1-7) is positioned above the insulated gate dielectric (1-6), and the electric field optimization auxiliary layer and the insulated dielectric layer (1-8) are connected between the grid electrode (1-7) and the drain electrode (1-11).
7. The high voltage lateral GaN high electron mobility transistor of claim 6, wherein: the upper end of the left side of the insulated gate dielectric (1-6) horizontally extends to the left to the source (1-5) and covers the AlGaN barrier layer (1-4).
8. The high voltage lateral GaN high electron mobility transistor of claim 6, wherein: the upper part of the grid electrode (1-7) horizontally extends to the right and is partially covered by an insulating medium layer (1-8).
9. The high voltage lateral GaN high electron mobility transistor of claim 6, wherein: the upper part of the drain electrode (1-11) extends horizontally leftwards and is partially covered by an insulating dielectric layer (1-8).
CN202311636393.0A 2023-12-01 2023-12-01 High-voltage transverse GaN high-electron mobility transistor Pending CN117423725A (en)

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US20200006500A1 (en) * 2018-06-27 2020-01-02 Ohio State Innovation Foundation Dielectric Passivation for Electronic Devices
CN114883398A (en) * 2022-03-23 2022-08-09 深圳智芯微电子科技有限公司 Gallium nitride device and switching power supply product with same
CN115315814A (en) * 2020-04-09 2022-11-08 高通股份有限公司 Multi-gate High Electron Mobility Transistor (HEMT) with tuned recess depth gate for improved device linearity

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007048866A (en) * 2005-08-09 2007-02-22 Toshiba Corp Nitride semiconductor element
US20150155358A1 (en) * 2013-12-02 2015-06-04 International Rectifier Corporation Group III-V Transistor with Semiconductor Field Plate
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