CN115050813A - Manufacturing method of GaN HEMT device with gradient doped step fluorine ion terminal - Google Patents

Manufacturing method of GaN HEMT device with gradient doped step fluorine ion terminal Download PDF

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CN115050813A
CN115050813A CN202210829590.3A CN202210829590A CN115050813A CN 115050813 A CN115050813 A CN 115050813A CN 202210829590 A CN202210829590 A CN 202210829590A CN 115050813 A CN115050813 A CN 115050813A
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fluorine ion
passivation layer
manufacturing
doped
stepped
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魏杰
赵智家
邓思宇
杨可萌
郗路凡
孙涛
廖德尊
张�成
贾艳江
罗小蓉
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Junction Field-Effect Transistors (AREA)

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a manufacturing method of a GaN HEMT device with a gradient doped step fluorine ion terminal. In the manufacturing method, a photoetching process is adopted to form windows with the widths sequentially reduced, then the stepped grooves with the depths sequentially reduced are realized through one-time dry etching of the windows with the widths sequentially reduced, and finally one-time fluorine ion implantation is carried out to form the gradient doped stepped fluorine ion terminals. The terminal can better optimize a surface electric field and improve the withstand voltage of the device, and the manufacturing method forms a fluorine ion area under a grid and a gradient doped step fluorine ion terminal by one-time fluorine ion injection, simultaneously realizes enhancement and improves the withstand voltage of the device, and reduces the difficulty of the process. In addition, in the manufacturing method, fluorine ions are injected into the passivation layer instead of being directly injected into the AlGaN barrier layer, so that the influence on the mobility of two-dimensional electron gas can be reduced, the increase of dynamic resistance and the current collapse effect can be inhibited, and the forward conduction and the dynamic characteristics of the device can be improved.

Description

Manufacturing method of GaN HEMT device with gradient doped step fluorine ion terminal
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a manufacturing method of a GaN HEMT device with a gradient doped step fluorine ion terminal.
Background
The GaN HEMT (high electron mobility transistor) device has wide application prospect in the application field of high-current, low-power consumption, medium-low voltage switching devices, but the electric field intensively excites hot electrons under high field to cause grid failure or leakage current sharp increase, and the withstand voltage of the device is far from the theoretical limit. The current methods for improving the breakdown voltage of the device mainly comprise: the method comprises the following steps of field plate technology, fluorine ion implantation, terminal technology, polarized super junction technology, compensation doping technology and the like. In addition, it is difficult to obtain an enhanced high voltage device with a high threshold voltage due to the presence of a high density two-dimensional electron gas at the heterointerface. This not only increases the danger of circuit misopening, has also increased the design degree of difficulty of the consumption and the drive circuit of whole circuit. Typical ways to implement enhancements today include: groove gate technology, P-GaN technology, Cascode cascade technology, fluorine ion implantation technology, thin barrier technology and the like.
Disclosure of Invention
The invention provides a manufacturing method of a GaN HEMT device with a gradient doped step fluorine ion terminal based on the application requirement of the GaN HEMT device. The method comprises the steps of firstly adopting a photoetching process to form windows with the widths being sequentially reduced, then realizing stepped grooves with the depths being sequentially reduced through one-time etching of the windows with the widths being sequentially reduced, finally carrying out one-time fluorine ion injection to form gradient doped stepped fluorine ion terminals, realizing enhancement and optimization of a surface electric field, improving the withstand voltage of a device, and reducing the difficulty of the process.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a manufacturing method of a GaN HEMT device with a gradient doped step fluorine ion terminal is characterized by comprising the following steps:
step 1: preparing materials, wherein the materials comprise a substrate 1, a GaN buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 from bottom to top;
step 2: depositing a medium on the AlGaN barrier layer 4 to form a medium passivation layer 5;
and step 3: etching two ends of the medium passivation layer 5 by adopting an etching process, exposing a source electrode hole and a drain electrode hole at two ends of the AlGaN barrier layer 4, depositing a first conductive material, and forming a source electrode 6 and a drain electrode 12 by adopting an etching or stripping process;
and 4, step 4: etching the upper surface of the dielectric passivation layer 5 by adopting an etching process to form a gate groove 7, wherein the depth of the gate groove 7 is less than the thickness of the dielectric passivation layer 5;
and 5: coating photoresist 11 above the dielectric passivation layer 5, and forming a window region 9 by photoetching, wherein the window region 9 comprises a plurality of windows 90-9N which are narrowed in sequence along the direction from the source electrode to the drain electrode, the window closest to the source electrode is aligned with the gate groove 7 in the vertical direction, and the window closest to the drain electrode has a distance with the drain electrode;
step 6: etching the dielectric passivation layer 5 through the window region 9 by adopting a dry etching process to form a plurality of dielectric grooves 101-10N with the depth gradually becoming shallow along the direction from the source electrode to the drain electrode, wherein the dielectric passivation layer 5 is still reserved at the bottom of the deepest dielectric groove, and meanwhile, the gate groove 7 is further etched;
and 7: injecting fluorine ions into the medium passivation layer 5 through the window region 9 to form a plurality of fluorine ion injection regions, wherein the fluorine ion injection region positioned below the gate groove 7 penetrates through the medium passivation layer 5 and enters the AlGaN barrier layer 4, while other fluorine ion regions are only arranged in the medium passivation layer 5, and the medium groove and the fluorine ion injection region jointly form a gradient doped step fluorine ion terminal 8; removing the photoresist 11 and annealing;
and 8: a second conductive material is deposited and an etching or lift-off process is used to form the gate 13.
Preferably, the distances of the fluorine ion regions 81-8N in the gradient doped step fluorine ion terminal 8 in the transverse direction of the device are equal.
Preferably, the distances between the fluorine ion regions 81-8N in the graded doped step fluorine ion terminal 8 in the transverse direction of the device are different, and the distances increase in sequence along the direction from the source to the drain.
Preferably, the first conductive material is one or a combination of Ti, TiN, Al, Ni, and Au.
Preferably, the second conductive material is a combination of Ni and Au.
Preferably, the substrate 1 is made of one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO, and GaAs.
Preferably, the passivation layer 5 is made of SiN x 、SiO 2 、Al 2 O 3 And AlN.
The method has the advantages that the photoetching process is adopted to form windows with the widths being gradually reduced, then the stepped grooves with the depths being gradually reduced are realized through one-time dry etching of the windows with the widths being gradually reduced, finally one-time fluorine ion injection is carried out to form the fluorine ion region under the gate and the gradient doped stepped fluorine ion terminal, and meanwhile, the enhancement mode and the optimized surface electric field are realized, the voltage resistance of the device is improved, and the process difficulty is reduced. Compared with a common fluorine ion terminal, the gradient doped step fluorine ion terminal can better optimize a surface electric field, improve the withstand voltage of the device, and improve the forward conduction and dynamic characteristics of the device by injecting fluorine ions into the passivation layer.
Drawings
FIG. 1 is a schematic diagram of a two-dimensional structure of example 1;
FIG. 2 is a process flow diagram of example 1;
FIG. 3 is a specific process step of example 1, wherein:
(a) is a schematic view of the device structure after the dielectric passivation layer is formed in step 2 in the process flow of embodiment 1;
(b) is a schematic view of the device structure after the source-drain conductive material is formed in step 3 in the process flow of embodiment 1;
(c) is a schematic view of the device structure after the dielectric trench is formed in step 4 in the process flow of embodiment 1;
(d) is a schematic view of a device structure after a masking layer is formed and subjected to photolithography in step 5 in the process flow of embodiment 1;
(e) is a schematic view of the structure of the device after etching in step 6 in the process flow of embodiment 1;
(f) is a schematic view of the device structure after fluorine ion implantation in step 7 in the process flow of embodiment 1;
(g) is a schematic view of the device structure after the gate conductive material is formed in step 8 in the process flow of embodiment 1;
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and embodiments:
example 1:
step 1: preparing materials, wherein the materials comprise a substrate 1, a GaN buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 from bottom to top;
step 2: depositing a medium on the AlGaN barrier layer 4 to form a medium passivation layer 5;
and step 3: etching two ends of the medium passivation layer 5 by adopting an etching process, exposing a source electrode hole and a drain electrode hole at two ends of the AlGaN barrier layer 4, depositing a first conductive material, and forming a source electrode 6 and a drain electrode 12 by adopting an etching or stripping process;
and 4, step 4: etching the upper surface of the dielectric passivation layer 5 by adopting an etching process to form a gate groove 7, wherein the depth of the gate groove 7 is less than the thickness of the dielectric passivation layer 5;
and 5: coating photoresist 11 above the dielectric passivation layer 5 and forming a window region 9 by photoetching, wherein the window region 9 comprises a plurality of windows which become narrower in sequence along the direction from the source electrode to the drain electrode, the window closest to the source electrode is aligned with the gate groove 7 in the vertical direction, and the window closest to the drain electrode has a distance with the drain electrode;
step 6: etching the dielectric passivation layer 5 through the window region 9 by adopting a dry etching process to form a plurality of dielectric grooves 101-10N with the depth gradually becoming shallow along the direction from the source electrode to the drain electrode, wherein the dielectric passivation layer 5 is still reserved at the bottom of the deepest dielectric groove, and meanwhile, the gate groove 7 is further etched;
and 7: injecting fluorine ions into the medium passivation layer 5 through the window region 9 to form a plurality of fluorine ion injection regions, wherein the fluorine ion injection region positioned below the gate groove 7 penetrates through the medium passivation layer 5 and enters the AlGaN barrier layer 4, while other fluorine ion regions are only arranged in the medium passivation layer 5, and the medium groove and the fluorine ion injection region jointly form a gradient doped step fluorine ion terminal 8; removing the photoresist 11 and annealing;
and 8: a second conductive material is deposited and an etching or lift-off process is used to form the gate 13.
The GaN HEMT device with the gradient doped step fluorine ion terminal, which is prepared by the manufacturing method, is characterized in that a photoetching process is firstly adopted to form a window with the width being sequentially reduced, then the step groove with the depth being sequentially reduced is realized through one-time etching of the window with the width being sequentially reduced, finally one-time fluorine ion injection is carried out to form a fluorine ion region under a grid and the gradient doped step fluorine ion terminal, and meanwhile, the enhancement of the device is realized, the surface electric field is optimized, the voltage resistance of the device is improved, and the difficulty of the process is reduced. Compared with a common fluorine ion terminal, the gradient doped step fluorine ion terminal can better optimize a surface electric field, improve the withstand voltage of the device, and improve the forward conduction and dynamic characteristics of the device by injecting fluorine ions into the passivation layer.

Claims (7)

1. A manufacturing method of a GaN HEMT device with a gradient doped step fluorine ion terminal is characterized by comprising the following steps:
step 1: the preparation method comprises the following steps of preparing materials, wherein the materials comprise a substrate (1), a GaN buffer layer (2), a GaN channel layer (3) and an AlGaN barrier layer (4) which are stacked from bottom to top;
step 2: depositing a medium on the AlGaN barrier layer (4) to form a medium passivation layer (5);
and step 3: etching two ends of the medium passivation layer (5) by adopting an etching process, exposing a source electrode hole and a drain electrode hole at two ends of the AlGaN barrier layer (4), depositing a first conductive material, and forming a source electrode (6) and a drain electrode (12) by adopting an etching or stripping process;
and 4, step 4: etching to form a gate groove (7) on the upper surface of the dielectric passivation layer (5) by adopting an etching process, wherein the depth of the gate groove (7) is smaller than the thickness of the dielectric passivation layer (5);
and 5: coating photoresist (11) on the dielectric passivation layer (5) and forming a window region (9) by photoetching, wherein the window region (9) comprises a plurality of windows which become narrower in sequence along the direction from the source electrode to the drain electrode, the window closest to the source electrode is aligned with the gate groove (7) in the vertical direction, and the window closest to the drain electrode has a distance with the drain electrode;
step 6: etching the dielectric passivation layer (5) through the window region (9) by adopting a dry etching process to form a plurality of dielectric grooves with the depth becoming shallow in sequence along the direction from the source electrode to the drain electrode, wherein the dielectric passivation layer (5) is still reserved at the bottom of the deepest dielectric groove;
and 7: fluorine ions are injected into the dielectric passivation layer (5) through the window region (9) to form a plurality of fluorine ion injection regions, wherein the fluorine ion injection region positioned below the gate groove (7) penetrates through the dielectric passivation layer (5) to enter the AlGaN barrier layer (4), other fluorine ion regions are only arranged in the dielectric passivation layer (5), and the dielectric groove and the fluorine ion injection region jointly form a gradient doped stepped fluorine ion terminal (8); removing the photoresist (11) and annealing;
and 8: and depositing a second conductive material, and forming a grid electrode (13) by adopting an etching or stripping process.
2. The method of fabricating a GaN HEMT device having graded-doped stepped fluorine ion terminations according to claim 1, wherein the individual fluorine ion regions in the graded-doped stepped fluorine ion terminations (8) are equally spaced in the lateral direction of the device.
3. The method of manufacturing a GaN HEMT device with a graded-doped stepped fluorine ion termination according to claim 1, wherein the respective fluorine ion regions in the graded-doped stepped fluorine ion termination (8) have different pitches in the lateral direction of the device, and the pitches increase sequentially in the direction from the source to the drain.
4. The method for manufacturing a GaN HEMT device with a graded doped stepped fluorine ion termination according to claim 1, wherein the first conductive material is one or more of Ti, TiN, Al, Ni and Au.
5. The method of claim 1, wherein the second conductive material is a combination of Ni and Au.
6. The manufacturing method of the GaN HEMT device with the gradually-doped stepped fluorine ion terminal is characterized in that the substrate (1) is made of one of sapphire, Si, SiC, AlN, GaN, AlGaN, ZnO and GaAs.
7. The method for manufacturing a GaN HEMT device with a graded doped step fluorine ion termination according to claim 1, wherein the dielectric passivation layer (5) is made of SiN x 、SiO 2 、Al 2 O 3 And AlN.
CN202210829590.3A 2022-07-15 2022-07-15 Manufacturing method of GaN HEMT device with gradient doped step fluorine ion terminal Pending CN115050813A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117116764A (en) * 2023-10-20 2023-11-24 深圳市至信微电子有限公司 Gallium nitride device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117116764A (en) * 2023-10-20 2023-11-24 深圳市至信微电子有限公司 Gallium nitride device and manufacturing method thereof
CN117116764B (en) * 2023-10-20 2024-02-06 深圳市至信微电子有限公司 Gallium nitride device and manufacturing method thereof

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