CN117423705A - Array substrate, display panel and display device - Google Patents

Array substrate, display panel and display device Download PDF

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Publication number
CN117423705A
CN117423705A CN202311527357.0A CN202311527357A CN117423705A CN 117423705 A CN117423705 A CN 117423705A CN 202311527357 A CN202311527357 A CN 202311527357A CN 117423705 A CN117423705 A CN 117423705A
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China
Prior art keywords
branch
main
trace
test
array substrate
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CN202311527357.0A
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Chinese (zh)
Inventor
潘陟成
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Shanghai AVIC Optoelectronics Co Ltd
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Shanghai AVIC Optoelectronics Co Ltd
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Priority to CN202311527357.0A priority Critical patent/CN117423705A/en
Publication of CN117423705A publication Critical patent/CN117423705A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a display area and a non-display area surrounding the display area; the array substrate further includes: a substrate base; the test signal lines and the test pads are positioned in the non-display area, and the film layer where the test pads are positioned is positioned at the side of the film layer where the test signal lines are away from the substrate; the test signal line comprises a main line wiring and a branch line wiring, and the test pad is electrically connected with the main line wiring through the branch line wiring. In the invention, the test pad is connected with the main line by the branch line, and the existence of the branch line is equivalent to providing a certain corrosion allowance for the test signal line, so that the main line is prevented from being directly influenced after the test pad is corroded, the corrosion problem of the main line is improved, and the normal transmission of the test signal is ensured.

Description

Array substrate, display panel and display device
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
The display panel used at present usually uses the display chip to drive and carry out image display, in the manufacturing process, the display panel can be firstly subjected to a lighting test, and after the display panel is determined to be normally lighted, the display chip is bound, so that the material waste of the display chip is avoided. The display panel can form a test pad for inputting test signals and a corresponding test wire in the manufacturing process; when the lighting test is performed, the inspection device is connected to the test pad to input a corresponding test signal to the display panel. Because the test pad needs to be contacted with the probe of the detection equipment, the test pad can be exposed in the external environment, electric corrosion is easy to occur, and when the corrosion phenomenon is serious, the connected test wiring can be damaged.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a display panel and a display device, so as to improve the problem of corrosion of the test traces during the testing stage of the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, including a display area and a non-display area surrounding the display area; the array substrate further includes:
a substrate base;
the test signal lines and the test pads are positioned in the non-display area, and the film layer where the test pads are positioned is positioned at one side of the film layer where the test signal lines are away from the substrate;
the test signal line comprises a main line wiring and a branch line wiring, and the test pad is electrically connected with the main line wiring through the branch line wiring.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate according to the first aspect of the present invention.
In a third aspect, an embodiment of the present invention further provides a display apparatus, including a display panel according to the second aspect of the present invention.
The array substrate provided by the embodiment of the invention comprises a display area and a non-display area surrounding the display area; the array substrate further includes: a substrate base; the test signal lines and the test pads are positioned in the non-display area, and the film layer where the test pads are positioned is positioned at the side of the film layer where the test signal lines are away from the substrate; the test signal line comprises a main line wiring and a branch line wiring, and the test pad is electrically connected with the main line wiring through the branch line wiring. In the invention, the test pad is connected with the main path by the branch path, and if the test pad is corroded by water vapor in the test process, the corrosion area can spread to the branch path along the connection part. The existence of the branch wiring is equivalent to providing a certain corrosion allowance for the test signal wire, avoiding the direct influence on the main wiring after the test pad is corroded, improving the corrosion problem of the main wiring and ensuring the normal transmission of the test signal.
Drawings
FIG. 1 is a schematic top view of a related art test pad and a test signal line;
FIG. 2 is a schematic cross-sectional view of FIG. 1 along A-A';
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 4 is an enlarged schematic view of FIG. 3 at B;
FIG. 5 is a schematic cross-sectional view of FIG. 4 along line C-C';
fig. 6 is a schematic diagram of a partial structure of an array substrate according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a partial structure of another array substrate according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of FIG. 7 along the direction D-D';
FIG. 9 is a schematic diagram of a partial structure of another array substrate according to an embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view of FIG. 9 along E-E';
FIG. 11 is a schematic diagram of a partial structure of another array substrate according to an embodiment of the present invention;
fig. 12 is a schematic view of a partial structure of another array substrate according to an embodiment of the present invention;
FIG. 13 is a schematic view of a partial structure of another array substrate according to an embodiment of the present invention;
FIG. 14 is a schematic cross-sectional view of FIG. 13 along the direction F-F';
fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
Fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The words expressing the positions and directions described in the present invention are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present invention. The drawings of the present invention are merely schematic representations, not true to scale, of the relative positional relationships of the various components.
Fig. 1 is a schematic top view of a test pad and a test signal line in the related art, and fig. 2 is a schematic cross-sectional view along A-A' of fig. 1. Referring to fig. 1 and 2, in the related art, a test pad 3' is disposed in a different layer from a test signal line 2', and in a direction perpendicular to a film layer where the test signal line 2' is located, the test pad 3' overlaps with a test 2' to which it is electrically connected, and the test pad 3' is perforated and connected with the test signal line 2' at the overlapping position. The inventors found that in this arrangement in the related art, when the test pad 3' is electrically corroded, the corrosion region directly propagates to the test signal line 2' along the via hole, thereby corroding the entire test signal line 2'.
Based on the above-mentioned drawbacks of the related art, the present application proposes an array substrate including a display area and a non-display area surrounding the display area; the array substrate further includes:
a substrate base;
the test signal lines and the test pads are positioned in the non-display area, and the film layer where the test pads are positioned is positioned at the side of the film layer where the test signal lines are away from the substrate;
the test signal line comprises a main line wiring and a branch line wiring, and the test pad is electrically connected with the main line wiring through the branch line wiring.
Through the technical scheme, if the test pad is corroded by water vapor in the test process, the corrosion area can spread to the branch wiring along the connecting position. The existence of the branch wiring is equivalent to providing a certain corrosion allowance for the test signal wire, avoiding the direct influence on the main wiring after the test pad is corroded, improving the corrosion problem of the main wiring and ensuring the normal transmission of the test signal.
The foregoing is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
Fig. 3 is a schematic structural view of an array substrate according to an embodiment of the present invention, fig. 4 is an enlarged structural view of fig. 3 at B, fig. 5 is a schematic structural view of fig. 4 along C-C', and referring to fig. 3 to 5, in an embodiment of the present invention, the array substrate includes a display area AA and a non-display area NA surrounding the display area AA; the array substrate further includes: a substrate 1; the test signal lines 2 and the test pads 3 are arranged on one side of the substrate 1, the test signal lines 2 and the test pads 3 are both positioned in the non-display area NA, and the film layer where the test pads 3 are positioned is positioned on one side of the film layer where the test signal lines 2 are positioned, which is away from the substrate 1; the test signal line 2 includes a main line trace 21 and a branch line trace 22, and the test pad 3 and the main line trace 21 are electrically connected by the branch line trace 22.
Specifically, as shown in fig. 3 to 5, the substrate 1 may be a flexible substrate or a rigid substrate, the flexible substrate may be a polymer substrate, and the rigid substrate may be a glass substrate, which is not described herein in detail or limited thereto. A pixel circuit (not shown) and a signal transmission wiring (not shown) and the like may be provided in the display area AA of the substrate 1, and a non-display area NA of the substrate 1 is provided around the display area AA for providing a driving chip (not shown), an extraction signal line (not shown), a test pad 3, a test signal line 2 and the like. The test pad 3 and the test signal line 2 may be disposed in the test bonding area NA1, and fig. 3 illustrates that the test pad 3 and the test signal line 2 are located in a non-display area NA, i.e., a lower frame area, below the display area AA, and the enlarged area of fig. 4 is the test bonding area NA1.
With continued reference to fig. 3 to 5, in order to avoid the corrosion of the test pad 3 in the related art from directly affecting the test signal line 2, the embodiment of the present invention proposes that the test signal line 2 may be divided into a main trace 21 and a branch trace 22. One end of the main trace 21 extends toward the display area AA and is connected to the signal transmission trace in the display area AA. The signal transmission lines may include scan lines, data lines, and/or common signal lines, etc., through which scan signals are transmitted to the pixels within the display area AA, through which data signals are transmitted to the pixels, and through which common voltage signals are transmitted to the pixels. Of course, the signal transmission trace may also include other signal traces known to those skilled in the art, and the embodiment of the present invention is not limited thereto. The other end of the main path wiring 21 can be bound with a driving chip to realize the external connection of the main path wiring 21, and the driving chip can transmit a grounding signal to the main path wiring 21 when the display panel is normally applied to lead out residual signals on the main path wiring 21, so that the influence on the normal transmission of display signals caused by the existence of stray signals or static electricity residues in the test signal line 2 after the test of the display panel is finished is avoided. In addition, the test signal line 2 is connected with the driving chip, and when the display panel is normally applied, the test signal line 2 can be used for transmitting signals required by display to the display area AA, so that the utilization rate of the test signal line 2 is improved.
As shown in fig. 3 to 5, in the present invention, the test pad 3 is not directly connected to the main trace 21, and the two are electrically connected through the branch trace 22. The test signal is transmitted to the main trace 21 via the test pad 3 and the branch trace 22, and further transmitted to the display area AA. Wherein the main routing 21 and the branch routing 22 are positioned on different film layers with the test pad 3; it will be appreciated that, since the test pad 3 needs to be in contact with the probe, the test pad 3 should be disposed on a side of the film layer where the test signal line 2 is located away from the substrate 1, that is, the test pad 3 may be located on a surface layer of the array substrate, the test signal line 2 is located inside the array substrate, the film layer where the test pad 3 is located and the film layer where the test signal line 2 is located are separated by the insulating layer 4, and the branch trace 22 and the test pad 3 may be perforated to implement electrical connection.
In the invention, the test pad 3 is connected with the main line 21 by the branch line 22, and if the test pad 3 is corroded by water vapor in the test process, the corrosion area can be spread to the branch line 22 along the connection part. The existence of the branch wires 22 is equivalent to providing a certain corrosion allowance for the test signal wires 2, avoiding the main wire 21 from being directly influenced after the test pad 3 is corroded, improving the corrosion problem of the main wire 21 and ensuring the normal signal transmission of the main wire 21.
The main routing 21 and the branch routing 22 may be located on the same film layer or different film layers, which is not limited in the embodiment of the present invention, and may be set by those skilled in the art according to actual requirements. In the embodiment shown in fig. 3, the main trace 21 and the branch trace 22 are located on the same layer, which is not limited thereto.
In an embodiment of the present invention, the array substrate includes a display area, a non-display area surrounding the display area, and: a substrate base; the test signal lines and the test pads are positioned in the non-display area, and the film layer where the test pads are positioned is positioned at the side of the film layer where the test signal lines are away from the substrate; the test signal line comprises a main line wiring and a branch line wiring, and the test pad is electrically connected with the main line wiring through the branch line wiring. In the invention, the test pad is connected with the main path by the branch path, and if the test pad is corroded by water vapor in the test process, the corrosion area can spread to the branch path along the connection part. The existence of the branch wiring is equivalent to providing a certain corrosion allowance for the test signal wire, avoiding the direct influence on the main wiring after the test pad is corroded, improving the corrosion problem of the main wiring and ensuring the normal transmission of the test signal.
Optionally, with continued reference to fig. 4 and 5, in an embodiment of the present invention, an end of the branch trace 22 away from the main trace 21 may include a widened region 23, where the branch trace 22 is electrically connected to the test pad 3 through the first via 5.
Specifically, since the test pad 3 needs to be in contact with the probe of the inspection apparatus, the width of the test pad 3 in the direction perpendicular to the extending direction of the branch wirings 22 is generally larger than the line width of the branch wirings 22. Based on this, in order to secure the connection effect of the test pad 3 and the branch trace 22, the line width of the area of the branch trace 22 to be electrically connected to the test pad 3 may be widened, and a widened region 23 may be formed, that is, the widened region 23 of the branch trace 22 overlaps the test pad 3 in a direction perpendicular to the plane of the substrate 1, and the widened region 23 is electrically connected to the test pad 3 through the first via 5. The specific size relationship between the line width of the branch trace 22 at the widened region 23 and the width of the test pad 3 in the extending direction of the vertical branch trace 22 is not limited, and fig. 4 exemplarily shows that the line width of the widened region 23 is equal to the width of the test pad 3, which is not limited in practice, and may be set by those skilled in the art according to practical situations.
Alternatively, with continued reference to fig. 3-5, in some possible embodiments, the main trace 21 and the branch trace 22 may be arranged in the same layer, with the main trace 21 and the branch trace 22 being directly connected; the test pad 3 is electrically connected to the branch trace 22 through the first via hole 5, and the first via hole 5 and the main trace 21 do not overlap in a direction perpendicular to the plane of the substrate 1.
Specifically, as shown in fig. 3 to 5, the main trace 21 and the branch trace 22 may be disposed on the same film layer, and meanwhile, an overlapping region exists between the test pad 3 and the branch trace 22 along a direction perpendicular to a plane on which the substrate 1 is disposed, and holes are punched in the overlapping region of the two, so as to electrically connect the branch trace 22 and the test pad 3. In this arrangement, the orthographic projection of the first via hole 5 on the plane of the substrate 1 and the orthographic projection of the main trace 21 on the plane of the substrate 1 do not overlap, so that the corrosion area can be prevented from spreading to the main trace 21 along the first via hole 5. The main routing 21 and the branch routing 22 are arranged on the same film layer, the main routing 21 and the branch routing 22 can be prepared in the same process, the film layer number of the array substrate can be reduced, and the thickness of the array substrate can be reduced.
Optionally, the number of the first vias 5 between the test pads 3 and the branch traces 22 is not limited, and those skilled in the art may set the number according to the actual situation, and the number is shown in fig. 5 only as an example.
Alternatively, with continued reference to fig. 3-5, in some embodiments, the test pad 3 does not overlap the main trace 21 in a direction perpendicular to the plane of the substrate 1.
Specifically, as an alternative embodiment, the test pad 3 as a whole does not overlap with the main routing 21 in the direction perpendicular to the plane in which the substrate 1 is located, so that the problem of the first via 5 being enlarged to cause the test pad 3 to be connected to the main routing 21 can be avoided.
Alternatively, with continued reference to fig. 4, in the orthographic projection of the plane of the substrate 1, the test pads 3 and the main routing traces 21 may be arranged alternately along the first direction X, which is parallel to the extending direction of the edge of the display area AA.
Specifically, the whole main routing lines 21 may extend along the second direction Y, and be arranged in the first direction X, where the first direction X may be a direction parallel to the lower edge of the display area AA of the array substrate, and the second direction Y may be a direction in which the lower edge of the display area AA points to the upper edge of the display area AA, so that the test pads 3 are located on the lower frame. Of course, when the layout positions of the test pads 3 and the test signal lines 2 are different, the extending directions of the first directions X are different.
As an alternative embodiment, as shown in fig. 4, the test pads 3 may be arranged along the first direction X, and when the front projection is made on the plane of the substrate 1, one test pad 3 is arranged between two adjacent main routing wires 21, so that the test pads 3 and the main routing wires 21 are alternately arranged along the first direction X. The test pad 3 may be located at one side of the main routing 21 electrically connected thereto in the first direction X.
In this arrangement, the distance between each test pad 3 (or the branch trace 22) and the main trace 21 electrically connected with the test pad is relatively short in the first direction X, and the arrangement of the branch traces 22 is relatively simple and regular. When the first direction X is parallel to the lower edge of the display area AA, since the length of the non-display area NA of the lower frame in the first direction X is greater than that in the second direction Y, a larger layout space is provided for the test pad 3.
Further alternatively, with continued reference to fig. 3 and 4, the main routing 21 may include a first extension 211 and a second extension 212 connected to each other, the first extension 211 extending along a first direction X, the second extension 212 extending along a second direction Y, the first direction X and the second direction Y intersecting; the test pad 3 and the second extension 212 are electrically connected through the branch trace 22, and among the electrically connected branch trace 22, test pad 3, and second extension 212, the branch trace 22 and the test pad 3 are located on the same side of the second extension 212 in the first direction X.
Specifically, as shown in fig. 3 and 4, in general, a chip binding area NA2 for binding a driving chip (not shown in the drawings) is located in the middle of a non-display area NA of the lower frame. The test binding area NA1 may be disposed at one side or both sides of the chip binding area NA 2. In this arrangement, to realize the electrical connection between the main trace 21 and the driving chip and the signal transmission trace (not shown in the figure) in the display area AA, the main trace 21 may be configured by a first extension portion 211 extending along the first direction X and a second extension portion 212 extending along the second direction Y, where one end of the first extension portion 211 is electrically connected to the driving chip, the other end of the first extension portion 211 is connected to one end of the second extension portion 212, and the other end of the second extension portion 212 extends toward the display area AA. The first extending portions 211 of the different main routing wires 21 are arranged in the second direction Y, and the second extending portions 212 are arranged in the first direction X.
Correspondingly, the test pads 3 and the second extending portions 212 are alternately arranged in the first direction X, and a group of test groups including the test pads 3, the branch wires 22 and the main wires 21 electrically connected with each other can be defined, where the test pads 3 and the branch wires 22 are located at one side of the second extending portions 212 of the main wires 21. Unless specifically described, the positional relationships among the test pads 3, the main routing traces 21, and the branch routing traces 22, which are indicated below, may refer to the positional relationships among the test pads 3, the main routing traces 21, and the branch routing traces 22 of the same test group. Fig. 4 exemplarily shows that the test pad 3 and the branch trace 22 are located on the right side of the second extension 212 of the same group in the first direction X, which is not limited thereto in practice.
Alternatively, with continued reference to fig. 4 and 5, in some embodiments, the branch trace 22 may include a third extension 221 and a fourth extension 222 connected to each other, the third extension 221 extending in the first direction X, the fourth extension 222 extending in the second direction Y; one end of the third extension part 221 away from the fourth extension part 222 is electrically connected with the second extension part 212, and one side of the fourth extension part 222 away from the third extension part 221 is electrically connected with the test pad 3 through the first via hole 5.
Specifically, as shown in fig. 4 and 5, the branch trace 22 may be formed of two branches, the extension direction of the third extension portion 221 is the same as the extension direction of the first extension portion 211 of the main trace 21, and the extension direction of the fourth extension portion 222 is the same as the extension direction of the second extension portion 212 of the main trace 21. In the test signal line 2, the second extending portions 212 of the main trace 21 and the fourth extending portions 222 of the branch trace 22 are alternately arranged in order along the first direction X. The third extension 221 of the branch trace 22 is used to connect the second extension 212 of the main trace 21 and the fourth extension 222 of the branch trace 22. In the direction perpendicular to the plane of the substrate 1, one end of the fourth extension portion 222, which is not connected with the third extension portion 221, overlaps the test pad 3, and a first via hole 5 is formed by punching in the insulating layer 4 in the overlapping region of the two, so as to electrically connect the branch line 22 and the test pad 3.
The branch wirings 22 are formed by the third extending part 221 and the fourth extending part 222, so that the connection path between the test pad 3 and the main wiring 21 electrically connected with the test pad is longer, if the test pad 3 corrodes, the spreading path of the corrosion area from the test pad 3 to the main wiring 21 is longer, the corrosion allowance of the branch wirings 22 is larger, and the spreading of the corrosion area to the main wiring 21 is further avoided.
Fig. 6 is a schematic partial structure of an array substrate according to an embodiment of the present invention, in the embodiment shown in fig. 6, the branch trace 22 includes only one branch portion (which may be the third extension portion 221) extending along the first direction X, and in this arrangement manner, the extension length of the branch trace 22 is relatively short, the arrangement density of the test signal lines 2 in the test binding area is relatively small, and the arrangement difficulty of the test signal lines 2 is relatively low.
It should be noted that, in the direction perpendicular to the plane of the substrate 1, a distance threshold should be maintained between the main trace 21 and the branch trace 22 overlapping the test pad 3, for example, a first distance d1 is provided between the second extension 212 and the area overlapping the test pad 3 and the fourth extension 222 shown in fig. 4, so that the problem of misconnection between the main trace 21 and the branch trace 22 at the punching position caused by too small distance is avoided. The specific value of the first interval d1 may be set by a person skilled in the art according to actual needs, and the embodiment of the present invention is not repeated and limited.
Alternatively, fig. 7 is a schematic partial structure of another array substrate according to an embodiment of the present invention, fig. 8 is a schematic cross-sectional structure of fig. 7 along D-D', and referring to fig. 7 and 8, in other possible embodiments, in a direction along a plane perpendicular to the substrate 1, the test pad 3 overlaps the main routing 21, and in a direction along a plane perpendicular to the substrate 1, the test pad 3 is spaced from the main routing 21 by the insulating layer 4.
Specifically, as shown in fig. 7 and 8, the main trace 21 and the branch trace 22 may still be arranged in the same layer, unlike the above-described embodiment, in this embodiment, in the orientation shown in fig. 8, the test pad 3 may be located above the branch trace 22 and the main trace 21 such that the test pad 3 overlaps the main trace 21 and the branch trace 22 in a direction perpendicular to the plane in which the substrate 1 is located. The test pad 3 is connected to the branch trace 22 through the first via 5, and the test pad 3 is spaced from the main trace 21 by the insulating layer 4. In this arrangement, since the test pad 3 may overlap the main routing 21, the length between two adjacent main routing 21 occupied by the test pad 3 in the first direction X is reduced, and compared with the embodiment shown in fig. 4, in the case that the width of the test pad 3 in the first direction X is the same, the space between two adjacent main routing 21 in the first direction X may be correspondingly reduced, thereby compressing the size of the test bonding area in the first direction X. The distance between the test binding area and the edge of the array substrate can be increased to a certain extent, and defects caused by too close distance between the test wiring and the corners when corners are broken due to cutting of the special-shaped screen are avoided.
Alternatively, with continued reference to fig. 7 and 8, the test pad 3 may include a first region 31 and a second region 32, where the first region 31 and the first region 31 are located on both sides of the main routing 21, respectively, in a direction parallel to a plane in which the substrate 1 is located; the first region 31 and/or the second region 32 are electrically connected to the main trace 21 through the branch trace 22.
Specifically, in the present embodiment, the test pad 3 may be divided into a first region 31, a second region 32 and a third region 33, the orthographic projections of the first region 31 and the second region 32 on the film layer where the test signal line 2 is located may be located at two sides of the main trace 21 along the first direction X, and the orthographic projections of the third region 33 on the film layer where the test signal line 2 is located may overlap with the main trace 21.
Accordingly, for such an arrangement of the test pad 3, the branch trace 22 may be arranged differently, and if the first region 31 or the second region 32 of the test pad 3 is electrically connected to the branch trace 22 through the first via 5, the branch trace 22 may be arranged on one side of the main trace 21 along the first direction X. Illustratively, in the orientation shown in fig. 6, if the branch trace 22 is disposed to the left of the main trace 21 in the first direction X, then the branch trace 22 may be electrically connected to the first region 31 of the test pad 3 also located to the left of the main trace 21 through the first via 5 (as shown in fig. 7); if the branch trace 22 is disposed on the right side of the main trace 21 along the first direction X, the branch trace 22 may be electrically connected to the second region 32 of the test pad 3, which is also located on the right side of the main trace 21, through the first via 5.
For example, fig. 9 is a schematic view of a partial structure of another array substrate according to an embodiment of the present invention, fig. 10 is a schematic view of a cross-sectional structure of fig. 9 along the direction of E-E', and referring to fig. 9 and 10, when the first area 31 and the second area 32 are electrically connected to the main trace 21 through the branch trace 22, the branch trace 22 includes a first sub-branch trace 223 and a second sub-branch trace 224, and the first sub-branch trace 223 and the second sub-branch trace 224 are electrically connected to the same main trace 21; the first sub-branch wirings 223 and the second sub-branch wirings 224 are located on both sides of the main-path wirings 21 in a direction parallel to the plane in which the substrate 1 is located; the first sub-branch trace 223 is used for electrically connecting the main trace 21 with the first region 31, and the second sub-branch trace 224 is used for electrically connecting the main trace 21 with the second region 32.
Specifically, in the present embodiment, the branch wirings 22 connected to the same main wiring 21 may include a first sub-branch wiring 223 and a second sub-branch wiring 224, which may be respectively located at two sides of the main wiring 21 along the first direction X. And in a direction perpendicular to the plane of the substrate 1, the first sub-branch trace 223 overlaps the first region 31 of the test pad 3, and the second sub-branch trace 224 overlaps the second region 32 of the test pad 3; in other words, the first sub-branch trace 223 and the first region 31 of the test pad 3 are located on the same side of the main trace 21, and the second sub-branch trace 224 and the second region 32 of the test pad 3 are located on the same side of the main trace 21. One end of the first sub-branch trace 223, which is not connected to the main trace 21, is electrically connected to the first region 31 of the test pad 3 through the first via 5, and one end of the second sub-branch trace 224, which is not connected to the main trace 21, is electrically connected to the second region 32 of the test pad 3 through the first via 5.
In this way, the first area 31 and the second area 32 of the test pad 3 are electrically connected with the main path wiring 21 through a sub-branch wiring, so that the connection effect of the test pad 3 and the test signal line 2 can be ensured, and the problems that the wire breakage occurs and the test signal cannot be transmitted are avoided.
Alternatively, referring to fig. 9 and 10, the main trace 21 may include a first extension portion 211 and a second extension portion 212 connected to each other, the first extension portion 211 extending along a first direction X, the second extension portion 212 extending along a second direction Y, the first direction X being parallel to an extension direction of an edge of the display area AA, the first direction X and the second direction Y intersecting; the first sub-branch trace 223 and the second sub-branch trace 224 are located at two sides of the second extension 212, respectively.
Specifically, the shape of the main routing 21 is the same as that of the above embodiment, and will not be described here again. In this arrangement of the main trace 21, two sub-branch traces electrically connected to the same main trace 21 may be located at two sides of the second extension 212 along the first direction X. When the first direction X is parallel to the lower edge of the display area AA, since the length of the non-display area NA of the lower frame in the first direction X is greater than that in the second direction Y, a larger layout space is provided for the test pad 3 and the branch trace 22.
Optionally, with continued reference to fig. 9 and 10, the first sub-branch trace 223 includes a fifth extending portion 2231 and a sixth extending portion 2232 connected to each other, the fifth extending portion 2231 extending in the first direction X, the sixth extending portion 2232 extending in the second direction Y; one end of the fifth extension 2231, which is far from the sixth extension 2232, is electrically connected with the second extension 212, and one side of the sixth extension 2232, which is far from the fifth extension 2231, is electrically connected with the first region 31 through the first via 5; the second sub-branch trace 224 includes a seventh extension 2241 and an eighth extension 2242 connected to each other, the seventh extension 2241 extending in the first direction X, the eighth extension 2242 extending in the second direction Y; one end of the seventh extension 2241 remote from the eighth extension 2242 is electrically connected with the second extension 212, and one side of the eighth extension 2242 remote from the seventh extension 2241 is electrically connected with the second region 32 through the first via 5.
Specifically, as shown in fig. 9 and 10, the sub-branch line may be formed of two branches, and the two branches of the sub-branch line may be arranged in a similar manner to the two branches of the branch line 22 in the above embodiment, and may extend in the first direction X and the second direction Y, respectively. For the first sub-branch trace 223, the two branches are a fifth extension portion 2231 extending along the first direction X and a sixth extension portion 2232 extending along the second direction Y. The fifth extension portion 2231 is used for connecting the second extension portion 212 of the main trace 21 and the sixth extension portion 2232 of the first sub-branch trace 223, and one end of the sixth extension portion 2232, which is not connected to the fifth extension portion 2231, is electrically connected to the first region 31 of the test pad 3 through the first via 5. For the second sub-branch trace 224, the two branches are a seventh extending portion 2241 extending along the first direction X and an eighth extending portion 2242 extending along the second direction Y. The seventh extension 2241 is configured to connect the second extension 212 of the main trace 21 and the eighth extension 2242 of the second sub-branch trace 224, and an end of the eighth extension 2242 not connected to the seventh extension 2241 is electrically connected to the second region 32 of the test pad 3 through the first via 5.
The sub-branch wirings are formed by two extending parts, so that the connecting path between the test pad 3 and the main wiring 21 electrically connected with the test pad is longer, the corrosion allowance of the sub-branch wirings is larger, and the corrosion area is prevented from spreading to the main wiring 21.
In the embodiment shown in fig. 9, in the electrically connected main trace 21, branch trace 22 and test pad 3, the width d2 of the test pad 3 in the first direction X is greater than the distance d3 in the first direction X between two sides of the two sub-branch traces facing away from each other, where the two sides of the two sub-branch traces facing away from each other refer to the two sides of the other area except the widened area facing away from each other. In this arrangement, the width of the test pad 3 along the first direction X is larger, so that the area of the test pad 3 is larger, which is beneficial to the contact between the test pad 3 and the probe.
Fig. 11 is a schematic partial structure of another array substrate according to the embodiment of the present invention, referring to fig. 11, in the main routing 21, the branch routing 22 and the test pad 3 that are electrically connected, the width d2 of the test pad 3 in the first direction X is smaller than or equal to the distance d3 between two sides of the two sub-branch routing 22 that are away from each other in the first direction X, in this arrangement, the width d2 of the test pad 3 along the first direction X is smaller, the test pad 3 does not extend to a position above the gap between two adjacent main routing 21, and the gap between two adjacent main routing 21 can be reduced appropriately, so as to further reduce the space occupied by the whole test bonding area, and make more layout space for other signal routing.
Alternatively, with continued reference to fig. 9 or 10, in some embodiments, the areas of the first region 31 and the second region 32 are the same. It is also understood that the width of the first region 31 of the test pad 3 in the first direction X is equal to the width of the second region 32 in the first direction X, and that the first region 31 and the second region 32 occupy the same area as the entire test pad 3. In this arrangement, the first region 31 and the second region 32 of the test pad 3 have a larger area and are electrically connected to the underlying sub-branch trace.
Of course, in the practical application process, a person skilled in the art may adjust the area ratio of the first area 31 and the second area 32 according to the practical situation, which is not limited in the embodiment of the present invention.
Optionally, fig. 12 is a schematic view of a partial structure of still another array substrate according to an embodiment of the present invention, referring to fig. 12, in other embodiments, the test pad 3 may only include a third region 33 located above the main trace 21 and a fourth region 34 located on either side of the main trace 21. Fig. 12 exemplarily shows that the projection of the fourth area 34 on the film layer on which the main routing 21 is located on the right side along the main routing 21, which is not limited thereto in practice. Accordingly, the branch trace 22 may be located on the same side of the main trace 21 as the fourth region 34 of the test pad 3, and the fourth region 34 of the test pad 3 may be electrically connected to the branch trace 22 through the first via.
Optionally, fig. 13 is a schematic view of a partial structure of another array substrate provided in the embodiment of the present invention, fig. 14 is a schematic view of a cross-sectional structure of fig. 13 along the direction of F-F', and referring to fig. 13 and fig. 14, the main trace 21 and the branch trace 22 are arranged in different layers, and the main trace 21 and the branch trace 22 are electrically connected through the second via hole 6; the test pad 3 is electrically connected to the branch trace 22 through the first via hole 5, and the first via hole 5 and the second via hole 6 do not overlap in a direction perpendicular to the plane of the substrate 1.
Specifically, as shown in fig. 13 and 14, in this embodiment, the main trace 21 and the branch trace 22 may be located in different layers, and the layer where the main trace 21 is located may be defined as a first conductive layer, the layer where the branch trace 22 is located is a second conductive layer, and the first conductive layer and the second conductive layer are separated by the insulating layer 4. The branch wires 22 and the main wires 21 can be electrically connected through the second via holes 6.
Further, the present embodiment further defines that the first via hole 5 and the second via hole 6 do not overlap in a direction perpendicular to the plane in which the substrate 1 lies. In this way, direct communication between the first via 5 and the second via 6 can be avoided, and further, direct electrical connection between the main routing 21 and the test pad 3 through the via can be avoided.
The main routing 21 and the branch routing 22 are arranged on different film layers, and along the direction perpendicular to the plane of the substrate 1, the branch routing 22 can overlap with the main routing 21, so that the space occupied by a group of main routing 21 and branch routing 22 in the arrangement direction of the two is compressed. Assuming that the main trace 21 is still formed by the first extension portion 211 and the second extension portion 212, the branch trace 22 is still electrically connected to the second extension portion 212, and the layout space of the main trace 21 and the branch trace 22 in the first direction X in the present embodiment can be properly reduced, so as to further compress the size of the test signal line 2 in the first direction X.
In addition, since the main trace 21 and the branch trace 22 are respectively located on different conductive layers, when the branch trace 22 includes the widened region 23, the line width of the main trace 21 overlapping with the branch trace 22 may be increased to be similar to or the same as the widened region 23, and the increase of the line width of the main trace 21 may avoid the risk of line breakage, thereby improving the reliability of the transmission of the test signal by the main trace 21.
Alternatively, with continued reference to fig. 13 and 14, the test pad 3 overlaps the main routing 21 in a direction perpendicular to the plane of the substrate 1.
Because the main routing 21, the branch routing 22 and the test pad 3 are all located in different conductive layers and can be arranged in the direction perpendicular to the plane of the substrate 1, the main routing 21, the branch routing 22 and the test pad 3 are all overlapped, so that the size of the whole test binding area in the first direction X is compressed.
In the embodiment shown in fig. 13 and 14, the film layer where the main trace 21 is located is on the side of the film layer where the branch trace 22 is located, which is away from the film layer where the test pad 3 is located. That is, along the side of the substrate 1, which is directed to the film layer where the test pad 3 is located, the first conductive layer, the second conductive layer and the film layer where the test pad 3 is located are sequentially arranged, and any two adjacent conductive film layers are separated by the insulating layer 4. In this arrangement, the distance between the main routing 21 and the test pad 3 in the direction perpendicular to the plane of the substrate 1 is relatively large, which is beneficial to reducing the risk of direct interconnection between the first via 5 and the second via 6 caused by reaming.
In other embodiments, not shown, the film layer on which the main trace 21 is located may be located between the film layer on which the test pad 3 is located and the film layer on which the branch trace 22 is located, that is, along the side of the substrate 1 pointing to the film layer on which the test pad 3 is located, where the second conductive layer, the first conductive layer, and the film layer on which the test pad 3 is located are sequentially disposed, and any two adjacent conductive film layers are separated by the insulating layer 4, which is not described in detail in the embodiments of the present invention. In the practical application process, a person skilled in the art can adjust the relationship between the film layers of the main routing 21 and the branch routing 22 according to practical situations.
The array substrate provided by the embodiment of the invention can also comprise any film layer structure known to a person skilled in the art, and the embodiment of the invention is not repeated and limited.
Based on the same inventive concept, the embodiment of the present invention further provides a display panel, and fig. 15 is a schematic structural diagram of the display panel provided by the embodiment of the present invention, and referring to fig. 15, the display panel provided by the embodiment of the present invention includes the array substrate 100 provided by any of the embodiments described above, and may further include an opposite substrate 200 disposed opposite to the array substrate 100, and a display function layer 300 between the array substrate 100 and the opposite substrate 200, where the opposite substrate 200 may be a cover plate or other packaging layers. The display panel provided by the embodiment of the present invention includes all the technical features and corresponding beneficial effects of the array substrate 100 provided by any embodiment of the present invention, and will not be described herein. The display panel may be one of a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, a quantum dot display panel, or a micro-LED display panel, for example, which is not limited in the embodiment of the present invention.
Based on the same inventive concept, the embodiment of the invention also provides a display device. Fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 16, the display device includes the display panel 1000 provided in any embodiment of the present invention, so the display device provided in the embodiment of the present invention has the corresponding beneficial effects of the display panel provided in the embodiment of the present invention, and will not be described herein. The display device may be, for example, an electronic device such as a mobile phone, a computer, a smart wearable device (e.g., a smart watch), and a vehicle-mounted display device, which is not limited in the embodiment of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (18)

1. An array substrate is characterized by comprising a display area and a non-display area surrounding the display area; the array substrate further includes:
a substrate base;
the test signal lines and the test pads are positioned in the non-display area, and the film layer where the test pads are positioned is positioned at one side of the film layer where the test signal lines are away from the substrate;
the test signal line comprises a main line wiring and a branch line wiring, and the test pad is electrically connected with the main line wiring through the branch line wiring.
2. The array substrate of claim 1, wherein the main trace and the branch trace are arranged in the same layer, and the main trace and the branch trace are directly connected;
the test pad is electrically connected with the branch wiring through a first via hole, and the first via hole is not overlapped with the main wiring along the direction perpendicular to the plane of the substrate.
3. The array substrate of claim 2, wherein the test pads do not overlap the main routing lines in a direction perpendicular to a plane in which the substrate lies.
4. An array substrate according to claim 2 or 3, wherein in the orthographic projection of the plane of the substrate, the test pads and the main routing lines are alternately arranged along a first direction, and the first direction is parallel to the extending direction of the edge of the display area.
5. The array substrate of claim 4, wherein the main routing includes a first extension portion and a second extension portion connected to each other, the first extension portion extending in the first direction, the second extension portion extending in a second direction, the first direction and the second direction intersecting;
The test pad and the second extension portion are electrically connected through the branch wiring, and the branch wiring, the test pad and the second extension portion are electrically connected, wherein the branch wiring and the test pad are located on the same side of the second extension portion in the first direction.
6. The array substrate of claim 5, wherein the branch trace includes a third extension portion and a fourth extension portion connected to each other, the third extension portion extending in the first direction, the fourth extension portion extending in the second direction;
one end of the third extension part far away from the fourth extension part is electrically connected with the second extension part, and one side of the fourth extension part far away from the third extension part is electrically connected with the test pad through the first via hole.
7. The array substrate of claim 2, wherein the test pads overlap the main routing lines in a direction perpendicular to a plane of the substrate, and the test pads are spaced apart from the main routing lines by an insulating layer in a direction perpendicular to the plane of the substrate.
8. The array substrate of claim 7, wherein the test pad comprises a first region and a second region, the first region and the first region being respectively located at two sides of the main routing line in a direction parallel to a plane in which the substrate is located;
The first region and/or the second region is/are electrically connected with the main path wiring through the branch wiring.
9. The array substrate of claim 8, wherein when the first and second regions are electrically connected to the main trace via the branch trace, the branch trace includes first and second sub-branch traces electrically connected to the same main trace;
in the direction parallel to the plane of the substrate, the first sub-branch wiring and the second sub-branch wiring are positioned at two sides of the main path wiring; the first sub-branch wire is used for electrically connecting the main line wire and the first area, and the second sub-branch wire is used for electrically connecting the main line wire and the second area.
10. The array substrate of claim 9, wherein the main routing includes a first extension portion and a second extension portion connected to each other, the first extension portion extending in a first direction, the second extension portion extending in a second direction, the first direction being parallel to an extension direction of the display area edge, the first direction and the second direction intersecting;
The first sub-branch wiring and the second sub-branch wiring are respectively positioned at two sides of the second extension part.
11. The array substrate of claim 10, wherein the first sub-branch trace includes a fifth extension portion and a sixth extension portion connected to each other, the fifth extension portion extending in the first direction, the sixth extension portion extending in the second direction; one end of the fifth extension part far away from the sixth extension part is electrically connected with the second extension part, and one side of the sixth extension part far away from the fifth extension part is electrically connected with the first region through the first via hole;
the second sub-branch wiring comprises a seventh extending part and an eighth extending part which are connected with each other, the seventh extending part extends along the first direction, and the eighth extending part extends along the second direction; one end of the seventh extension part far away from the eighth extension part is electrically connected with the second extension part, and one side of the eighth extension part far away from the seventh extension part is electrically connected with the second region through the first via hole.
12. The array substrate of claim 8, wherein the first region and the second region have the same area.
13. The array substrate of claim 1, wherein the main trace and the branch trace are arranged in different layers, and the main trace and the branch trace are electrically connected through a second via;
the test pad is electrically connected with the branch wiring through a first via hole, and the first via hole and the second via hole are not overlapped along the direction perpendicular to the plane of the substrate.
14. The array substrate of claim 13, wherein the test pads overlap the main routing traces in a direction perpendicular to a plane of the substrate.
15. The array substrate of claim 13, wherein the film layer on which the main trace is located at a side of the film layer on which the branch trace is located, the side facing away from the film layer on which the test pad is located.
16. The array substrate of claim 1, wherein an end of the branch trace remote from the main trace includes a widened region, the branch trace being electrically connected to the test pad through a first via at the widened region.
17. A display panel, comprising: the array substrate of any one of claims 1-16.
18. A display device, comprising: the display panel of any one of claims 17.
CN202311527357.0A 2023-11-15 2023-11-15 Array substrate, display panel and display device Pending CN117423705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311527357.0A CN117423705A (en) 2023-11-15 2023-11-15 Array substrate, display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311527357.0A CN117423705A (en) 2023-11-15 2023-11-15 Array substrate, display panel and display device

Publications (1)

Publication Number Publication Date
CN117423705A true CN117423705A (en) 2024-01-19

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Family Applications (1)

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