CN113437095A - Display substrate, display panel and display device - Google Patents
Display substrate, display panel and display device Download PDFInfo
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- CN113437095A CN113437095A CN202110837151.2A CN202110837151A CN113437095A CN 113437095 A CN113437095 A CN 113437095A CN 202110837151 A CN202110837151 A CN 202110837151A CN 113437095 A CN113437095 A CN 113437095A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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Abstract
The invention relates to the technical field of display equipment, in particular to a display substrate, a display panel comprising the display substrate and a display device comprising the display substrate. The display substrate comprises a display area and a peripheral area, the peripheral area comprises a first connecting line and a signal line connected with the driving circuit, and one end of the first connecting line is used for being connected with the electrical test area; the display substrate is provided with a first via hole, a second via hole and a first conducting layer, the first via hole and the second via hole are in an orthographic projection non-overlapping area on the display substrate, the first conducting layer is electrically connected with the signal line through the first via hole, and the first conducting layer is electrically connected with the first connecting line through the second via hole. After the first connecting line is cut off, the corrosion trend can be blocked by the first through hole and the second through hole which are separately arranged, and the material of the first conducting layer has better corrosion resistance compared with the first connecting line, so that the reliability test of a product is ensured to pass.
Description
Technical Field
The invention relates to the technical field of display equipment, in particular to a display substrate, a display panel comprising the display substrate and a display device comprising the display substrate.
Background
Narrow frame design is the mainstream direction in present display field, and conventional narrow frame is mainly GOA design and GOA Layout narrow frame design, optimizes the frame size on left and right sides, and the frame of upper and lower side especially DP side is owing to need bind IC and FPC, hardly carries out narrow frame design.
In order to reduce the frame distance of the DP side, the design that the FPC binding region is arranged on two sides of the IC binding region is adopted in the related technology, the width of the DP side frame can be ensured to be smaller than the width of the left side frame and the right side frame after the design is adopted, but after detection is finished, the region where a test electrode electrically connected with the IC binding region and the FPC binding region is located can be cut off, so that a connecting lead can be exposed, and further a signal line is corroded due to the fact that the signal line directly contacts the water oxygen environment.
Disclosure of Invention
In view of this, embodiments of the present invention provide a display substrate, and further provide a display panel and a display device including the display substrate, so as to solve the technical problem that after a region where a test electrode is located is cut off, a connection wire is exposed, and further a signal line is corroded due to direct contact with a water-oxygen environment in the related art.
In order to achieve the above object, according to an aspect of an embodiment of the present invention, there is provided a display substrate.
The display substrate according to the first aspect of the embodiments of the present invention includes a display area and a peripheral area, and is characterized in that the peripheral area includes a first connection line and a signal line connected to a driving circuit, and one end of the first connection line is used for being connected to an electrical test area;
the display substrate is provided with a first via hole, a second via hole and a first conducting layer, the first via hole and the second via hole are in an orthographic projection non-overlapping area on the display substrate, the first conducting layer is electrically connected with the signal line through the first via hole, and the first conducting layer is electrically connected with the first connecting line through the second via hole.
In an implementation manner of the embodiment of the present invention, the display substrate includes a passivation layer and a gate insulating layer that are sequentially stacked, the first connection line is located on a surface of the gate insulating layer and covered by the passivation layer, the signal line is located in the gate insulating layer, the first via hole sequentially penetrates through the passivation layer and the gate insulating layer to reach the surface of the signal line, and the second via hole penetrates through the passivation layer to reach the surface of the first connection line.
In an implementation manner of the embodiment of the present invention, a distance between the first via and the second via is 100-600 μm.
In an implementation manner of the embodiment of the present invention, the signal line is a GOA signal line or a Source signal line.
In an implementation manner of the embodiment of the present invention, a fracture is formed on the first connection line, and the first connection lines on two sides of the fracture are electrically connected through the second conductive layer.
In an implementation manner of the embodiment of the present invention, the second conductive layer is located below the first connection line and is respectively overlapped with the first connection lines on two sides of the fracture; or the second conducting layer is filled in the fracture.
In an implementation manner of the embodiment of the present invention, the fracture is located right above the gate line, and a width of the fracture is greater than a width of the gate line.
In an implementation manner of the embodiment of the present invention, the display substrate further includes an electrical test area, and the electrical test area is electrically connected to the first connection line.
In an implementation manner of the embodiment of the present invention, the display substrate includes an IC output bonding area, a signal line, an IC input bonding area, an FPC bonding area, and an electrical test area, which are sequentially arranged from the middle portion to the left and right sides, the electrical test area is electrically connected to the signal line through the first connection line, and the IC input bonding area and the FPC bonding area are located on the same side of the first connection line.
In an implementation manner of the embodiment of the present invention, a cutting line for cutting off the electrical test area is formed between the FPC bonding area and the electrical test area, and a distance between the cutting line and the signal line is greater than 3 mm.
In order to achieve the above object, according to a second aspect of the embodiments of the present invention, there is also provided a display panel including the display substrate according to the first aspect of the embodiments of the present invention.
In order to achieve the above object, according to a third aspect of the embodiments of the present invention, there is also provided a display device including the display panel according to the second aspect of the embodiments of the present invention.
The display substrate provided by the embodiment of the invention is used for connecting a first connecting line connected with an electrical test area and a signal line through a first through hole, a second through hole and a first conductive layer, is not directly connected with an IC binding area, after the first connecting line is cut off to generate a breakpoint, the corrosion trend of the external environment can be blocked by the first through hole and the second through hole which are separately arranged, and the material of the first conductive layer has better corrosion resistance compared with the first connecting line, so that the reliability test of a product is ensured to pass.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and their description illustrate the embodiments of the invention and do not limit it. In the drawings:
FIG. 1 is a schematic diagram of a layout area of a display panel according to the related art;
FIG. 2 is a schematic diagram of another layout area of a display panel according to the related art;
FIG. 3 is a sectional plan view of a display panel according to an embodiment of the present invention;
FIG. 4 is a plan view of a wiring region of a display panel according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of a connection region of a first connection line and a signal line according to embodiment 1 of the present invention;
fig. 6 is a first cross-sectional view of a first fracture region of a connection line provided in embodiment 2 of the present invention;
fig. 7 is a second cross-sectional view of a fracture region of a first connection line provided in embodiment 2 of the present invention;
fig. 8 is a third cross-sectional view of a fracture region of a first connecting line provided in embodiment 2 of the present invention; and
fig. 9 is a wiring structure diagram of a metal basic wiring area provided in embodiment 3 of the present invention.
In the figure:
1. a first connecting line; 2. an electrical test area; 3. a signal line; 4. a first via hole; 5. a second via hole; 6. a first conductive layer; 7. a passivation layer; 8. a gate insulating layer; 9. breaking off; 10. a second conductive layer; 11. a gate line; 12. an IC output binding region; 13. an IC input binding area; 14. an FPC bonding area; 15. cutting a line; 16. a substrate.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the above-described drawings are intended to cover non-exclusive inclusions, such that a system, product or apparatus that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such product or apparatus.
In this application, the terms "upper", "lower", "inner", "middle", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.
Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.
Furthermore, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Fig. 1 is a schematic design diagram of a display substrate DP side of a conventional display product in the related art, in which a lower area (not shown) of the DP side is a display area of the display substrate, electrical test areas are located at two sides of an IC bonding area, and an FPC bonding area is disposed at one side of the IC bonding area away from the display area. The FPC binding area and the IC binding area in the plane layout structure are longitudinally arranged, so that the frame on the DP side is larger and far larger than the frames on the left side and the right side of the display substrate.
In order to solve the problem that the side frame of the display substrate in the wiring mode DP in fig. 1 is too wide, a double-side wiring design as shown in fig. 2 is adopted in the related art, wherein the peripheral region of the display substrate includes an IC output bonding region, a GOA signal line, an IC input bonding region and an FPC bonding region which are sequentially arranged from the middle part to the left and right sides, the electrical test region is located on one side of the IC input bonding region and the FPC bonding region away from the display region, the electrical test region is connected with the GOA signal line through a test signal line, after the electrical test is completed, the electrical test region is cut along a cutting line (cutting) in fig. 2, and a bare test signal line exists at the cutting line, so that the test signal line directly contacts with a water-oxygen environment to be corroded in the reliability test, and further causes a risk that the GOA signal line is corroded. Through the statistics of the actual product routing corrosion length, the farthest corrosion distance is larger than 1.2mm, and the reliability of the product is seriously influenced.
In order to solve the related art problems, the present invention provides the following embodiments 1 to 3, in order to reduce the risk that the GOA signal line directly connected to the test signal line is corroded due to direct contact with the water-oxygen environment when the test signal line is exposed after the electrical test area is cut off in the related art.
Example 1
As shown in fig. 3, the display substrate provided in the embodiment of the invention includes a display area and a peripheral area, and the improvement point of the embodiment is to improve the structure of the peripheral area, and is particularly suitable for improving the layout design of the DP side of the peripheral area.
As shown in fig. 4 and 5, the peripheral area includes a first connection line 1 and a signal line 3, the signal line 3 is used for connecting with a driving circuit, one end of the first connection line 1 is used for connecting with the electrical test area 2, and the other end is used for connecting with the signal line 3. The display substrate is provided with a first through hole 4, a first connecting line and a second through hole 5, and the first through hole 4 and the second through hole 5 are in orthographic projection non-overlapping areas on the display substrate. The display substrate is further provided with a first conducting layer 6, the first conducting layer 6 is electrically connected with the signal line 3 through the first via hole 4, and the first conducting layer 6 is electrically connected with the first connecting line 1 through the second via hole 5.
In the above embodiment, the first connection line 1 for connecting with the electrical test area 2 and the signal line 3 are connected through the first via hole 4, the second via hole 5 and the first conductive layer 6, and are not directly connected with the IC bonding area 14, after the first connection line 1 is cut, the corrosion tendency of the external environment is blocked by the first via hole 4 and the second via hole 5 which are separately arranged, and generally, the first connection line 1 is made of metal, and the first conductive layer 6 has better corrosion resistance than the first connection line 1, so as to ensure that the reliability test of the product passes. The material of the first conductive layer 6 is selected from a metal oxide having a better resistance to water-oxygen corrosion than metal, such as at least one of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), Indium Gallium Oxide (IGO), or Aluminum Zinc Oxide (AZO), and preferably Indium Tin Oxide (ITO).
As shown in fig. 5, the display substrate includes a passivation layer 7, a gate insulating layer 8 and a substrate 16 stacked in sequence, the first connection line 1 is located on a surface of the gate insulating layer 8 and covered by the passivation layer 7, the signal line 3 is located on a surface of the substrate 16 and covered by the gate insulating layer 8, the first via hole 4 sequentially penetrates through the passivation layer 7 and the gate insulating layer 8 to a surface of the signal line 3, and the second via hole 5 penetrates through the passivation layer 7 to a surface of the first connection line 1.
Wherein the thickness of the gate insulating layer 8 is preferably
The gate insulating layer 8 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer; wherein the thickness of the passivation layer 7 is preferably
The passivation layer 7 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.
On the basis of the above embodiments, the distance between the first via 4 and the second via 5 is 100-600 μm. The adjustment can be specifically performed according to the trend relationship between the first connection line 1 and the signal line 3, generally, the first connection line 1 and the signal line 3 are orthogonally arranged in the via hole connection region, when the first connection line 1 is connected with the nearest signal line 3 through a via hole, the distance between the first via hole 4 and the second via hole 5 can be controlled to be about 100 μm, and when the first connection line 1 is connected with the farthest signal line 3 through a via hole, the distance between the first via hole 4 and the second via hole 5 can be controlled to be about 600 μm. In the design, the connection distance between the first connection line 1 and the signal line 3 is far greater than the distance 10 μm of the conventional via hole, so that the conductivity and corrosion resistance of the first conductive layer 6 can be fully exerted, the corrosion resistance of the first connection line 1 is further increased, and the reliability of the device product is improved.
In the above embodiments, the signal line 3 for connecting with the first connecting line 1 through a via may be a GOA signal line or a Source signal line. In the display substrate, if the first connection line 1 connected to the GOA signal line is cut off at the cutting stage to generate corrosion exposed points, the first connection line 1 and the GOA signal line are connected through the first via 4, the second via 5 and the first conductive layer 6 in the above embodiments, and the first via 4 penetrates through the surface of the GOA signal line; in the display substrate, if the first connection line 1 connected with the Source signal line is cut off at the cutting stage to generate corrosion exposed points, the first connection line 1 and the Source signal line are connected through the first via 4, the second via 5 and the first conductive layer 6 in the above embodiment, and the first via 4 penetrates through the surface of the Source signal line; in the display substrate, if the first connection line 1 connected to the Source signal line and the first connection line 1 connected to the GOA signal line are both cut at the cutting stage to generate corrosion exposed points, the first connection line 1 and the Source signal line, and the first connection line 1 and the GOA signal line are connected through the first via 4, the second via 5, and the first conductive layer 6 in the above embodiments.
In the above embodiment, in order to facilitate the deposition of the first conductive layer 6 on the device surface, the hole walls of the first via 4 and the second via 5 are preferably arranged obliquely, as shown in fig. 6, the width of the first via 4 is gradually expanded in the direction away from the signal line 3, so as to form a structure with a wide opening and a narrow bottom; similarly, the width of the second via 5 is gradually widened in a direction away from the first connection line 1, resulting in a structure having a wide opening and a narrow bottom. Wherein, the ratio of the top width of the first via hole 4 to the bottom width of the first via hole 4 is (1.5-2): 1, the ratio of the top width of the second via hole 5 to the bottom width of the second via hole 5 is (1.05-1.2): 1, for example, the top width of the first via 4 is 10.5 μm, the bottom width of the first via 4 is 5.5 μm, the top width of the second via 5 is 10.5 μm, and the bottom width of the second via 5 is 9.5 μm.
Example 2
As shown in fig. 3, the display substrate provided in the embodiment of the invention includes a display area and a peripheral area, and the improvement point of the embodiment is to improve the structure of the peripheral area, and is particularly suitable for improving the layout design of the DP side of the peripheral area.
As shown in fig. 4 and 6 to 8, the peripheral area includes a first connection line 1 and a signal line 3, the signal line 3 is used for connecting with a driving circuit, one end of the first connection line 1 is used for connecting with the electrical test area 2, and the other end thereof is used for connecting with the signal line 3. The first connecting line 1 is shaped upwardA fracture 9 is formed, and the first connecting lines 1 on two sides of the fracture 9 are electrically connected through a second conductive layer 10. The material of the second conductive layer 10 may be selected from metal oxides with better resistance to water and oxygen corrosion than metals, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), and indium oxide (In)2O3) At least one of Indium Gallium Oxide (IGO) or Aluminum Zinc Oxide (AZO), preferably Indium Tin Oxide (ITO).
In the above embodiment, the first connection line 1 for connecting with the electrical test area 2 is broken at the fracture 9 and connected through the second conductive layer 10 with stronger corrosion resistance, after the first connection line 1 is cut off, the corrosion trend of the external environment is blocked by the fracture 9, and the corrosion trend can be slowed down or prevented from extending across the fracture 9, so as to ensure that the reliability test of the product passes.
As shown in fig. 6 to 8, the display substrate includes a passivation layer 7, a gate insulating layer 8 and a substrate 16, which are sequentially stacked, the first connection line 1 is located on a surface of the gate insulating layer 8 and covered by the passivation layer 7, and the fracture 9 sequentially penetrates through the passivation layer 7 and the first connection line 1 to a surface of the gate insulating layer 8. Wherein the thickness of the gate insulating layer 8 is preferably
The gate insulating layer 8 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer; wherein the thickness of the passivation layer 7 is preferably
The passivation layer 7 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.
In the above embodiments, the specific arrangement form of the second conductive layer 10 may be two. Alternatively, as shown in fig. 6, the second conductive layer 10 is filled in the fracture 9, and has a bottom surface and a top surface both flush with the first connection line 1, a bottom formed on the gate insulating layer 8, and a top covered by the passivation layer 7; alternatively, as shown in fig. 7, the second conductive layer 10 is located below the first connection line 1 and overlaps the first connection lines 1 on both sides of the fracture 9, respectively, and the fracture 9 is filled with the passivation layer 7. The two embodiments do not have any essential influence on the purpose and effect of the invention, and those skilled in the art can specifically define the embodiments according to the needs and design requirements, and from the viewpoint of the manufacturing process, it is preferable to adopt the configuration of the second conductive layer 10 as shown in fig. 7, and after the fracture 9 is formed by etching, the passivation layer 7 is directly formed without depositing metal oxide again, so that the manufacturing process is simpler.
In some embodiments, as shown in fig. 8, there is a crossing between the gate line 11 and the first connection line 1 of the display substrate, where the break 9 is located right above the gate line 11, and the width of the break 9 is greater than the width of the gate line 11. The purpose of this embodiment is to avoid the first connecting line 1 and the gate line 11 from having an overlapping area in the routing design of the peripheral region, and to prevent an electrostatic Discharge (ESD) problem, in this design, the second conductive layer 10 is used to connect the first connecting lines 1 at two ends of the fracture 9, so that on one hand, corrosion can be delayed, and on the other hand, overlapping of the first connecting line 1 and the gate line 11 can be avoided. Preferably, the width of the gate line 11 is 50-150 μm, the width of the break 9 is 100-.
Example 3
As shown in fig. 3 and 9, the display substrate provided in the embodiment of the invention includes a display area and a peripheral area, and the improvement point of the embodiment is to improve the structure of the peripheral area, and is particularly suitable for improving the layout design of the peripheral area DP side.
The peripheral area of the display substrate comprises an IC output binding area 12, a signal wire 3, an IC input binding area 13, an FPC binding area 14 and an electrical test area 2 which are sequentially arranged from the middle part to the left side and the right side, wherein the electrical test area 2 is electrically connected with the signal wire 3 through the first connecting wire 1, and the IC input binding area 13 and the FPC binding area 14 are located on the same side of the first connecting wire 1. As shown in fig. 9, the wirings are formed to be symmetrically arranged in the left-right direction.
In the wiring manner in the above embodiment, the electrical detection regions are respectively located at the left and right ends of the wiring region, and do not need to occupy the space in the vertical direction, and can be applied to the DP side of the display substrate, thereby significantly reducing the frame width of the DP side.
Specifically, a cutting line 15 for cutting off the electrical test area 2 is formed between the FPC bonding area 14 and the electrical test area 2, electrical performance detection can be performed through the electrical test area 2 after the single panel is attached, and after the detection is completed, the electrical test area 2 can be cut off along the cutting line 15, so that the size of the frame is further reduced. Because set up electricity test area 2 both ends about the peripheral region alone, electricity test area 2 only is connected with the GOA signal line through first connecting wire 1 usually, and at the in-process of excision electricity detection area, first connecting wire 1 is cut off, and the corruption of breakpoint department only can lead to the fact the influence to the GOA signal line, and can not influence the Source line, and the different apparent risk that the corruption leads to can reduce some. In contrast to the layout of fig. 2, the cutting line 15(cutting) cuts off the GOA signal line and also cuts off the Source trace (not shown), which results in a higher corrosion risk.
In this embodiment, since the IC input bonding area 13 and the FPC bonding area 14 are located on the same side of the first connecting line 1, that is, the IC input bonding area 13 and the FPC bonding area 14 are integrally arranged side by side with the first connecting line 1, the distance between the cutting point of the first connecting line 1 and the signal line 3 can reach at least 3mm due to the physical size space existing in the left-right direction of the IC input bonding area 13 and the FPC bonding area 14, and the size is far greater than the farthest corrosion distance shown in the drawing in the related art, so that the corrosion resistance effect can be significantly enhanced. In the related art wiring manner shown in fig. 2, since the electrical detection area and other areas are vertically arranged, in order to reduce the width of the frame, the distance of the cut GOA wiring is only less than 0.2mm, and the GOA wiring cannot withstand the corrosion of the environment.
It should be noted that the technical solutions in the above embodiments 1 to 3 of the present invention are not isolated, and can be combined with each other to improve the reliability of the display panel, for example, in the display panel, the first connecting line 1 and the signal line 3 can be connected through the first via 4, the second via 5 and the first conductive layer 6 in embodiment 1, on the one hand, and the first connecting line 1 can be separated through the break 9 in embodiment 2, on the other hand, and the wiring layout form in embodiment 3 can be adopted.
The embodiment of the invention also provides a display panel and a display device, wherein the display panel adopts the display substrate provided by the embodiment of the invention.
The display panel comprises a display substrate and a packaging cover plate. The display substrate is provided in the above embodiments of the present invention, and may include a driving substrate, a pixel defining layer formed on the driving substrate, a light emitting layer formed on the pixel defining layer, and a top electrode formed on the light emitting layer.
The display device provided by the embodiment of the application can be as follows: any product or component with a display function, such as a liquid crystal panel, electronic paper, an Organic Light Emitting Diode (OLED) panel, an Active Matrix Organic Light Emitting Diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator. The display device disclosed in the embodiment of the present application includes the display substrate provided in the above embodiment, so that the display panel and the display device having the display substrate also have all the above technical effects, and are not described in detail herein. Other configurations, principles, and methods of making display panels and display devices will be known to those of ordinary skill in the art and will not be described in detail herein.
Some embodiments in this specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A display substrate comprises a display area and a peripheral area, and is characterized in that the peripheral area comprises first connecting lines and signal lines connected with a driving circuit, and one end of each first connecting line is used for being connected with an electrical test area;
the display substrate is provided with a first via hole, a second via hole and a first conducting layer, the first via hole and the second via hole are in an orthographic projection non-overlapping area on the display substrate, the first conducting layer is electrically connected with the signal line through the first via hole, and the first conducting layer is electrically connected with the first connecting line through the second via hole.
2. The display substrate according to claim 1, wherein the display substrate comprises a passivation layer and a gate insulating layer which are sequentially stacked, the first connection line is located on a surface of the gate insulating layer and covered by the passivation layer, the signal line is located in the gate insulating layer, the first via hole sequentially penetrates through the passivation layer and the gate insulating layer to a surface of the signal line, and the second via hole penetrates through the passivation layer to a surface of the first connection line.
3. The display substrate of claim 1, wherein the distance between the first via and the second via is 100-600 μm.
4. The display substrate according to claim 1, wherein the signal line is a GOA signal line or a Source signal line.
5. The display substrate according to claim 1, wherein a break is formed in the first connecting line, and the first connecting lines on both sides of the break are electrically connected to each other through the second conductive layer.
6. The display substrate of claim 5,
the second conducting layer is located below the first connecting line and is respectively lapped with the first connecting lines on two sides of the fracture; or
The second conductive layer is filled in the fracture.
7. The display substrate according to claim 5, wherein the discontinuity is located right above the gate line, and a width of the discontinuity is greater than a width of the gate line.
8. The display substrate according to any one of claims 1 to 7, further comprising an electrical test area electrically connected to the first connection line.
9. The display substrate according to claim 8, comprising an IC output bonding area, a signal line, an IC input bonding area, an FPC bonding area and an electrical test area which are sequentially arranged from the middle part to the left and right sides, wherein the electrical test area is electrically connected with the signal line through the first connecting line, and the IC input bonding area and the FPC bonding area are located on the same side of the first connecting line.
10. The display substrate according to claim 9, wherein a cutting line for cutting off the electrical test area is formed between the FPC bonding area and the electrical test area, and a distance between the cutting line of the first connection line and the signal line is greater than 3 mm.
11. A display panel comprising the display substrate according to any one of claims 1 to 10.
12. A display device characterized by comprising the display panel according to claim 11.
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| CN202110837151.2A CN113437095A (en) | 2021-07-23 | 2021-07-23 | Display substrate, display panel and display device |
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| CN202110837151.2A CN113437095A (en) | 2021-07-23 | 2021-07-23 | Display substrate, display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023070574A1 (en) * | 2021-10-29 | 2023-05-04 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method therefor, and display apparatus |
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