CN117395867A - Technological method for easily identifying drilling surface times and Stub values of back of PCB - Google Patents

Technological method for easily identifying drilling surface times and Stub values of back of PCB Download PDF

Info

Publication number
CN117395867A
CN117395867A CN202311187496.3A CN202311187496A CN117395867A CN 117395867 A CN117395867 A CN 117395867A CN 202311187496 A CN202311187496 A CN 202311187496A CN 117395867 A CN117395867 A CN 117395867A
Authority
CN
China
Prior art keywords
copper
pcb
back drilling
layer
drilling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311187496.3A
Other languages
Chinese (zh)
Inventor
段李权
许士玉
李星
李春斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiuyang Sunshine Pcb Technology Co ltd
Shenzhen Sunshine Circuit Technology Co ltd
Original Assignee
Jiuyang Sunshine Pcb Technology Co ltd
Shenzhen Sunshine Circuit Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiuyang Sunshine Pcb Technology Co ltd, Shenzhen Sunshine Circuit Technology Co ltd filed Critical Jiuyang Sunshine Pcb Technology Co ltd
Priority to CN202311187496.3A priority Critical patent/CN117395867A/en
Publication of CN117395867A publication Critical patent/CN117395867A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047—Drilling of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Drilling And Boring (AREA)

Abstract

The invention discloses a process method for easily identifying the back drilling surface times and the Stub values of a PCB (printed circuit board), which comprises a grouping group, wherein all back drills with the same surface times are intensively placed from shallow to deep according to the back drilling depth, and all back drills are grouped into a module; copper is drawn by back drills, copper is drawn by each back drill of the back drill module from the initial layer to the target layer, and the diameter of the copper is larger than that of a back drill bit; copper is paved on each layer, copper PAD is paved from each back drilling module to the rest layers, and the size of the back drilling module is larger than the diameter of a back drilling bit; copper is paved on the surface layer, and a copper PAD with the diameter larger than that of the via hole is arranged on the initial layer of the back drilling module; and setting a mark, wherein each back drill of the back drill module is provided with a corresponding target layer mark near the initial layer. The invention solves the problem of judgment errors caused by difficult resolution of the back drilling surface times and the Stub values of the PCB in the prior art.

Description

Technological method for easily identifying drilling surface times and Stub values of back of PCB
Technical Field
The invention relates to the field of PCB back drilling, in particular to a process method for easily identifying the back drilling surface times and the Stub values of a PCB.
Background
One of the challenges facing PCB design and manufacture is how to protect signal integrity issues. The backdrilling, also known as controlled depth drilling, is used to remove conductive via stubs of copper cans in PCB vias. As part of the via, the stub can lead to severe signal integrity in high speed designs.
At present, high-speed boards have signal integrity requirements, so most high-speed boards have back drilling technology, back drilling has surface quality requirements, namely, the back drilling is carried out from an initial layer to a target layer, and the back drilling needs to be controlled to a Stub value without drilling through the layer, the conventional monitoring mode is slicing, the back drilling surface quality is difficult to distinguish by slicing, or surface quality is easy to be confused, so that judgment errors are caused.
In view of this, the technical scheme provides a process method for easily identifying the back drilling surface times and the Stub values of the PCB, which can enable the back drilling process and the quality to be more convenient and visual to observe, and can easily identify the back drilling surface times and the Stub values.
Disclosure of Invention
The technical scheme aims to solve one of the technical problems in the related technology at least to a certain extent. Therefore, the main purpose of the present invention is to provide a process method for easily identifying the back drilling level and the Stub value of a PCB board, which aims to solve the problem of erroneous determination caused by the difficulty in distinguishing the back drilling level and the Stub value of the PCB in the prior art.
In order to achieve the above object, the present invention provides a process for easily identifying the back drilling surface times and Stub values of a PCB board, comprising the steps of,
grouping the collection: centralizing the back drills with the same surface times according to the depth of the back drills from shallow to deep, and centralizing the back drills into a module;
back drilling copper drawing: copper is drawn from the initial layer to the target layer by each back drill of the back drill module, and the diameter of the copper is larger than that of a back drill bit;
copper is paved on each layer: copper PAD is paved from the non-drilled layer to the rest layers of the back drilling module, and the size of the copper PAD is larger than the diameter of a back drilling bit;
copper is spread on the surface layer: the initial layer of the back drilling module is provided with copper PAD with the diameter larger than that of the via hole;
setting an identification: and each back drill of the back drill module is provided with a corresponding target layer mark near the initial layer.
As a still further aspect of the invention, in the back drilling copper scooping step, the copper scooping diameter is 0.8mmm larger than the back drilling bit diameter.
As a still further aspect of the invention, in each layer copper laying step, the copper PAD is not laid from layer to the rest of all layers by a size 0.4mm larger than the diameter of the back drill bit.
As a still further aspect of the invention, in the blanket copper step, the copper PAD diameter is 0.1mm greater than the via diameter.
As a still further aspect of the invention, the copper PAD laid down each not drilled to the layer to all remaining layers is a solid copper PAD.
As a still further proposal of the invention, after the marking step, the back drilling setting of the PCB is carried out, and the back drilling setting step of the PCB is as follows:
and back drilling modules are respectively arranged at four corners of the PNL board of the PCB board, and the cutting safety distance is reserved.
As still further aspects of the present invention, in the PCB back drill setting step, the back drill module is set to a position close to the finished product position.
As a still further proposal of the invention, in the PCB back drilling setting step, the reserved cutting slice safety distance is 5mm-8mm.
As still further aspects of the present invention, in the step of setting the identification, the set target layer identification is an identification aperture formed in the PNL board of the PCB.
As a still further aspect of the invention, in the step of setting the indicia, the apertures are provided with a diameter less than the diameter of the backdrill bit.
The beneficial effects of the invention are as follows:
according to the technical method for easily identifying the back drilling surface times and the Stub values of the PCB, the back drilling is arranged according to the surface times and the back drilling depths, copper is drawn out, copper is paved to the through holes, and finally the marks are distinguished, so that the back drilling surface times which are easily confused originally are easy to distinguish, accurate distinction can be carried out after slicing, and the problem of error judgment of the back drilling surface times is greatly reduced. In addition, the quality of back drilling and the value of back drilling Stub are also convenient to intuitively identify, and the problem of incomplete appearance of subsequent processing of the high-speed plate is avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the inventions in the prior art, the following description will briefly explain the embodiments or the drawings needed in the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the technical solutions of the present invention, and other drawings can be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the implementation steps of the scheme of the invention.
Fig. 2 is a schematic cross-sectional view of a partial structure of a back drilling module according to the present invention.
FIG. 3 is a graph of the back drilling modules and Stub values of the present invention after slicing.
FIG. 4 is a graph showing the diameter and Stub values of back drills after slicing and back drills of another embodiment of the present invention.
Detailed Description
The following are provided:
referring to figures 1-3 of the drawings,
the method comprises the following steps of: centralizing the back drills with the same surface times according to the depth of the back drills from shallow to deep, and centralizing the back drills into a module; back drilling copper drawing: copper is drawn from the initial layer to the target layer by each back drill of the back drill module, and the diameter of the copper is larger than that of a back drill bit; copper is paved on each layer: copper PAD is paved from the non-drilled layer to the rest layers of the back drilling module, and the size of the copper PAD is larger than the diameter of a back drilling bit; copper is spread on the surface layer: the initial layer of the back drilling module is provided with copper PAD with the diameter larger than that of the via hole; setting an identification: and each back drill of the back drill module is provided with a corresponding target layer mark near the initial layer. In the PCB back drilling setting step, the set back drilling module is close to the finished product position.
Explanation of working principle:
why will there be Stub (also called Stub, etc.)? Because there are always more wire stubs than there are wires in the design of the PCB, and there are also some cases where there are potentially open stubs, namely stubs (or so-called Stub wires), which are generally not allowed to occur, and the extra stubs may cause antenna radiation effects, seriously cause signal reflection, and finally, signal integrity problems.
Therefore, it is necessary to eliminate these Stub by technical means. The current method is to drill the stumps from the initial layer to the target layer by back drilling, and in the drilling process, the numerical value of "no-drill-through layer" (namely, the Stub value) needs to be controlled to prevent drill-through. While this machining method requires "monitoring", the current monitoring method is slicing (which can be understood as slicing sampling), the slicing method is inconvenient for people to distinguish the back drilling surface (for example, L1-L10 in FIG. 2 is one surface, L10-L1 is one surface, and the like, because some machining sequences can be reversed, for example, one surface of L1-L10 is drilled from top to bottom, and one surface of L10-L1 is drilled from bottom to top), and thus the machining methods are easy to confuse.
According to the technical scheme, the back drilling module is manufactured in the mode, after slicing, whether the surface is correct or not can be judged at a glance, layers are not drilled, the number of layers is not needed, measurement of the Stub is also convenient, the layers are not staggered, the surface is not drilled, and convenience is provided for production operation, quality and judgment. The modular design firstly arranges the back drills of the same surface level according to the depth sequence to form a module, and then carries out copper drawing (namely copper reduction and copper drawing) operation, wherein the copper drawing is carried out from an initial layer (a surface layer or a bottommost layer) to a target layer (a layer needing to be eliminated). After copper is drawn out from the target layer, the distance between the drill bit and the nearest layer (without drilling to the layer) is Stub, and the Stub value is the Stub value. At this time, copper PADs (copper PAD) may be deposited without drilling the layers until all the remaining layers are reached, and then the initial layer may be provided with copper PADs (copper PAD) slightly larger than the via holes (0.1 mm).
And finally, adding marks after back drilling copper digging and copper laying are completed. The identifier is an "information symbol" that facilitates quick identification, and the "information symbol" is represented by a target layer, such as 1-8, 1-9, 1-10.. . Or 24-6, etc. The modularized back drilling process is completed, and then back drilling of all corners of the PCB can be performed. In the step of setting the identification, the set target layer identification is an identification small hole formed on the PNL board of the PCB. The diameter of the small hole is smaller than that of the back drill bit. The reason for the small holes is that they can be "knocked out" in subsequent backdrilling processes, merging with existing backdrilling.
In a preferred embodiment of the invention: in the back drilling copper drawing step, the diameter of copper drawing is 0.8mmm larger than that of a back drill bit.
If the diameter of the copper scooping is equal to the diameter of the back drill bit or the diameter of the copper scooping is smaller than the diameter of the back drill bit, the problem of copper deficiency can occur when the back drill scoops copper.
In a preferred embodiment of the invention: in each layer copper laying step, the size of each copper PAD laid from layer to the rest of all layers is 0.4mm larger than the diameter of the back drill bit.
In a preferred embodiment of the invention: in the blanket copper step, the copper PAD diameter is 0.1mm greater than the via diameter.
If the copper PAD diameter is equal to the via diameter, or the copper PAD diameter is smaller than the via diameter, then the copper deficiency problem occurs during back drilling.
In a preferred embodiment of the invention: the copper PAD laid down each not drilled into the layer to all the remaining layers is solid copper PAD.
In a preferred embodiment of the invention: after the marking step, the back drilling setting of the PCB is carried out, and the back drilling setting step of the PCB is as follows:
and back drilling modules are respectively arranged at four corners of the PNL board of the PCB board, and the cutting safety distance is reserved. In the PCB back drilling setting step, the reserved cutting slice safety distance is 5mm-8mm.
The safe distance of 5mm-8mm can prevent the layers on one side from being cut by mistake during slicing.
The foregoing description is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the scope of the technical solution of the present invention, and all the equivalent structural changes made by the technical solution description and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the technical solution of the present invention.

Claims (10)

1. A process method for easily identifying drilling surface times and Stub values of a back surface of a PCB board is characterized by comprising the following steps,
s1, grouping the collection groups:
centralizing the back drills with the same surface times according to the depth of the back drills from shallow to deep, and centralizing the back drills into a module;
s2, back drilling copper drawing:
copper is drawn from the initial layer to the target layer by each back drill of the back drill module, and the diameter of the copper is larger than that of a back drill bit;
s3, copper is paved on each layer:
copper PAD is paved from the non-drilled layer to the rest layers of the back drilling module, and the size of the copper PAD is larger than the diameter of a back drilling bit;
s4, copper is paved on the surface layer:
the initial layer of the back drilling module is provided with copper PAD with the diameter larger than that of the via hole;
s5, setting a mark:
and each back drill of the back drill module is provided with a corresponding target layer mark near the initial layer.
2. The process for easily identifying back drilling surface times and Stub values of a PCB according to claim 1, wherein in the back drilling copper drawing step of S2, the copper drawing diameter is 0.8mmm larger than the back drilling bit diameter.
3. The process for easily identifying back drilling surface times and Stub values of a PCB according to claim 1, wherein in each layer copper laying step of S3, the size of each copper PAD laid from layer to the rest of all layers is 0.4mm larger than the diameter of the back drill bit.
4. The process for easily identifying the back drilling level and the Stub value of the PCB according to claim 1, wherein in the step of surface layer copper laying in S4, the diameter of copper PAD is 0.1mm larger than the diameter of the via hole.
5. The process for easily identifying back drilling level and Stub values of a PCB according to claim 1, wherein the copper PAD laid from each not drilled layer to all remaining layers is a solid copper PAD.
6. The process method for easily identifying the back drilling surface times and the Stub values of the PCB according to claim 1, wherein the back drilling setting of the PCB is performed after the step of setting the identification in S5, and the step of setting the back drilling of the PCB is as follows:
s6, back drilling modules are respectively arranged at four corners of the PNL board of the PCB board, and the cutting safety distance is reserved.
7. The method for easily identifying PCB back drilling surface times and Stub values according to claim 6, wherein in the step of setting PCB back drilling of S6, the set back drilling module is located close to the finished product.
8. The process method for easily identifying the back drilling surface times and the Stub values of the PCB according to claim 6, wherein in the step of setting the back drilling of the PCB in S6, the reserved safe distance for slicing is 5mm-8mm.
9. The process for easily identifying the back drilling level and the Stub value of the PCB according to claim 1, wherein in the step of setting the identification in S5, the set target layer identification is an identification small hole formed on the PNL board of the PCB.
10. The process for easily identifying the back drilling surface times and the Stub values of the PCB according to claim 1, wherein in the step of setting the identification of S5, the diameter of the set small hole is smaller than the diameter of the back drill bit.
CN202311187496.3A 2023-09-14 2023-09-14 Technological method for easily identifying drilling surface times and Stub values of back of PCB Pending CN117395867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311187496.3A CN117395867A (en) 2023-09-14 2023-09-14 Technological method for easily identifying drilling surface times and Stub values of back of PCB

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311187496.3A CN117395867A (en) 2023-09-14 2023-09-14 Technological method for easily identifying drilling surface times and Stub values of back of PCB

Publications (1)

Publication Number Publication Date
CN117395867A true CN117395867A (en) 2024-01-12

Family

ID=89436336

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311187496.3A Pending CN117395867A (en) 2023-09-14 2023-09-14 Technological method for easily identifying drilling surface times and Stub values of back of PCB

Country Status (1)

Country Link
CN (1) CN117395867A (en)

Similar Documents

Publication Publication Date Title
CN103533761B (en) A kind of preparation method that promotes pcb board back of the body borehole accuracy
CN101547561A (en) Closed loop backdrilling system
US9426902B2 (en) Printed circuit board, and method and apparatus for drilling printed circuit board
CN110475432B (en) PCB and manufacturing and back drilling method thereof
CN105430913B (en) A kind of boring method of printed circuit board
CN111935912B (en) Method for acquiring characteristic parameters of multilayer circuit board and drilling process data acquisition device
CN110893629B (en) Method for manufacturing circuit board and drilling machine
CN117395867A (en) Technological method for easily identifying drilling surface times and Stub values of back of PCB
CN109526135B (en) Circuit board reliability evaluation method
CN108024450B (en) Method for processing double-sided blind hole circuit board
CN114828424B (en) Method for improving back drilling alignment degree
CN112867266B (en) PCB grooving process method
CN113133226B (en) Circuit board high-precision back drilling method and circuit board
CN112399716A (en) Back drilling method and preparation method of PCB and prepared PCB
CN110662353B (en) Drilling quality evaluation method, drilling parameter determination method and circuit board
CN106507590B (en) The production method of base plate of plug hole
CN110708878A (en) Processing method of printed circuit board
CN112797887B (en) Depth test structure and method for back drilling hole layer of high-rise multilayer board
CN114559070B (en) Drilling method based on numerical control drilling machine and numerical control drilling machine
CN117560855B (en) PCB back drilling detection structure and manufacturing method and application thereof
CN112911791B (en) Printed circuit board for detecting deviation of drilling hole
WO1988004977A1 (en) Improved grinding guide and method
CN117279196A (en) Circuit board, circuit board drilling device and circuit board drilling method
CN112672502A (en) PCB (printed circuit board), deep forming processing method thereof and numerical control device
CN115474338A (en) Circuit board and back drilling processing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination