CN117390936B - Method and system for solving warpage of chip packaging reliability model - Google Patents
Method and system for solving warpage of chip packaging reliability model Download PDFInfo
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Abstract
The invention provides a method and a system for solving warpage of a chip packaging reliability model, which belong to the field of chip packaging simulation modeling, wherein the method comprises the following steps: taking the solder ball arrangement array between the actual substrate and the chip as a reference, keeping the size of the solder ball coverage surface, the volume occupied by the solder balls relative to the underfill and the height of the solder balls unchanged, increasing the volume of a single solder ball and the space between the solder balls, and obtaining a sparse equivalent solder ball arrangement array; constructing a chip packaging reliability model, and performing grid division on the chip packaging reliability model; establishing a quasi-static viscoelastic analysis step of numerical simulation, applying symmetrical constraint conditions, and loading temperature impact load; and solving the displacement of the chip packaging reliability model in the thickness direction under the temperature impact load by using a finite element analysis method, and obtaining the warpage of the chip packaging. According to the invention, the calculation time of the chip packaging reliability model is reduced by thinning the solder balls, and meanwhile, the calculation precision of the warpage can be ensured.
Description
Technical Field
The invention belongs to the field of chip package simulation modeling, and particularly relates to a method and a system for solving warpage of a chip package reliability model.
Background
At present, chip packages are increasingly integrated, high-density packages lead to the development of solder balls in a small and dense direction, and the chip packages warp due to the difference of thermal expansion coefficients of different materials, so that the problem of mechanical reliability of the chip packages is caused. The numerical simulation method can reduce the test cost of the product and shorten the design period.
The high-density chip packages the solder balls in a large number and small size, and the chip has larger size difference; if modeling is performed according to the structure size, the number of grids in finite element calculation is huge, and the number exceeds the limit of the current finite element software processing, so that the problem that the existing computer cannot submit calculation exists. Therefore, equivalent sparsification treatment is required to be carried out on the number of the chip package solder balls in the simulation model so as to meet the requirements of construction of the simulation model and efficient numerical calculation of the warping degree.
There are many equivalent processing methods of the solder ball model at present, such as global material homogenization, submodel, and local material homogenization. However, the sub-model method and the local material homogenizing method cannot effectively reduce the complexity of the simulation model, and the global material homogenizing method completely simplifies all solder balls and underfill, so that the simulation result and the real result have larger access, and therefore, a more accurate equivalent method of the solder balls is required when the warpage of the chip package is calculated.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a method and a system for solving the warpage of a chip package reliability model, realize quick numerical simulation of chip package, and solve the problems that the number of numerical simulation grids of high-density chip package is large, the calculation time is long, and even the warpage cannot be calculated by the existing computer.
In order to achieve the above object, in a first aspect, the present invention provides a method for solving warpage of a chip package reliability model, including the following steps:
the method comprises the steps of taking an array of solder balls arranged between an actual substrate and a chip as a reference, keeping the size of the coverage surface of the solder balls, the occupied volume of the solder balls relative to underfill and the height of the solder balls unchanged, increasing the volume of a single solder ball and the distance between the solder balls, and obtaining the array of solder balls arranged after sparse equivalence; wherein, the base plate is located at the bottom of the chip, the solder ball is surrounded by the underfill;
based on the sparse equivalent solder ball arrangement array, constructing a chip packaging reliability model, and performing grid division on the chip packaging reliability model;
establishing a quasi-static viscoelastic analysis step of numerical simulation, applying symmetrical constraint conditions and loading temperature impact load to the reliability model of the chip package after grid division;
solving the displacement of the chip packaging reliability model in the thickness direction under the temperature impact load by using a finite element analysis method to obtain the warpage of the chip packaging;
the chip packaging reliability model is a three-dimensional model for calculating the chip packaging reliability by simulating a chip packaging structure comprising a chip, a substrate, solder balls and underfill.
Further preferably, the volume of the individual solder balls after the thinning equivalent is:
wherein,thinning the volume of the equivalent single solder ball; />To sparsate the total volume of the equivalent pre-solder balls;Mthe number of the solder balls after the equivalent thinning;
the solder balls are equivalent to be cylindrical, and the diameters of the solder balls after the sparse equivalent are as follows:
wherein,dthe diameter of the equivalent solder ball is thinned;his the height of the solder balls.
Further preferably, the method for meshing the chip package reliability model specifically includes:
dividing solder balls and underfill in a chip packaging reliability model into hexahedral meshes, and dividing a chip and a substrate into hexahedral meshes; wherein, the single solder ball is divided into at least 4 layers, and each layer is provided with at least 8 hexahedral meshes; the underfill is divided into at least four layers of hexahedral meshes, and the hexahedral mesh nodes corresponding to the underfill and the hexahedral mesh nodes in the solder balls are subjected to joint coupling treatment.
Further preferably, the solder balls in the array of solder ball arrangements are uniformly and equidistantly arranged after the equivalent thinning.
In a second aspect, the present invention provides a system for solving warpage of a chip package reliability model, including:
the solder ball thinning processing module is used for taking the solder ball arrangement array between the actual substrate and the chip as a reference, keeping the size of the coverage surface of the solder balls, the occupied volume of the solder balls relative to the underfill and the height of the solder balls unchanged, increasing the volume of a single solder ball and the distance between the solder balls, and obtaining the solder ball arrangement array after thinning equivalence; wherein, the base plate is located at the bottom of the chip, the solder ball is surrounded by the underfill;
the initial construction module of the chip packaging reliability model is used for constructing the chip packaging reliability model based on the sparse equivalent solder ball arrangement array and performing grid division on the chip packaging reliability model;
the model parameter condition loading module is used for establishing a quasi-static viscoelastic analysis step of numerical simulation for the reliability model of the chip package after grid division, applying symmetrical constraint conditions and loading temperature impact load;
the warping degree calculation module is used for solving the displacement of the chip packaging reliability model in the thickness direction under the temperature impact load by using a finite element analysis method to obtain the warping degree of the chip packaging;
the chip packaging reliability model is a three-dimensional model for calculating the chip packaging reliability by simulating a chip packaging structure comprising a chip, a substrate, solder balls and underfill.
Further preferably, the volume of a single solder ball after the sparse equivalent in the solder ball sparse processing module is:
wherein,thinning the volume of the equivalent single solder ball; />To sparsate the total volume of the equivalent pre-solder balls;Mthe number of the solder balls after the equivalent thinning;
the solder balls are equivalent to be cylindrical, and the diameters of the solder balls after the sparse equivalent are as follows:
wherein,dthe diameter of the equivalent solder ball is thinned;his the height of the solder balls.
Further preferably, the method for meshing the chip package reliability model in the initial construction module of the chip package reliability model specifically includes:
dividing solder balls and underfill in a chip packaging reliability model into hexahedral meshes, and dividing a chip and a substrate into hexahedral meshes; wherein, the single solder ball is divided into at least 4 layers, and each layer is provided with at least 8 hexahedral meshes; the underfill is divided into at least four layers of hexahedral meshes, and the hexahedral mesh nodes corresponding to the underfill and the hexahedral mesh nodes in the solder balls are subjected to joint coupling treatment.
Further preferably, the solder balls in the solder ball arrangement array are uniformly and equidistantly arranged after the equivalent solder ball thinning in the solder ball thinning processing module.
In a third aspect, the present invention provides an electronic device comprising: at least one memory for storing a program; at least one processor for executing a memory-stored program, the processor being adapted to perform the method of the first aspect or any of the further preferred described methods of the first aspect when the memory-stored program is executed.
In a fourth aspect, the present invention provides a computer readable storage medium storing a computer program which, when run on a processor, causes the processor to perform the method of the first aspect or any of the further preferred described methods of the first aspect.
In a fifth aspect, the invention provides a computer program product which, when run on a processor, causes the processor to perform the method of the first aspect or any of the further preferred described methods of the first aspect.
It will be appreciated that the advantages of the second to fifth aspects may be found in the relevant description of the first aspect, and are not described here again.
In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:
the invention provides a method and a system for solving warpage of a chip packaging reliability model, wherein the size of a covered surface of a solder ball, the occupied volume of the solder ball relative to underfill and the height of the solder ball are kept unchanged, the volume of a single solder ball is increased, the solder ball is equivalent to be cylindrical, and the distance between the solder ball and the solder ball is increased, so that the density of hexahedral meshes is reduced and the total mesh number is reduced when numerical simulation is carried out; the calculation time of the numerical simulation is positively correlated with the grid quantity, so that the calculation time of the chip packaging reliability model can be reduced by performing sparsification equivalent on the solder balls, and the efficiency of the numerical simulation is improved; on the other hand, the number of the grids in the numerical simulation exceeds ten millions, and the numerical simulation cannot be performed beyond the calculation capability of the existing computer, so that the number of the grids is reduced, and the occurrence of incapability of performing the numerical simulation can be effectively avoided. Therefore, the invention provides a new solution for the numerical simulation of the chip package reliability model from the two aspects of feasibility and timeliness of the numerical simulation.
The invention provides a method and a system for solving warpage of a chip packaging reliability model, wherein the volume ratio of a solder ball is kept unchanged during the equivalent process, namely the ratio of the volume of the solder ball to the volume of underfill is kept unchanged, the thermal expansion coefficients of two materials are kept unchanged, and when the two materials are expanded or contracted by a temperature load, the contribution degree of the expansion amount and the contraction amount is unchanged from that before the equivalent process; in the prior art, the solder balls and the underfill are subjected to homogenization treatment, so that the influence of the solder balls is ignored, and the accuracy of a numerical simulation result of a chip packaging reliability model is reduced; by comparison, the invention can find that the warpage error under different temperature working conditions obtained by calculation is smaller by simplifying the number of the solder balls.
Drawings
FIG. 1 is a flow chart of a method for solving warpage of a chip package reliability model provided by an embodiment of the present invention;
FIG. 2 (a) is a diagram of solder ball distribution in a raw model provided by an embodiment of the present invention;
FIG. 2 (b) is a graph of solder ball distribution after the first sparsification model is sparse according to an embodiment of the present invention;
FIG. 2 (c) is a diagram of a distribution of solder balls after the second sparsification model is sparse according to an embodiment of the present invention;
FIG. 2 (d) is a diagram of a distribution of solder balls after the third sparse model is sparse according to an embodiment of the present invention;
FIG. 3 is a comparison chart of simulation results of warpage of an original model, a first sparse model, a second sparse model, a third sparse model and a material homogenization model provided by an embodiment of the present invention;
fig. 4 is a schematic diagram of a system for solving warpage of a chip package reliability model according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The terms "first" and "second" and the like in the description and in the claims are used for distinguishing between different objects and not for describing a particular sequential order of objects.
In embodiments of the invention, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
More specifically, the invention provides a method for solving warpage of a chip package reliability model, wherein solder balls are subjected to sparsification equivalent in the calculation of the warpage of the chip package reliability model, and the periphery of the solder balls in the chip package reliability model is completely filled with underfill. As shown in fig. 1, the method specifically comprises the following steps:
step 1: taking the solder ball arrangement array between the actual substrate and the chip as a reference, and carrying out sparsification treatment on the number of solder balls according to the constant volume ratio of the solder balls relative to underfill, so as to construct a chip packaging reliability model; the chip packaging reliability model is a three-dimensional model for calculating the chip packaging reliability by simulating a chip packaging structure comprising a chip, a substrate, solder balls and underfill;
more specifically, assume thatThe total volume of the solder balls and the underfill in the chip packaging reliability model is V, and the total volume of all the solder balls isThe number of the solder balls isNThe method comprises the steps of carrying out a first treatment on the surface of the If the model parameters are to be equivalent in the finite element, the equivalent solder ball total volume ratio is required to be equal, that is, the solder ball volume/(solder ball volume+underfill volume) is not changed, and the thinned equivalent solder ball total volume is +.>Assume that the number of solder balls after thinning is equivalent toMThe volume of the individual solder balls after thinning is:
after the volume of the solder ball is obtained, the solder ball is approximately equivalent to a cylinder, and the diameter of the thinned solder ball can be obtained as follows:
wherein,dis the diameter of the solder ball;his the height of the solder balls;
what should be explained here is: determining the size of the sparse solder ball coverage surface and the underfill coverage surface, keeping the height of the solder balls unchanged, and simplifying a three-dimensional model of the chip packaging reliability model by adopting the number of the sparse equivalent solder balls and the diameters of the solder balls; after the equivalent treatment is carried out, the total number of the solder balls is reduced, and the volume of a single solder ball is increased; the solder ball array changes from dense to relatively sparse, assuming that a single solder ball needs to be divided into a fixed number of cells (hexahedral mesh) in numerical simulationnCan meet the requirement of calculation precision,nif the value does not change with the change of the volume of the single solder ball, then when the total number of the solder balls is reduced, the number of units divided by all the solder balls is correspondingly reduced, so that the number of units of the whole chip package reliability model is reduced, and calculation is further causedThe amount is reduced, and the calculation rate is improved;
because the volume ratio of the solder ball is kept unchanged in the equivalent process, the ratio of the volume of the solder ball to the volume of the underfill is unchanged, and the thermal expansion coefficients of the two materials are kept unchanged, when the two materials expand or contract under the temperature load, the contribution degree of the expansion amount and the contraction amount is unchanged from that before the equivalent process; therefore, the method for solving the warpage based on the chip packaging reliability model with simplified solder ball quantity is adopted, and the warpage error under different temperature working conditions obtained by calculation is smaller;
step 2: performing grid division on the chip packaging reliability model after equivalent sparsification of the solder balls;
the method comprises the following steps: dividing the solder balls and the underfill into hexahedral meshes, and equally dividing the chip and the substrate into hexahedral meshes; the single solder ball constructed in the chip packaging reliability model is divided into at least 4 layers, and at least 8 hexahedral meshes are arranged on each layer; the underfill is also divided into at least four layers of hexahedral meshes, the underfill is subjected to joint coupling treatment corresponding to hexahedral mesh nodes and solder balls, other modules in the chip packaging reliability model are also divided into at least 4 layers, and the connection between the modules uses joint coupling or bonding; the substrate is positioned at the bottom of the chip, a solder ball is arranged between the substrate and the chip, and the solder ball is surrounded by underfill;
step 3: performing simulation pretreatment on a chip packaging reliability model including solder balls;
the specific simulation pretreatment comprises the following steps: establishing a quasi-static viscoelastic analysis step of numerical simulation, and applying symmetrical constraint to a chip packaging reliability model and loading temperature impact load;
step 4: solving the displacement in the thickness direction of the chip packaging reliability model by using a finite element analysis method, wherein the displacement is the warping degree;
the method comprises the following steps: because the thermal expansion coefficients of the module materials in the chip package reliability model are inconsistent, expansion or contraction can be caused under the temperature load, and a quasi-static analysis step is adopted to calculate the Z-direction displacement of the chip package reliability model (the Z direction is the thickness direction of the chip package reliability model).
Example 1
According to the method for simplifying the number of the solder balls, the ABAQUS software is adopted to establish a chip packaging reliability model containing the solder balls, and an original model, a first equivalent sparse model, a second equivalent sparse model and a third equivalent sparse model are respectively established, as shown in fig. 2 (a) to fig. 2 (d), solder ball distribution diagrams corresponding to the original model, the first equivalent sparse model, the second equivalent sparse model and the third equivalent sparse model are respectively established; under the working conditions of different temperature impact, the warping degree of each simulation model is calculated, and the comparison result is shown in table 1:
TABLE 1
According to the warp calculation result and the knowledge in fig. 3, compared with the original model, the number of the solder balls of the first sparse model is reduced to 1/4 of the original number, the solving time of the computer is reduced to half of the original model, the error is controlled within 4%, and the better accuracy is ensured while the calculation efficiency is improved.
Similarly, the second and third sparsification models improve the calculation efficiency and ensure better accuracy (within 5 percent, better).
While the solder balls and underfill are regarded as uniform materials in the prior art, although the computer solving time is short, the error reaches-17.7 percent, the accuracy requirement cannot be met, and the numerical simulation can bring misleading of results. The material homogenizing method is to consider the solder ball and the underfill as a whole, and the material parameters are subjected to equivalent treatment during calculation, and the specific equivalent mode is not repeated.
The calculation in this embodiment is that the same simulation calculation workstation (CPU number: 128 cores, memory size: 512G) adopts the same setting method to solve.
The solder ball sparsification equivalent method provided by the invention can be obtained through comparison of the simulation results, the number of meshes of the model is reduced, modeling complexity is reduced, meanwhile, finite element solving efficiency is greatly improved, and the warping degree error is controlled within a range acceptable by finite element calculation (generally, the numerical simulation result error is considered to be within 5 percent to be a range with higher accuracy).
The prior art submodel method requires higher finite element skill level, is complex in setting, has larger numerical calculation result error in the prior art material homogenization method, and cannot meet the precision requirement. Therefore, the equivalent method for sparsizing the volume ratio of the solder balls can improve the efficiency and meet the numerical simulation calculation precision.
Example 2
As shown in fig. 4, an embodiment of the present invention provides a system for solving warpage of a chip package reliability model, including:
the solder ball sparsification processing module 101 is used for keeping the size of the coverage surface of the solder balls, the volume occupied by the solder balls relative to underfill and the height of the solder balls unchanged, increasing the volume of a single solder ball, and equivalently obtaining a sparsified equivalent solder ball arrangement array by using the solder balls as cylinders;
the initial construction module 201 of the chip package reliability model is used for constructing the chip package reliability model based on the sparse equivalent solder ball arrangement array and performing grid division on the chip package reliability model;
the model parameter condition loading module 301 is configured to establish a quasi-static viscoelastic analysis step of numerical simulation for the reliability model of the grid-divided chip package, apply symmetrical constraint conditions, and load impact loads of different temperatures;
the warpage calculation module 401 is configured to solve the displacement of the chip package reliability model in the thickness direction under different temperature impact loads by using a finite element analysis method, so as to obtain the warpage of the chip package;
the chip packaging reliability model is a three-dimensional model for simulating a chip packaging structure comprising a chip, a substrate, solder balls and underfill, and calculating the chip packaging reliability; the substrate is positioned at the bottom of the chip, and solder balls are arranged between the substrate and the chip and are surrounded by underfill.
Further preferably, the volume of a single solder ball after the sparse equivalent in the solder ball sparse processing module is:
wherein,thinning the volume of the equivalent single solder ball; />The total volume of the solder balls after equivalent thinning;Mthe number of the solder balls after the equivalent thinning;
the diameter of the solder ball after the thinning equivalent is as follows:
wherein,dthe diameter of the equivalent solder ball is thinned;his the height of the solder balls.
Further preferably, the method for meshing the chip package reliability model in the initial construction module of the chip package reliability model specifically includes:
dividing solder balls and underfill in a chip packaging reliability model into hexahedral meshes, and dividing a chip and a substrate into hexahedral meshes; wherein, the single solder ball is divided into at least 4 layers, and each layer is provided with at least 8 hexahedral meshes; the underfill is divided into at least four layers of hexahedral meshes, and the hexahedral mesh nodes corresponding to the underfill and the hexahedral mesh nodes in the solder balls are subjected to joint coupling treatment.
Further preferably, the solder balls in the solder ball arrangement array are uniformly and equidistantly arranged after the equivalent solder ball thinning in the solder ball thinning processing module.
It should be understood that, the system is used to execute the method in the foregoing embodiment, and corresponding program modules in the system implement principles and technical effects similar to those described in the foregoing method, and the working process of the system may refer to the corresponding process in the foregoing method, which is not repeated herein.
In summary, compared with the prior art, the invention has the following advantages:
the invention provides a method and a system for solving warpage of a chip packaging reliability model, wherein the size of a covered surface of a solder ball, the occupied volume of the solder ball relative to underfill and the height of the solder ball are kept unchanged, the volume of a single solder ball is increased, the solder ball is equivalent to be cylindrical, and the distance between the solder ball and the solder ball is increased, so that the density of hexahedral meshes is reduced and the total mesh number is reduced when numerical simulation is carried out; the calculation time of the numerical simulation is positively correlated with the grid quantity, so that the calculation time of the chip packaging reliability model can be reduced by performing sparsification equivalent on the solder balls, and the efficiency of the numerical simulation is improved; on the other hand, the number of the grids in the numerical simulation exceeds ten millions, and the numerical simulation cannot be performed beyond the calculation capability of the existing computer, so that the number of the grids is reduced, and the occurrence of incapability of performing the numerical simulation can be effectively avoided. Therefore, the invention provides a new solution for the numerical simulation of the chip package reliability model from the two aspects of feasibility and timeliness of the numerical simulation.
The invention provides a method and a system for solving warpage of a chip packaging reliability model, wherein the volume ratio of a solder ball is kept unchanged during the equivalent process, namely the ratio of the volume of the solder ball to the volume of underfill is kept unchanged, the thermal expansion coefficients of two materials are kept unchanged, and when the two materials are expanded or contracted by a temperature load, the contribution degree of the expansion amount and the contraction amount is unchanged from that before the equivalent process; in the prior art, the solder balls and the underfill are subjected to homogenization treatment, so that the influence of the solder balls is ignored, and the accuracy of a numerical simulation result of a chip packaging reliability model is reduced; by comparison, the invention can find that the warpage error under different temperature working conditions obtained by calculation is smaller by simplifying the number of the solder balls.
Based on the method in the above embodiment, the embodiment of the invention provides an electronic device. The apparatus may include: at least one memory for storing programs and at least one processor for executing the programs stored by the memory. Wherein the processor is adapted to perform the method described in the above embodiments when the program stored in the memory is executed.
Based on the method in the above embodiment, the embodiment of the present invention provides a computer-readable storage medium storing a computer program, which when executed on a processor, causes the processor to perform the method in the above embodiment.
Based on the method in the above embodiments, an embodiment of the present invention provides a computer program product, which when run on a processor causes the processor to perform the method in the above embodiments.
It is to be appreciated that the processor in embodiments of the invention may be a central processing unit (centralprocessing unit, CPU), other general purpose processor, digital signal processor (digital signalprocessor, DSP), application specific integrated circuit (application specific integrated circuit, ASIC), field programmable gate array (field programmable gate array, FPGA) or other programmable logic device, transistor logic device, hardware components, or any combination thereof. The general purpose processor may be a microprocessor, but in the alternative, it may be any conventional processor.
The method steps in the embodiments of the present invention may be implemented by hardware, or may be implemented by executing software instructions by a processor. The software instructions may be comprised of corresponding software modules that may be stored in random access memory (random access memory, RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable PROM (EPROM), electrically erasable programmable EPROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable system. The computer instructions may be stored in or transmitted across a computer-readable storage medium. The computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.
It will be appreciated that the various numerical numbers referred to in the embodiments of the present invention are merely for ease of description and are not intended to limit the scope of the embodiments of the present invention.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. The method for solving warpage of the chip packaging reliability model is characterized by comprising the following steps of:
the method comprises the steps of taking an array of solder balls arranged between an actual substrate and a chip as a reference, keeping the size of the coverage surface of the solder balls, the occupied volume of the solder balls relative to underfill and the height of the solder balls unchanged, increasing the volume of a single solder ball and the distance between the solder balls, and obtaining the array of solder balls arranged after sparse equivalence; wherein, the base plate is located at the bottom of the chip, the solder ball is surrounded by the underfill;
based on the sparse equivalent solder ball arrangement array, constructing a chip packaging reliability model, and performing grid division on the chip packaging reliability model;
establishing a quasi-static viscoelastic analysis step of numerical simulation, applying symmetrical constraint conditions and loading temperature impact load to the reliability model of the chip package after grid division;
solving the displacement of the chip packaging reliability model in the thickness direction under the temperature impact load by using a finite element analysis method to obtain the warpage of the chip packaging;
the chip packaging reliability model is a three-dimensional model for calculating the chip packaging reliability by simulating a chip packaging structure comprising a chip, a substrate, solder balls and underfill;
the method for meshing the chip packaging reliability model specifically comprises the following steps:
dividing solder balls and underfill in a chip packaging reliability model into hexahedral meshes, and dividing a chip and a substrate into hexahedral meshes; wherein, the single solder ball is divided into at least 4 layers, and each layer is provided with at least 8 hexahedral meshes; the underfill is divided into at least four layers of hexahedral meshes, and the hexahedral mesh nodes corresponding to the underfill and the hexahedral mesh nodes in the solder balls are subjected to joint coupling treatment.
2. The method for solving warpage in a chip package reliability model according to claim 1, wherein the volume of a single solder ball after sparse equivalence is:
wherein,thinning the volume of the equivalent single solder ball; />To sparsate the total volume of the equivalent pre-solder balls;Mthe number of the solder balls after the equivalent thinning;
the solder balls are equivalent to be cylindrical, and the diameters of the solder balls after the sparse equivalent are as follows:
wherein,dthe diameter of the equivalent solder ball is thinned;his the height of the solder balls.
3. The method for solving warpage in a chip package reliability model according to claim 1, wherein the solder balls in the array of sparse equivalent solder ball arrangements are uniformly equidistantly arranged.
4. A system for solving warpage in a chip package reliability model, comprising:
the solder ball thinning processing module is used for taking the solder ball arrangement array between the actual substrate and the chip as a reference, keeping the size of the coverage surface of the solder balls, the occupied volume of the solder balls relative to the underfill and the height of the solder balls unchanged, increasing the volume of a single solder ball and the distance between the solder balls, and obtaining the solder ball arrangement array after thinning equivalence; wherein, the base plate is located at the bottom of the chip, the solder ball is surrounded by the underfill;
the initial construction module of the chip packaging reliability model is used for constructing the chip packaging reliability model based on the sparse equivalent solder ball arrangement array and performing grid division on the chip packaging reliability model;
the model parameter condition loading module is used for establishing a quasi-static viscoelastic analysis step of numerical simulation for the reliability model of the chip package after grid division, applying symmetrical constraint conditions and loading temperature impact load;
the warping degree calculation module is used for solving the displacement of the chip packaging reliability model in the thickness direction under the temperature impact load by using a finite element analysis method to obtain the warping degree of the chip packaging;
the chip packaging reliability model is a three-dimensional model for calculating the chip packaging reliability by simulating a chip packaging structure comprising a chip, a substrate, solder balls and underfill;
the method for meshing the chip packaging reliability model in the initial construction module of the chip packaging reliability model specifically comprises the following steps:
dividing solder balls and underfill in a chip packaging reliability model into hexahedral meshes, and dividing a chip and a substrate into hexahedral meshes; wherein, the single solder ball is divided into at least 4 layers, and each layer is provided with at least 8 hexahedral meshes; the underfill is divided into at least four layers of hexahedral meshes, and the hexahedral mesh nodes corresponding to the underfill and the hexahedral mesh nodes in the solder balls are subjected to joint coupling treatment.
5. The system for solving warpage in a chip package reliability model according to claim 4, wherein the volume of a single solder ball after the equivalent of the sparsification in the solder ball sparsification processing module is:
wherein,thinning the volume of the equivalent single solder ball; />To sparsate the total volume of the equivalent pre-solder balls;Mthe number of the solder balls after the equivalent thinning;
the solder balls are equivalent to be cylindrical, and the diameters of the solder balls after the sparse equivalent are as follows:
wherein,dthe diameter of the equivalent solder ball is thinned;his the height of the solder balls.
6. The system for solving warpage in a chip package reliability model according to claim 4, wherein the solder balls in the array of solder ball arrangements are uniformly equidistantly arranged after the equivalent of the sparsification in the solder ball sparsification processing module.
7. A computer readable storage medium storing a computer program, characterized in that the computer program, when run on a processor, causes the processor to perform the method according to any one of claims 1-3.
8. A computer program product, characterized in that the computer program product, when run on a processor, causes the processor to perform the method according to any of claims 1-3.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6285560B1 (en) * | 1999-09-20 | 2001-09-04 | Texas Instruments Incorporated | Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified |
| US6689634B1 (en) * | 1999-09-22 | 2004-02-10 | Texas Instruments Incorporated | Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability |
| WO2022111842A1 (en) * | 2020-11-27 | 2022-06-02 | Graphcore Limited | Controlling warpage of a substrate for mounting a semiconductor die |
| CN216980539U (en) * | 2022-03-14 | 2022-07-15 | 长电集成电路(绍兴)有限公司 | Fan-out packaging structure and chip packaging body |
| CN217691134U (en) * | 2022-07-20 | 2022-10-28 | 长电集成电路(绍兴)有限公司 | Chip packaging structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6696763B2 (en) * | 2001-04-02 | 2004-02-24 | Via Technologies, Inc. | Solder ball allocation on a chip and method of the same |
-
2023
- 2023-12-12 CN CN202311700062.9A patent/CN117390936B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6285560B1 (en) * | 1999-09-20 | 2001-09-04 | Texas Instruments Incorporated | Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified |
| US6689634B1 (en) * | 1999-09-22 | 2004-02-10 | Texas Instruments Incorporated | Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability |
| WO2022111842A1 (en) * | 2020-11-27 | 2022-06-02 | Graphcore Limited | Controlling warpage of a substrate for mounting a semiconductor die |
| CN216980539U (en) * | 2022-03-14 | 2022-07-15 | 长电集成电路(绍兴)有限公司 | Fan-out packaging structure and chip packaging body |
| CN217691134U (en) * | 2022-07-20 | 2022-10-28 | 长电集成电路(绍兴)有限公司 | Chip packaging structure |
Non-Patent Citations (7)
| Title |
|---|
| Analysis of warpage of a flip-chip BGA package under thermal loading: Finite element modelling and experimental validation;A. Salahouelhadj等;Microelectronic Engineering;20230203;第1-11页 * |
| BGA几何建模对仿真分析结果的影响研究;葛光亚等;强度与环境;20230831;第8-14页 * |
| Parametric study of thermally induced warpage of FpBGA package using finite element methods;Y. Venkata Naga Chandana等;Materials Today: Proceedings;20210619;第430-434页 * |
| The Study of Thermally Induced Warpage of BGA Package during Reflow Soldering;Yao Bin等;2018 19th International Conference on Electronic Packaging Technology;20181004;第1411-1414页 * |
| 多芯片焊球阵列封装体受热载荷作用数值模拟;毛佳;江振宇;陈广南;张为华;;国防科技大学学报;20101015(第05期);第23-28页 * |
| 提高BGA焊接的可靠性方法与实践;李晓明等;科技风;20200831;第140页 * |
| 晶圆级封装翘曲研究及仿真自动化;白红圆等;中国集成电路;20230831;第70-75+89页 * |
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