CN117375615A - Analog-to-digital converter (ADC) verification device - Google Patents
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Abstract
The application relates to an ADC verification device, comprising: a communication interface module for receiving configuration request data; an analog input interface module for receiving an externally input analog signal; the signal mixing module is coupled with the analog input interface module and mixes analog signals according to the mixing control signals; the FPGA module is coupled with the communication interface module, realizes the digital filter according to the configuration requirement data, and feeds back the calculation result of the digital filter and the running state of the verification device to the upper computer; the FPGA module is further coupled with the signal mixing module, generates a mixing control signal according to the configuration requirement data and sends the mixing control signal to the signal mixing module; and the modulator interface module is coupled with the signal mixing module and the FPGA module, is coupled with the hardware modulator under the control of the FPGA module, receives and modulates the mixed signals, and outputs the modulation result to the FPGA module. The application also relates to an ADC verification system and an ADC verification method.
Description
Technical Field
The present application relates to a test device, and in particular to an analog-to-digital converter (ADC) verification device.
Background
An analog-to-digital converter (ADC) is made up of a modulator and a digital filter. The modulator converts the input analog signal into a digital bit stream, and the digital filter converts the digital bit stream into data words representing the amplitude of the analog signal. The noise spectrum of the analog signal is shaped by the modulator and then passed through the digital filter to eliminate most of the quantization noise energy, thereby greatly improving the total signal-to-noise ratio.
The digital filter is a device which inputs and outputs digital signals, and changes the relative proportion of frequency components contained in the input signals or filters out certain frequency components through a certain operation relation. A digital filter is a discrete-time system that performs a filtering process on a digital signal to obtain a desired response characteristic. If analog signals are to be processed, matched conversion can be performed in signal form by means of an ADC and a DAC (digital-to-analog converter), and the analog signals can be filtered using a digital filter as well.
In designing ADC chips, testing is required for many fields of communications, automotive electronics, industrial control, aerospace, data centers, etc. The most commonly used test means at present are simulation by using a software model, and the test method has long test period, cannot be combined with the real running environment of a chip, and cannot be used for docking an actual hardware module.
Disclosure of Invention
To the technical problem that exists among the prior art, this application provides an ADC verifying attachment, include: the communication interface module is coupled with a communication interface of the upper computer and is configured to receive configuration requirement data; an analog input interface module configured to receive an externally input analog signal; a signal mixing module coupled to the analog input interface module and configured to mix the analog signal according to the mixing control signal; the FPGA module is coupled with the communication interface module and is configured to realize a digital filter according to the configuration requirement data, and the calculation result of the digital filter and the running state of the verification device are fed back to the upper computer through the communication interface module; the FPGA module is further coupled with the signal mixing module and is configured to generate a mixing control signal according to the configuration requirement data and send the mixing control signal to the signal mixing module; and a modulator interface module coupled with the signal mixing module and the FPGA module; the device is configured to be coupled with the hardware modulator under the control of the FPGA module, receive the mixed signals from the signal mixing module, modulate the mixed signals, and output the modulation result of the hardware modulator to the FPGA module.
In particular, wherein the authentication device further comprises: and the external modulator data input interface module is coupled with the FPGA module, and is configured to receive the modulation result of the external analog modulator under the control of the FPGA module and output the modulation result to the FPGA module.
In particular, wherein the FPGA module comprises: a communication interface control module coupled to the communication interface module and configured to receive configuration requirement data from the communication interface module; a bit stream processing module coupled with the modulator interface module and the external modulator data input interface module; a digital filter configuration module coupled to the bit stream processing module and the communication interface control module; a digital filter calculation module coupled with the digital filter configuration module; a modulator configuration module coupled with the bit stream processing module, the communication interface control module, and the signal mixing module; the modulator configuration module is configured to receive configuration requirement data, analyze the configuration requirement data and send data related to the modulator structure and parameters to the bit stream processing module; the modulator configuration module is further configured to generate a mixing control signal according to the configuration requirement data and send the mixing control signal to the signal mixing module; wherein the bit stream processing module is configured to control and selectively receive the modulation result from the modulator interface module or the external modulator data input interface module according to the data from the modulator configuration module; the digital filter configuration module receives configuration requirement data, analyzes data related to the digital filter structure and parameters from the configuration requirement data, receives a modulation result output by the bit stream processing module, sends the data related to the digital filter structure and parameters and the modulation result to the digital filter calculation module, and calculates the output of the digital filter.
In particular, the bit stream processing module is further configured to pre-process the received modulation result.
Particularly, the FPGA module further comprises a data and state buffer module which is coupled with other modules in the verification device; the system is configured to receive and store the calculation result from the digital filter calculation module and the running state of the verification device, and feed back to the upper computer through the communication interface control module and the communication interface module.
Specifically, the FPGA module further includes a system clock management module, which is respectively coupled to all other modules in the FPGA module, and configured to generate clock signals with different frequencies required by each module.
In particular, wherein the digital filter configuration module further comprises: the digital filter structure configuration module is configured to receive the configuration requirement data and analyze the configuration requirement data to obtain data related to the digital filter structure; the digital filter parameter configuration module is configured to receive configuration requirement data and to parse data related to digital filter parameters therefrom.
In particular, wherein the communication interface control module further comprises: a serial port control module, an Ethernet interface control module and/or a PCI-E interface control module.
In particular, the verification device further comprises an external mixed signal input interface module and/or a noise interference signal generation module positioned in the FPGA module; the external mixing signal input interface module is coupled with the signal mixing module, and is configured to receive a first noise interference signal generated by the outside and output the first noise interference signal to the signal mixing module; the noise interference signal generation module is coupled with the modulator configuration module and the signal mixing module, and is configured to generate a second noise interference signal according to the configuration requirement data and output the second noise interference signal to the signal mixing module.
In particular, the signal mixing module is coupled to the analog input interface module, the external mixing signal input interface module, and the noise interference signal generating module and is configured to mix the first noise interference signal and/or the second noise interference signal with the analog signal according to the mixing control signal.
In particular, wherein the communication interface module further comprises: a serial communication interface module, an ethernet interface module, and/or a PCI-E interface module.
In particular, wherein the modulator interface module further comprises a first modulator interface and a second modulator interface configured to couple with different hardware modulators.
The application also provides an ADC verification system which comprises the ADC verification device and an upper computer; the upper computer is a computer or a singlechip outside the verification device and is configured to send configuration requirement data to the verification device; and the digital filter is also configured to receive the calculation result of the digital filter fed back by the verification device according to the configuration requirement data and the operation state of the verification device, and evaluate and analyze the calculation result.
The application also provides an ADC verification method, which comprises the following steps: the communication interface module receives configuration requirement data from the upper computer and sends the configuration requirement data to the FPGA module; the FPGA module controls and selectively receives modulation results from different modulators according to the configuration requirement data; when the FPGA module selects to receive the modulation result of the hardware modulator: the analog input interface module receives an externally input analog signal; the signal mixing module mixes the analog signals according to the mixing control signals; the modulator interface module is connected with the hardware modulator, receives the mixed analog signals, modulates the mixed analog signals, and outputs the modulation result of the hardware modulator to the FPGA module; alternatively, when the FPGA module selects to receive the modulation result of the external analog modulator: the external modulator data input interface module receives a modulation result of an external analog modulator according to configuration requirement data and outputs the modulation result to the FPGA module; the FPGA module receives the modulation result, realizes the digital filter according to the configuration requirement data, and feeds back the calculation result of the digital filter and the running state of the verification device to the upper computer.
In particular, the external mixing signal input interface module of the verification device is capable of receiving an externally generated first noise interference signal and transmitting the first noise interference signal to the signal mixing module; the FPGA module can locally generate a second noise interference signal according to the configuration requirement data and send the second noise interference signal to the signal mixing module; the signal mixing module mixes the first noise interference signal and/or the second noise interference signal with the analog signal according to the mixing control signal.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
FIG. 1 is a schematic diagram of the structure of an ADC authentication device according to one embodiment of the present application;
FIG. 2 is a schematic diagram of the structure of an FPGA module in an ADC verification device according to one embodiment of the present application;
fig. 3 is a schematic structural diagram of a waveform generation control module in a noise interference signal generation module implemented by using a DDS signal generator according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a sinc type 5-order CIC digital filter structure according to one embodiment of the present application;
FIG. 5 is a schematic diagram of a FIR type digital filter with a tap number M according to one embodiment of the present application; and
fig. 6 is a schematic diagram of the structure of a direct II IIR type digital filter according to one embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. For the purpose of illustration only, the connection between elements in the figures is meant to indicate that at least the elements at both ends of the connection are in communication with each other and is not intended to limit the inability to communicate between elements that are not connected. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the output terminals provided, and is not intended to limit the communication between the two units to only signals as shown in the figures.
The application provides an ADC verification device adopting a Field Programmable Gate Array (FPGA) device, which can realize hardware acceleration verification of the ADC.
FPGAs are integrated circuits with programmable characteristics that are pre-designed and implemented on silicon chips that can be configured to a specified circuit configuration according to the needs of a user without having to rely entirely on Application Specific Integrated Circuit (ASIC) chips provided by the chip manufacturer. The FPGA device has high integration level and small volume, has the function of realizing special application through user programming, and allows a user to utilize a development platform based on a computer to perform design input, simulation, test and verification until an expected result is achieved.
The FPGA device can greatly shorten the development period of the system, reduce the investment and conveniently carry out on-line modification on the design. Therefore, the FPGA device has wide application in the fields of prototype verification, communication, automobile electronics, industrial control, aerospace, data centers and the like.
The hardware acceleration verification is to utilize the rapid reconfiguration characteristic of the FPGA, and has obvious acceleration effect and good expectation on scheme evaluation in the initial stage of chip design and performance fumbling in the middle and later stages. The use of FPGA devices in the system design allows custom hardware to be added at any point in the design cycle. The user may write the software code immediately and run directly on the hardware portion prior to finalization. In addition, the development tool of the FPGA device can realize seamless switching between hardware and software, so that a user can also decide which part of codes are realized by hardware instead of software according to requirements. Unlike computer simulation, which can only use a software model, the FPGA device can generate a real circuit inside and can also interface with real hardware, and compared with computer simulation, the FPGA device has the ability to find more hidden holes during verification and testing.
According to one embodiment, the ADC may include a modulator and a digital signal processing module, wherein the modulator is configured to convert an input analog signal into a digital bit stream.
According to one embodiment, the digital signal processing module may comprise a digital filter configured to convert the digital bit stream into data words representing the amplitude of the analog signal.
The ADC verification device comprises an FPGA device and other functional modules connected with the FPGA device, can realize signal generation and mixing functions, and can perform hardware acceleration verification on a modulator and/or a digital filter in the ADC.
According to one embodiment, the ADC verification device provided by the application may fix the modulator structure and parameters in the ADC to be verified, obtain final output data by configuring the structure and parameters of the digital filter in the ADC, and evaluate the performance of the digital filter with different structures and parameters according to the data, find an optimal digital filter adapted to the fixed modulator for the ADC to be verified.
According to one embodiment, the ADC verification device provided by the present application may fix the digital filter structure and parameters in the verified ADC, determine the performance of the modulators of different structures and parameters by using the modulators of different structures or parameters according to the final output result, and find an optimal modulator adapted to the fixed digital filter for the verified ADC.
According to one embodiment, the ADC verification device provided by the application can also pertinently superimpose different noise interference signals on the input of the modulator in the verification process, such as alternating current power frequency of 50/60Hz and harmonic waves thereof, electromagnetic interference, thermal noise or clock frequency jitter and the like. And analyzing whether the final output result after the noise interference signal is overlapped meets the design target or not, and whether the project Product Requirement Document (PRD) is met or not. The method can quickly evaluate or debug the performance of the verified ADC in a complex application scene of actual operation.
Therefore, the ADC verification device provided by the application can be used for carrying out hardware acceleration verification on the modulator and/or the digital filter in the ADC in combination with the actual running environment, is suitable for evaluating, verifying and debugging the modulator and/or the digital filter in the ADC, provides reference data which is closer to the actual application scene for products, and efficiently verifies and debugs the design of the ADC, so that the products are faster and more stable to market.
Fig. 1 is a schematic structural diagram of an ADC verification device according to an embodiment of the application.
According to one embodiment, the ADC verification device shown in fig. 1 may include an FPGA module 400.
According to one embodiment, the ADC verification device shown in fig. 1 may include a communication interface module 500 coupled to the FPGA module 400, where the ADC verification device is connected to an upper computer, such as an external computer or a single-chip microcomputer, through the communication interface module 500, so as to implement flexible and efficient data transmission.
According to one embodiment, the communication interface module 500 shown in fig. 1 may include a plurality of sub-modules, such as: the serial port communication interface module 501, the ethernet interface module 502 and the PCI-E interface module 503 may be corresponding sub-modules according to the type of the communication interface of the connected host computer in practical application.
According to one embodiment, the sub-module of the communication interface module 500 is configured to convert configuration requirement data required for the verification test sent by the connected upper computer into a digital signal and send the digital signal to the FPGA module 400; the sub-modules of the communication interface module 500 are also configured to send the final output of the modulator and/or digital filter to be verified, obtained by the ADC verification device according to the configuration requirement data, to the host computer for evaluation and analysis.
According to one embodiment, as shown in fig. 2, FPGA module 400 may include a communication interface control module 470 coupled to communication interface module 500.
According to one embodiment, the communication interface control module 470 may call the IP core of the FPGA vendor, and perform configuration in combination with the user's own requirements; the communication interface control module 470 shown in fig. 2 may include a plurality of sub-modules, such as: the sub-modules of the communication interface control module 470 in practical application may be respectively connected with the sub-modules of the corresponding types in the communication interface module 500, where the serial port control module 4701, the ethernet interface control module 4702, and the PCI-E interface control module 4703.
According to one embodiment, the submodules of the communication interface control module 470 are configured to receive the configuration requirement data sent by the submodules of the corresponding communication interface module 500, and perform communication protocol parsing on the data; the sub-modules of the communication interface control module 470 are also configured to send the final output of the modulator and/or digital filter to be verified, obtained by the ADC verification device according to the configuration requirement data, to the sub-modules of the corresponding communication interface module 500.
According to one embodiment, communication interface module 500 may include other types of sub-modules, and communication interface control module 470 may also include other types of sub-modules. According to one embodiment, the number of sub-modules included in communication interface module 500 is the same as the number of sub-modules included in communication interface control module 470, and the types of sub-modules included in both are in a one-to-one correspondence.
According to one embodiment, the ADC verification device shown in fig. 1 may include an analog input interface module 101, an external mixing signal input interface module 102, and a signal mixing module 200.
According to one embodiment, the signal mixing module 200 may include four input ports M IN1 、M IN2 、M IN3 And M IN4 And two output ports M OU1 And M OU2 。
According to one embodiment, the analog input interface module 101 and the input port M of the signal mixing module 200 IN1 Coupling; external mixing signal input interface module 102 and input port M of signal mixing module 200 IN2 And (3) coupling.
According to one embodiment, the analog input interface module 101 may include a shielding connector and a front-end filter circuit (not shown), where the analog input interface module 101 is configured to receive an externally input analog signal to be modulated, and to pre-filter the input analog signal and transmit the pre-filtered analog signal to the input port M of the signal mixing module 200 IN1 。
According to one embodiment, the external mixing signal input interface module 102 is configured to receive a noise interference signal of a specific requirement generated and input by an external signal generator and to transmit the noise interference signal to the input port M of the signal mixing module 200 IN2 。
Fig. 2 is a schematic structural diagram of an FPGA module in an ADC verification device according to an embodiment of the application.
According to one embodiment, as shown in fig. 2, the FPGA module 400 in the ADC verification device of the present application may include a noise interference signal generating module 460 and an input port M of the signal mixing module 200 IN3 Coupling; the noise interference signal generating module 460 is configured as a signal generator algorithm and circuit (such as a DDS signal generator and a DAC circuit) implemented by using local programming of the FPGA, and can generate noise interference signals with arbitrary waveforms or generate specific noise interference signals difficult to be generated by the external signal generator according to user requirements, such as actual environment where the ADC is verified to operate in future, and transmit the noise interference signals to the input port M of the signal mixing module 200 IN3 。
According to one embodiment, the noise interference signal generation module 460 may include a waveform memory and waveform generation control module.
According to one embodiment, the waveform memory is implemented by using a Block Random Access Memory (BRAM) of the FPGA device, and the maximum supporting period length is 32768 points, so that some non-periodic signals such as white noise can be better simulated.
According to one embodiment, the waveform generation control module may employ the structure of a DDS signal generator. Fig. 3 is a schematic structural diagram of a waveform generation control module in a noise interference signal generation module implemented by using a DDS signal generator according to an embodiment of the present application. The frequency control word K and the phase control word P are used for outputting addresses of the waveform memory, and finally analog noise interference signals obtained through the DAC are output to the input port M of the signal mixing module 200 IN3 。
According to one embodiment, the ADC verification device shown in fig. 1 may include a modulator interface module 300 configured to interface with a hardware modulator.
According to one embodiment, as shown in fig. 1, modulator interface module 300 may include sub-modules such as: modulator interface module 301 and modulator interface module 302; each sub-module may be configured to connect to a hardware modulator.
According to one embodiment, the connection manner between the sub-modules of the modulator interface module 300 and the hardware modulator may be implemented by using a test fixture (socket) board, and a board-to-board socket, so as to provide abundant support for hardware modulators of different types and orders.
According to one embodiment, the sub-modules of the modulator interface module 300 may support a high-speed bit stream of 8bits at maximum and a sampling frequency of 8.192MHz at maximum.
According to one embodiment, modulator interface modules 301 and 302 may be connected to two different hardware modulators simultaneously; it is also possible that only one of the modulator interface modules is connected to one of the hardware modulators and the other modulator interface module is left free.
According to one embodiment, the input port M of the signal mixing module 200 IN1 Configured to receive an analog signal from the analog input interface module 101; input port M IN2 Configured to receive an externally generated noise interference signal from the external mixed signal input interface module 102; input port M IN3 The noise interference signal generated locally from the noise interference signal generation module 460 in the FPGA module 400 is received.
According to one embodiment, the input port M of the signal mixing module 200 IN3 Coupled to the modulator configuration module 450 in the FPGA module 400, configured to receive the mixing control signals generated and sent by the modulator configuration module 450 according to the configuration requirement data.
According to one embodiment, the signal mixing module 200 is based on the input port M IN3 The received mixing control signal will input port M IN2 And/or input port M IN3 Received noise interference signal and input port M IN1 The received analog signals are mixed to obtain mixed analog signals, and the mixed analog signals are transmitted through an output port M OU1 And/or output port M OU2 Output to hardware modulators connected to modulator interface modules 301 and/or 302.
According to one embodiment, the signal mixing module 200 may be implemented by an analog multiplier to achieve better signal-to-noise ratio and harmonic distortion.
According to one embodiment, the output port M of the signal mixing module OU1 Configured to output the mixed analog signal to a hardware modulator connected to the modulator interface module 301; output port M OU2 Configured to output the mixed analog signal to a hardware modulator coupled to modulator interface module 302.
According to other embodiments, according to input port M IN3 The received mixing control signal, input port M of signal mixing module 200 IN2 And input port M IN3 The signal mixing module 200 directly receives the signal from the input port M without receiving any noise interference information IN1 Is output to a hardware modulator coupled to modulator interface module 301 and/or 302.
According to one embodiment, the ADC verification device shown in fig. 1 may include an external modulator data input interface module 303 configured to receive a digital bit stream output by a modulator that is programmed to be analog by an external computer.
According to one embodiment, an external computer programmed analog modulator may comprise: the Simulink modulator simulation model under design, or a modulator whose hardware is not compatible with the modulator interface modules 301 and 302, requires programming simulation by an external computer.
According to one embodiment, the external modulator data input interface module 303 may also be configured to receive signals of the digital bit stream output by the external computer programming analog modulator superimposed with the external analog specific noise disturbance signal, as desired.
According to one embodiment, as shown in fig. 2, the FPGA module 400 may include a system clock management module 480, which is respectively coupled to other respective modules in the FPGA module 400 and configured to set a frequency multiplication and division ratio according to an externally input crystal oscillator clock, and output clock signals of different frequencies as required to the other respective modules in the FPGA module 400 using a phase-locked loop and frequency division logic (not shown) integrated inside the FPGA device, including, for example: system host processing clock, modulator sampling clock, digital filter clock, serial port clock, ethernet interface clock, PCI-E interface clock, and noise disturbance signal generator clock.
According to one embodiment, as shown in fig. 2, FPGA module 400 may include a bit stream processing module 410, a digital filter configuration module 420, and a modulator configuration module 450.
According to one embodiment, the bit stream processing module 410 may include five input ports B IN1 To B IN5 And an output port B OU 。
According to one embodiment, input port B of bitstream processing module 410 IN5 Coupled to the system clock management module 480, is configured to receive a clock signal from the system clock management module 480.
According to one embodiment, input port B of bitstream processing module 410 IN1 Coupled to the modulator interface module 301, configured to receive a digital bit stream from a hardware modulator output coupled to the modulator interface module 301; input port B IN2 Coupled to the modulator interface module 302, configured to receive a digital bit stream from a hardware modulator output coupled to the modulator interface module 302; input port B IN3 Coupled to the external modulator data input interface module 303, configured to receive the digital bit stream output by the external modulator data input interface module 303.
According to one embodiment, output port B of bit stream processing module 410 OU Coupled to the digital filter configuration module 420.
According to one embodiment, digital filter configuration module 420 and modulator configuration module 450 are both coupled with communication interface control module 470; digital filter configuration module 420 and modulator configuration module 450 receive configuration requirement data through communication interface control module 470.
According to one embodiment, digital filter configuration module 420 is configured to parse and receive configuration data relating to the structure and parameters of the digital filter in the configuration requirement data; modulator configuration module 450 is configured to parse and receive configuration data relating to modulator structures and parameters in the configuration requirement data.
According to one embodiment, modulator configuration module 450 generates a mixing control signal based on the received modulator configuration data and sends the mixing control signal to signal mixing module 200.
According to one embodiment, the modulator configuration module 450 is coupled to the noise interference signal generating module 460, and if the configuration requirement data received by the modulator configuration module 450 requires a locally generated noise interference signal, the modulator configuration module 450 sends the relevant configuration requirement data to the noise interference signal generating module 460, and the noise interference signal generating module 460 generates the required noise interference signal and retransmits the required noise interference signal to the signal mixing module 200.
According to one embodiment, modulator configuration module 450 passes data regarding modulator structure and parameters from the received configuration requirement data via input port B IN4 To the bit stream processing module 410; the bit stream processing module 410 controls different input ports according to the received configuration requirement data, and selects to receive the data from the input port B IN1 、B IN2 Or B is a IN3 Is provided).
According to one embodiment, the bit stream processing module 410 further performs relevant configuration, such as modulator bit width, according to the received configuration requirement data, and controls a Multiplexer (MUX) of the input port pins.
According to one embodiment, the bit stream processing module 410 may also adjust the encoding mode according to the bit data characteristics of the received digital bit stream to adapt to the subsequent digital filter processing, for example: the received original digital bit stream has only one bit, 0 represents-1 and 1 represents +1, and the bit stream processing module 410 is required to expand the original digital bit stream into two signed data types, and the signed data types are transmitted through the output port B OU And outputting to a digital filter configuration module.
According to one embodiment, the bit stream processing module 410 may also provide Global Chop (Global Chop) control for the received digital bit stream, may automatically swap the analog input positive and negative ends of the modulator, and eliminate Offset (Offset) errors of the channels.
According to one embodiment, as shown in fig. 2, the digital filter configuration module 420 in the FPGA module 400 may include a digital filter structure configuration module 4201, and a digital filter parameter configuration module 4202.
According to one embodiment, the digital filter structure configuration module 4201 parses and stores data related to digital filter structures from configuration requirement data.
According to one embodiment, the digital filter structure configuration module 4201 may be configured as a maximum of 5 stages of digital filters in series, where each stage of digital filter may be one of the sinc, FIR, IIR type of digital filters, as required for verification.
According to one embodiment, a sinc type digital filter may be configured with 1 to 16384 times downsampling, supporting an order of 1 to 5 orders, and differentially delaying 1 to 5 units. The transfer function is:
according to one embodiment, the sinc type digital filter may be implemented using a Cascaded Integrator Comb (CIC) filter, and the accumulation and difference units are time-multiplexed after decimation to save chip resources. Fig. 4 is a schematic diagram of a sinc type 5-order CIC filter structure according to an embodiment of the application.
According to one embodiment, the FIR type digital filter may be configured with a downsampling number of 1 to 128, supporting a maximum 128 th order, with a computational accuracy using 32-bit fixed point decimal. The FIR type digital filter can be used as a compensation filter for the sinc type digital filter, and can also be used for realizing high-pass, low-pass and band-pass digital filters. The characteristic of the linear phase of the FIR type digital filter is utilized to keep the time domain waveform of the signal, and meanwhile, the configuration of the maximum 128 th order can meet the ripple requirements of roll-off and pass-stop bands in most occasions. The downsampling configuration of 1 to 128 is well suited for multi-rate signal systems such as ADCs. The input-output relation of the FIR type digital filter with the extraction number M is as follows:
According to one embodiment, in order to save chip resources, the FIR type digital filter in the application adopts a filter polyphase decomposition technology, so that unnecessary calculation can be removed during signal rate conversion, the running speed is improved, and the resource occupation is reduced. Fig. 5 is a schematic diagram of a FIR type digital filter structure with a decimation number M according to an embodiment of the present application.
According to one embodiment, the IIR type digital filter supports an order of 1 to 4 steps, the calculation accuracy uses a 32-bit fixed point decimal, and the low-pass, high-pass, and band-stop characteristics of the digital filter can be realized according to coefficient configuration. The cut-off frequency may be configured to be below 1Hz to several hundred Hz. The effect of the high-order FIR type digital filter can be achieved by using the IIR type digital filter with lower order, so that the cost of chip resources is reduced. The transfer function of the IIR type digital filter related to the application is as follows:
according to one embodiment, the IIR type digital filter referred to in this application may be implemented using a direct ii type architecture. Fig. 6 is a schematic diagram of the structure of a direct II IIR type digital filter according to one embodiment of the present application.
According to one embodiment, each stage of digital filter configured in series in the digital filter structure configuration module 4201 may be of the same type and the same order, may be of the same type and different orders, or may be of different types.
According to one embodiment, the digital filter structure configuration module 4201 may also be configured as other types of digital filters as required by test verification.
According to one embodiment, the digital filter parameter configuration module 4202 parses and stores data related to digital filter parameters from the configuration requirement data.
According to one embodiment, digital filter parameter configuration module 4202 may include Block Random Access Memory (BRAM) of an FPGA device, write control logic, and output mapping logic (not shown).
According to one embodiment, the BRAM may be divided into 6 partitions (not shown), and partitions 1 to 5 sequentially store the loading control parameters of the digital filter, the filter type parameters, the order, the downsampling rate parameters, and coefficient information (representing differential delay coefficients if a sinc type digital filter is used).
According to one embodiment, partition 6 of BRAM stores modulator configuration parameters including, for example, mixing control, modulator clock, and coding control parameters.
According to one embodiment, as shown in fig. 2, FPGA module 400 may include a digital filter computation module 430 coupled to digital filter configuration module 420.
According to one embodiment, as shown in FIG. 2, FPGA module 400 may include a data and status caching module 440 coupled with a digital filter computation module 430.
According to one embodiment, the digital filter configuration module 420 sends the stored data of the digital filter structure and parameters, and the digital bit stream received from the bit stream processing module 410, to the digital filter calculation module 430, and the output result is calculated by the digital filter calculation module 430.
According to one embodiment, the digital filter calculation module 430 may call a hardware Digital Signal Processor (DSP) unit of the FPGA device, write the calculated output result of the digital filter into the data and status buffer module 440 according to the structure multiplexing multiply-add unit, and the upper computer reads the output result of the digital filter through the communication interface module 500 and the communication interface control module 470.
According to one embodiment, the digital filter calculation module 430 may also write the calculated output result of the digital filter to the data and status caching module 440 in other manners.
According to one embodiment, data and status buffer module 440 may include a digital filter data asynchronous first-in-first-out (FIFO) buffer, and a status register (not shown).
According to one embodiment, the digital filter data asynchronous FIFO (not shown) in data and status buffer module 440 uses 32 bits wide and has a depth of 2048. The use of asynchronous FIFO buffers enables cross-clock domain data transfer with the communication interface control module 470 with empty-full indication and control, avoiding data loss.
According to one embodiment, the data and status caching module 440 is further coupled to other various modules in the ADC verification device and configured to store the operating status parameters of the other various modules in its own status register, and the host computer reads the operating status of the ADC verification device through the communication interface control module 470 and the communication interface module 500, including, for example: the configuration data of the digital filter can be read back, and the number of the output data of the digital filter and whether the data is saturated or not can be obtained.
The application also provides an ADC verification system which comprises the ADC verification device and an upper computer; the upper computer is a computer or a singlechip outside the ADC verification device and is configured to send configuration requirement data to the ADC verification device; and the system is also configured to receive the digital filter calculation result fed back by the ADC verification device according to the configuration requirement data and the operation state of the ADC verification device, and evaluate and analyze the data.
The application also provides an ADC verification method, which comprises the following steps:
the communication interface module receives configuration requirement data from the upper computer and sends the configuration requirement data to the FPGA module;
the FPGA module controls and selectively receives modulation results from different modulators according to the configuration requirement data;
When the FPGA module selects to receive the modulation result of the hardware modulator:
the analog input interface module receives an externally input analog signal;
the signal mixing module mixes the analog signals according to the mixing control signals;
the modulator interface module is connected with the hardware modulator, receives the mixed analog signals, modulates the mixed analog signals, and outputs the modulation result of the hardware modulator to the FPGA module; or alternatively
When the FPGA module selects to receive the modulation result of the external analog modulator:
an external modulator data input interface module receives external analog modulation according to configuration requirement data
The modulation result of the device is output to the FPGA module;
the FPGA module receives the modulation result, realizes the digital filter according to the configuration requirement data, and feeds back the calculation result of the digital filter and the running state of the ADC verification device to the upper computer.
According to one embodiment, the external mixing signal input module of the ADC verification device may receive the externally generated first noise interference signal and send it to the signal mixing module; the FPGA module can also locally generate a second noise interference signal according to the configuration requirement data and send the second noise interference signal to the signal mixing module; the signal mixing module mixes the first noise interference signal and/or the second noise interference signal with the analog signal according to the mixing control signal.
The above embodiments are provided for illustrating the present application and are not intended to limit the present application, and various changes and modifications can be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.
Claims (15)
1. An analog-to-digital converter (ADC) verification apparatus, comprising:
the communication interface module is coupled with a communication interface of the upper computer and is configured to receive configuration requirement data;
an analog input interface module configured to receive an externally input analog signal;
a signal mixing module coupled to the analog input interface module and configured to mix the analog signal according to a mixing control signal;
the FPGA module is coupled with the communication interface module and is configured to realize a digital filter according to the configuration requirement data and feed back a calculation result of the digital filter and the running state of the verification device to the upper computer through the communication interface module; the FPGA module is further coupled with the signal mixing module and is configured to generate the mixing control signal according to the configuration requirement data and send the mixing control signal to the signal mixing module; and
A modulator interface module coupled with the signal mixing module and the FPGA module; and the hardware modulator is configured to be coupled with the hardware modulator under the control of the FPGA module, receive the mixed signals from the signal mixing module, modulate the mixed signals and output the modulation result of the hardware modulator to the FPGA module.
2. The authentication device of claim 1, wherein the authentication device further comprises: and the external modulator data input interface module is coupled with the FPGA module, and is configured to receive the modulation result of the external analog modulator under the control of the FPGA module and output the modulation result to the FPGA module.
3. The authentication device of claim 1 or 2, wherein the FPGA module comprises:
a communication interface control module coupled to the communication interface module and configured to receive the configuration requirement data from the communication interface module;
a bit stream processing module coupled with the modulator interface module and the external modulator data input interface module;
a digital filter configuration module coupled with the bit stream processing module and the communication interface control module;
A digital filter computation module coupled with the digital filter configuration module;
a modulator configuration module coupled with the bit stream processing module, the communication interface control module, and the signal mixing module;
the modulator configuration module is configured to receive the configuration requirement data, analyze the configuration requirement data and send the data related to the modulator structure and parameters to the bit stream processing module; the modulator configuration module is further configured to generate the mixing control signal according to the configuration requirement data and send the mixing control signal to the signal mixing module;
wherein the bit stream processing module is configured to control and select to receive a modulation result from the modulator interface module or the external modulator data input interface module according to the data from the modulator configuration module;
the digital filter configuration module receives the configuration requirement data, analyzes data related to digital filter structures and parameters from the configuration requirement data, receives the modulation result output by the bit stream processing module, and sends the data related to the digital filter structures and parameters and the modulation result to the digital filter calculation module to calculate the output of the digital filter.
4. A validation apparatus according to claim 3 wherein the bit stream processing module is further configured to pre-process the received modulation result.
5. A verification device as claimed in claim 3 wherein said FPGA module further comprises a data and status caching module coupled to all other modules in said verification device; and the system is configured to receive and store the calculation result from the digital filter calculation module and the running state of the verification device, and feed back the calculation result to the upper computer through the communication interface control module and the communication interface module.
6. A verification device as claimed in claim 3 wherein said FPGA module further comprises a system clock management module respectively coupled to all other modules within said FPGA module and configured to generate clock signals of different frequencies required by each module.
7. A verification device as claimed in claim 3 wherein said digital filter configuration module further comprises:
the digital filter structure configuration module is configured to receive the configuration requirement data and analyze data related to the digital filter structure from the configuration requirement data;
and the digital filter parameter configuration module is configured to receive the configuration requirement data and analyze the configuration requirement data to obtain data related to the digital filter parameters.
8. A verification device as claimed in claim 3 wherein said communication interface control module further comprises: a serial port control module, an Ethernet interface control module and/or a PCI-E interface control module.
9. A verification device as claimed in claim 3 wherein said verification device further comprises an external mixed signal input interface module and/or a noise interference signal generation module located within said FPGA module;
the external mixing signal input interface module is coupled with the signal mixing module, and is configured to receive a first noise interference signal generated externally and output the first noise interference signal to the signal mixing module;
the noise interference signal generation module is coupled with the modulator configuration module and the signal mixing module, and is configured to generate a second noise interference signal according to the configuration requirement data and output the second noise interference signal to the signal mixing module.
10. The authentication device of claim 9, wherein the signal mixing module is coupled to the analog input interface module, the external mixing signal input interface module, and the noise-interference signal generation module and is configured to mix the first noise-interference signal and/or the second noise-interference signal with the analog signal in accordance with the mixing control signal.
11. The authentication device of claim 1, wherein the communication interface module further comprises: a serial communication interface module, an ethernet interface module, and/or a PCI-E interface module.
12. The authentication device of claim 1, wherein the modulator interface module further comprises a first modulator interface and a second modulator interface configured to couple with different hardware modulators.
13. An analog-to-digital converter (ADC) verification system comprising an ADC verification device according to any one of claims 1-12 and a host computer;
the upper computer is a computer or a singlechip outside the verification device and is configured to send configuration requirement data to the verification device; and the system is also configured to receive the digital filter calculation result fed back by the verification device according to the configuration requirement data and the operation state of the verification device, and evaluate and analyze the digital filter calculation result and the operation state of the verification device.
14. An analog-to-digital converter (ADC) verification method, comprising:
the communication interface module receives configuration requirement data from the upper computer and sends the configuration requirement data to the FPGA module;
the FPGA module controls and selectively receives modulation results from different modulators according to the configuration requirement data;
When the FPGA module selects to receive the modulation result of the hardware modulator:
the analog input interface module receives an externally input analog signal;
the signal mixing module mixes the analog signals according to the mixing control signals;
the modulator interface module is connected with the hardware modulator, receives the mixed analog signals, modulates the mixed analog signals, and outputs the modulation result of the hardware modulator to the FPGA module;
or alternatively
When the FPGA module selects to receive the modulation result of the external analog modulator:
the external modulator data input interface module receives a modulation result of the external analog modulator according to the configuration requirement data and outputs the modulation result to the FPGA module;
and the FPGA module receives the modulation result, realizes a digital filter according to the configuration requirement data, and feeds back a calculation result of the digital filter and the running state of the verification device to the upper computer.
15. The authentication method of claim 14, wherein an external mixing signal input interface module of the authentication device is capable of receiving an externally generated first noise interference signal and transmitting to the signal mixing module; the FPGA module can locally generate a second noise interference signal according to the configuration requirement data and send the second noise interference signal to the signal mixing module; the signal mixing module mixes the first noise interference signal and/or the second noise interference signal with the analog signal according to the mixing control signal.
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