CN112511161A - Simulation test system and method for sinc filter of sigma-delta ADC chip - Google Patents
Simulation test system and method for sinc filter of sigma-delta ADC chip Download PDFInfo
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Abstract
The invention provides a sinc filter simulation test system and a sinc filter simulation test method for a sigma-delta ADC chip, wherein the system comprises: the device comprises a data source generating module, a testing module and a testing module, wherein the data source generating module is used for simulating output and input signals of a sigma-delta ADC chip, and the testing module is used for transmitting read bit stream data to a module to be tested according to a clock signal; and the module to be tested is used for receiving the transmitted bit stream data and displaying the transmitted bit stream data as a filtering signal. According to the invention, two sine waves are superposed, and then the superposed waveform is modulated to obtain bit stream data, so that output and input signals of a sigma-delta ADC chip are simulated, a clock signal is modulated, the bit stream data is read according to the clock signal, a low-pass filtering effect can be achieved, the waveform can be observed in the modulation process, the filtering effect can be verified early and corrected in time through simulation test, a circuit test environment does not need to be set up, the modulation efficiency is improved, and the cost is reduced.
Description
Technical Field
The invention mainly relates to the technical field of signal modulation, in particular to a sinc filter simulation test system and method for a sigma-delta ADC chip.
Background
The current sigma-delta ADC chip outputs a high-frequency bit stream by an oversampling technology, but a high-frequency signal needs to be filtered through a modulation process to obtain an effective signal.
However, the conventional debugging device is too simple, a signal result is directly output, and if the result is not accurate, the link in which the problem occurs cannot be judged, and repeated debugging is needed, so that the filtering effect is poor and the efficiency is low; debugging is also performed by building a circuit test environment, but the method is high in cost.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a sinc filter simulation test system and method for a sigma-delta ADC chip.
The technical scheme for solving the technical problems is as follows: a signal emulation test system for a sigma-delta ADC chip, comprising:
the data source generation module is used for generating a triangular wave and two sine waves according to preset parameters, superposing the two sine waves to obtain a superposed waveform, comparing the superposed waveform with the triangular wave, modulating the compared waveform into bit stream data, simulating output and input signals of the sigma-delta ADC chip, and storing the bit stream data;
the test module is used for generating an initial clock signal, modulating the initial clock signal according to an inversion operation method to obtain a clock signal, introducing preset reading times, continuously reading bit stream data from the data source generation module according to the preset reading times, and transmitting the read bit stream data to a module to be tested according to the clock signal;
the test module is used for receiving the transmitted bit stream data and displaying the transmitted bit stream data as a filtering signal;
the data source generation module is also used for displaying the superposed waveform and the comparison waveform.
Another technical solution of the present invention for solving the above technical problems is as follows: a signal simulation test method for a sigma-delta ADC chip comprises the following steps:
s1: generating a triangular wave and two sine waves according to preset parameters, superposing the two sine waves to obtain a superposed waveform, and displaying the superposed waveform;
s2: comparing the superposed waveform with the triangular wave, modulating the compared waveform into bit stream data, realizing output and input signals of an analog sigma-delta ADC chip, displaying the compared waveform, and storing the bit stream data;
s3: generating an initial clock signal, and modulating the initial clock signal according to an inversion operation method to obtain a clock signal;
s4: leading in preset reading times, and continuously reading the bit stream data according to the preset reading times;
s5: the bitstream data is displayed as a filtered signal.
The invention has the beneficial effects that: the two sine waves are superposed, the superposed waveform is modulated to obtain bit stream data, so that output and input signals of a sigma-delta ADC chip are simulated, a clock signal is modulated, the bit stream data is read according to the clock signal, the low-pass filtering effect can be achieved, the waveform can be observed in the modulation process, the filtering effect can be verified in an early stage and corrected in time through simulation test, a circuit test environment does not need to be built, the modulation efficiency is improved, and the cost is reduced.
Drawings
Fig. 1 is a functional block diagram of a sinc filter simulation test system according to an embodiment of the present invention;
fig. 2 is a flowchart of a sinc filter simulation test method according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a data source generation module according to an embodiment of the present invention.
In the drawings, the names of the components represented by the respective symbols are as follows:
1. the device comprises a first sine wave generator, a second sine wave generator, a triangular wave generator, a adder, a comparator, a first oscilloscope, a second oscilloscope, a memory and a comparator, wherein the first oscilloscope, the second oscilloscope, the third oscilloscope and the memory are sequentially connected with one another.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Fig. 1 is a functional block diagram of a signal simulation test system according to an embodiment of the present invention.
As shown in fig. 1, a signal simulation test system for a sigma-delta ADC chip includes:
the data source generation module is used for generating a triangular wave and two sine waves according to preset parameters, superposing the two sine waves to obtain a superposed waveform, comparing the superposed waveform with the triangular wave, modulating the compared waveform into bit stream data, simulating output and input signals of the sigma-delta ADC chip, and storing the bit stream data;
the test module is used for generating an initial clock signal, modulating the initial clock signal according to an inversion operation method to obtain a clock signal, introducing preset reading times, continuously reading bit stream data from the data source generation module according to the preset reading times, and transmitting the read bit stream data to a module to be tested according to the clock signal;
the test module is used for receiving the transmitted bit stream data and displaying the transmitted bit stream data as a filtering signal;
the data source generation module is also used for displaying the superposed waveform and the comparison waveform.
In the above embodiment, two sine waves are superimposed, and the superimposed waveform is modulated to obtain bit stream data, so that output and input signals of the sigma-delta ADC chip are simulated, a clock signal is modulated, the bit stream data is read according to the clock signal, a low-pass filtering effect can be achieved, the waveform can be observed during the modulation process, the filtering effect can be verified early and corrected in time through simulation test, a circuit test environment does not need to be set up, the modulation efficiency is improved, and the cost is reduced.
Fig. 3 is a schematic structural diagram of a test module according to an embodiment of the present invention.
Optionally, as an embodiment of the present invention, as shown in fig. 3, the test module includes a first sine wave generator 1, a second sine wave generator 2, a triangular wave generator 3, an adder 4, a comparator 5, a first oscilloscope 6, a second oscilloscope 7, and a memory 8; the first sine wave generator 1 and the second sine wave generator 2 are respectively connected with the adder, the adder 4 is respectively connected with the first oscilloscope 6 and the comparator 5, the triangular wave generator 3 is connected with the comparator 5, and the comparator 5 is respectively connected with the second sine wave generator 2 and the memory 4.
Specifically, a data source is generated by using matlab, two sine waves with different frequencies are superposed, and the superposed signals are modulated into 0 and 1 bit stream data.
The test module is built in a simulink environment. After the modules are built and the parameters are set, the simulink is operated, and the first sine wave and the second sine wave are superposed to obtain a superposed waveform.
In particular, the connection between the test module and the module to be tested is set up by modelsim.
Optionally, as an embodiment of the present invention, the first sine wave generator 1 is configured to generate a first sine wave according to a first preset parameter;
the second sine wave generator 2 is used for generating a second sine wave according to a second preset parameter;
the adder 5 is configured to superimpose the first sine wave and the second sine wave to obtain a superimposed waveform;
the triangular wave generator 3 is used for generating triangular waves according to a third preset parameter;
the comparator 5 is configured to compare the superimposed waveform with the triangular wave, and obtain bit stream data of 0 and 1 according to the comparison waveform;
the first oscilloscope 6 is configured to display the superimposed waveform;
the second oscilloscope 7 is used for displaying the comparison waveform;
and the memory 8 is used for generating a txt format document from the bit stream data of 0 and 1 and storing the txt format document.
In the above embodiment, two sine waves of different frequencies are added, and the result is compared with a triangular wave to obtain 0, 1 bit stream data. An environment for obtaining bit stream data of 0 and 1 is constructed by a first sine wave generator, a second sine wave generator, a triangular wave generator, an adder and a comparator.
Optionally, as an embodiment of the present invention, the first preset parameter is: the frequency of the first sine wave is 10Hz, and the amplitude is 0-500;
the second preset parameter is as follows: the frequency of the second sine wave is 20KHz, and the amplitude is 0-500;
the second preset parameter is as follows: the frequency of the triangular wave is 100KHz, and the amplitude is 0-500.
After the modules are built and the parameters are set, the simulink is operated, and the first sine wave and the second sine wave are superposed to obtain a superposed waveform.
Optionally, as an embodiment of the present invention, the module to be tested is further configured to generate a clock signal to be tested;
the test module is further specifically configured to connect to a clock signal to be tested in the test module, update the clock signal to be tested according to the clock signal, and transmit read bit stream data to the test module whenever the clock signal is at a rising edge.
Specifically, the connection of the clock signal of the test module and the clock signal of the module to be tested, and the connection of the bit stream signals of the test module 0 and 1 and the data input signal of the module to be tested are realized by instantiating the module to be tested in modelsim.
Specifically, the 0, 1 bit stream data generated by the test module is read and transmitted to the data input terminal adc _ mdat _ i of the module to be tested on the rising edge of the clock signal adc _ mclk.
Optionally, as an embodiment of the present invention, the test module is specifically configured to perform an inversion operation on the initial clock signal according to a preset clock frequency and an inversion operation method, so as to generate a clock signal.
Optionally, as an embodiment of the present invention, the preset clock frequency is an inversion operation performed every 50 ns.
Specifically, the inversion operation is performed every 50ns clock, and the frequency of the generated clock signal is 10M.
In the above embodiment, the bit stream data is read when the clock signal is at the rising edge, so that a high-frequency signal of 20KHz can be filtered out, and a low-frequency signal of 10Hz is retained, thereby playing a role of low-pass filtering.
It should be understood that the testing module and the module to be tested of the system are equivalent to a sinc filter, the high-frequency signal of 20KHz is filtered out by the analog sinc filter, the low-frequency signal of 10Hz is reserved, and the function of low-pass filtering is achieved, so that the filtering effect of the sinc filter is verified. Furthermore, through simulation test, the filtering result can be observed in an early stage and corrected in time.
Fig. 2 is a flowchart of a sinc filter simulation test method according to an embodiment of the present invention.
Alternatively, as another embodiment of the present invention, as shown in fig. 2, a signal simulation test method for a sigma-delta ADC chip includes the following steps:
s1: generating a triangular wave and two sine waves according to preset parameters, superposing the two sine waves to obtain a superposed waveform, and displaying the superposed waveform;
s2: comparing the superposed waveform with the triangular wave, modulating the compared waveform into bit stream data, realizing output and input signals of an analog sigma-delta ADC chip, displaying the compared waveform, and storing the bit stream data;
s3: generating an initial clock signal, and modulating the initial clock signal according to an inversion operation method to obtain a clock signal;
s4: leading in preset reading times, and continuously reading the bit stream data according to the preset reading times;
s5: and obtaining a filtering signal from the read bit stream data according to the clock signal, and displaying the filtering signal. Optionally, as another embodiment of the present invention, the process of step S1 includes:
generating a first sine wave according to a first preset parameter;
generating a second sine wave according to a second preset parameter;
superposing the first sine wave and the second sine wave to obtain a superposed waveform, and displaying the superposed waveform;
generating a triangular wave according to a third preset parameter;
comparing the superposed waveform with the triangular wave, obtaining bit stream data of 0 and 1 according to the compared waveform, and displaying the compared waveform;
and generating a txt format document from the bit stream data of 0 and 1, and storing the txt format document.
Specifically, the first preset parameter is: the frequency of the first sine wave is 10Hz, and the amplitude is 0-500;
the second preset parameter is as follows: the frequency of the second sine wave is 20KHz, and the amplitude is 0-500;
the second preset parameter is as follows: the frequency of the triangular wave is 100KHz, and the amplitude is 0-500.
Optionally, as another embodiment of the present invention, the process of obtaining the filtered signal from the read bitstream data according to the clock signal is:
the read bitstream data is taken as a filtered signal whenever the clock signal is on a rising edge.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. A sinc filter simulation test system for a sigma-delta ADC chip, comprising:
the data source generation module is used for generating a triangular wave and two sine waves according to preset parameters, superposing the two sine waves to obtain a superposed waveform, comparing the superposed waveform with the triangular wave, modulating the compared waveform into bit stream data, simulating output and input signals of the sigma-delta ADC chip, and storing the bit stream data;
the test module is used for generating an initial clock signal, modulating the initial clock signal according to an inversion operation method to obtain a clock signal, introducing preset reading times, continuously reading bit stream data from the data source generation module according to the preset reading times, and transmitting the read bit stream data to a module to be tested according to the clock signal;
the test module is used for receiving the transmitted bit stream data and displaying the transmitted bit stream data as a filtering signal;
the data source generation module is also used for displaying the superposed waveform and the comparison waveform.
2. The sinc filter simulation test system of claim 1, wherein the data source generation module comprises a first sine wave generator, a second sine wave generator, a triangular wave generator, an adder, a comparator, a first oscilloscope, a second oscilloscope, and a memory; the first sine wave generator and the second sine wave generator are respectively connected with the adder, the adder is respectively connected with the first oscilloscope and the comparator, the triangular wave generator is connected with the comparator, and the comparator is respectively connected with the second oscilloscope and the memory.
3. The sinc filter simulation test system of claim 2,
the first sine wave generator is used for generating a first sine wave according to a first preset parameter;
the second sine wave generator is used for generating a second sine wave according to a second preset parameter;
the adder is used for overlapping the first sine wave and the second sine wave to obtain an overlapped waveform;
the triangular wave generator is used for generating triangular waves according to a third preset parameter;
the comparator is used for comparing the superposed waveform with the triangular wave and obtaining bit stream data of 0 and 1 according to the compared waveform;
the first oscilloscope is used for displaying the superposed waveform;
the second oscilloscope is used for displaying the comparison waveform;
and the memory is used for generating a txt format document from the bit stream data of 0 and 1 and storing the txt format document.
4. The sinc filter simulation test system of claim 3,
the first preset parameter is as follows: the frequency of the first sine wave is 10Hz, and the amplitude is 0-500;
the second preset parameter is as follows: the frequency of the second sine wave is 20KHz, and the amplitude is 0-500;
the second preset parameter is as follows: the frequency of the triangular wave is 100KHz, and the amplitude is 0-500.
5. The signal simulation test system according to any one of claims 1 to 4, wherein the test module is specifically configured to perform an inversion operation on the initial clock signal according to a preset clock frequency and an inversion operation method to generate a clock signal.
6. The signal modulation system according to claim 5, wherein the predetermined clock frequency is inverted every 50 ns.
7. The sinc filter simulation test system of any one of claims 1 to 4, wherein the module under test is further configured to generate a clock signal to be tested;
the test module is further specifically configured to connect to a clock signal to be tested in the test module, update the clock signal to be tested according to the clock signal, and transmit read bit stream data to the test module whenever the clock signal is at a rising edge.
8. A simulation test method of a sinc filter for a sigma-delta ADC chip is characterized by comprising the following steps:
s1: generating a triangular wave and two sine waves according to preset parameters, superposing the two sine waves to obtain a superposed waveform, and displaying the superposed waveform;
s2: comparing the superposed waveform with the triangular wave, modulating the compared waveform into bit stream data, realizing output and input signals of an analog sigma-delta ADC chip, displaying the compared waveform, and storing the bit stream data;
s3: generating an initial clock signal, and modulating the initial clock signal according to an inversion operation method to obtain a clock signal;
s4: leading in preset reading times, and continuously reading the bit stream data according to the preset reading times;
s5: and obtaining a filtering signal from the read bit stream data according to the clock signal, and displaying the filtering signal.
9. The sinc filter simulation test method of claim 8, wherein the process of S1 comprises:
generating a first sine wave according to a first preset parameter;
generating a second sine wave according to a second preset parameter;
generating a triangular wave according to a third preset parameter;
superposing the first sine wave and the second sine wave to obtain a superposed waveform, and displaying the superposed waveform;
comparing the superposed waveform with the triangular wave, obtaining bit stream data of 0 and 1 according to the compared waveform, and displaying the compared waveform;
and generating a txt format document from the bit stream data of 0 and 1, and storing the txt format document.
10. The sinc filter simulation test method of claim 8 or 9, wherein the process of obtaining the filtered signal from the read bitstream data according to the clock signal is:
the read bitstream data is taken as a filtered signal whenever the clock signal is on a rising edge.
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