CN117648664A - Data processing method and device based on multi-digital filter fusion - Google Patents
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Abstract
The invention provides a data processing method and a device based on multi-digital filter fusion, wherein the method comprises the steps of obtaining an original data stream; synchronizing the original data stream to a system clock domain and configuring a corresponding target digital filter according to a set parameter and an output rate; transmitting the original data stream to the target digital filter to trigger the target digital filter to execute preset calculation in a corresponding effective time sequence so as to obtain a filtered target data stream; outputting the target data stream after the filtering processing according to the set output rate; wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period. The same group of operation units are multiplexed in a time-sharing way, so that the number of the operation units which are actually called is relatively small, and the power consumption of the digital processing circuit is reduced and the area of the digital processing circuit is minimized.
Description
Technical Field
The invention relates to the technical field of digital signal processing, in particular to a data processing method and device based on multi-digital filter fusion.
Background
With the development of very large scale integrated circuit technology, digital filters are one of the important branches of digital signal processing, and are a widely used component in voice, image signal processing and digital communication. Since a digital filter includes a large number of operations, it is demanded to make full use of hardware resources and reduce the area while high performance is being sought, and this is a currently attracting attention.
FIG. 1 is a block diagram of a data processing flow provided in the conventional art. As shown in fig. 1, in the data processing scheme provided by the conventional technology, implementation paths of a plurality of digital filters are separated independently, each digital filter includes an adder and a multiplier, and when each digital filter performs a filtering process, operation units such as the adder and the multiplier need to be called respectively, so that a digital-analog hybrid circuit chip with a digital processing circuit is larger in size, higher in working voltage, and often, area and power consumption are important technical indexes of the design of the digital-analog hybrid circuit chip.
In addition, when digital signals with different frequencies are sampled, noise suppression and bandwidth of the digital signals with different frequencies are also different, so that the digital signals are also required to be output at different data output rates. Similarly, for different sampling frequencies and data output frequencies, the digital processing circuit of the subsequent stage also needs to select different types of digital filters according to different application scenarios.
Therefore, in order to solve the above-mentioned technical problems, it is needed to provide a data processing method and device based on multi-digital filter fusion.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a data processing method and device based on multi-digital filter fusion, so as to solve the technical problems in the prior art.
The invention adopts the following technical scheme:
according to an aspect of the present invention, there is provided a data processing method based on multi-digital filter fusion, wherein the method includes: acquiring an original data stream; synchronizing the original data stream to a system clock domain and configuring a corresponding target digital filter according to a set parameter and an output rate; transmitting the original data stream to the target digital filter to trigger the target digital filter to execute preset calculation in a corresponding effective time sequence so as to obtain a filtered target data stream; outputting the target data stream after the filtering processing according to the set output rate; wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period.
Further, the method further comprises: a matched system clock frequency is determined based on the conversion frequency of the ADC.
Further, the method for determining the matched system clock frequency based on the conversion frequency of the ADC comprises the following steps:
determining a number of available system clock cycles in each ADC conversion period based on the ADC conversion time and the system clock frequency to determine a matched system clock frequency; and/or
Distributing the number of system clock cycles corresponding to the operation resources according to the operation resources required by each digital filter for executing the preset calculation, and determining the matched system clock frequency according to the number of the system clock cycles; wherein a calculation step is allocated in each of said system clock cycles.
Further, the transmitting the raw data stream to the target digital filter to trigger the target digital filter to perform a preset calculation within a corresponding valid time sequence includes: in the effective timing of each of the target digital filters, the values and coefficients of the original data stream are applied to the inputs of the combinational logic in the same set of multiply-add devices by sequentially applying them to the inputs of the combinational logic.
Further, the method further comprises: and adopting gating clock control to enable the high-frequency clock only in the operation window corresponding to each target digital filter.
Optionally, the method further comprises: data is received and the selected digital filter is configured in a register table corresponding to the different target output rates.
Further, the method for outputting the target data stream in the corresponding data output period includes:
configuring a current data output rate;
and outputting the target data stream in a corresponding data output period according to the current data output rate.
Further, the method for outputting the target data stream in the corresponding data output period further comprises:
judging whether the current operation period is the output period of the set data output rate or not;
if yes, carrying out subsequent calibration calculation on the data of the target data stream after the current filtering processing and outputting final conversion data;
otherwise, the target data stream after the current filtering processing is stored and transferred to the next ADC conversion period for processing.
Further, the method further comprises: and performing calibration processing on the output target data stream.
According to another aspect of the present invention, there is provided a data processing apparatus based on multi-digital filter fusion, the apparatus comprising:
a data acquisition unit for acquiring an original data stream;
the synchronization and matching unit is used for synchronizing the original data stream to a system clock domain and configuring a corresponding target digital filter according to the setting parameters and the output rate;
the data processing unit is used for receiving the original data stream and triggering the target digital filter to execute preset calculation in a corresponding effective time sequence so as to obtain a filtered target data stream; and
the data output unit is used for outputting the target data stream after the filtering processing according to the set output rate;
wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period.
Compared with the common technology, the data processing method and device based on multi-digital filter fusion provided by the embodiment of the invention have the advantages that the number of the actually-called operation units is small by multiplexing the same group of operation units in a time-sharing way, and in a digital-analog hybrid chip, even if the characteristic size is large and the working voltage is high, the power consumption of a digital processing circuit can be reduced, and the area of the digital processing circuit is minimized.
Furthermore, the high-frequency system clock is gated, so that the digital processing circuit has good balance among operation speed, area and power consumption.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a data processing flow provided in the conventional art.
Fig. 2 is a flow chart of a data processing method based on multi-digital filter fusion according to an embodiment of the present invention.
FIG. 3 is a block diagram of a data processing flow provided by an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a calculation step of a system clock period corresponding to an ADC conversion period according to an embodiment of the invention.
Fig. 5 is a timing diagram of a CIC filter in a non-decimated period according to an embodiment of the invention.
Fig. 6 is a timing diagram of a CIC filter at a decimation period according to an embodiment of the invention.
FIG. 7 is a timing diagram of a window function filter at a non-output period according to an embodiment of the present invention.
Fig. 8 is a timing diagram of a window function filter at an output period according to an embodiment of the present invention.
Fig. 9 is a block diagram of a data processing apparatus based on multiple digital filter fusion according to an embodiment of the present invention.
Detailed Description
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Fig. 2 is a flow chart of a data processing method based on multi-digital filter fusion according to an embodiment of the present invention, and fig. 3 is a flow chart of data processing according to an embodiment of the present invention.
Referring to fig. 2, a data processing method based on multi-digital filter fusion provided by an embodiment of the present invention includes the following steps:
step S10, obtaining an original data stream;
step S20, synchronizing the original data stream to a system clock domain and configuring a corresponding digital filter according to a setting parameter and an output rate;
step S30, transmitting the original data stream to the target digital filter to trigger the target digital filter to execute preset calculation in a corresponding effective time sequence so as to obtain a filtered target data stream;
step S40, outputting the target data stream after the filtering processing according to the set output rate;
wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period.
Steps S10 to S40 will be specifically described below with reference to fig. 3.
In step S10, the ADC receives a corresponding plurality of analog signals and outputs a corresponding digital signal, for example, a bit stream as a digital signal. In the embodiment of the invention, the data stream converted by the ADC is obtained as an original data stream.
In step S20, the original data stream is synchronized to a system clock domain and a target digital filter matching the original data stream is selected from a plurality of digital filters according to a target output rate of the original data stream. This is because the original data stream and the system clock belong to two different systems, each having a different clock, and if the synchronization process is not performed, a clock violation phenomenon occurs. Therefore, the raw data stream output by the ADC conversion needs to be synchronized to the system clock domain before being input to the digital signal processing circuit for processing.
For example, the target output rate of the original data stream may have different configurations according to application scenarios, so the register table may be generally written by using an SPI universal interface, different filters may be used according to the target output rate configuration of the original data stream and different filtering requirements (spectrum response), for example, in the embodiment of the present invention, a vanity filter (Cascaded integrator comb filter, CIC) or a window function filter or a combination of both may be configured for different cut-off frequencies and for the suppression effect of 50hz and 60hz of the power frequency. In addition, other types of filters may be configured and used according to different application requirements, and embodiments of the present invention are not limited herein.
In step S30, the original data stream is transmitted to the target digital filter to trigger the target digital filter to perform a preset calculation in a corresponding effective time sequence, so as to obtain a filtered target data stream;
in particular, since the ADC in this example is an "oversampling ADC", it is often necessary to perform continuous decimation in the post-stage digital processing circuit of the ADC output, for example, decimating one data stream (data signal) at intervals to finally achieve the effect of moving average, and different frequency spectrums have different decimation patterns, thereby configuring different filters. For example, a comb filter (CIC) is used as one of the decimation filters, which has a simple structure, has only an adding unit, can realize multiple-rate down-conversion, and can filter out high-frequency components. And the method can be used as a simple and effective sample rate conversion method without multiplying factors and storing coefficients. Comb filters (CIC) are typically formed by a cascade of an integrating comb filter, also called integrating part, and a decimating filter, also called differencing part.
Illustratively, in an embodiment of the present invention, the ADC may be a Sigma Delta ADC or similar type of circuit, the ADC having an oversampling ratio (OSR) of N, where N is a positive integer greater than 1. For example, a 1-bit ADC may have an OSR of n=3600, and the OSR of the ADC may be set by the control logic.
The target digital filter is triggered to perform corresponding digital filtering operation under the corresponding effective time sequence, and performs preset calculation, for example, the comb filter (CIC) performs 3 times of integral operation and then extracts, and then performs 3 times of differential operation and outputs. In general, the effective timing corresponds to a period from a low level to a high level of a pulse waveform of a system clock cycle.
In step S40, when digital signals of different frequencies are sampled, the digital signals of different frequencies are different in noise suppression and bandwidth, and therefore, it is also necessary to output at different data output rates. In the embodiment of the invention, different data output rates can be configured at the output end of the target digital filter, and the extraction multiple and the multiplication and addition coefficient of the digital filter are adjusted according to the different output rates, so that the filtered target data stream is output according to the set data output rate.
Wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period.
Illustratively, the method for outputting the filtered target data stream at the set output rate includes: configuring a current data output rate; and outputting the target data stream in a corresponding data output period according to the current data output rate.
Illustratively, the method for outputting the filtered target data stream at the set output rate further includes: judging whether the current operation period is the output period of the set data output rate or not;
if yes, carrying out subsequent calibration calculation on the data of the target data stream after the current filtering processing and outputting final conversion data;
otherwise, the target data stream after the current filtering processing is stored and transferred to the next ADC conversion period for processing.
The technical scheme provided by the embodiment of the invention realizes the fusion of multiple digital filters by adopting a mode of multiplexing the same group of multiply-add devices in a time-sharing way, thereby achieving the purpose of reducing the area of a digital circuit and static power consumption. By reducing the area of the digital circuit, the cost can be well controlled while the performance of the digital-analog hybrid chip is improved.
Further, the method further comprises: a matched system clock frequency is determined based on the conversion frequency of the ADC.
Specifically, in one embodiment, prior to circuit design, the number of system clock cycles available at each ADC conversion cycle is determined based on the ADC conversion time and the system clock frequency to determine a matching system clock frequency.
In yet another embodiment, according to an operation resource required by each digital filter to execute the preset calculation, the number of system clock cycles corresponding to the operation resource is allocated, and according to the number of system clock cycles, the matched system clock frequency is determined; wherein a calculation step is allocated in each of said system clock cycles.
In another embodiment, the two embodiments may be combined.
Fig. 4 is a schematic diagram illustrating a calculation step of a system clock period corresponding to an ADC conversion period according to an embodiment of the invention.
As shown in fig. 4, the computation steps required for the plurality of digital filters are arranged within each system clock cycle, wherein each computation step will time-division multiplex the same set of multiply-add devices 1. It should be appreciated that the plurality of digital filters share the same digital signal processing link and are time-division triggered to perform preset calculations within an effective time sequence.
For example, the conversion frequency of the ADC is 256Khz (which is typically determined by analog circuitry), and the relationship between the corresponding system clock frequency and the conversion frequency of the ADC is estimated by computing resources required for each of a plurality of digital filters on subsequent digital signal processing links to subsequently perform the preset calculation, if the CIC filter requires to perform 6 calculation steps, the window function filter requires to perform 3 calculation steps, and the calculation steps of subsequent calibration calculations. At this time, the clock frequency of the system is 4096Khz, which can meet the calculation cycle requirement.
Further, the transmitting the raw data stream to the target digital filter to trigger the target digital filter to perform a preset calculation within a corresponding valid time sequence includes: in the effective timing of each of the target digital filters, the values and coefficients of the original data stream are applied to the inputs of the combinational logic in the same set of multiply-add devices by sequentially applying them to the inputs of the combinational logic. The mode of the combination logic is adopted to transfer the input one stage and the first stage, and then the needed data is fetched through the time sequence control logic.
Alternatively, the coefficients may be stored by each target digital filter itself or may be generated by controlling writing to a register table or generating a desired coefficient sequence. The embodiments of the present invention are not limited herein.
Optionally, the method further comprises: data is received and the selected digital filter is configured in a register table corresponding to the different target output rates.
Further, the method further comprises: and performing calibration processing on the output target data.
Fig. 5 is a timing diagram of a CIC filter in a non-decimated period according to an embodiment of the invention.
As shown in fig. 5, in the non-decimation period of the CIC filter, the CIC integrating part is an operation window, and the CIC differentiating part is a non-operation window, so in each ADC conversion period, only the high frequency clock of the system needs to be connected to the operation unit in the time window corresponding to the CIC integrating part (operation window), and the other non-operation window time windows are gated by the clock so that the high frequency clock of the system is low and not turned over. That is, only the multiplier-adder 1 at this time allows the system high-frequency clock to access the register storing the operation result in the time window corresponding to the CIC integration section (operation window), and takes out the operation data. Specifically, the gating clock module is used for controlling the system clock to be released only in the operation window period of the target digital filter, and the system clock is closed in other non-operation window periods, so that the high-frequency system clock does not need to be started all the time, and the dynamic power consumption caused by the turnover of the high-frequency clock is reduced.
Fig. 6 is a timing diagram of a CIC filter at a decimation period according to an embodiment of the invention.
As shown in fig. 6, in the extraction period, that is, in the data output period, the operation window in the CIC integration section and the operation window in the CIC difference section and the operation window in the subsequent calculation step enable the high frequency clock of the system, that is, the operation window in the CIC integration section and the operation window in the CIC difference section and the operation window in the subsequent calculation step access the storage register of the operation result.
It should be noted that, since the processing of the data may not be completed in the current ADC conversion period, another set of multiplier-adder 2 may be turned on at the same time in the next ADC conversion period, and the calibration calculation may be performed while the digital filtering process is being performed.
FIG. 7 is a timing diagram of a window function filter at a non-output period according to an embodiment of the present invention. Fig. 8 is a timing diagram of a window function filter at an output period according to an embodiment of the present invention.
As shown in fig. 7 and 8, for example, if the "oversampling" of the ADC employs a decimation of 64 times, the decimation needs to be performed in the corresponding 64 ADC conversion periods, where the window function filter is in a non-output period, such as only multiplication, multiplied by the corresponding coefficient, from the 1 st ADC conversion period to the 63 st ADC conversion period. And at the 64 th ADC conversion period, the window function filter is at the output period. Similarly, when the window function filters are all in the non-output period, the system clock is released only in the operation window, and the system clock is closed in other non-operation window periods, so that the high-frequency system clock does not need to be always started, and the dynamic power consumption caused by the turnover of the high-frequency clock is reduced. When the window function filters are all in the output period, the high-frequency clock of the system is started in both the operation window of the window function filters and the operation window of the subsequent calculation step.
Compared with the common technology, the data processing method and device based on multi-digital filter fusion provided by the embodiment of the invention have the advantages that the number of the actually-called operation units is small by multiplexing the same group of operation units in a time-sharing way, and in a digital-analog hybrid chip, even if the characteristic size is large and the working voltage is high, the power consumption of a digital processing circuit can be reduced, and the area of the digital processing circuit is minimized.
Furthermore, the high-frequency system clock is gated, so that the digital processing circuit has good balance among operation speed, area and power consumption.
Further, when the operation period is not satisfied, another set of operation units (e.g., the multiplier-adder 2) may be turned on in parallel, which balances the operation speed and the area power consumption of the digital processing circuit. By reducing the area of the digital processing circuit, the cost can be well controlled while the performance of the digital-analog hybrid chip is improved.
Fig. 9 is a block diagram of a data processing apparatus based on multiple digital filter fusion according to an embodiment of the present invention.
As shown in fig. 9, according to another aspect of the present invention, an embodiment of the present invention further provides a data processing apparatus 300 based on multiple digital filter fusion, where the apparatus 300 includes:
a data acquisition unit 310 for acquiring an original data stream;
a synchronizing and matching unit 320, configured to synchronize the original data stream to a system clock domain and configure a corresponding digital filter according to a setting parameter and an output rate;
the data processing unit 330 is configured to receive the original data stream and trigger the target digital filter to perform a preset calculation in a corresponding effective time sequence, so as to obtain a filtered target data stream;
a data output unit 340, configured to output the filtered target data stream according to a set output rate;
wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period.
Illustratively, in the data acquisition unit 310, the ADC receives a corresponding plurality of analog signals and outputs a corresponding digital signal, such as a bit stream, as a digital signal. In the embodiment of the invention, the data stream converted by the ADC is obtained as an original data stream.
The synchronization and matching unit 320 includes a selector for selecting a matched one of the target digital filters based on different application scenarios.
After synchronizing the original data stream to a system clock domain, a target digital filter that matches the original data stream is selected from a plurality of digital filters according to a target output rate of the original data stream.
For example, the target output rate of the original data stream may have different configurations according to application scenarios, so the register table may be generally written by using an SPI universal interface, different filters may be used according to the target output rate configuration of the original data stream and different filtering requirements (spectrum response), for example, in the embodiment of the present invention, a vanity filter (Cascaded integrator comb filter, CIC) or a window function filter or a combination of both may be configured for different cut-off frequencies and for the suppression effect of 50hz and 60hz of the power frequency. In addition, other types of filters may be configured and used according to different application requirements, and embodiments of the present invention are not limited herein.
The data output unit 340 includes a discriminator for judging whether the current operation period is an output period of the set data output rate according to the currently configured data output rate.
By adopting the technical scheme provided by the embodiment of the invention, the same group of operation units are multiplexed in a time-sharing way, so that the number of the operation units which are actually called is relatively small, and in a digital-analog hybrid chip, even if the characteristic size is large and the working voltage is high, the power consumption of the digital processing circuit can be reduced, and the area of the digital processing circuit is minimized.
It should be understood that the execution principle, other aspects and effects of each unit (module) in the data processing apparatus based on the multiple digital filter fusion can be referred to the content of the foregoing embodiment, and will not be repeated herein.
The above describes in detail the data processing method and apparatus based on multiple digital filters fusion provided by the embodiments of the present invention, and specific examples are applied to describe the principles and embodiments of the present invention, where the description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A method for processing data based on multiple digital filter fusion, the method comprising:
acquiring an original data stream;
synchronizing the original data stream to a system clock domain and configuring a corresponding target digital filter according to a set parameter and an output rate;
transmitting the original data stream to the target digital filter to trigger the target digital filter to execute preset calculation in a corresponding effective time sequence so as to obtain a filtered target data stream;
outputting the target data stream after the filtering processing according to the set output rate;
wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period.
2. The multiple digital filter fusion-based data processing method of claim 1, further comprising:
a matched system clock frequency is determined based on the conversion frequency of the ADC.
3. The multiple digital filter fusion-based data processing method of claim 2, wherein the method of determining the matched system clock frequency based on the conversion frequency of the ADC comprises:
determining a number of available system clock cycles in each ADC conversion period based on the ADC conversion time and the system clock frequency to determine a matched system clock frequency; and/or
Distributing the number of system clock cycles corresponding to the operation resources according to the operation resources required by each digital filter for executing the preset calculation, and determining the matched system clock frequency according to the number of the system clock cycles; wherein a calculation step is allocated in each of said system clock cycles.
4. The method of claim 1, wherein transmitting the raw data stream to the target digital filter to trigger the target digital filter to perform a preset calculation within a corresponding effective time sequence comprises:
in the effective timing of each of the target digital filters, the values and coefficients of the original data stream are applied to the inputs of the combinational logic in the same set of multiply-add devices by sequentially applying them to the inputs of the combinational logic.
5. The multiple digital filter fusion-based data processing method of claim 1, further comprising:
and adopting gating clock control to enable the high-frequency clock only in the operation window corresponding to each target digital filter.
6. The multiple digital filter fusion-based data processing method of claim 1, further comprising:
data is received and the selected digital filter is configured in a register table corresponding to the different target output rates.
7. The method for processing data based on multiple digital filters fusion according to claim 1, wherein the method for outputting the filtered target data stream at a set output rate comprises:
configuring a current data output rate;
and outputting the target data stream in a corresponding data output period according to the current data output rate.
8. The multiple digital filter fusion-based data processing method according to claim 7, wherein the method of outputting the filtered target data stream at a set output rate further comprises:
judging whether the current operation period is the output period of the set data output rate or not;
if yes, carrying out subsequent calibration calculation on the data of the target data stream after the current filtering processing and outputting final conversion data;
otherwise, the target data stream after the current filtering processing is stored and transferred to the next ADC conversion period for processing.
9. The multiple digital filter fusion-based data processing method of claim 1, further comprising:
and performing calibration processing on the output target data stream.
10. A data processing apparatus based on multiple digital filter fusion, the apparatus comprising:
a data acquisition unit for acquiring an original data stream;
the synchronization and matching unit is used for synchronizing the original data stream to a system clock domain and configuring a corresponding target digital filter according to the setting parameters and the output rate;
the data processing unit is used for receiving the original data stream and triggering the target digital filter to execute preset calculation in a corresponding effective time sequence so as to obtain a filtered target data stream; and
the data output unit is used for outputting the target data stream after the filtering processing according to the set output rate;
wherein the plurality of digital filters time-division multiplex the same set of multiply-add devices within one ADC conversion period.
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