CN117334732A - Planar silicon carbide MOSFET with high-K dielectric layer and preparation method - Google Patents
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention discloses a planar silicon carbide MOSFET with a high-K dielectric layer and a preparation method thereof, wherein the planar silicon carbide MOSFET comprises the high-K dielectric layer; the high-K dielectric layer is positioned between the drift layer and the gate oxide layer; the high-K dielectric layer is adjacent to the drift layer and the gate oxide layer. According to the invention, the high-K dielectric layer is inserted between the drift layer and the gate oxide layer of the silicon carbide MOSFET, so that the performance of the silicon carbide MOSFET device is improved, the high-K dielectric layer can bear larger voltage than silicon dioxide, and the reliability of the gate dielectric layer is enhanced; the high-K dielectric layer can enable the gate oxide layer and the dielectric layer to be laminated to be thinner, so that the on-resistance of the silicon carbide MOSFET device is reduced; the high-K dielectric layer effectively blocks diffusion of carbon atoms in silicon carbide to the gate oxide layer to form an interface state, and improves channel mobility of the silicon carbide MOSFET device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a planar silicon carbide MOSFET with a high-K dielectric layer and a preparation method thereof.
Background
In the development of the power electronics industry, semiconductor technology plays a decisive role. Among them, power semiconductor devices have been considered as a key component of power electronics. With the widespread use of power electronics technology in industry, medical treatment, traffic, consumer, etc., power semiconductor devices directly affect the cost and efficiency of these power electronics devices. Silicon-based power semiconductor devices have played an important role since the fifties of the twentieth century when vacuum tubes were replaced by solid state devices. However, with increasing industry demand, silicon MOSFET devices have begun to be unsuitable for some high voltage, high temperature, high efficiency, and high power density applications due to their own physical limitations.
Silicon carbide materials have been attracting attention and research due to their superior physical properties. Compared with the silicon materials widely used at present, the silicon carbide material has higher thermal conductivity and higher forbidden bandwidth. The higher thermal conductivity determines the characteristics of the silicon carbide MOSFET device with high current density, and the higher forbidden bandwidth determines the high breakdown voltage and high operating temperature of the silicon carbide MOSFET device. In the aspect of application of the silicon carbide MOSFET device, compared with the silicon MOSFET device with the same power level, the on-resistance and the switching loss of the silicon carbide MOSFET device are greatly reduced, the silicon carbide MOSFET device is suitable for higher working frequency, and the high-temperature stability is greatly improved due to the high-temperature working characteristic of the silicon carbide MOSFET device. The silicon carbide MOSFET of the third-generation semiconductor device is widely applied to the fields of high voltage, high frequency and high power such as new energy automobiles, high-speed rails and smart grids due to the advantages of large forbidden bandwidth, high critical breakdown field intensity, high thermal conductivity, high dielectric constant and the like.
At present, a silicon dioxide gate dielectric layer grown on silicon carbide of a silicon carbide MOSFET device is limited by the existence of carbon atom impurities, the interface state density of the silicon dioxide gate dielectric layer is higher than that of the silicon dioxide gate dielectric layer grown on silicon, the dielectric constant of the silicon dioxide gate dielectric layer is smaller than that of the silicon carbide, and the risk of breakdown in advance exists, so that the reliability problem of the gate dielectric layer in a high-voltage high-frequency environment exists in the silicon carbide MOSFET device, which is a main problem limiting the application prospect of the silicon carbide MOSFET device.
Disclosure of Invention
In order to solve at least one technical problem, the invention aims to provide a planar silicon carbide MOSFET with a high-K dielectric layer and a preparation method thereof, so as to solve the problem of reliability of a grid dielectric layer of a silicon carbide MOSFET device.
The aim of the invention is realized by adopting the following technical modes:
in a first aspect, the present invention provides a planar silicon carbide MOSFET having a high-K dielectric layer, comprising a high-K dielectric layer;
the high-K dielectric layer is positioned between the drift layer and the gate oxide layer;
the high-K dielectric layer is adjacent to the drift layer and the gate oxide layer.
Preferably, the ratio of the dielectric constant of the high-K dielectric layer to the dielectric constant of silicon carbide is greater than 2.
Preferably, the dielectric constant of the high-K dielectric layer is 20-30.
Preferably, the length of the high-K dielectric layer is 4um.
Preferably, the thickness of the high-K dielectric layer is 5nm.
Preferably, the distance between the high-K dielectric layer and the grid electrode is 20nm.
Preferably, the material of the high-K dielectric layer is HfGdON.
Preferably, the semiconductor device further comprises a drain electrode, a substrate, a drift layer, a P well layer, an N+ layer, a P+ layer, a gate electrode and a source electrode;
the drain electrode is positioned below the substrate;
the substrate is positioned below the drift layer;
the P+ layer, the P well layer and the N+ layer are positioned on the upper layer of the drift layer;
the N+ layer is positioned above the P well layer;
the source is located above the n+ layer and the p+ layer.
In a second aspect, the present invention provides a method for fabricating a planar silicon carbide MOSFET having a high K dielectric layer, comprising:
epitaxially forming a drift layer on a substrate;
forming a P well layer by ion implantation on the upper layer of the drift layer;
forming a dielectric layer over the drift layer;
depositing silicon dioxide above the dielectric layer to form a gate oxide layer;
depositing polysilicon above the gate oxide layer to form a gate;
depositing silicon dioxide above the grid electrode to form a protective layer;
forming an N+ layer and a P+ layer on the upper layer of the P well layer through ion implantation annealing;
a source is formed over the n+ layer and the p+ layer, and a drain is formed under the substrate.
Preferably, the forming a dielectric layer above the drift layer includes:
depositing HfO over the drift layer 2 ；
The HfO is subjected to 2 At N 2 Gd doping is performed in the environment of (1) to form an HfGdON dielectric layer.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the high-K dielectric layer is inserted between the drift layer and the gate oxide layer of the silicon carbide MOSFET, so that the performance of the silicon carbide MOSFET device is improved; the high-K dielectric layer can bear larger voltage than silicon dioxide, so that the reliability of the gate dielectric layer is enhanced; the high-K dielectric layer can enable the gate oxide layer and the dielectric layer to be laminated to be thinner, so that the on-resistance of the silicon carbide MOSFET device is reduced; the high-K dielectric layer effectively blocks diffusion of carbon atoms in silicon carbide to the gate oxide layer to form an interface state, and improves channel mobility of the silicon carbide MOSFET device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
In order to more clearly describe the technical solutions in the embodiments or the background of the present application, the following description will describe the drawings that are required to be used in the embodiments or the background of the present application.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 is a schematic structural diagram of a planar silicon carbide MOSFET with a high K dielectric layer according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for preparing a planar silicon carbide MOSFET with a high-K dielectric layer according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram a of a method for manufacturing a planar silicon carbide MOSFET with a high-K dielectric layer according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram B of a method for manufacturing a planar silicon carbide MOSFET with a high K dielectric layer according to an embodiment of the present invention.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without some of these specific details. In some instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present invention.
Silicon carbide materials have been attracting attention and research due to their superior physical properties. Compared with the silicon materials widely used at present, the silicon carbide material has higher thermal conductivity and higher forbidden bandwidth. The higher thermal conductivity determines the characteristics of the silicon carbide MOSFET device with high current density, and the higher forbidden bandwidth determines the high breakdown voltage and high operating temperature of the silicon carbide MOSFET device. In the aspect of application of the silicon carbide MOSFET device, compared with the silicon MOSFET device with the same power level, the on-resistance and the switching loss of the silicon carbide MOSFET device are greatly reduced, the silicon carbide MOSFET device is suitable for higher working frequency, and the high-temperature stability is greatly improved due to the high-temperature working characteristic of the silicon carbide MOSFET device. The silicon carbide MOSFET of the third-generation semiconductor device is widely applied to the fields of high voltage, high frequency and high power such as new energy automobiles, high-speed rails and smart grids due to the advantages of large forbidden bandwidth, high critical breakdown field intensity, high thermal conductivity, high dielectric constant and the like.
At present, a silicon dioxide gate dielectric layer grown on silicon carbide of a silicon carbide MOSFET device is limited by the existence of carbon atom impurities, and the interface state density is 3 orders of magnitude higher than that of a silicon dioxide gate dielectric layer grown on traditional silicon, so that the channel mobility of the silicon carbide MOSFET device is lower than that of the silicon MOSFET device; the ratio of the dielectric constant of silicon carbide to the dielectric constant of silicon dioxide is about 2.5, so the electric field strength inside the silicon dioxide gate dielectric layer is about 2.5 times that inside silicon carbide, and the silicon dioxide gate dielectric has the risk of breakdown in advance under the environment of a large electric field. The problem causes the reliability problem of the grid dielectric layer in the high-voltage high-frequency environment of the silicon carbide MOSFET device, which is a main problem of limiting the application prospect of the silicon carbide MOSFET device.
According to the invention, the high-K dielectric layer is inserted between the drift layer and the gate oxide layer of the silicon carbide MOSFET, so that the performance of the silicon carbide MOSFET device is improved; the high-K dielectric layer can bear larger voltage than silicon dioxide, so that the reliability of the gate dielectric layer is enhanced; the high-K dielectric layer can enable the gate oxide layer and the dielectric layer to be laminated to be thinner, so that the on-resistance and the cost of the silicon carbide MOSFET device are reduced; the high-K dielectric layer effectively blocks diffusion of carbon atoms in silicon carbide to the gate oxide layer to form an interface state, improves channel mobility of the silicon carbide MOSFET device, effectively reduces leakage current and reduces switching loss of the silicon carbide MOSFET device.
Example 1
A planar silicon carbide MOSFET having a high-K dielectric layer is provided, see fig. 1, comprising a high-K dielectric layer;
the high-K dielectric layer is positioned between the drift layer and the gate oxide layer;
the high-K dielectric layer is adjacent to the drift layer and the gate oxide layer.
In early MOSFET devices, the gate dielectric layer was silicon dioxide as the gate oxide layer. Silicon carbide MOSFET devices are used as a new type of power device that uses silicon dioxide as the material for the gate dielectric layer. However, the gate oxide difficulty of silicon carbide MOSFET devices is one of the problems that limit their reliability. The barrier height at the interface of the grid oxide layer of the silicon carbide MOSFET device is lower, and carriers in a channel can more easily pass through the barrier to enter the grid oxide layer by the lower barrier height, so that the quality of the grid oxide layer is affected. On the other hand, carbon elements remaining at the interface during oxidation of silicon carbide can lead to higher interface state densities at the interface of silicon carbide and silicon dioxide. The high density of interface states can affect the performance and reliability of silicon carbide MOSFET devices. Specifically, charge traps at the interface reduce carrier density by trapped charges and carrier mobility by coulomb scattering, thereby affecting the current capability, transconductance, and other properties of the silicon carbide MOSFET; the interface state charge traps trap and release carriers causing the threshold voltage to drift when the silicon carbide MOSFET device is turned on and off. The gate oxide layer and the interface state charge trap increase the tunneling current and leakage current of the silicon carbide MOSFET device in a high electric field, and breakdown of the gate dielectric layer causes failure of the silicon carbide MOSFET device.
In the embodiment, the high-K dielectric layer is inserted between the drift layer and the gate oxide layer of the silicon carbide MOSFET, so that the interface characteristic of the gate oxide layer and the silicon carbide is improved, and the performance of the silicon carbide MOSFET device is improved; the high-K dielectric layer effectively blocks diffusion of carbon atoms in silicon carbide to the gate oxide layer to form an interface state, improves channel mobility of the silicon carbide MOSFET device, effectively reduces leakage current and reduces switching loss of the silicon carbide MOSFET device. Note that, the silicon carbide MOSFET in fig. 1 is exemplified by an N-type planar silicon carbide MOSFET, and this embodiment is not represented as being implemented only in an N-type MOSFET, and the type of the silicon carbide MOSFET is not limited in this embodiment.
Preferably, the ratio of the dielectric constant of the high-K dielectric layer to the dielectric constant of silicon carbide is greater than 2.
The dielectric constant is a physical parameter that characterizes the dielectric or polarization properties of a dielectric material, and its value is equal to the ratio of the capacitance of a capacitor of the same size made with the predicted material as the medium and with vacuum as the medium. When the dielectric is applied with an electric field, induced charges are generated to weaken the electric field, and the ratio of the original applied electric field to the electric field in the final dielectric is the dielectric constant, which is also called the dielectric constant. If a material with a high dielectric constant is placed in an electric field, the strength of the electric field will drop considerably within the dielectric. The polarity of the polymer material can be determined according to the dielectric constant of the substance. Typically, the material having a dielectric constant greater than 3.6 is a polar material; the material with dielectric constant in the range of 2.8-3.6 is weak polar material; a non-polar material having a dielectric constant less than 2.8. The dielectric constant of silicon dioxide is 3.9, the dielectric constant of silicon carbide is 9.6, namely the dielectric constant of silicon carbide is about 2.5 times of the dielectric constant of silicon dioxide, the electric field intensity inside silicon dioxide is about 2.5 times of the electric field intensity inside silicon carbide, the voltage born by a grid dielectric layer is 2.5 times of that of a silicon carbide drift layer, and the grid dielectric layer has the risk of breakdown in advance under the environment of a large electric field. In some embodiments, the ratio of the dielectric constant of the high-K dielectric layer to the dielectric constant of silicon carbide is greater than 2, and the dielectric constant of the high-K dielectric layer is at least one time greater than the dielectric constant of silicon carbide, so that the high-K dielectric layer can bear a voltage greater than that of silicon carbide, and the reliability of the gate dielectric layer is enhanced.
Preferably, the dielectric constant of the high-K dielectric layer is 20-30.
In some embodiments, the high-K dielectric layer has a dielectric constant of 20-30. As a preferred embodiment, the high K dielectric layer has a dielectric constant of 28. The dielectric constant of silicon carbide is 9.6, and the high-K dielectric layer with the dielectric constant being three times that of the silicon carbide is selected, so that the born voltage is only one third of that of the silicon carbide, the reliability of the gate dielectric layer is greatly enhanced, and the performance of the MOSFET device is optimized.
Preferably, the length of the high-K dielectric layer is 4um.
Preferably, the thickness of the high-K dielectric layer is 5nm.
Preferably, the distance between the high-K dielectric layer and the gate is 20nm.
The thickness of the gate dielectric layer refers to the thickness of the insulating layer between the gate and the substrate in a MOSFET where the thickness of the gate dielectric layer has a significant impact on the MOSFET device. The main function of the gate dielectric layer is to prevent current leakage between the gate and the substrate to ensure the switching characteristics of the MOSFET. The thinner gate dielectric layer can provide better insulation performance, reduce current leakage, and thus improve the switching speed and accuracy of the MOSFET device. However, too thin a gate dielectric layer may cause electron tunneling, thereby reducing the insulation performance, and a thinner gate dielectric layer may also increase the probability of leakage current occurrence, thereby reducing the efficiency of the device. When designing a MOSFET device, it is necessary to balance the thickness of the gate dielectric layer to ensure sufficient insulating properties. The thickness of the gate dielectric layer also affects the reliability of the MOSFET device. Thinner gate dielectric layers are susceptible to voltage and thermal stresses, resulting in damage to the dielectric layers and failure of the MOSFET device, and when designing the MOSFET device, it is desirable to balance the thickness of the gate dielectric layers to ensure reliability and lifetime of the MOSFET device while improving the quality and stability of the dielectric layers.
In some embodiments, the length of the high-K dielectric layer is set to 4um, the thickness of the high-K dielectric layer is set to 5nm, the distance between the high-K dielectric layer and the gate is set to 20nm, and the high-K dielectric layer can enable the gate oxide layer and the dielectric layer to be thinner than the traditional silicon dioxide dielectric layer, so that the on-resistance of the silicon carbide MOSFET device is reduced. The high-K dielectric layer is interposed between the drift layer and the gate electrode, and the thickness of the gate dielectric layer should be a stack of the gate oxide layer and the high-K dielectric layer, i.e., the high-K dielectric layer and the gate oxide layer together form a gate insulating layer. The length of the high-K dielectric layer refers to the width of the high-K dielectric layer in the horizontal direction, and the height of the high-K dielectric layer refers to the height of the high-K dielectric layer in the vertical direction.
Preferably, the material of the high-K dielectric layer is HfGdON.
HfO 2 As a main chemical product of hafnium, the zirconium-hafnium separation product is commonly used as an optical coating material, and a small amount of zirconium-hafnium separation product is tried for high-efficiency integrated circuits (efficient integrated circuits), namely HfO 2 Applications in the high-end area have yet to be developed. HfO (HfO) 2 The melting point of the (B) is relatively high, the absorption cross section of the hafnium atoms is relatively large, the neutron capturing capability is high, and the chemical properties are particularly stable, so that the (B) has great application value in the atomic energy industry. Since the last century, optical coatings have been rapidly developed, hfO 2 The optical characteristics of the HfO are more and more suitable for the requirements of the optical coating technology 2 The application in the field of film plating is also becoming wider and wider, especially the application has wider transparent wave band for light, and the light passes through HfO 2 In the case of a thin film, the absorption of light is small, and most of the light passes through the thin film by refraction, so that HfO 2 Applications in the field of optical coating are becoming more and more important. HfO (HfO) 2 Is an oxide with a relatively high dielectric constant. As a dielectric material, hfO has a high dielectric constant, a large forbidden bandwidth, and good stability on a substrate 2 Is considered to be an ideal material for replacing the conventional silicon dioxide dielectric layer in a MOSFET. If the size of the cmos device is less than 1um, the technology using silicon dioxide as the conventional gate dielectric layer brings a series of problems such as increased heat generation of the chip and polysilicon loss, and as the size of the MOSFET device is reduced, the silicon dioxide dielectric layer needs to be thinner and thinner, but the value of the leakage current increases sharply with the smaller thickness of the silicon dioxide dielectric layer due to the influence of quantum effect, so that a more feasible substance is needed to replace silicon dioxide as the gate dielectric layer. HfO (HfO) 2 Is a ceramic material with wide band gap and high dielectric constant, and recently has attracted great attention in industry, especially in microelectronics field, because it replaces the gate insulating layer silicon dioxide of the core device MOSFET of the present integrated circuit, the size limit problem of the development of the traditional silicon dioxide and silicon structure in the present MOSFET is solved.
In some embodiments, the material of the high-K dielectric layer is HfGdON. By at HfO 2 The intermediate doping rare earth element Gd can further improve HfO 2 Increasing the bandgap width; by reacting HfO to 2 N is carried out 2 The treatment can inhibit oxygen atom diffusion of the dielectric layer and improve interface characteristics.
Preferably, the semiconductor device further comprises a drain electrode, a substrate, a drift layer, a P well layer, an N+ layer, a P+ layer, a gate electrode and a source electrode;
the drain electrode is positioned below the substrate;
the substrate is positioned below the drift layer;
the P+ layer, the P well layer and the N+ layer are positioned on the upper layer of the drift layer;
the N+ layer is positioned above the P well layer;
the source is located above the n+ layer and the p+ layer.
Example 2
A method for preparing a planar silicon carbide MOSFET with a high K dielectric layer is provided, see fig. 2, 3 and 4, comprising:
s100, epitaxially forming a drift layer on a substrate;
the drift layer is formed by growing a specific monocrystalline film on the basis of a wafer through an epitaxial process, and the substrate wafer and the epitaxial film are collectively called as an epitaxial wafer, wherein the silicon carbide drift layer is grown on a conductive silicon carbide substrate to prepare the silicon carbide homoepitaxial wafer. Because silicon carbide power devices are different from traditional silicon power device manufacturing processes, cannot be directly manufactured on silicon carbide single crystal materials, high-quality epitaxial materials must be additionally grown on a conductive single crystal substrate, and various devices are manufactured on a drift layer, so that the quality of epitaxy has a great influence on the performance of the devices. The performance improvement of different power devices also places higher demands on the thickness, doping concentration and defects of the drift layer. The preparation method of the silicon carbide drift layer mainly comprises the following steps: vapor deposition, liquid phase epitaxial growth, molecular beam epitaxial growth, and chemical vapor deposition, wherein chemical vapor deposition is the primary method of current production. Chemical vapor deposition is a method of proton-transferring a reactive substance in a gas phase to a solid surface and forming a thin film. Silicon carbide epitaxy processes can be divided into two types, pyrolytic chemical vapor deposition and low pressure chemical vapor deposition, respectively. Pyrolytic chemical vapor deposition is carried out at high temperature, and generally requires heating a reaction chamber to 1500-1800 ℃ and reacting with a carbon source gas such as methane and a silicon source gas such as dimethylsilane, which can obtain a high-quality silicon carbide film, but has high equipment cost and slow growth rate. Low pressure chemical vapor deposition is performed at relatively low pressures, typically using a vapor phase precursor such as hexamethyldisilane and a reactant gas such as hydrogen. Low pressure chemical vapor deposition has advantages of fast growth rate and low equipment cost compared to pyrolytic chemical vapor deposition, however, low pressure chemical vapor deposition may not obtain the same quality of film as pyrolytic chemical vapor deposition due to lower concentration of reaction gas.
S200, forming a P well layer by ion implantation on the upper layer of the drift layer;
doping is a process of doping a certain amount of impurities into a semiconductor material in order to change the electrical characteristics of the semiconductor material, thereby obtaining desired electrical parameters. The methods of doping are mainly diffusion and ion implantation, both of which are useful in discrete devices or integrated circuits and which are said to be complementary, for example, diffusion can be applied to form deep junctions and ion implantation can form shallow junctions. In the conventional silicon power device process, high-temperature diffusion and ion implantation are the most dominant doping control methods, and both have advantages and disadvantages. Generally, the high temperature diffusion process is simple, equipment is relatively inexpensive, the doping profile is isotropic, and the high temperature diffusion process introduces low lattice damage. The ion implantation process is complex and expensive, but the main benefit of ion implantation is that the impurity doping amount can be controlled accurately, good repeatability is maintained, and the processing temperature of ion implantation is lower than diffusion. In the silicon carbide power device doping process, common doping elements are: n-type doping, nitrogen element and phosphorus element; p-type doping, aluminum element and boron element. The diffusion coefficient of the doping elements in silicon is relatively high, and high-temperature diffusion doping can be realized at the temperature of about 1200 ℃. The diffusion coefficient of these doping elements is very low in silicon carbide compared to that of silicon, which requires extremely high temperatures above 2000 degrees celsius to achieve a reasonable diffusion coefficient. However, high-temperature diffusion at extremely high temperature causes many problems, and various diffusion defects are introduced at high temperature to deteriorate the device performance, so that common photoresist cannot be used as a mask, and the like. The ion implantation process becomes the only choice for silicon carbide MOSFET devices.
Ion implantation is a technique of implanting an ion beam into a material, and by controlling parameters of ion implantation, such as implantation energy, implantation dose, and implantation time, chemical composition and physical properties of the material can be changed. A typical high energy ion implantation apparatus used in silicon carbide process fabrication consists essentially of an ion source, a plasma, an extraction assembly, an analysis magnet, an ion beam, an acceleration tube, a process chamber, and a scan disk. The ion implantation of the silicon carbide MOSFET device is usually carried out at high temperature, so that damage of ion bombardment to crystal lattices can be reduced to the greatest extent, nitrogen ions and phosphorus ions are usually implanted into the N-type region for manufacturing the silicon carbide wafer, and aluminum ions and boron ions are usually implanted into the P-type region for manufacturing the P-type region. In order to achieve the purpose of uniform doping concentration in the ion implantation region, the overall concentration distribution of the implantation region is generally adjusted by adopting a multi-step ion implantation mode; in the actual process manufacturing process, the doping concentration and the doping depth of the ion implantation area can be controlled by adjusting the implantation energy and the implantation dosage of the ion implanter, and the ion implanter performs uniform ion implantation on the surface of the silicon carbide wafer in operation by a multi-scanning mode on the surface of the silicon carbide wafer.
In this embodiment, a mask is formed in the non-implanted region according to the mask requirements, a P-well layer is formed by high temperature aluminum ion implantation, and the mask is removed after the P-well layer is formed.
S300, forming a dielectric layer above the drift layer;
s400, silicon dioxide is deposited above the dielectric layer to form a gate oxide layer;
the gate oxide layer is a critical part of the semiconductor device structure and its growth process refers to the process of depositing an oxide layer on a substrate. The principle of gate oxide formation mainly involves two processes, namely oxidation and diffusion. In the oxidation reaction, oxygen chemically reacts with silicon atoms on the substrate surface to form silicon dioxide. During diffusion, oxygen diffuses downward through the already formed silicon dioxide, increasing the thickness of the oxide layer. In the integrated circuit manufacturing process, the method for forming the gate oxide layer mainly comprises a thermal oxidation method and a chemical vapor deposition method. The thermal oxidation method is a method of growing an oxide layer by thermal oxidation reaction in a high temperature oxygen atmosphere, and the chemical vapor deposition method is a method of forming silicon dioxide deposited on a substrate by heating and decomposing a chemical gas in a gas phase. The oxidation process refers to a process of forming silicon dioxide on the surface of a substrate by a thermal oxidation method. The oxidation process is divided into dry oxidation and wet oxidation. Dry oxygen oxidation is to take dry pure oxygen as an oxidation atmosphere, directly react with silicon at a high temperature of about 1000 ℃, the dry oxygen oxidation rate is lower than that of wet oxygen oxidation, the time of the dry oxygen oxidation is usually as long as 2 hours, and the time of the wet oxygen oxidation is shortened to about 12 minutes, but the quality of an oxidized film is higher than that of the wet oxygen oxidation, so that the growth of a shielding oxide layer, a substrate oxide layer and a gate oxide layer with thinner thickness is generally oxidized by dry oxygen. Wet oxygen oxidation is the replacement of oxygen with water, which at high temperatures decomposes to HO, which diffuses at a higher rate in silica than dry oxygen oxidation. Wet oxygen oxidation is used to grow thicker oxide layers such as shadow oxide, full area coverage oxide, LOCOS oxide, etc. In the wet oxygen oxidation method, oxygen firstly passes through deionized water at 95-98 ℃ to bring water vapor into an oxidation furnace, and the oxygen and the water vapor are subjected to oxidation reaction with silicon at the same time. The quality of the silicon dioxide film produced by the oxidation method is slightly poorer than that of the silicon dioxide film produced by the dry oxidation method, but the silicon dioxide film has better effect than that of the water vapor oxidation method, and the growth speed is faster. Therefore, in the case where the thickness of the oxide layer is thick and the electrical properties of the oxide layer are not required, such a method is often employed for productivity. The equipment of the thermal oxidation method mainly comprises two types of horizontal type equipment and vertical type equipment. Wafers with a size below 6 inches all use a horizontal oxidation oven and wafers with a size above 8 inches all use a vertical oxidation oven. Both the oxidation furnace and the wafer boat carrying the wafers are made of quartz materials. In the oxidation process, to prevent impurity pollution and metal pollution, in order to reduce human factors, automatic control is mostly adopted in modern manufacturing.
In this embodiment, a silicon dioxide gate oxide layer is formed on the surface of the dielectric layer by high temperature wet oxygen.
S500, depositing polysilicon above the gate oxide layer to form a gate;
chemical vapor deposition is a commonly used method for preparing polysilicon. Chemical vapor deposition is performed by decomposing a silicon source gas into silicon atoms at a high temperature and depositing a polysilicon film on the surface of a substrate. In the chemical vapor deposition method, the deposition process is realized by controlling parameters such as gas flow, temperature, pressure and the like. The prepared silicon source gas is first introduced into the reaction chamber through a gas inlet and mixed with an inert carrier gas such as hydrogen. And then brought to an appropriate temperature, typically between 600 and 700 degrees celsius, by heating the reaction. Under high temperature conditions, the silicon source gas will decompose to form silicon atoms and deposit on the substrate surface. Deposition rate and film quality can be controlled by adjusting reaction temperature, gas flow rate, pressure, and other parameters.
In this embodiment, a polysilicon gate structure is formed by depositing polysilicon over a gate oxide layer.
S600, silicon dioxide is deposited above the grid electrode to form a protective layer;
s700, forming an N+ layer and a P+ layer on the upper layer of the P well layer through ion implantation annealing;
the ion implantation process introduces a large number of defects and impurities, which affect the properties of the material, and thermal annealing is introduced into the ion implantation process in order to eliminate these defects and impurities. In the thermal annealing process after ion implantation, it is first necessary to select an appropriate annealing temperature and annealing time, which should be higher than the melting point of the material, but not so high as to avoid melting or other irreversible changes in the material. The annealing time is determined according to the thickness of the material and the parameters of ion implantation, and the uniform annealing effect inside the silicon carbide needs to be satisfied. Thermal annealing is a method of heating a material to a certain temperature in a specific atmosphere, maintaining the temperature for a period of time, and then cooling at a suitable rate. The process of thermal annealing mainly includes three stages, such as defect removal, lattice rearrangement, and grain growth. During annealing, the high temperature may cause defects within the material to diffuse and rearrange, thereby reducing or eliminating defects introduced by ion implantation. Lattice rearrangement refers to the rearrangement of atoms within a material to optimize the structure and properties of the material. Grain growth means that grains in the material grow again, so that grain boundaries of the material are reduced, and the mechanical property and the electric conductivity of the material are improved.
In this embodiment, high-temperature high-dose nitrogen ions and aluminum ions are implanted on the P-well layer to form an n+ layer and a p+ layer, and finally high-temperature annealing is performed.
S800, forming a source electrode over the n+ layer and the p+ layer, and forming a drain electrode under the substrate.
In the embodiment, the performance of the silicon carbide MOSFET device is improved by inserting a high-K dielectric layer between the drift layer and the gate oxide layer of the silicon carbide MOSFET; the high-K dielectric layer can bear larger voltage than silicon dioxide, so that the reliability of the gate dielectric layer is enhanced; the high-K dielectric layer can enable the gate oxide layer and the dielectric layer to be laminated to be thinner, so that the on-resistance and the cost of the silicon carbide MOSFET device are reduced; the high-K dielectric layer effectively blocks diffusion of carbon atoms in silicon carbide to the gate oxide layer to form an interface state, improves channel mobility of the silicon carbide MOSFET device, effectively reduces leakage current and reduces switching loss of the silicon carbide MOSFET device.
Preferably, forming a dielectric layer over the drift layer includes:
depositing HfO over a drift layer 2 ；
Will HfO 2 At N 2 Gd doping is performed in the environment of (1) to form an HfGdON dielectric layer.
In some embodiments, hfO is grown over the drift layer 2 Dielectric layer and at N 2 Gd doping is carried out in the atmosphere, and an HfGdON material is formed to serve as a dielectric layer. By at HfO 2 The intermediate doping rare earth element Gd can further improve HfO 2 Increasing the bandgap width; by reacting HfO to 2 N is carried out 2 The treatment can inhibit oxygen atom diffusion of the dielectric layer and improve interface characteristics.
The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A planar silicon carbide MOSFET with a high-K dielectric layer is characterized by comprising the high-K dielectric layer;
the high-K dielectric layer is positioned between the drift layer and the gate oxide layer;
the high-K dielectric layer is adjacent to the drift layer and the gate oxide layer.
2. The planar silicon carbide MOSFET of claim 1 wherein the ratio of the dielectric constant of the high K dielectric layer to the dielectric constant of silicon carbide is greater than 2.
3. The planar silicon carbide MOSFET of claim 1 having a high K dielectric layer with a dielectric constant of 20-30.
4. The planar silicon carbide MOSFET of claim 1 having a high K dielectric layer with a length of 4um.
5. The planar silicon carbide MOSFET having a high-K dielectric layer of claim 1, wherein the high-K dielectric layer has a thickness of 5nm.
6. The planar silicon carbide MOSFET of claim 1 having a high K dielectric layer, wherein the high K dielectric layer is spaced from the gate by a distance of 20nm.
7. The planar silicon carbide MOSFET having a high-K dielectric layer of claim 1, wherein the high-K dielectric layer is HfGdON.
8. The planar silicon carbide MOSFET of claim 1 further comprising a drain, a substrate, a drift layer, a P-well layer, an n+ layer, a p+ layer, a gate, and a source;
the drain electrode is positioned below the substrate;
the substrate is positioned below the drift layer;
the P+ layer, the P well layer and the N+ layer are positioned on the upper layer of the drift layer;
the N+ layer is positioned above the P well layer;
the source is located above the n+ layer and the p+ layer.
9. The preparation method of the planar silicon carbide MOSFET with the high-K dielectric layer is characterized by comprising the following steps of:
epitaxially forming a drift layer on a substrate;
forming a P well layer by ion implantation on the upper layer of the drift layer;
forming a dielectric layer over the drift layer;
depositing silicon dioxide above the dielectric layer to form a gate oxide layer;
depositing polysilicon above the gate oxide layer to form a gate;
depositing silicon dioxide above the grid electrode to form a protective layer;
forming an N+ layer and a P+ layer on the upper layer of the P well layer through ion implantation annealing;
a source is formed over the n+ layer and the p+ layer, and a drain is formed under the substrate.
10. The method of fabricating a planar silicon carbide MOSFET having a high K dielectric layer according to claim 9, wherein said forming a dielectric layer over said drift layer comprises:
depositing HfO over the drift layer 2 ；
The HfO is subjected to 2 At N 2 Gd doping is performed in the environment of (1) to form an HfGdON dielectric layer.
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