CN114678419A - Semiconductor device and manufacturing method thereof, power switch device and power amplifier device - Google Patents
Semiconductor device and manufacturing method thereof, power switch device and power amplifier device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The invention relates to the technical field of semiconductors, in particular to the field of semiconductor emergency protection circuit switches, and specifically relates to a semiconductor device and a manufacturing method thereof, a power switch device and a power amplifier device, wherein the semiconductor device comprises the following components in parts by weight: the semiconductor device comprises a drain electrode, an epitaxial layer, at least two groups of first hole doping layers, a grid electrode, a first electron doping layer, a second electron doping layer and a source electrode, wherein the epitaxial layer is in ohmic contact with the drain electrode on one side, the first hole doping layers are arranged in a relatively separated mode, the first hole doping layers are connected with the other side of the epitaxial layer, the grid electrode is in ohmic contact with the first hole doping layers and exposed to the outside of the semiconductor device, and the first electron doping layers, the second electron doping layers and the source electrode are connected with the first hole doping layers and the epitaxial layer; a channel region is included between the adjacent first hole doping layers; the first electron doped layer is connected with the epitaxial layer and the first hole doped layer through the channel region. By multiple times of epitaxial growth and ion implantation, a narrower and shorter channel region can be prepared, the influence of Miller capacitance is reduced, the on-resistance and parasitic parameters are reduced, and the breakdown voltage is improved; the device size and cost are reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to the field of semiconductor emergency protection circuit switches, and specifically relates to a semiconductor device and a manufacturing method thereof, a power switch device and a power amplifier device.
Background
Semiconductor materials have been widely applied to power switching devices, in the existing unipolar power semiconductor devices, because the semiconductor materials need to simultaneously reduce on-resistance and increase breakdown voltage, a common solution needs to introduce a plurality of connecting devices and structures, and the connecting devices and structures have different connecting modes, so that the area parasitic parameters are very many, and the generation reasons are mainly as follows: the resistance, inductance, capacitance and the like of each area of the device can form capacitance between parallel conductors, the inductance capacitance resistance of the device, the inductance arranged in order can generate coupling effect and the like. A commonly used solution, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device is based on a commonly used silicon-based MOS Transistor structure in the prior art, and has good adaptability and matching property with the existing silicon-based MOS device, but because the MOS interface has the problems of high interface defect density and low channel electron mobility, the performance is lower than expected, and the reliability of the gate Oxide layer and the short-circuit capability of the device still need to be further improved. Another commonly used solution is that a Junction Field Effect Transistor (JFET) device controls the on and off of the device by means of a gate PN Junction depletion layer, which avoids a series of problems caused by excessive interface defect density, but the JFET device is planar or trench-type, and has a long channel, which results in that other parasitic parameters such as on-resistance of the JFET device cannot be further reduced, and the performance of the device cannot be significantly improved; the planar SiC JFET device has too long horizontal channel, large on-resistance, large switching loss, large cell size and high cost; the groove type SiC JFET device is long in vertical channel, large in on-resistance and incapable of accurately controlling side wall ion implantation; meanwhile, the JFET device with two PN junction structures requires multiple ion implantation processes to prepare the P-type buried layer and the P-type area below the grid electrode, and higher requirements are put forward on the process operation precision.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the related art and to reducing the on-resistance and parasitic parameters of a unipolar power semiconductor device.
At present, because the forbidden band width of a silicon (Si) material is narrow, the silicon (Si) power device has poor bearing capacity to environments such as high temperature and high pressure, and the like, the traditional Si power device can not meet the requirements of advanced fields such as aerospace, rail transit, new energy and the like on device performance. The third generation semiconductor material silicon carbide (SiC) has the advantages of wide forbidden band, high critical electric field, high electronic saturation velocity, high thermal conductivity and the like, so that the SiC becomes an ideal material for manufacturing high-temperature and high-pressure resistant high-power devices. The breakdown voltage and the on-resistance of the power device have theoretical contradiction, and the on-resistance is inevitably increased while the breakdown voltage is increased; while reducing the on-resistance, the breakdown voltage is also reduced, so obtaining both high breakdown voltage and low on-resistance requires a compromise. Compared with Si, the SiC improves the performance, and the breakdown voltage of the SiC is higher under the same on-resistance; however, the limit of the SiC material is not reached, and the introduction of the buried gate can easily enable the SiC device to reach high breakdown voltage and extremely low on-resistance.
The invention adopts a Buried Gate Static Induction Transistor (BGSIT) device, the length and the width of a channel can be reduced due to a PN junction formed by a Buried Gate, and the on-resistance and the parasitic parameters of the SiC BGSIT are lower than those of the SiC JFET by multiple times of epitaxial growth and preparation of a second electron doping layer only on the top of a first electron doping layer of the SiC BGSIT; meanwhile, ion implantation operation is not needed to be carried out on the groove or the channel region, the process complexity is reduced, the yield is improved, an oxide layer is not needed to be prepared on the grid electrode, and the risk of short circuit of a device caused by poor reliability of the grid electrode oxide layer is reduced. Therefore, SiC BGSIT devices are believed to maximize the superior performance of SiC materials for high voltage and high frequency applications.
The multiple epitaxial growth technology starts in SiC, a new improved multiple epitaxial growth process is created, heteroepitaxy (an N-type upper growth P type or a P-type upper growth N type) is adopted to realize the simultaneous epitaxial growth of an N-type epitaxial growth layer on the surfaces of a P-type layer and another N-type layer, the fact that a BGSIT device needs to prepare connecting layers respectively when the heteroepitaxy is connected is simplified, the problem that defects easily exist in secondary connection of the connecting layers is also avoided, the preparation steps are greatly simplified, and the efficiency and the reliability are improved.
In order to achieve the above object, the present invention provides a semiconductor device, comprising a drain, an epitaxial layer having one side in ohmic contact with the drain, at least two sets of first hole doping layers oppositely and separately disposed and connected to the other side of the epitaxial layer, a gate exposed to the outside of the semiconductor device by the first hole doping layers and in ohmic contact with the part of the first hole doping layers, a first electron doping layer connected to the first hole doping layer and the epitaxial layer, a second electron doping layer connected to the first electron doping layer, and a source in ohmic contact with the second electron doping layer;
a channel region is included between the adjacent first hole doping layers; the ratio of the length of the channel region to the length of the first electron doped layer is 1-40: 41; the first electron doped layer is connected with the epitaxial layer and the first hole doped layer through the channel region.
In one aspect of the invention, the doping concentration of the second electron doping layer ≧ the doping concentration of the first electron doping layer;
in one aspect of the present invention, since the substrate voltage occupies most of the on-resistance, the epitaxial layer includes a third electron doping layer connected to the drain, a fourth electron doping layer connected to the third electron doping layer, and a fifth electron doping layer connected to the fourth electron doping layer; the fifth electron doped layer is simultaneously connected with the first hole doped layer and the second electron doped layer.
Preferably, the doping concentration of the second electron doping layer and the third electron doping layer is 1e19-1e21cm-3(ii) a The first electron doping layer and the fourth electronThe doping concentration of the doping layer is 1e16-1e19cm-3(ii) a The doping concentration of the fifth electron doping layer is 1e13-1e17cm-3(ii) a The doping concentration of the first hole-doped layer is 1e19-1e21cm-3。
Preferably, the width of the channel region is 0.5-5 μm; the length of the channel region is 0.5-5 μm; the length of the first electronic doping layer is 1.0-40 mu m; when the first hole doping layer is provided with three or more groups, the interval between adjacent channel regions is 1.0-10 mu m.
Preferably, the doping bases of the first electron doping layer, the second electron doping layer, the third electron doping layer, the fourth electron doping layer, the fifth electron doping layer, and the first hole doping layer are elemental carbon or a compound of elemental carbon that can be used for semiconductors.
Preferably, the doped substrate is any one of silicon carbide or silicon; the doping elements of the first electron doping layer, the second electron doping layer, the third electron doping layer and the fourth electron doping layer are any one of nitrogen, phosphorus, arsenic, antimony and bismuth; the doping element of the first hole doping layer is any one of boron, aluminum, gallium, indium and thallium; the drain electrode, the source electrode and the grid electrode are selected from any one of platinum, gold, silver, copper and aluminum.
The preparation method of the semiconductor device is used for preparing the semiconductor device and comprises the following steps:
step 1: growing a source region of a first hole doping layer on the epitaxial layer;
step 2: preparing a first hole doping layer from a source region of the first hole doping layer;
and step 3: preparing a first electron doping layer on the first hole doping layer and the epitaxial layer;
and 4, step 4: preparing a second electron doping layer on the top of the first electron doping layer;
and 5: processing the first electron doping layer and the second electron doping layer to obtain a partially exposed first hole doping layer;
step 6: and respectively preparing a drain electrode, a grid electrode and a source electrode.
Preferably, the step 1 and the step 3 are carried out in a hydrogen atmosphere under a heating condition, and the raw materials are introduced into the reactor with an inlet flow ratio of 3: 1 silane and propane.
Preferably, step 1 is:
heating the epitaxial layer 2 to 1500-1700 ℃ in a hydrogen atmosphere for preheating;
keeping the hydrogen flux and the temperature unchanged, and introducing mixed gas of silane and propane with the flow rate of 25-40sccm for 10-20 min; the doping raw material is a simple substance or a compound of boron, aluminum, gallium, indium or thallium, and the gas inlet flow is 1000-10000 sccm; further preferably any one of borane, aluminum, gallium, indium or thallium;
keeping other conditions unchanged, reducing the temperature to 1450-1650 ℃ to primarily grow the first hole doping layer for 10-20 min;
keeping other conditions unchanged, further reducing the temperature to 1400-1600 ℃, accelerating the growth of the first hole doping layer, and the reaction time is 1-2 h.
Preferably, step 3 is:
heating the device with the first hole doping layer processed in the step 2 to 1300-1500 ℃ in a hydrogen atmosphere for preheating;
keeping the hydrogen flux and the temperature unchanged, and introducing mixed gas of silane and propane with the flow rate of 50-80sccm for 10-20 min; introducing simple substances or compounds of nitrogen, phosphorus, arsenic, antimony or bismuth with the gas inlet flow of 10-1000 sccm; further preferably any one of simple substances of nitrogen, ammonia, phosphine, phosphorus, arsenic, antimony or bismuth;
keeping other conditions unchanged, raising the temperature to 1500-1700 ℃, adjusting the pressure to 40-100 mbar, and growing the first electron doping layer for 1-2 h.
Preferably, the method for preparing the first hole doping layer in step 2 and processing the first electron doping layer and the second electron doping layer in step 5 is dry etching.
Preferably, the dry etching is ICP inductively coupled plasma etching or CCP capacitively coupled plasma etching.
Preferably, the preparation of the second electron doping layer is realized by injecting ions into the outer surface of the first electron doping layer.
A power switch device comprises the semiconductor device or the semiconductor device prepared by the preparation method.
A power amplifier device comprising the semiconductor device or the semiconductor device prepared by the above manufacturing method; the audio amplifier can be used for voice equipment.
Advantageous effects
1. According to the invention, through multiple epitaxial growth and the preparation of the second electron doping layer only on the top of the first electron doping layer of the SiC BGSIT, a narrower and shorter channel region can be prepared, so that the on-resistance and parasitic parameters of the SiC BGSIT are lower than those of the SiC JFET; the method overcomes the theoretical contradiction between the breakdown voltage and the on-resistance, is beneficial to exerting the high breakdown voltage characteristic of the SiC, avoids the problem that the high voltage and the low on-resistance cannot be considered in the traditional design, further excavates the potential of the silicon carbide material, and can easily enable the SiC device to reach the high breakdown voltage and the extremely low on-resistance by introducing the buried gate;
2. the invention is provided with an independent first electronic doping layer, and the doping concentration of the second electronic doping layer is larger than or equal to that of the first electronic doping layer; the second electron doping layer is not directly connected with the first hole doping layer, so that the loss of voltage applied to a grid electrode to conduction current when the device is conducted is avoided, the influence of the grid electrode voltage on Miller capacitance when the device is conducted is reduced, and the on-resistance is further reduced; meanwhile, the phenomenon that when a traditional groove type JFET device is conducted, overlarge forward voltage is not easily applied to a grid electrode to avoid introducing overlarge current is avoided; the contradiction between larger voltage and reverse voltage of the source electrode is needed when the circuit is in the off state, so that the control difficulty is reduced;
3. the method adopts a unique multiple epitaxial growth process, particularly a growth heteroepitaxy process, overcomes the problem of heteroepitaxial growth of different doping concentrations (for example, the P-type buried gate is simultaneously connected with N-type materials of different doping concentrations), reduces the number of P-type regions of different doping concentrations, simplifies the manufacturing process, is beneficial to reducing the length and the width of a channel region, further realizes that the P-type buried gate forms a plurality of tiny channel regions, and utilizes electrostatic induction to generate a depletion layer to flexibly control the on-off of a switch in the channel and further reduce the energy consumption.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 schematically illustrates a semiconductor device in accordance with an embodiment of the present invention;
FIG. 2a schematically represents a staged sample prepared in step 1 of one embodiment of the invention;
FIG. 2b schematically shows a staged sample prepared in step 2 of one embodiment of the invention;
FIG. 2c schematically shows a staged sample prepared in step 3 of one embodiment of the invention;
FIG. 2d schematically shows a staged sample prepared in step 4 of one embodiment of the invention;
FIG. 2e schematically shows a staged sample prepared in step 5 of one embodiment of the invention;
FIG. 2f schematically shows a staged sample prepared at step 6 of one embodiment of the invention;
fig. 3 schematically shows the dimensions of each part of the semiconductor device of the present invention;
fig. 4 schematically shows a flow of a method of manufacturing a semiconductor device according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the scope of the present invention.
In the description of the present invention, unless otherwise specified, the terms "top," "bottom," "upper," "lower," and the like refer to orientations or positional relationships illustrated in the drawings, which are used for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced system or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present invention.
It is to be understood that, unless otherwise expressly stated or limited, the term "coupled" is used in a generic sense as defined herein, e.g., fixedly attached or removably attached or integrally attached; may be directly connected or indirectly connected through an intermediate. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The present invention relates to a concept "threshold voltage" which is a gate voltage whether a semiconductor device having an on-off function can be turned on or off; "breakdown voltage" is the semiconductor reverse breakdown voltage; the "on-resistance" is the ratio of the voltage across the semiconductor to the on-current after the semiconductor is turned on. Unless otherwise stated, the length of the first electron doping layer is the thickness of the first electron doping layer; the channel region length or channel length is the thickness or depth of the channel region or channel in the longitudinal direction in the corresponding view.
As shown in fig. 1, the present invention discloses a semiconductor device, which comprises a drain electrode 1, an epitaxial layer 2 in ohmic contact with one side and the drain electrode 1, at least two sets of first hole doping layers 3 oppositely and separately arranged and connected with the other side of the epitaxial layer 2, a gate electrode 4 exposed to the part of the ohmic contact of the first hole doping layer 3 outside the semiconductor device, a first electron doping layer 5 connected with the first hole doping layer 3 and the epitaxial layer 2, a second electron doping layer 6 connected with the first electron doping layer 5, and a source electrode 7 in ohmic contact with the second electron doping layer 6;
a channel region 51 is included between the adjacent first hole doping layers 3; the ratio of the length of the channel region 51 to the length of the first electron-doped layer 5 is 1-40: 41; the first electron doped layer 5 is connected to the epitaxial layer 2 and the first hole doped layer 3 through the channel region 51.
The drain electrode 1 is a metal electrode which selects any one of platinum, gold, silver, copper and aluminum and is in ohmic contact with one side of the epitaxial layer 2; the part of the first hole doped layer 3 exposed to the outside of the semiconductor device includes a gate 4 for applying an external reverse voltage; the first hole doping layer 3 is used for embedding a large number of parallel P-type regions, and the adjacent epitaxial layer 2 and the first electron doping layer 5 form two PN junctions; the first electron-doped layers 5 extend deeply into the channel region 51 between the adjacent first hole-doped layers 3 arranged in parallel, and are connected to the epitaxial layer 2 and the first hole-doped layers 3 through the channel region 51. Applying negative voltage to the gate 4 and the source 7, the first hole doping layer 3 is depleted towards the N-type channel region, and the depletion layer becomes wider as the absolute value of the negative voltage increases; the vertical channel is pinched off when the depletion layer is wide enough to expand and fully occupy the N-type channel region. At this time, almost no current flows between the source and the drain of the SiC BGSIT, and the device is in an off state. When no negative voltage is applied to the gate 4 and source 7, the device is in an on state and current flows from the source 7 to the drain 1 through the vertical channel. The ratio of the length of the channel region 51 to the length of the first electron doped layer 5 may be in the range of 1-40: 41 are varied to match different source to drain turn-off negative voltages when the device is in the off state. Preferably, the width of the channel region 51 is 0.5-5 μm; the length of the channel region 51 is 0.5-20 μm; the length of the first electronic doping layer 5 is 1.0-40 μm; when three or more sets of the first hole doping layers 3 are provided, the adjacent channel regions 51 are spaced apart by 1 to 10 μm. Compared with the traditional groove type JFET device, the length and width space is required to be reserved for ion implantation, the channel can obtain smaller length and width due to the adoption of epitaxial growth and etching preparation, and the on-resistance and grid parasitic parameters of the device can be greatly reduced while the reverse breakdown voltage of the device is not reduced. The current of the on-state semiconductor device flows from the source 7, passes through the vertical channel region 51 of the buried layer, flows directly into the drift region of the epitaxial layer 2, and is collected by the drain 1.
In one aspect of the invention, the first electron doped layer 5 is independently included and the second electron doped layer 6 has a doping concentration ≧ the doping concentration of the first electron doped layer 5; the second electron doping layer 6 is not directly connected with the first hole doping layer 3, so that the loss of voltage applied to the grid 4 to conduction current when the device is conducted is avoided, the influence of the grid voltage on Miller capacitance when the device is conducted is reduced, the on-resistance is further reduced, and the energy consumption of a semiconductor device is reduced; meanwhile, the phenomenon that the grid electrode is not easy to apply overlarge forward voltage when the traditional groove type JFET device is conducted is avoided, and overlarge current is avoided; and the contradiction between larger voltage and reverse voltage of the source electrode is needed when the circuit is in an off state, so that the control difficulty is reduced.
In one aspect of the present invention, the epitaxial layer 2 includes a third electron doping layer 21 connected to the drain 1, a fourth electron doping layer 22 connected to the third electron doping layer 21, and a fifth electron doping layer 23 (drift region) connected to the fourth electron doping layer 22; the fifth electron doped layer 23 is simultaneously connected to the first hole doped layer 3 and the second electron doped layer 6. Preferably, the doping concentrations of the second electron doping layer 6 and the third electron doping layer 21 are 1e19-1e21cm-3(ii) a The doping concentrations of the first electron doping layer 5 and the fourth electron doping layer 22 are 1e16-1e19cm-3(ii) a The doping concentration of the fifth electron doping layer 23 is 1e13-1e17cm-3(ii) a The doping concentration of the first hole doping layer 3 is 1e19-1e21cm-3。
The third electron doping layer 21 is an N-type substrate layer, and is a conductive path in a conducting state, and one end of the conductive path is in ohmic contact with the drain electrode 1; the off state has no current flow.
The fourth electron doped layer 22 is an N-type buffer layer that provides a field stop region during reverse breakdown, allowing the device to punch through.
The fifth electron doped layer 23 is an N-type drift region, and carriers provide a drift region of a drift path, i.e., a conductive path, and also provide voltage-resistant protection for reverse breakdown.
In one aspect of the present invention, the doping substrates of the first electron doping layer 5, the second electron doping layer 6, the third electron doping layer 21, the fourth electron doping layer 22, the fifth electron doping layer 23, and the first hole doping layer 3 are elemental carbon or a compound of elemental carbon that can be used for a semiconductor. The doped substrate is any one of silicon carbide or silicon; the doping elements of the first electron doping layer 5, the second electron doping layer 6, the third electron doping layer 21 and the fourth electron doping layer 22 are any one of nitrogen, phosphorus, arsenic, antimony and bismuth; the doping element of the first hole doping layer 3 is any one of boron, aluminum, gallium, indium and thallium; the drain electrode 1, the source electrode 7 and the grid electrode 4 are obtained by selecting any one of platinum, gold, silver, copper and aluminum through a deposition film forming mode; thickness: 1-10 μm.
The method for manufacturing a semiconductor device as disclosed in fig. 2 a-2 f and 4 comprises the following steps:
step 1: growing a source region of the first hole doping layer 3 on the epitaxial layer 2;
step 2: preparing a first hole doping layer 3 from a source region of the first hole doping layer 3;
and 3, step 3: preparing a first electron doping layer 5 on the first hole doping layer 3 and the epitaxial layer 2;
and 4, step 4: preparing a second electron doping layer 6 on the top of the first electron doping layer 5;
and 5: processing the first electron doping layer 5 and the second electron doping layer 6 to obtain a partially exposed first hole doping layer 3;
step 6: the drain electrode 1, the gate electrode 4 and the source electrode 7 are separately prepared to obtain a semiconductor device.
In one aspect of the invention, step 1 comprises:
heating the epitaxial layer 2 to 1500-1700 ℃ in a pure hydrogen atmosphere of 50-100 slm (0 ℃, 1 atm) for preheating;
keeping the hydrogen flux and the temperature unchanged, and introducing mixed gas of silane and propane with the flow rate of 25-40sccm for 10-20 min; the gas inflow ratio of the mixed gas of silane and propane is 3: 1; the doping raw material is a simple substance or a compound of boron, aluminum, gallium, indium or thallium, and the inlet gas flow range is 1000-10000 sccm; further preferably any one of borane, aluminum, gallium, indium or thallium;
keeping other conditions unchanged, reducing the temperature to 1450-1650 ℃ to primarily grow the first hole doping layer 3 for 10-20 min;
keeping other conditions unchanged, further reducing the temperature to 1400 ℃ and 1600 ℃, accelerating the growth of the first hole doping layer 3, reacting for 1-2 h, and preparing the doping concentration 1e19-1e21cm-3A source region of first hole doped layer 3.
In one aspect of the present invention, the method for preparing the first hole doping layer 3 in step 2 and processing the first electron doping layer 5 and the second electron doping layer 6 in step 5 is dry etching.
Preferably, the dry etching is ICP inductively coupled plasma etching or CCP capacitively coupled plasma etching.
In one aspect of the present invention, the method for preparing the first hole doping layer 3 from the source region of the first hole doping layer 3 in step 2 is as follows:
dry etching the source region of the first hole doping layer 3, adopting Ni metal as an etching mask layer, and performing dry etching on SF6The first hole doping layer 3 is prepared by etching in gas, the etching speed is about 10-200 nm/min, the etching depth is 0.5-20 mu m, the etching width is 0.5-5 mu m, and the etching distance between adjacent channel regions is 1-10 mu m.
In one aspect of the present invention, step 3 comprises:
heating the device with the first hole doping layer 3 processed in the step 2 to 1300-1500 ℃ in a pure hydrogen atmosphere of 50-100 slm (0 ℃, 1 atm) for preheating;
keeping the hydrogen flux and the temperature unchanged, and introducing mixed gas of silane and propane with the flow rate of 50-80sccm for 10-20 min; introducing simple substances or compounds of nitrogen, phosphorus, arsenic, antimony or bismuth, wherein the gas inflow is 10-1000 sccm; further preferably any one of simple substances of nitrogen, ammonia, phosphine, phosphorus, arsenic, antimony or bismuth;
keeping other conditions unchanged, raising the temperature to 1500-1700 ℃, adjusting the pressure to 40-100 mbar, growing the first electron doping layer 5, reacting for 1-2 h, and preparing the doping concentration 1e16-1e19cm-3A first electron doped layer 4.
In one aspect of the present invention, the preparation of the second electron doping layer 6 in step 4 is performed by implanting ions into the outer surface of the first electron doping layer 5:
performing ion implantation for multiple times on the semi-finished device with the first electron doping layer 5, wherein the ion raw materials are selected from nitrogen, phosphorus, arsenic, antimony and bismuth ions; then, rapid thermal annealing (RTP) treatment is carried out in the inert atmosphere of rare gas such as argon, the annealing temperature is 1500-1800 ℃, the time is 5-10 min, and finally, the doping concentration of 1e19-1e21cm is formed on the top of the first electron doping layer 5-30.5-20 mu thickm second electron doped layer 6.
In one aspect of the present invention, the method for processing the first electron doping layer 5 and the second electron doping layer 6 in step 5 to obtain the partially exposed first hole doping layer 3 includes:
performing dry etching on the device semi-finished product processed in the step 4 again, taking Ni metal as an etching mask layer, and performing dry etching on the SF6The first electron doping layer 5 and the second electron doping layer 6 are obliquely etched in gas, the etching rate is about 10-200 nm/min, the etching depth is 1-40 mu m, the etching width is 10-50 mu m, the etching inclination angle is 20-70 degrees, and part of the first hole doping layer 3 is finally exposed so as to lead out the grid 4.
In one aspect of the present invention, the dimensions of the semiconductor device prepared by the above method are as shown in table 1 below:
TABLE 1
Table 1 gives the reasonable coverage of the invention after optimization, and fig. 3 gives detailed comments on each tag size position; wherein the first electron doped layer 5 has a length = Tn+Tch。
The preparation method of the epitaxial layer 2 is not limited by the invention, and the doping concentration of the third electron doping layer needs to be limited to 1e19-1e21cm-3(ii) a The doping concentration of the fourth electron doping layer is defined as 1e16-1e19cm-3(ii) a The doping concentration of the fifth electron doping layer is defined as 1e13-1e17cm-3(ii) a May be prepared by epitaxial growth processes well established in the art.
The method for forming the drain electrode 1, the source electrode 7 and the grid electrode 4 by deposition is not further limited, and can be realized by chemical vapor deposition coating or magnetic co-sputtering coating mature in the field.
A power switch device comprises the semiconductor device or the semiconductor device prepared by the preparation method.
A power amplifier device comprises the semiconductor device or the semiconductor device prepared by the preparation method.
In order to better illustrate the technical effects, the invention is provided with the following embodiments:
example 1
The embodiment discloses a method for preparing a semiconductor device, wherein a doped substrate selects silicon carbide, and the method comprises the following steps:
Selecting an outsourcing epitaxial layer 2, heating to 1500 ℃ in pure hydrogen atmosphere of 50slm (0 ℃, 1 atm), and preheating;
keeping the hydrogen flux and the temperature unchanged, and introducing mixed gas of silane and propane with the flow rate of 28sccm for 10 min; the inlet gas flow rates of the mixed gas silane and propane are respectively 21sccm and 7 sccm; the doping raw material is aluminum, and the flow rate is 1000 sccm;
keeping other conditions unchanged, reducing the temperature to 1450 ℃, and primarily growing the first hole doping layer 3 for 10 min;
keeping other conditions unchanged, further reducing the temperature to 1400 ℃, accelerating the growth of the first hole doping layer 3, reacting for 1h, and preparing the doping concentration 1e19cm-3A source region of the first hole doping layer 3;
In one aspect of the present invention, the method for preparing the first hole doping layer 3 from the source region of the first hole doping layer 3 in step 2 is as follows:
etching by adopting ICP (inductively coupled plasma); ni metal is used as an etching mask layer in SF6Etching in gas to prepare a first hole doping layer 3, wherein the etching rate is about 10nm/min, the etching depth is 0.5 mu m, the etching width is 0.5 mu m, and the etching distance between adjacent channel regions is 1 mu m;
Heating the device with the first hole doping layer 3 processed in the step 2 to 1300 ℃ in pure hydrogen atmosphere of 50slm (0 ℃, 1 atm) and preheating;
keeping the hydrogen flux and the temperature unchanged, and respectively introducing mixed gas silane and propane with the gas inlet flow of 42sccm and 14 sccm; lasting for 10 min; the doping raw material is ammonia gas, and the flow rate is 10 sccm;
keeping other conditions unchanged, increasing the temperature to 1500 ℃, and pressingStrongly adjusting to 40mbar, growing a first electron doping layer 5, reacting for 1h, and preparing the doping concentration of 1e16 cm-3A first electron doping layer 4;
Performing ion implantation for multiple times on the semi-finished device with the first electron doping layer 5, wherein the ion raw material is selected from nitrogen ions; then, rapid thermal annealing (RTP) treatment is carried out in an inert atmosphere of rare gas such as argon, the annealing temperature is 1500 ℃, the annealing time is 5min, and finally, the doping concentration of 1e19cm is formed on the top of the first electron doping layer 5-3The second electron doping layer 6;
And (4) performing ICP (inductively coupled plasma) etching on the semi-finished product of the device processed in the step (4), adopting Ni metal as an etching mask layer, and obliquely etching the first electron doping layer 5 and the second electron doping layer 6 in SF6 gas, wherein the etching rate is about 10nm/min, the etching depth is 1 mu m, the etching width is 10 mu m, the etching inclination angle is 20 degrees, and finally, part of the first hole doping layer 3 is exposed so as to lead out the grid 4.
Preparing a drain electrode 1, a grid electrode 4 and a source electrode 7 by using chemical vapor deposition; the film is a conductive copper film.
The dimensions of the semiconductor device prepared by the method of this embodiment are shown in table 2 below:
TABLE 2
Example 2
The embodiment discloses a method for preparing a semiconductor device, wherein a doping substrate selects a silicon simple substance, and the method comprises the following steps:
Selecting an outsourcing epitaxial layer 2, heating to 1700 ℃ in pure hydrogen atmosphere of 100slm (0 ℃, 1 atm), and preheating;
keeping the hydrogen flux and the temperature unchanged, and keeping the inflow rates of the silane and the propane which are mixed gases to be introduced to be 21sccm and 7sccm respectively for 20 min; the doping raw material is borane, and the flow rate is 5000 sccm;
keeping other conditions unchanged, reducing the temperature to 1650 ℃ to primarily grow the first hole doping layer 3 for 20 min;
keeping other conditions unchanged, further reducing the temperature to 1600 ℃, accelerating the growth of the first hole doping layer 3, reacting for 2 h, and preparing the doping concentration 1e21cm-3A source region of the first hole doping layer 3;
The method of preparing the first hole doping layer 3 is CCP capacitively coupled plasma etching.
In one aspect of the present invention, the method for preparing the first hole doping layer 3 from the source region of the first hole doping layer 3 in step 2 is as follows:
CCP capacitive coupling plasma etching is carried out on the source region of the first hole doping layer 3, Ni metal is used as an etching mask layer, and SF is carried out6Etching in gas to prepare a first hole doping layer 3, wherein the etching rate is about 200 nm/min, the etching depth is 20 mu m, the etching width is 5 mu m, and the etching distance between adjacent channel regions is 10 mu m;
Heating the device with the first hole doping layer 3 processed in the step 2 to 1500 ℃ in a pure hydrogen atmosphere of 100slm (0 ℃, 1 atm) and preheating;
keeping the hydrogen flux and the temperature constant, introducing a mixed gas of silane and propane with the flow rate of 80sccm, wherein the volume ratio of the silane to the propane is 3: 1, lasting for 20 min; the doping raw material is phosphine, and the flow rate or the concentration is 100 sccm;
keeping other conditions unchanged, raising the temperature to 1700 ℃, adjusting the pressure to 100 mbar, growing the first electron doping layer 5, reacting for 2 h, and preparing the doping concentration 1e19cm-3A first electron doping layer 4;
Performing ion implantation for multiple times on the semi-finished device with the first electron doping layer 5, wherein phosphorus ions are selected as the ion raw material; then, rapid thermal annealing (RTP) treatment is carried out in an inert atmosphere of rare gas such as argon, the annealing temperature is 1800 ℃, the annealing time is 10min, and finally, the doping concentration of 1e21cm is formed on the top of the first electron doping layer 5-3Is thick and thickA second electron doped layer 6 with a temperature of 20 μm;
Performing CCP capacitive coupling plasma etching on the semi-finished product of the device processed in the step 4 again, adopting Ni metal as an etching mask layer, and performing SF plasma etching on the Ni metal6The first electron doping layer 5 and the second electron doping layer 6 are obliquely etched in gas, the etching speed is about 200 nm/min, the etching depth is 40 micrometers, the etching width is 50 micrometers, the etching inclination angle is 70 degrees, and finally a part of the first hole doping layer 3 is exposed so as to lead out the grid 4.
Preparing a drain electrode 1, a grid electrode 4 and a source electrode 7 by using magnetic co-sputtering coating; the film is a conductive silver film.
The dimensions of the semiconductor device prepared by the method of this embodiment are shown in table 3 below:
TABLE 3
Example 3
The embodiment discloses a method for preparing a semiconductor device, wherein a doped matrix selects silicon carbide, and the method comprises the following steps:
Selecting an outsourcing epitaxial layer 2, heating to 1600 ℃ in a pure hydrogen atmosphere of 80slm (0 ℃, 1 atm), and preheating;
keeping the hydrogen flux and the temperature unchanged, and keeping the inflow rates of the silane and the propane which are mixed gases to be introduced to be 21sccm and 7sccm respectively for 15 min; the doping raw material is an aluminum simple substance with the flow rate of 10000 sccm;
keeping other conditions unchanged, and reducing the temperature to 1550 ℃ to primarily grow the first hole doping layer 3 for 15 min;
keeping other conditions unchanged, further reducing the temperature to 1500 ℃, accelerating the growth of the first hole doping layer 3, reacting for 1.5h, and preparing the doping concentration 1e20cm-3A source region of the first hole doping layer 3;
The method for preparing the first hole doping layer 3 by adopting ICP (inductively coupled plasma) inductively coupled plasma etching and preparing the first hole doping layer 3 from the source region of the first hole doping layer 3 comprises the following steps:
performing ICP (inductively coupled plasma) etching on the source region of the first hole doping layer 3, adopting Ni metal as an etching mask layer, and performing SF etching on the source region6Etching in gas to prepare a first hole doping layer 3, wherein the etching rate is about 100 nm/min, the etching depth is 10 mu m, the etching width is 2 mu m, and the etching distance between adjacent channel regions is 5 mu m;
Heating the device with the first hole doping layer 3 processed in the step 2 to 1400 ℃ in a pure hydrogen atmosphere of 64slm (0 ℃, 1 atm) and preheating;
keeping the hydrogen flux and the temperature unchanged, introducing 42sccm of silane and 14sccm of propane for 15 min; the doping raw material is nitrogen, and the flow rate is 1000 sccm;
keeping other conditions unchanged, increasing the temperature to 1580 ℃, adjusting the pressure to 70 mbar, growing the first electron doping layer 5, reacting for 1.5h, and preparing the doping concentration 1e17cm-3A first electron doping layer 4;
Performing ion implantation on the prepared semi-finished device of the first electronic doping layer 5 for multiple times, wherein the ion raw material is selected from nitrogen ions; then, rapid thermal annealing (RTP) treatment is carried out in an inert atmosphere of rare gas such as argon, the annealing temperature is 1700 ℃, the annealing time is 8min, and finally, the doping concentration of 1e20cm is formed on the top of the first electron doping layer 5-3A second electron doping layer 6 with a thickness of 10 μm;
Etching the device semi-finished product processed in the step 4 by adopting ICP (inductively coupled plasma) inductively coupled plasma, taking Ni metal as an etching mask layer, and performing SF etching6The first electron doping layer 5 and the second electron doping layer 6 are obliquely etched in gas, the etching speed is about 100 nm/min, the etching depth is 20 micrometers, the etching width is 25 micrometers, the etching inclination angle is 50 degrees, and finally a part of the first hole doping layer 3 is exposed so as to lead out the grid electrode 4.
Preparing a drain electrode 1, a grid electrode 4 and a source electrode 7 by using chemical vapor deposition coating; the film is a conductive aluminum film.
The dimensions of the semiconductor device prepared by the method of this embodiment are shown in table 4 below:
TABLE 4
In standard IEC 60147-4-1976, general principles of basic rating and characteristics of semiconductor devices and measurement methods, section 4: acceptance and reliability, the semiconductor devices prepared in examples 1-3 were tested under the same conditions as CN114256820A, a bidirectional dc solid-state circuit breaker based on SiC JFETs and CN114420745A, a silicon carbide MOSFET and the semiconductor devices in the preparation method thereof, and the results were as follows:
TABLE 5
The results show that: under the same voltage, the embodiments 1 to 3 of the present invention have higher breakdown voltage and lower on-resistance than the silicon carbide JFET and the silicon carbide MOSFET because a narrower and shorter channel region can be prepared by multiple epitaxial growth and preparing the second electron doped layer only on top of the first electron doped layer of the SiC BGSIT so that the on-resistance and parasitic parameters of the SiC BGSIT are lower than those of the SiC JFET and thus have higher breakdown voltage; meanwhile, the first electron doping layer is indirectly connected with the source electrode through the second electron doping layer, so that the influence of grid voltage on the Miller capacitance when the device is conducted is reduced, the on-resistance is further reduced, and the loss power of the device is reduced.
The method adopts a unique multiple epitaxial growth process, particularly a growth heteroepitaxy process, overcomes the problem of heteroepitaxial growth of different doping concentrations (for example, the P-type buried gate is simultaneously connected with N-type materials of different doping concentrations), reduces the number of P-type regions of different doping concentrations, simplifies the manufacturing process, is beneficial to reducing the length and the width of a channel region, further realizes that the P-type buried gate forms a plurality of tiny channel regions, and utilizes electrostatic induction to generate a depletion layer to flexibly control the on-off of a switch in the channel and further reduce the energy consumption.
Example 4
Selecting any one of the semiconductor devices of embodiments 1-3 to prepare a power switch device, which contains the semiconductor device or the semiconductor device prepared by the preparation method; the size of the power supply channel is controlled by the grid voltage, so that the purpose of controlling the on-off of the current can be achieved.
Example 5
A power amplifier device comprising the semiconductor device or the semiconductor device manufactured by the manufacturing method is manufactured by using the semiconductor device according to any one of embodiments 1 to 3. The size of the power supply channel is controlled by the grid voltage, so that the purpose of controlling the current can be achieved, and the power supply can be used for audio amplifiers such as sound equipment, earphones, microphones and the like.
Finally, it is noted that the above-mentioned preferred embodiments illustrate rather than limit the invention, and that, although the invention has been described in detail with reference to the above-mentioned preferred embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.
Claims (16)
1. The semiconductor device is characterized by comprising a drain electrode (1), an epitaxial layer (2) with one side in ohmic contact with the drain electrode (1), at least two groups of first hole doping layers (3) which are oppositely and separately arranged and are connected with the other side of the epitaxial layer (2), a grid electrode (4) which is exposed to the part of the ohmic contact of the first hole doping layer (3) and the external part of the semiconductor device, a first electron doping layer (5) which is connected with the first hole doping layer (3) and the epitaxial layer (2), a second electron doping layer (6) which is connected with the first electron doping layer (5), and a source electrode (7) which is in ohmic contact with the second electron doping layer (6);
a channel region (51) is contained between the adjacent first hole doping layers (3); the ratio of the length of the channel region (51) to the length of the first electron doped layer (5) is 1-40: 41; the first electron doped layer (5) is connected to the epitaxial layer (2) and the first hole doped layer (3) via the channel region (51).
2. The semiconductor device according to claim 1, wherein the second electron doped layer (6) has a doping concentration ≧ the doping concentration of the first electron doped layer (5); the epitaxial layer (2) comprises a third electron doping layer (21) connected with the drain electrode (1), a fourth electron doping layer (22) connected with the third electron doping layer (21) and a fifth electron doping layer (23) connected with the fourth electron doping layer (22); the fifth electron doped layer (23) is connected to both the first hole doped layer (3) and the second electron doped layer (6).
3. The semiconductor device according to claim 2, wherein the doping concentrations of the second electron-doped layer (6) and the third electron-doped layer (21) are 1e19-1e21cm-3(ii) a The doping concentration of the first electron doping layer (5) and the fourth electron doping layer (22) is 1e16-1e19cm-3(ii) a The doping concentration of the fifth electron doping layer (23) is 1e13-1e17cm-3(ii) a The doping concentration of the first hole doping layer (3) is 1e19-1e21cm-3。
4. A semiconductor device according to claim 1, characterized in that the width of the channel region (51) is 0.5-5 μm; the length of the channel region (51) is 0.5-20 μm; the length of the first electron doping layer (5) is 1.0-40 mu m; when three or more groups of the first hole doping layers (3) are arranged, the interval between the adjacent channel regions (51) is 1.0-10 mu m.
5. The semiconductor device according to claim 1, wherein a doping substrate of the first electron doping layer (5), the second electron doping layer (6), the third electron doping layer (21), the fourth electron doping layer (22), the fifth electron doping layer (23), and the first hole doping layer (3) is a simple substance of a carbon group element or a compound of a carbon group element.
6. The semiconductor device according to claim 5, wherein the doped substrate is any one of silicon carbide or silicon; the doping elements of the first electron doping layer (5), the second electron doping layer (6), the third electron doping layer (21) and the fourth electron doping layer (22) are any one of nitrogen, phosphorus, arsenic, antimony and bismuth; the doping element of the first hole doping layer (3) is any one of boron, aluminum, gallium, indium and thallium; the drain electrode (1), the source electrode (7) and the grid electrode (4) are selected from any one of platinum, gold, silver, copper and aluminum.
7. Method for manufacturing a semiconductor device, characterized in that it is used for manufacturing a semiconductor device according to any of claims 1-6, comprising the steps of:
step 1: growing a source region of the first hole doping layer (3) on the epitaxial layer (2);
step 2: preparing a first hole doping layer (3) from a source region of the first hole doping layer (3);
and step 3: preparing a first electron doped layer (5) on the first hole doped layer (3) and the epitaxial layer (2);
and 4, step 4: preparing a second electron doping layer (6) on top of the first electron doping layer (5);
and 5: processing the first electron doping layer (5) and the second electron doping layer (6) to obtain a partially exposed first hole doping layer (3);
step 6: and respectively preparing a drain electrode (1), a grid electrode (4) and a source electrode (7).
8. The method according to claim 7, wherein the steps 1 and 3 are carried out in a hydrogen atmosphere under heating, and the raw materials are fed in a feed gas flow ratio of 3: 1 silane and propane.
9. The preparation method according to claim 8, wherein the step 1 comprises the following steps:
A) heating the epitaxial layer (2) to 1500-1700 ℃ in a hydrogen atmosphere for preheating;
B) keeping the hydrogen flux and the temperature unchanged, and introducing mixed gas of silane and propane with the flow rate of 25-40sccm for 10-20 min; the doping raw material is a simple substance or a compound of boron, aluminum, gallium, indium or thallium, and the gas inlet flow is 1000-10000 sccm;
C) keeping other conditions unchanged, reducing the temperature to 1450-1650 ℃ to primarily grow the first hole doping layer (3) for 10-20 min;
D) keeping other conditions unchanged, further reducing the temperature to 1400-1600 ℃, accelerating the growth of the first hole doping layer (3), and the reaction time is 1-2 h.
10. The preparation method according to claim 8, wherein the step 3 is as follows:
A) heating the device with the first hole doping layer (3) processed in the step 2 to 1300-1500 ℃ in a hydrogen atmosphere for preheating;
B) keeping the hydrogen flux and the temperature unchanged, and introducing mixed gas of silane and propane with the flow rate of 50-80sccm for 10-20 min; introducing simple substances or compounds of nitrogen, phosphorus, arsenic, antimony or bismuth with the gas inlet flow of 10-1000 sccm;
C) keeping other conditions unchanged, raising the temperature to 1500-1700 ℃, adjusting the pressure to 40-100 mbar, and growing the first electron doping layer (5) for 1-2 h.
11. The method of manufacturing according to claim 7, wherein the method of manufacturing the first hole doping layer (3) in step 2 and processing the first electron doping layer (5) and the second electron doping layer (6) in step 5 is dry etching.
12. The method according to claim 11, wherein the dry etching is ICP inductively coupled plasma etching or CCP capacitively coupled plasma etching.
13. Method according to claim 7, characterized in that the preparation of said second electron doped layer (6) is carried out by ion implantation into the outer surface of said first electron doped layer (5).
14. A power switching device comprising the semiconductor device according to any one of claims 1 to 6 or the semiconductor device manufactured by the manufacturing method according to any one of claims 7 to 13.
15. A power amplifier device comprising the semiconductor device according to any one of claims 1 to 6 or the semiconductor device manufactured by the manufacturing method according to any one of claims 7 to 13.
16. The power amplification device of claim 15, wherein the power amplifier is an audio amplifier for a voice device.
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| CN103794642A (en) * | 2012-10-31 | 2014-05-14 | Lg伊诺特有限公司 | Epitaxial wafer |
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| US20050006663A1 (en) * | 2003-07-08 | 2005-01-13 | Howard Gregory E. | Implant-controlled-channel vertical JFET |
| CN101040387A (en) * | 2004-03-12 | 2007-09-19 | 半南实验室公司 | Self-aligned silicon carbide semiconductor devices |
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