CN117334656A - Low parasitic inductance high power density double-sided heat dissipation power module and preparation method thereof - Google Patents
Low parasitic inductance high power density double-sided heat dissipation power module and preparation method thereof Download PDFInfo
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- CN117334656A CN117334656A CN202311296194.XA CN202311296194A CN117334656A CN 117334656 A CN117334656 A CN 117334656A CN 202311296194 A CN202311296194 A CN 202311296194A CN 117334656 A CN117334656 A CN 117334656A
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 31
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 30
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 542
- 229910052802 copper Inorganic materials 0.000 claims abstract description 542
- 239000010949 copper Substances 0.000 claims abstract description 542
- 238000003466 welding Methods 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 238000005476 soldering Methods 0.000 claims description 14
- 229910000831 Steel Inorganic materials 0.000 claims description 8
- 239000010959 steel Substances 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 229910002804 graphite Inorganic materials 0.000 claims description 6
- 239000010439 graphite Substances 0.000 claims description 6
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 9
- 230000010355 oscillation Effects 0.000 abstract description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 11
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
- H01L23/4924—Bases or plates or solder therefor characterised by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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Abstract
The invention provides a low parasitic inductance high power density double-sided heat dissipation power module and a preparation method thereof. Secondly, the copper block connector is used for connecting the power loops of the same node, so that the self inductance of the converter loop is reduced. The optimal design of the invention reduces the mutual inductance of each power loop between different DBC lining boards and between the same lining boards and reduces the self inductance in the same power loop, thus the invention can effectively reduce the voltage impact and the current oscillation of the chip in the switching process.
Description
Technical Field
The invention belongs to the technical field of semiconductor power modules, and particularly relates to a low parasitic inductance high power density double-sided heat dissipation power module and a preparation method thereof.
Background
The power module has wide application in the power electronic application fields of electric automobiles, traction locomotives and the like. However, conventional silicon-based power modules are increasingly unable to meet the demands of high-power applications for high temperature and high power density. In contrast, silicon carbide (SiC) power modules are attracting more and more attention, particularly in the field of electric automobiles and the like, with their excellent high-frequency, high-voltage and high-temperature properties.
However, most silicon carbide power modules still adopt the packaging technology of the traditional silicon-based modules at present, so that the excellent characteristics of the silicon carbide power devices cannot be fully exerted. Among other things, parasitic inductance issues are a key challenge for silicon carbide module packaging. Parasitic inductance may not only cause power device turn-off voltage spike and electromagnetic compatibility problems, but also increase switching loss of the power module, reduce reliability thereof, and even cause module failure. In order to fully exploit the advantages of silicon carbide power devices, there is a need to develop low parasitic inductance, high power density package integration techniques to better accommodate the performance and application requirements of silicon carbide power devices.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a low parasitic inductance high power density double-sided heat dissipation power module and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme:
in a first aspect, the present invention provides a low parasitic inductance high power density dual sided heat dissipating power module, comprising:
an upper DBC liner and a lower DBC liner disposed parallel to the upper DBC liner and electrically connected to respective ports of the upper DBC liner;
4 chips, power terminals, copper block connectors, grid copper surfaces, kelvin source copper surfaces, output terminals and bonding wires are arranged on the upper DBC lining plate and the lower DBC lining plate;
the power terminals are arranged on the same side of the upper DBC lining plate and the lower DBC lining plate, the power terminals of the upper DBC lining plate and the lower DBC lining plate comprise a DC+ node power terminal and a DC-node power terminal, and the DC+ node power terminal and the DC-node power terminal are staggered; the upper DBC lining plate is connected with the lower DBC lining plate through the copper block connector; the output terminal is arranged at one side far away from the power terminal; the grid copper surface and the Kelvin source copper surface are adjacently arranged inside the upper DBC lining plate and the lower DBC lining plate; and the chip is connected with the grid copper surface and the Kelvin source copper surface through the bonding wire.
In a second aspect, the present invention provides a method for manufacturing a low parasitic inductance high power density dual-sided heat dissipation power module, including:
selecting an upper DBC lining plate and a lower DBC lining plate, and soldering paste on the surfaces of the prepared upper DBC lining plate and the prepared lower DBC lining plate through a steel mesh;
Secondly, placing the chips at the appointed positions of an upper DBC lining plate and a lower DBC lining plate respectively through a chip mounter, and placing the chips into a vacuum welding furnace for vacuum welding by utilizing a graphite clamp;
thirdly, cleaning the surfaces of the chip and the lining board which are finished in the second step by using ultrasonic cleaning equipment so as to remove residual soldering paste;
fourthly, connecting the copper surfaces of the chip source electrode and the grid electrode with the copper surface of the Kelvin source electrode through a bonding machine;
fifthly, coating soldering paste on the surface of the copper block connector, the surface of the power copper surface and the surface of the ceramic substrate through a steel mesh;
sixthly, fixing the lining plate, the copper block connector and the power terminal through a graphite clamp, and then placing the lining plate, the copper block connector and the power terminal in a vacuum welding furnace for vacuum welding;
seventh, cleaning the lining board, the power terminal and the copper block connector which are finished in the sixth step by using ultrasonic cleaning equipment to remove residual soldering paste;
and eighth, injecting an insulating material into the module obtained after the seventh step in a vacuum encapsulating furnace to encapsulate the module to obtain the double-sided radiating power module with low parasitic inductance and high power density.
The beneficial effects are that:
1. the power module adopts the copper block connector to connect the power loops of the same node, realizes the overlapping design of the parallel power loops inside the chip by optimizing the layout of the module, and can effectively reduce the parasitic inductance of the power converter loop to about 1.2nH, thereby obviously reducing the overvoltage impact and current oscillation phenomena of the chip in the switching process.
2. The invention adopts the double-sided ceramic substrate to dissipate heat, and the upper tube chip and the lower tube chip of the half-bridge module are respectively arranged on the upper DBC lining plate and the lower DBC lining plate in an upper-lower overlapping mode so as to optimize the heat dissipation path of the chips. The design increases the heat dissipation area and greatly reduces the thermal resistance of the power module.
3. The power module has higher adaptability to application scenes with higher power density requirements, and has important significance for reducing the cost and improving the efficiency of a new energy automobile electric drive system and an industrial high-power servo motor.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is an exploded front view of a power module of the present invention
FIG. 2 is a northwest isometric view of an exploded view of a power module of the present invention
FIG. 3 is a schematic view of the underside of the upper DBC liner of FIG. 1;
FIG. 4 is a schematic view of the upper side of the lower DBC liner of FIG. 1;
FIG. 5 is a schematic view of the underside of the upper DBC liner of FIG. 1;
FIG. 6 is a schematic view of the upper side of the lower DBC liner of FIG. 1;
FIG. 7 is a schematic circuit diagram of a power module body according to the present invention;
FIG. 8 is a schematic structural diagram of a top side view of a silicon carbide MOSFET chip;
FIG. 9 is a process flow diagram of a power module of the present invention;
FIG. 10 is a schematic diagram of a current commutation path of a power module of the present invention;
FIG. 11 is a schematic diagram of a power copper face and copper block connector of a DC+ node of a power module of the present invention;
FIG. 12 is a schematic diagram of a power copper face and copper block connector of a DC-node of a power module of the present invention;
FIG. 13 is a schematic diagram of the connection of the upper DBC backing plate and the lower DBC backing plate of the power module according to the invention;
FIG. 14 is a perspective view of a power module chip layout one;
FIG. 15 is a partial left side view of a power module of the same commutation path of the power module according to the invention;
FIG. 16 is a schematic diagram of a power module layout;
FIG. 17 is a chip partial view of a different commutation loop of a power module according to the invention;
fig. 18 is a partial view of a chip layout of a power module according to the present invention.
Reference numerals:
a first chip 1A, a second chip 1B, a third chip 1C, a fourth chip 1D, a fifth chip 1E, a sixth chip 1F, a seventh chip 1G, and an eighth chip 1, a first bonding wire 2A, a second bonding wire 2B, a third bonding wire 2C, a fourth bonding wire 2D, a fifth bonding wire 2E, a sixth bonding wire 2F, a seventh bonding wire 2G, an eighth bonding wire 2H, a kelvin source terminal 311, a first kelvin source copper surface 3A, a second kelvin source copper surface 3B, a third kelvin source copper surface 3C, a fourth kelvin source copper surface 3D, a fifth kelvin source copper surface 3E, a sixth kelvin source copper surface 3F, a seventh kelvin source copper surface 3G, and an eighth kelvin source copper surface 3H, a first gate copper surface 4A, a second gate surface 4B, a third gate copper surface 4C, a fourth gate copper surface 4D, a fifth gate copper surface 4E, a sixth gate copper surface 4G, a seventh copper surface 4G, and a seventh gate electrode surface 4G gate terminal 411, ninth bond wire 5A, tenth bond wire 5B, eleventh bond wire 5C, twelfth bond wire 5D, thirteenth bond wire 5E, fourteenth bond wire 5F, fifteenth bond wire 5G, sixteenth bond wire 5H, seventeenth bond wire 6A, eighteenth bond wire 6B, nineteenth bond wire 6C, twentieth bond wire 6D, twenty-first bond wire 6E, twenty-second bond wire 6F, twenty-third bond wire 6G, twenty-fourth bond wire 6H, first power copper face 7, second power copper face 8, third power copper face 9, fourth power copper face 10, fifth power copper face 11, sixth power copper face 12, seventh power copper face 13, and eighth power copper face 14, ninth power copper face 15, tenth power copper face 16, eleventh power copper face 17, twelfth power copper face 18, thirteenth power copper face 19, fourteenth power copper face 20, the fifteenth power copper face 21 and the sixteenth power copper face 22, the first power terminal 23, the second power terminal 24, the third power terminal 25, the fourth power terminal 26, the fifth power terminal 27, the sixth power terminal 28, the seventh power terminal 29, the eighth power terminal 30, the first insulating layer 31, the second insulating layer 32, the first output terminal 33, the second output terminal 34, the first copper block connector 35, the second copper block connector 36, the third copper block connector 37, the fourth copper block connector 38, the fifth copper block connector 39, the sixth copper block connector 40, the seventh copper block connector 41, the eighth copper block connector 42, the ninth copper block connector 43, the tenth copper block connector 44, the eleventh copper block connector 45, the twelfth copper block connector 46, the thirteenth copper block connector 47, the fourteenth copper block connector 48, the first heat dissipation layer 49, and the second heat dissipation layer 50.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
In order to solve the above problems, the present invention provides a low parasitic inductance and high power density dual-sided heat dissipation power module package structure. The structure adjusts the power loop path of the parallel chip through the copper block connector to realize mutual inductance cancellation. The parasitic inductance of the power conversion loop can be reduced to be below 1.2nH by the innovative design, and overvoltage impact and current oscillation generated in the process of switching the chip are effectively reduced. In addition, the structure optimizes the heat dissipation path of the parallel chips, and adopts the double-sided ceramic substrate to dissipate heat, thereby increasing the heat dissipation area and greatly reducing the thermal resistance of the power module. The module structure is suitable for the power electronic application scene with high power density, and has important significance for improving the efficiency and the system power density of a new energy automobile electric drive system and an industrial high-power servo motor.
Referring to fig. 1 to 9, the present invention provides a low parasitic inductance high power density dual sided heat dissipation power module, comprising:
an upper DBC liner and a lower DBC liner disposed parallel to the upper DBC liner and electrically connected to respective ports of the upper DBC liner;
4 chips, power terminals, copper block connectors, grid copper surfaces, kelvin source copper surfaces, output terminals and bonding wires are arranged on the upper DBC lining plate and the lower DBC lining plate;
the power terminals are arranged on the same side of the upper DBC lining plate and the lower DBC lining plate, the power terminals of the upper DBC lining plate and the lower DBC lining plate comprise a DC+ node power terminal and a DC-node power terminal, and the DC+ node power terminal and the DC-node power terminal are staggered; the upper DBC lining plate is connected with the lower DBC lining plate through the copper block connector; the output terminal is arranged at one side far away from the power terminal; the grid copper surface and the Kelvin source copper surface are adjacently arranged inside the upper DBC lining plate and the lower DBC lining plate; and the chip is connected with the grid copper surface and the Kelvin source copper surface through the bonding wire.
The silicon carbide MOSFET chip is characterized in that the drain electrode of the silicon carbide MOSFET chip is welded on the corresponding upper DBC lining plate or lower DBC lining plate, the source electrode of the silicon carbide MOSFET chip is connected with the corresponding source electrode bonding wire, and the grid electrode of the silicon carbide MOSFET chip is connected with the corresponding grid electrode bonding wire.
The invention can also wrap the power module with low parasitic inductance and high power density and double-sided heat dissipation by the shell, and the power module is in the form of an electronic product. Of course, the housing of the present invention may be a plastic housing or a metal housing, and the present invention is not limited thereto. Of course, the invention can also protect the power module by filling the residual space in the packaging shell. The filler is made of resin, insulating glue or silicon rubber material,
the invention provides a low parasitic inductance high power density double-sided heat dissipation power module and a preparation method thereof. Secondly, the copper block connector is used for connecting the power loops of the same node, so that the self inductance of the converter loop is reduced. The optimal design of the invention reduces the mutual inductance of each power loop between different DBC lining boards and between the same lining boards and reduces the self inductance in the same power loop, thus the invention can effectively reduce the voltage impact and the current oscillation of the chip in the switching process. The invention is mainly applied to power electronic devices with high frequency and high power density. In these application scenarios, it is important to reduce parasitic parameters of the power module.
Referring to fig. 1 and 3, the upper DBC liner of the present invention includes a first insulating layer 31, a first heat dissipation layer, a 49 first metal layer, an upper gate copper surface, and an upper kelvin source copper surface; the grid copper surface arranged in the upper DBC lining plate is an upper grid copper surface, and the Kelvin source copper surface arranged in the upper DBC lining plate is an upper plate Kelvin source copper surface; the first insulating layer 31 is disposed between the first metal layer and the first heat dissipation layer 49; the chip is arranged at a corresponding position of the first metal layer;
referring to fig. 1 and 4, the lower DBC liner includes a second insulating layer 32, a second heat dissipation layer 50, a second metal layer, a lower gate copper surface, and a lower kelvin source copper surface; the grid copper surface arranged in the lower DBC lining plate is a lower grid copper surface, and the Kelvin source copper surface arranged in the lower DBC lining plate is a lower plate Kelvin source copper surface; the second insulating layer 32 is disposed between the second metal layer and the second heat dissipation layer 50; the chip is arranged at a corresponding position of the second metal layer;
grid terminals are respectively arranged on the upper grid copper surface and the lower grid copper surface; the upper grid copper surface is connected with an adjacent grid terminal; the lower grid copper surface is connected with an adjacent grid terminal; the upper Kelvin source copper surface and the lower Kelvin source copper surface are respectively provided with Kelvin source terminals, and the upper Kelvin source copper surface is connected with the adjacent Kelvin source terminals; the lower plate Kelvin source copper face is connected with an adjacent Kelvin source terminal.
Referring to fig. 3-7, the first metal layer includes a first power copper surface 7, a second power copper surface 8, a third power copper surface 9, a fourth power copper surface 10, a fifth power copper surface 11, a sixth power copper surface 12, a seventh power copper surface 13, and an eighth power copper surface 14; the second metal layer comprises a ninth power copper face 15, a tenth power copper face 16, an eleventh power copper face 17, a twelfth power copper face 18, a thirteenth power copper face 19, a fourteenth power copper face 20, a fifteenth power copper face 21 and a sixteenth power copper face 22;
wherein, the first power copper surface 7 and the second power copper surface 8 form a first copper surface area; the third power copper surface 9 and the fourth power copper surface 10 form a second copper surface area; the fifth power copper surface 11 and the sixth power copper surface 12 form a first copper surface area; the seventh power copper surface 13 and the eighth power copper surface 14 form a second copper surface area; the ninth power copper surface 15 and the tenth power copper surface 16 form a first copper surface area; the eleventh power copper surface 17 and the twelfth power copper surface 18 form a second copper surface area; the thirteenth power copper surface 19 and the fourteenth power copper surface 20 form a first copper surface area; the fifteenth power copper surface 21 and the sixteenth power copper surface 22 form a second copper surface area; the first copper surface areas and the second copper surface areas are staggered.
Referring to fig. 3 to 6, the 4 chips disposed on the lower DBC liner include a first chip 1A, a second chip 1B, a third chip 1C, and a fourth chip 1D; the 4 chips arranged on the upper DBC lining board comprise a fifth chip 1E, a sixth chip 1F, a seventh chip 1G and an eighth chip 1H;
the first chip 1A is connected to a corresponding position of the first power copper surface 7; the second chip 1B is connected to a corresponding position of the fourth power copper surface 10; the third chip 1C is connected to a corresponding position of the fifth power copper surface 11; the fourth chip 1D is connected to a corresponding position of the eighth power copper surface 14; the fifth chip 1E is connected to a corresponding position of the tenth power copper surface 16; the sixth chip 1F is connected to a corresponding position of the eleventh power copper surface 17; the seventh chip 1G is connected to a corresponding position of the fourteenth power copper surface 20; the eighth chip 1H is connected to a corresponding position of the fifteenth power copper surface 21.
The first chip 1A and the first power copper surface 7 are connected by welding, the second chip 1B and the fourth power copper surface 10 are connected by welding, the third chip 1C and the fifth power copper surface 11 are connected by welding, the fourth chip 1D and the eighth power copper surface 14 are connected by welding, the fifth chip 1E and the tenth power copper surface 16 are connected by welding, the sixth chip 1F and the eleventh power copper surface 17 are connected by welding, the seventh chip 1G and the fourteenth power copper surface 20 are connected by welding, and the eighth chip 1H and the fifteenth power copper surface 21 are connected by welding.
As shown in fig. 14, fig. 14 shows the layout of two chips in a certain power module. In this case, both chips are located on the upper DBC liner, underutilizing the vertical space. Because the distance between the two chips is relatively short, the heat dissipation effect is relatively poor. To achieve a better heat dissipation effect, the horizontal distance between the two chips must be increased, resulting in a decrease in space utilization.
Fig. 15 shows the layout of two chips of the same commutation loop in the present module, which design ingeniously makes use of the vertical distance to place the chips of the same commutation loop on different liners, respectively. This effectively increases the distance between the two chips without increasing the horizontal distance. Because the vertical distance is effectively utilized, the space utilization is high. Fig. 16 shows a layout of two chips in a power module, where the two chips are located on different boards, but they are placed on the same Z-axis. This arrangement does not effectively utilize the horizontal distance, resulting in a closer distance between the two chips, thereby affecting the heat dissipation of the module. In order to obtain a better heat dissipation effect, the vertical distance between the two chips needs to be increased, but this results in a decrease in space utilization. In contrast, the layout of two chips of different commutation loops in the present module is shown in fig. 17. They smartly use the horizontal distance, effectively increasing the distance between two chips without increasing the vertical distance. Because the horizontal distance is effectively utilized, the space utilization rate is high. Finally, fig. 18 shows four chips on two commutating streams, which fully utilize the horizontal and vertical space, so that the space utilization is high and the heat dissipation effect is also good.
Referring to fig. 1 to 7, the power terminals of the present invention include a first power terminal 23, a second power terminal 24, a third power terminal 25, a fourth power terminal 26, a fifth power terminal 27, a sixth power terminal 28, a seventh power terminal 29, and an eighth power terminal 30;
wherein the first power terminal 23, the third power terminal 25, the fifth power terminal 27 and the seventh power terminal 29 are DC-power terminals; the second, fourth, sixth and eighth power terminals 24, 26, 28, 30 are dc+ power terminals; the first power terminal 23 is connected with the second power copper surface 8; the second power terminal 24 is connected with the fourth power copper surface 10; the third power terminal 25 is connected to the sixth power copper surface 12, and the fourth power terminal 26 is connected to the eighth power copper surface 14; the fifth power terminal 27 is connected with the tenth power copper surface 16; the sixth power terminal 28 is connected to the twelfth power copper face 18; the seventh power terminal 29 is connected to the fourteenth power copper face 20, and the eighth power terminal 30 is connected to the sixteenth power copper face 22.
The first, second, third, sixth, fifth and tenth power copper surfaces 23, 8, 25, 12, 27, 16, 29 and 20 are dc+ nodes, the second, fourth, eighth, 14, 28, 18, 30 and 22 are dc+ nodes. The current of the commutation path flows from the DC + node to the DC-node.
As shown in fig. 10, current flows from the tenth power copper side 16 of the dc+ node to the second power copper side 8 of the DC-node, from the power copper side 10 of the dc+ node to the twelfth power copper side 18 of the DC-node, from the fourteenth power copper side 20 of the dc+ node to the sixth power copper side 12 of the DC-node, and from the eighth power copper side 14 of the dc+ node to the sixteenth power copper side 22 of the DC-node. The design is such that each adjacent commutation loop is opposite in direction and the power terminals of the DC + and DC-nodes are staggered in the vertical direction, as shown in fig. 2, e.g. the node of the power terminal 23 is DC-, the node of the power terminal 27 is dc+; also staggered in the horizontal direction, as shown in fig. 2, for example, the node of the power terminal 23 is DC-, and the node of the power terminal 24 is dc+. The arrangement ensures that the direction of each current-converting loop in the power module is opposite to the direction of the current-converting loop closest to the power module, so that the mutual inductance cancellation effect of the inductor is stronger, the total inductance is lower, the voltage overshoot when the module is turned off is reduced, the switching loss is reduced, the performance is improved, and the high-frequency use is particularly beneficial.
Referring to fig. 1 to 7, the output terminals include a first output terminal and a second output terminal; the first output terminal is arranged on one side of the first insulating layer 31, the first power copper surface 7, the third power copper surface 9, the fifth power copper surface 11 and the seventh power copper surface 13, which is far away from the power terminal, and is connected with the first insulating layer 31, the first power copper surface 7, the third power copper surface 9, the fifth power copper surface 11 and the seventh power copper surface 13;
The second output terminal is disposed on a side of the second insulating layer 32, the ninth power copper surface 15, the eleventh power copper surface 17, the thirteenth power copper surface 19, and the fifteenth power copper surface 21, which is far away from the power terminal, and is connected to the second insulating layer 32, the ninth power copper surface 15, the eleventh power copper surface 17, the thirteenth power copper surface 19, and the fifteenth power copper surface 21.
Referring to fig. 1 to 7, the copper block connectors include a first copper block connector 35, a second copper block connector 36, a third copper block connector 37, a fourth copper block connector 38, a fifth copper block connector 39, a sixth copper block connector 40, a seventh copper block connector 41, an eighth copper block connector 42, a ninth copper block connector 43, a tenth copper block connector 44, an eleventh copper block connector 45, a twelfth copper block connector 46, a thirteenth copper block connector 47, and a fourteenth copper block connector 48;
wherein one side of the first copper block connector 35 is connected with the second power copper surface 8; one side of the ninth copper block connector 43 is connected with the tenth power copper surface 16, and the other side of the first copper block connector 35 is connected with the other side of the ninth copper block connector 43; one side of the second copper block connector 36 is connected with the fourth power copper face 10; one side of the eighth copper block connector 42 is connected to the twelfth power copper face 18; the other side of the first copper block connector 35 is connected with the other side of the eighth copper block connector 42; one side of the third copper block connector 37 is connected with the fourth power copper face 10; one side of the eleventh copper block connector 45 is connected with the fourteenth power copper surface 20; the other side of the third copper block connector 37 is connected with the other side of the eleventh copper block connector 45; one side of the fourth copper block connector 38 is connected to the sixth power copper face 12; one side of the tenth copper block connector 44 is connected to the twelfth power copper face 18; the other side of the fourth copper block connector 38 is connected to the other side of the tenth copper block connector 44; one side of the fifth copper block connector 39 is connected with the sixth power copper face 12; one side of the twelfth copper block connector 46 is connected to the twelfth power copper face 18; the other side of the fifth copper block connector 39 is connected to the other side of the twelfth copper block connector 46; one side of the sixth copper block connector 40 is connected to the sixth power copper face 12; the fourteenth copper side is connected to the sixteenth power copper side 22; the other side of the sixth copper block connector 40 is connected to the other side of the fourteenth copper block connector 48; one side of the seventh copper block connector 41 is connected to the eighth power copper face 14; one side of the thirteenth copper block connector 47 is connected to the fourteenth power copper face 20; the other side of the seventh copper block connector 41 is connected to the other side of the thirteenth copper block connector 47.
Referring to fig. 1 to 7, the upper plate kelvin source copper surface includes a first kelvin source copper surface 3A, a second kelvin source copper surface 3B, a third kelvin source copper surface 3C, and a fourth kelvin source copper surface 3D; the lower plate Kelvin source copper face comprises a fifth Kelvin source copper face 3E, a sixth Kelvin source copper face 3F, a seventh Kelvin source copper face 3G and an eighth Kelvin source copper face 3H;
the upper grid copper surface comprises a first grid copper surface 4A, a second grid copper surface 4B, a third grid copper surface 4C and a fourth grid copper surface 4D; the lower gate copper face includes a fifth gate copper face 4E, a sixth gate copper face 4F, a seventh gate copper face 4G, and an eighth gate copper face 4H, wherein the gate copper faces are adjacent to the corresponding kelvin source copper faces.
Wherein the first kelvin source copper surface 3A and the third kelvin source copper surface 3C are located at the same side; the second Kelvin source copper surface 3B and the fourth Kelvin source copper surface 3D are positioned on the same side; the first Kelvin source copper surface 3A and the second Kelvin source copper surface 3B are located on different sides; the fifth Kelvin source copper surface 3E and the seventh Kelvin source copper surface 3G are positioned on the same side; the sixth Kelvin source copper surface 3F and the eighth Kelvin source copper surface 3H are positioned on the same side; the fifth kelvin source copper surface 3E and the sixth kelvin source copper surface 3F are located on different sides;
Referring to fig. 1 to 7, the bonding wires include a first bonding wire 2A, a second bonding wire 2B, a third bonding wire 2C, a fourth bonding wire 2D, a fifth bonding wire 2E, a sixth bonding wire 2F, a seventh bonding wire 2G, an eighth bonding wire 2H, a ninth bonding wire 5A, a tenth bonding wire 5B, an eleventh bonding wire 5C, a twelfth bonding wire 5D, a thirteenth bonding wire 5E, a fourteenth bonding wire 5F, a fifteenth bonding wire 5G, a sixteenth bonding wire 5H, a seventeenth bonding wire 6A, an eighteenth bonding wire 6B, a nineteenth bonding wire 6C, a twentieth bonding wire 6D, a twenty-first bonding wire 6E, a twenty-second bonding wire 6F, a twenty-third bonding wire 6G, and a twenty-fourth bonding wire 6H;
one side of the first bonding wire 2A is connected with the first chip 1A, and the other side of the first bonding wire is connected with the second power copper surface 8; one side of the second bonding wire 2B is connected with the second chip 1B, and the other side of the second bonding wire is connected with the third power copper surface 9; one side of the third bonding wire 2C is connected with the third chip 1C, and the other side is connected with the sixth power copper surface 12; one side of the fourth bonding wire 2D is connected with the fourth chip 1D, and the other side is connected with the seventh power copper surface 13; one side of the fifth bonding wire 2E is connected with the fifth chip 1E, and the other side is connected with the ninth power copper surface 15; one side of the sixth bonding wire 2F is connected to the sixth chip 1F, and the other side is connected to the twelfth power copper surface 18; one side of the seventh bonding wire 2G is connected with the seventh chip 1G, and the other side is connected with the thirteenth power copper surface 19; one side of the eighth bonding wire 2H is connected with the eighth chip 1H, and the other side is connected with the sixteenth power copper surface 22; one side of the ninth bonding wire 5A is connected with the first chip 1A, and the other side of the ninth bonding wire is connected with the first grid copper surface; one side of the tenth bonding wire 5B is connected with the second chip 1B, and the other side is connected with the second grid copper surface; one side of the eleventh bonding wire 5C is connected with the third chip 1C, and the other side of the eleventh bonding wire is connected with the third grid copper surface; one side of the twelfth bonding wire 5D is connected with the fourth chip 1D, and the other side of the twelfth bonding wire is connected with the fourth grid copper surface; one side of the thirteenth bonding wire 5E is connected with the fifth chip 1E, and the other side is connected with the fifth grid copper surface; one side of the fourteenth bonding wire 5F is connected with the second chip 1B, and the other side is connected with the sixth grid copper surface; one side of the fifteenth bonding wire 5G is connected with the second chip 1B, and the other side is connected with the seventh grid copper surface; one side of the sixteenth bonding wire 5H is connected with the second chip 1B, and the other side is connected with the eighth grid copper surface; one side of the seventeenth bonding wire 6A is connected with the first chip 1A, and the other side is connected with the first kelvin source copper surface 3A; one side of the eighteenth bonding wire 6B is connected with the second chip 1B, and the other side is connected with the second kelvin source copper surface 3B; one side of the nineteenth bonding wire is connected with the third chip 1C, and the other side of the nineteenth bonding wire is connected with the third kelvin source copper surface 3C; one side of the twentieth bonding wire 6D is connected with the fourth chip 1D, and the other side of the twentieth bonding wire is connected with the fourth Kelvin source copper surface 3D; one side of the twenty-first bonding wire 6E is connected with the fifth chip 1E, and the other side of the twenty-first bonding wire is connected with the fifth Kelvin source copper surface; one side of the twenty-second bonding wire 6F is connected with the sixth chip 1F, and the other side of the twenty-second bonding wire is connected with the sixth Kelvin source copper surface; one side of the twenty-third bond wire 6G is connected with the seventh chip 1G, and the other side of the twenty-third bond wire is connected with the seventh Kelvin source copper surface; and one side of the twenty-fourth bonding wire 6H is connected with the eighth chip 1H, and the other side of the twenty-fourth bonding wire is connected with the eighth Kelvin source copper surface.
As shown in fig. 11 and 12, copper block connectors connect the power copper faces of the same node dispersed on the upper and lower plates. For example, the dispersed fourth power copper face 10, tenth power copper face 16, eighth power copper face 14, and fourteenth power copper face 20 are connected together by copper block connectors, connecting the dispersed dc+ nodes to one another as well. Likewise, the second, sixth, twelfth and sixteenth power copper faces 8, 12, 18, 22 are also connected together by the copper block connector so that they are all DC-nodes. This innovative design effectively reduces loop resistance and total inductance.
As shown in fig. 9, the present invention provides a method for preparing a low parasitic inductance high power density double-sided heat dissipation power module.
The materials and equipment required by the process are as follows:
the ceramic substrate, the commercial power chip, the customized terminal(s), the steel mesh are used for coating soldering paste, soldering paste materials, a vacuum heating furnace and potting materials for insulation at specific positions of the ceramic substrate.
The preparation process is as follows:
selecting an upper DBC lining plate and a lower DBC lining plate, and soldering paste on the surfaces of the prepared upper DBC lining plate and the prepared lower DBC lining plate through a steel mesh;
The steel mesh of the present invention should be given a suitable thickness to ensure the connection of the solder and to ensure that it is not overcoated. The first insulating layer and the second insulating layer may be made of Al2O3, alN, si3N4, a composite resin, or the like, either alone or in combination. The thickness of the first insulating layer and the second insulating layer is recommended to be 0.6mm. The first metal layer 12 and the second metal layer 22 should be copper, and their thickness is preferably 0.3mm.
Secondly, placing the chips at the appointed positions of an upper DBC lining plate and a lower DBC lining plate respectively through a chip mounter, and placing the chips into a vacuum welding furnace for vacuum welding by utilizing a graphite clamp;
thirdly, cleaning the surfaces of the chip and the lining board which are finished in the second step by using ultrasonic cleaning equipment so as to remove residual soldering paste;
fourthly, connecting the copper surfaces of the chip source electrode and the grid electrode with the copper surface of the Kelvin source electrode through a bonding machine;
fifthly, coating soldering paste on the surface of the copper block connector, the surface of the power copper surface and the surface of the ceramic substrate through a steel mesh; the solder paste material was Sn63-Pb37.
Sixthly, fixing the lining plate, the copper block connector and the power terminal through a graphite clamp, and then placing the lining plate, the copper block connector and the power terminal in a vacuum welding furnace for vacuum welding; the welding temperature was set at 180 ℃.
Seventh, cleaning the lining board, the power terminal and the copper block connector which are finished in the sixth step by using ultrasonic cleaning equipment to remove residual soldering paste;
and eighth, injecting an insulating material into the module obtained after the seventh step in a vacuum encapsulating furnace to encapsulate the module to obtain the double-sided radiating power module with low parasitic inductance and high power density.
The filler can also be made of other suitable materials such as resin, insulating glue, silicon rubber and the like, and is used for improving the insulating strength and protecting the chip.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A low parasitic inductance high power density double sided heat dissipating power module comprising:
an upper DBC liner and a lower DBC liner disposed parallel to the upper DBC liner and electrically connected to respective ports of the upper DBC liner;
4 chips, power terminals, copper block connectors, grid copper surfaces, kelvin source copper surfaces, output terminals and bonding wires are arranged on the upper DBC lining plate and the lower DBC lining plate;
the power terminals are arranged on the same side of the upper DBC lining plate and the lower DBC lining plate, the power terminals of the upper DBC lining plate and the lower DBC lining plate comprise a DC+ node power terminal and a DC-node power terminal, and the DC+ node power terminal and the DC-node power terminal are staggered; the upper DBC lining plate is connected with the lower DBC lining plate through the copper block connector; the output terminal is arranged at one side far away from the power terminal; the grid copper surface and the Kelvin source copper surface are adjacently arranged inside the upper DBC lining plate and the lower DBC lining plate; and the chip is connected with the grid copper surface and the Kelvin source copper surface through the bonding wire.
2. The low parasitic inductance high power density double sided heat dissipating power module of claim 1, wherein the upper DBC liner comprises a first insulating layer, a first heat dissipating layer, a first metal layer, an upper grid copper face, and an upper plate kelvin source copper face; the grid copper surface arranged in the upper DBC lining plate is an upper grid copper surface, and the Kelvin source copper surface arranged in the upper DBC lining plate is an upper plate Kelvin source copper surface; the first insulating layer is arranged between the first metal layer and the first heat dissipation layer; the chip is arranged at a corresponding position of the first metal layer;
the lower DBC lining plate comprises a second insulating layer, a second metal layer of a second heat dissipation layer, an upper grid copper surface and an upper Kelvin source copper surface; the grid copper surface arranged in the lower DBC lining plate is a lower grid copper surface, and the Kelvin source copper surface arranged in the lower DBC lining plate is a lower plate Kelvin source copper surface; the second insulating layer is arranged between the second metal layer and the second heat dissipation layer; the chip is arranged at a corresponding position of the second metal layer;
grid terminals are respectively arranged on the upper grid copper surface and the lower grid copper surface; the upper grid copper surface is connected with an adjacent grid terminal; the lower grid copper surface is connected with an adjacent grid terminal; the upper Kelvin source copper surface and the lower Kelvin source copper surface are respectively provided with Kelvin source terminals, and the upper Kelvin source copper surface is connected with the adjacent Kelvin source terminals; the lower plate Kelvin source copper face is connected with an adjacent Kelvin source terminal.
3. The low parasitic inductance high power density double sided heat dissipating power module of claim 2, wherein the first metal layer comprises a first power copper face, a second power copper face, a third power copper face, a fourth power copper face, a fifth power copper face, a sixth power copper face, a seventh power copper face, and an eighth power copper face;
the second metal layer comprises a ninth power copper surface, a tenth power copper surface, an eleventh power copper surface, a twelfth power copper surface, a thirteenth power copper surface, a fourteenth power copper surface, a fifteenth power copper surface and a sixteenth power copper surface;
the first power copper surface and the second power copper surface form a first copper surface area; the third power copper surface and the fourth power copper surface form a second copper surface area; the fifth power copper surface and the sixth power copper surface form a first copper surface area; the seventh power copper surface and the eighth power copper surface form a second copper surface area; the ninth power copper surface and the tenth power copper surface form a first copper surface area; the eleventh power copper surface and the twelfth power copper surface form a second copper surface area; the thirteenth power copper surface and the fourteenth power copper surface form a first copper surface area; the fifteenth power copper surface and the sixteenth power copper surface form a second copper surface area; the first copper surface areas and the second copper surface areas are staggered.
4. The low parasitic inductance high power density dual sided heat dissipating power module of claim 3, wherein the power terminals comprise a first power terminal, a second power terminal, a third power terminal, a fourth power terminal, a fifth power terminal, a sixth power terminal, a seventh power terminal, and an eighth power terminal;
wherein the first, third, fifth and seventh power terminals are DC-power terminals; the second power terminal, the fourth power terminal, the sixth power terminal and the eighth power terminal are dc+ power terminals; the first power terminal is connected with the second power copper surface; the second power terminal is connected with the fourth power copper surface; the third power terminal is connected with the sixth power copper surface, and the fourth power terminal is connected with the eighth power copper surface; the fifth power terminal is connected with a tenth power copper surface; the sixth power terminal is connected with the twelfth power copper surface; the seventh power terminal is connected with the fourteenth power copper surface, and the eighth power terminal is connected with the sixteenth power copper surface.
5. The low parasitic inductance, high power density, double sided heat dissipating power module of claim 4, wherein the output terminals comprise a first output terminal and a second output terminal; the first output terminal is arranged on one side of the first insulating layer, the first power copper surface, the third power copper surface, the fifth power copper surface and the seventh power copper surface, which is far away from the power terminal, and is connected with the first insulating layer, the first power copper surface, the third power copper surface, the fifth power copper surface and the seventh power copper surface;
The second output terminal is arranged on one side, far away from the power terminal, of the second insulating layer, the ninth power copper surface, the eleventh power copper surface, the thirteenth power copper surface and the fifteenth power copper surface, and is connected with the second insulating layer, the ninth power copper surface, the eleventh power copper surface, the thirteenth power copper surface and the fifteenth power copper surface.
6. The low parasitic inductance high power density double sided heat dissipating power module of claim 4, wherein the copper block connectors comprise a first copper block connector, a second copper block connector, a third copper block connector, a fourth copper block connector, a fifth copper block connector, a sixth copper block connector, a seventh copper block connector, an eighth copper block connector, a ninth copper block connector, a tenth copper block connector, an eleventh copper block connector, a twelfth copper block connector, a thirteenth copper block connector, and a fourteenth copper block connector;
one side of the first copper block connector is connected with a second power copper surface; one side of the ninth copper block connector is connected with a tenth power copper surface, and the other side of the first copper block connector is connected with the other side of the ninth copper block connector; one side of the second copper block connector is connected with the fourth power copper surface; one side of the eighth copper block connector is connected with a twelfth power copper surface; the other side of the first copper block connector is connected with the other side of the eighth copper block connector; one side of the third copper block connector is connected with the fourth power copper surface; one side of the eleventh copper block connector is connected with a fourteenth power copper surface; the other side of the third copper block connector is connected with the other side of the eleventh copper block connector; one side of the fourth copper block connector is connected with the sixth power copper surface; one side of the tenth copper block connector is connected with a twelfth power copper surface; the other side of the fourth copper block connector is connected with the other side of the tenth copper block connector; one side of the fifth copper block connector is connected with the sixth power copper surface; one side of the twelfth copper block connector is connected with a twelfth power copper surface; the other side of the fifth copper block connector is connected with the other side of the twelfth copper block connector; one side of the sixth copper block connector is connected with the sixth power copper surface; one side of the fourteenth copper device is connected with the sixteenth power copper surface; the other side of the sixth copper block connector is connected with the other side of the fourteenth copper block connector; one side of the seventh copper block connector is connected with the eighth power copper surface; one side of the thirteenth copper block connector is connected with the fourteenth power copper surface; the other side of the seventh copper block connector is connected with the other side of the thirteenth copper block connector.
7. The low parasitic inductance high power density dual sided heat dissipating power module of claim 6, wherein the 4 chips disposed on the lower DBC liner comprise a first chip, a second chip, a third chip, and a fourth chip; the 4 chips arranged on the upper DBC lining plate comprise a fifth chip, a sixth chip, a seventh chip and an eighth chip;
the first chip is connected to the corresponding position of the first power copper surface; the second chip is connected to the corresponding position of the fourth power copper surface; the third chip is connected to the corresponding position of the fifth power copper surface; the fourth chip is connected to the corresponding position of the eighth power copper surface; the fifth chip is connected to the corresponding position of the tenth power copper surface; the sixth chip is connected to the corresponding position of the eleventh power copper surface; the seventh chip is connected to the corresponding position of the fourteenth power copper surface; the eighth chip 1H is connected to a corresponding position of the fifteenth power copper surface.
8. The low parasitic inductance high power density double sided heat dissipating power module of claim 7, wherein the upper plate kelvin source copper face comprises a first kelvin source copper face, a second kelvin source copper face, a third kelvin source copper face, and a fourth kelvin source copper face; the lower plate Kelvin source copper surface comprises a fifth Kelvin source copper surface, a sixth Kelvin source copper surface, a seventh Kelvin source copper surface and an eighth Kelvin source copper surface;
The first Kelvin source copper surface and the third Kelvin source copper surface are positioned on the same side; the second Kelvin source copper surface and the fourth Kelvin source copper surface are positioned on the same side; the first Kelvin source copper face and the second Kelvin source copper face are located on different sides; the fifth Kelvin source copper surface and the seventh Kelvin source copper surface are positioned on the same side; the sixth Kelvin source copper surface and the eighth Kelvin source copper surface are positioned on the same side; the fifth Kelvin source copper face and the sixth Kelvin source copper face are located on different sides;
the upper grid copper surface comprises a first grid copper surface, a second grid copper surface, a third grid copper surface and a fourth grid copper surface; the lower grid copper surface comprises a fifth grid copper surface, a sixth grid copper surface, a seventh grid copper surface and an eighth grid copper surface; wherein the gate copper face is adjacent to the corresponding kelvin source copper face.
9. The low parasitic inductance high power density double sided heat dissipating power module of claim 8, wherein the bonding wire comprises a first bonding wire, a second bonding wire, a third bonding wire, a fourth bonding wire, a fifth bonding wire, a sixth bonding wire, a seventh bonding wire, an eighth bonding wire, a ninth bonding wire, a tenth bonding wire, an eleventh bonding wire, a twelfth bonding wire, a thirteenth bonding wire, a fourteenth bonding wire, a fifteenth bonding wire, a sixteenth bonding wire, a seventeenth bonding wire, an eighteenth bonding wire, a nineteenth bonding wire, a twentieth bonding wire, a twenty-first bonding wire, a twenty-second bonding wire, a twenty-third bonding wire, a twenty-fourth bonding wire;
One side of the first bonding wire is connected with the first chip, and the other side of the first bonding wire is connected with the second power copper surface; one side of the second bonding wire is connected with the second chip, and the other side of the second bonding wire is connected with the third power copper surface; one side of the third bonding wire is connected with the third chip, and the other side of the third bonding wire is connected with the sixth power copper surface; one side of the fourth bonding wire is connected with the fourth chip, and the other side of the fourth bonding wire is connected with the seventh power copper surface; one side of the fifth bonding wire is connected with the fifth chip, and the other side of the fifth bonding wire is connected with the ninth power copper surface; one side of the sixth bonding wire is connected with the sixth chip, and the other side of the sixth bonding wire is connected with the twelfth power copper surface; one side of the seventh bonding wire is connected with the seventh chip, and the other side of the seventh bonding wire is connected with the thirteenth power copper surface; one side of the eighth bonding wire is connected with the eighth chip, and the other side of the eighth bonding wire is connected with the sixteenth power copper surface; one side of the ninth bonding wire is connected with the first chip, and the other side of the ninth bonding wire is connected with the first grid copper surface; one side of the tenth bonding wire is connected with the second chip, and the other side of the tenth bonding wire is connected with the second grid copper surface; one side of the eleventh bonding wire is connected with the third chip, and the other side of the eleventh bonding wire is connected with the third grid copper surface; one side of the twelfth bonding wire is connected with the fourth chip, and the other side of the twelfth bonding wire is connected with the fourth grid copper surface; one side of the thirteenth bonding wire is connected with the fifth chip, and the other side of the thirteenth bonding wire is connected with the fifth grid copper surface; one side of the fourteenth bonding wire is connected with the second chip, and the other side of the fourteenth bonding wire is connected with the sixth grid copper surface; one side of the fifteenth bonding wire is connected with the second chip, and the other side of the fifteenth bonding wire is connected with the seventh grid copper surface; one side of the sixteenth bonding wire is connected with the second chip, and the other side of the sixteenth bonding wire is connected with the eighth grid copper surface; one side of the seventeenth bonding wire is connected with the first chip, and the other side of the seventeenth bonding wire is connected with the first Kelvin source copper surface; one side of the eighteenth bonding wire is connected with the second chip, and the other side of the eighteenth bonding wire is connected with the second Kelvin source copper surface; one side of the nineteenth bonding wire is connected with the third chip, and the other side of the nineteenth bonding wire is connected with the third Kelvin source copper surface; one side of the twentieth bonding wire is connected with the fourth chip, and the other side of the twentieth bonding wire is connected with the fourth Kelvin source copper surface; one side of the twenty-first bonding wire is connected with the fifth chip, and the other side of the twenty-first bonding wire is connected with the fifth Kelvin source copper surface; one side of the twenty-second bonding wire is connected with the sixth chip, and the other side of the twenty-second bonding wire is connected with the sixth Kelvin source copper surface; one side of the twenty-third bond wire is connected with the seventh chip, and the other side of the twenty-third bond wire is connected with the seventh Kelvin source copper surface; and one side of the twenty-fourth bonding wire is connected with the eighth chip, and the other side of the twenty-fourth bonding wire is connected with the eighth Kelvin source copper surface.
10. The preparation method of the low parasitic inductance high power density double-sided heat dissipation power module is characterized by comprising the following steps of:
selecting an upper DBC lining plate and a lower DBC lining plate, and soldering paste on the surfaces of the prepared upper DBC lining plate and the prepared lower DBC lining plate through a steel mesh;
secondly, placing the chips at the appointed positions of an upper DBC lining plate and a lower DBC lining plate respectively through a chip mounter, and placing the chips into a vacuum welding furnace for vacuum welding by utilizing a graphite clamp;
thirdly, cleaning the surfaces of the chip and the lining board which are finished in the second step by using ultrasonic cleaning equipment so as to remove residual soldering paste;
fourthly, connecting the copper surfaces of the chip source electrode and the grid electrode with the copper surface of the Kelvin source electrode through a bonding machine;
fifthly, coating soldering paste on the surface of the copper block connector, the surface of the power copper surface and the surface of the ceramic substrate through a steel mesh;
sixthly, fixing the lining plate, the copper block connector and the power terminal through a graphite clamp, and then placing the lining plate, the copper block connector and the power terminal in a vacuum welding furnace for vacuum welding;
seventh, cleaning the lining board, the power terminal and the copper block connector which are finished in the sixth step by using ultrasonic cleaning equipment to remove residual soldering paste;
and eighth, injecting an insulating material into the module obtained after the seventh step in a vacuum encapsulating furnace to encapsulate the module to obtain the double-sided radiating power module with low parasitic inductance and high power density.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311296194.XA CN117334656A (en) | 2023-10-08 | 2023-10-08 | Low parasitic inductance high power density double-sided heat dissipation power module and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311296194.XA CN117334656A (en) | 2023-10-08 | 2023-10-08 | Low parasitic inductance high power density double-sided heat dissipation power module and preparation method thereof |
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| CN117334656A true CN117334656A (en) | 2024-01-02 |
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| CN202311296194.XA Pending CN117334656A (en) | 2023-10-08 | 2023-10-08 | Low parasitic inductance high power density double-sided heat dissipation power module and preparation method thereof |
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| Country | Link |
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- 2023-10-08 CN CN202311296194.XA patent/CN117334656A/en active Pending
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