CN117316936B - Three-dimensional longitudinal and transverse groove MIS chip capacitor and preparation method thereof - Google Patents
Three-dimensional longitudinal and transverse groove MIS chip capacitor and preparation method thereof Download PDFInfo
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- CN117316936B CN117316936B CN202311382316.7A CN202311382316A CN117316936B CN 117316936 B CN117316936 B CN 117316936B CN 202311382316 A CN202311382316 A CN 202311382316A CN 117316936 B CN117316936 B CN 117316936B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 44
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 72
- 238000011049 filling Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 30
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000001301 oxygen Substances 0.000 claims abstract description 25
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 25
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims description 15
- 239000003292 glue Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 claims description 7
- 238000001704 evaporation Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 abstract description 15
- 239000004065 semiconductor Substances 0.000 abstract description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001883 metal evaporation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention belongs to the technical field of semiconductor devices and provides a three-dimensional longitudinal and transverse groove MIS chip capacitor and a preparation method thereof, wherein the three-dimensional longitudinal and transverse groove MIS chip capacitor comprises a P-type silicon substrate, a thin oxygen layer, an HfO 2 layer, an oxide layer, a filling layer, a front metal layer, a passivation layer and a back metal layer, wherein a reticular groove is formed on the P-type silicon substrate, the reticular groove can obtain larger specific surface area and has higher initial junction capacitance; and a thin oxygen layer (SiO 2）-HfO2 layer-oxide layer (SiO 2) structure is formed on the reticular structure, so that the low capacitance thickness is ensured, the capacitance value can be improved, a front metal layer is deposited after the filling layer adopts doped polysilicon, the metal is not easy to fall off, and the reliability of the MIS chip capacitor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a three-dimensional longitudinal and transverse groove MIS chip capacitor and a preparation method thereof.
Background
The MIS chip capacitor mainly comprises three parts of M (metal) -I (insulator) -S (semiconductor), wherein the thickness, material and contact area of the insulator and a metal electrode can influence the capacitance of the MIS device, and the device can realize the functions of energy storage, coupling, filtering and the like in electronic devices and circuits. With the reduction of the chip size, the requirement on the MIS capacitor insulating layer is improved, and when the thickness of the insulating layer is too small, the leakage current is increased sharply, so that the device is burnt; the thickness of the insulating layer is reduced, and electrons in the metal are more likely to migrate into the insulating layer, affecting the performance of the capacitor.
The manufacturing mode of the conventional MIS chip capacitor is simpler: and growing a layer of SiO 2 on the P-type substrate, depositing front metal Al on the SiO 2, and depositing back metal Al on the back of the P-type substrate to form ohmic contact. The charge storage capacity of the conventional MIS chip capacitor is low, if the charge storage capacity is required to be increased, the thickness of SiO 2 can be reduced, but the leakage current can be gradually increased along with the reduction of the thickness of an oxide layer, and the withstand voltage of the device can be reduced; the deep holes in the conventional hole digging design are independent individuals, and the speed in the middle of the dry etching hole is inconsistent with the speed at the edge of the hole due to the influence of a load effect, so that a process error exists; there is an interface between the metal layer and the insulating layer in the conventional MIS capacitor, and electrons in the metal may migrate into the insulating layer under the action of an electric field, resulting in a change in capacitance value.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a three-dimensional longitudinal and transverse groove MIS chip capacitor and a preparation method thereof, which are used for solving the problems of large leakage current and reduced voltage resistance of a device caused by increasing the thickness of SiO 2 to improve the charge storage capacity of the capacitor.
In a first aspect, the present invention provides a three-dimensional crossbar trench MIS chip capacitor, including:
a P-type silicon substrate, wherein a net-shaped groove is formed on the P-type silicon substrate;
the thin oxygen layer is arranged on the P-type silicon substrate;
A HfO 2 layer disposed on the thin oxygen layer;
An oxide layer disposed on the HfO 2 layer;
The filling layer is arranged on the oxide layer and used for filling the reticular groove, the edge of the filling layer is removed to form a first window, and the filling layer is doped polysilicon;
the front metal layer is arranged on the filling layer, and the edge of the front metal layer is aligned with the edge of the filling layer;
The passivation layer is arranged on the first window and the front metal layer, and the central area of the passivation layer is removed to form a second window so that the front metal layer is exposed;
and the back metal layer is arranged at the bottom of the P-type silicon substrate.
According to the technical scheme, the three-dimensional longitudinal and transverse groove MIS chip capacitor provided by the invention has the advantages that the mesh grooves are formed in the P-type silicon substrate, the polar plate area is increased, and the capacitance value is improved; simultaneously, the meshed grooves which are vertically and horizontally communicated can fully reflect the deviation of the etching process with the P-type silicon substrate; the thin oxygen layer, the HfO 2 layer and the oxide layer are sequentially formed, so that the capacitance value is improved when the thickness is ensured, and meanwhile, the oxide layer can overcome the problem that the HfO 2 layer is easy to absorb moisture, and the reliability is improved.
Optionally, the P-type silicon substrate has a crystal orientation of < 10 > and a resistivity of < 0>。
Optionally, the width of the mesh-shaped groove isDepth of. The specific surface area is increased by the opening of the longitudinal and transverse grooves, the netlike grooves are mutually communicated, etching gas can react with the P-type silicon substrate more fully when dry etching is performed, and the deviation of the etching process is reduced.
Optionally, the thin oxygen layer has a thickness ofA, the thickness of the HfO 2 layer isNm, the thickness of the oxide layer isÅ。
Optionally, the filling layer is boron doped polysilicon with doping concentration larger than. The boron-doped polysilicon is used as a conducting layer to fill the groove, electrons on the metal can be combined with holes of the boron-doped polysilicon, electrons are prevented from migrating to the insulating layer, and the breakdown failure of the device is avoided; and the polysilicon can be fully contacted with the insulating medium, and the front metal layer is not easy to fall off, so that the reliability of the MIS chip capacitor is improved.
Optionally, the passivation layer is PI glue. And after the front metal electrode is finished, spin-coating PI glue, and opening a second window in the central area of the PI glue to form a passivation layer. The PI adhesive has good insulating property and radiation resistance, and the film can be negatively charged, and the negative charge is beneficial to compensating the fixed positive charge frequently existing in thermally grown SiO 2 so as to play a role in surface passivation.
In a second aspect, the present invention provides a method for manufacturing a three-dimensional crossbar trench MIS chip capacitor, including:
s1, forming a reticular groove on a P-type silicon substrate;
s2, forming a thin oxygen layer on the P-type silicon substrate;
S3, depositing an HfO 2 layer on the thin oxygen layer;
S4, depositing an oxide layer on the HfO 2 layer;
S5, preparing a filling layer on the oxide layer for filling the reticular groove, and etching the edge of the filling layer to form a first window; the filling layer is formed by in-situ growth of doped polysilicon;
S6, evaporating the filling layer to form a front metal layer, wherein the edge of the front metal layer is aligned with the edge of the filling layer;
s7, forming a passivation layer on the first window and the front metal layer, and removing the central area of the passivation layer to form a second window so that the front metal layer is exposed;
s8, evaporating the bottom of the P-type silicon substrate to form a back metal layer.
By adopting the technical scheme, the application has at least the following technical effects:
The 1.P type silicon substrate is provided with the netlike grooves, the grooves are crisscrossed vertically and horizontally to obtain larger specific surface area, and under zero bias, the initial junction capacitance is far more than the conventional MIS chip capacitance; meanwhile, the netlike grooves are integrated, etching gas can react with the silicon substrate more fully, etching process deviation is reduced, compared with the load effect born by the deep hole structure, the speed in the middle of the dry etching holes is inconsistent with the speed at the edges of the holes, and process errors are reduced.
2. The insulating layer adopts a SiO 2-HfO2-SiO2 structure, the dielectric constant of HfO 2 is six times that of SiO 2, and the insulating layer has a larger capacitance value under the same thickness; in addition, the oxide layer can solve the problem that HfO 2 is easy to absorb moisture, and the reliability of the device is improved.
3. The boron-doped polysilicon is used as a conductive layer to fill the reticular groove, and when reverse voltage is applied, holes of the boron-doped polysilicon are combined with electrons on metal to prevent electrons from migrating to the insulating layer, so that breakdown failure is avoided; the polysilicon can be fully contacted with the insulating medium, and metal is not easy to fall off when a metal layer is deposited, so that the reliability of the MIS chip capacitor is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. Like elements or portions are generally identified by like reference numerals throughout the several figures. In the drawings, elements or portions thereof are not necessarily drawn to scale.
Fig. 1 shows a schematic diagram of a three-dimensional crossbar trench high-capacity MIS chip capacitor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a mesh trench according to an embodiment of the present invention;
FIG. 3 shows a schematic diagram of a MIS chip capacitor fully covered by a filler layer and a metal layer;
FIG. 4a is a schematic diagram of a MIS chip capacitor according to the prior art;
Fig. 4b is a schematic diagram of a three-dimensional cross trench high-capacity MIS chip capacitor according to an embodiment of the present invention;
Fig. 5 shows a flowchart of a method for manufacturing a three-dimensional crossbar trench high-capacity MIS chip capacitor according to another embodiment of the present invention.
Reference numerals:
A 1-P type silicon substrate; 2-mesh-shaped grooves; 3-a thin oxygen layer; 4-HfO 2 layers; a 5-oxide layer; 6-a filling layer; 7-a front side metal layer; 8-a passivation layer; 9-backside metal layer.
Detailed Description
Embodiments of the technical scheme of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present invention, and thus are merely examples, which should not be construed as limiting the scope of the present invention.
It is noted that unless otherwise indicated, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "width," "thickness," "upper," "lower," "top," "bottom," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. In the description of the present invention, the meaning of "plurality" is two or more unless specifically defined otherwise.
Example 1
As shown in fig. 1-2, the present embodiment provides a three-dimensional longitudinal and transverse groove high-capacity MIS chip capacitor, which comprises a P-type silicon substrate 1, wherein a mesh groove 2 is formed on the P-type silicon substrate 1; a thin oxygen layer 3, an HfO 2 layer 4, and an oxide layer 5, which are sequentially formed on a P-type silicon substrate 1, serve as insulating layers. According to a capacitance formula c= ɛ S/d, wherein ɛ is the dielectric constant of the medium between the polar plates, S is the polar plate area, and d is the distance between the polar plates; the mesh-shaped groove 2 on the P-type silicon substrate 1 increases the polar plate area S, the dielectric constant of the HfO 2 layer 4 is six times that of SiO 2, and the structure of the mesh-shaped groove 2 and the adoption of the HfO 2 as the insulating layer 4 can obviously increase the capacitance value of MIS chip capacitance.
The oxide layer 5 further comprises a filling layer 6, a front metal layer 7, a passivation layer 8 and a back metal layer 9.
The filling layer 6 is disposed on the oxide layer 5 to fill the mesh trench 2, the edge of the filling layer 6 is removed to form a first window, and the filling layer 6 is doped polysilicon. The filling layer 6 can be fully contacted with an insulating medium by adopting polysilicon, metal is deposited on the polysilicon later, the front metal layer 7 is not easy to fall off, and the reliability of the MIS chip capacitor is improved.
The front metal layer 7 is arranged on the filling layer 6, and the edge of the front metal layer 7 is aligned with the edge of the filling layer 6; the passivation layer 8 is disposed on the first window and the front metal layer 7, and a central region of the passivation layer 8 is removed to form a second window, so that the front metal layer 7 is exposed. The back metal layer 9 is provided at the bottom of the P-type silicon substrate 1.
A net-shaped groove 2 is formed on a P-type silicon substrate 1, the area of a polar plate is increased, and the capacitance is improved; simultaneously, the meshed grooves 2 which are vertically and horizontally communicated enable etching gas to fully react with the P-type silicon substrate 1, and etching process deviation is reduced; the thin oxygen layer 3, the HfO 2 layer 4 and the oxide layer 5 are sequentially formed, so that the capacitance value is improved when the thickness is ensured, and meanwhile, the oxide layer 5 can overcome the problem that the HfO 2 layer 4 is easy to absorb moisture, and the reliability is improved.
In a specific example, the P-type silicon substrate 1 has a crystal orientation of < 10 > and a resistivity of < 0>。
Alternatively, the width of the mesh-like grooves 2 isDepth of. The high aspect ratio of the reticular groove 2 enables the specific surface area to be larger, and under zero bias, the initial junction capacitance is far more than the conventional MIS chip capacitance; the network grooves 2 are mutually communicated, and etching gas can be more fully reacted with the P-type silicon substrate 1 when dry etching is performed, so that etching process deviation is reduced.
Alternatively, the thin oxygen layer 3 has a thickness ofThe thickness of the A, hfO 2 layer 4 isNm, thickness of oxide layer 5Å。
Optionally, the filling layer 6 is boron doped polysilicon with a doping concentration greater than. The boron-doped polysilicon is used as a conducting layer to fill the reticular groove 2, the boron-doped polysilicon is fully contacted with the dielectric of the insulating layer, so that the filling of the groove is facilitated, the subsequent metal deposition is facilitated, electrons on the metal can be combined with holes of the boron-doped polysilicon, the electrons are prevented from migrating to the insulating layer, the breakdown failure of a device is avoided, and the reliability of the MIS chip capacitor is improved.
In a specific example, the passivation layer 8 is PI glue. After the front metal electrode is finished, PI glue is spin-coated, and a second window is formed in the center area of the PI glue, so that a passivation layer 8 is formed. The PI adhesive has good insulating property and radiation resistance, can carry negative charges, and the negative charges are beneficial to compensating fixed positive charges frequently existing in thermally grown SiO 2 so as to play a role in surface passivation.
Fig. 3 shows a MIS chip capacitor fully covered by a filler layer 6 and a metal layer. After the chip is sliced, the MIS chip capacitor shown in fig. 3 has certain lattice defects and lattice damages at the edge of the device, which can reduce the breakdown voltage of the device. And if the moisture content in the air is too high, it may cause short circuits of the front metal layer 7, the filler layer 6 and the back metal layer 9 of the device, causing damage. The MIS chip capacitor provided by the embodiment can isolate water vapor by taking PI glue as the passivation layer 8, so that the problem of reducing the breakdown voltage of the device or causing short circuit of the device is avoided.
In a specific example, the front metal layer 7 and the back metal layer 9 are Al.
The technical scheme in the embodiment of the application at least has the following technical effects:
the mesh grooves 2 formed on the 1.P type silicon substrate 1 have high depth-to-width ratio, the crisscrossed mesh grooves 2 can obtain larger specific surface area, under zero bias, the initial junction capacitance is far more than the capacitance of a conventional MIS chip, the grooves are communicated into a latticed whole by the design of the crisscross grooves, etching gas can react with the silicon substrate more fully, and the deviation of the etching process is reduced;
2. The insulating layer adopts a thin oxygen layer 3 (SiO 2）-HfO2 layer 4-oxide layer 5 (SiO 2) structure, the dielectric constant of HfO 2 is six times that of SiO 2, and under the condition of the same thickness, the capacitance of the structure is far larger than that of a conventional MIS chip, meanwhile, the oxide layer 5 can overcome the problem that HfO 2 is easy to absorb moisture, and the reliability of the device is enhanced;
3. The MIS chip capacitance, now directly deposited with metal, is shown in fig. 4 a: the metal is in direct contact with the insulating layer, electrons in the metal are more likely to migrate into the insulating layer, the performance of the capacitor is weakened/damaged, the metal deposition cannot fully fill the groove, the contact between the metal and the insulating layer medium is uneven, the performance of the MIS chip capacitor is affected, and the metal is easy to fall off. While this embodiment is shown in fig. 4 b: the boron-doped polysilicon is used as a conducting layer to fill the groove, when reverse voltage is applied to the MIS chip capacitor, holes of the boron-doped polysilicon are compounded with electrons on metal, electrons are prevented from migrating to the insulating layer, and the device is prevented from being broken down and losing efficacy; and the polysilicon can be fully contacted with the insulating medium, and metal is deposited on the basis of the polysilicon later, so that the metal is not easy to fall off, and the reliability of the MIS chip capacitor is improved.
Example 2
As shown in fig. 5, the method for manufacturing a three-dimensional crossbar trench MIS chip capacitor provided in this embodiment includes:
s1, preprocessing a P-type silicon substrate 1, and forming a net-shaped groove 2 which is communicated transversely and longitudinally on the P-type silicon substrate 1 by first photoetching, wherein the width of the groove is Depth of。
S2, preparing a thin oxygen layer 3: forming a thickness of P-type silicon substrate 1 by dry oxygen methodThin oxygen layer 3 of a. The thin oxygen layer 3 is prepared by adopting a dry oxygen method, and the thin oxygen layer 3 has high density and few defects.
S3, depositing an HfO 2 layer 4 on the thin oxygen layer 3 by adopting an atomic layer deposition method, wherein the thickness of the HfO 2 layer 4 isÅ。
S4, depositing an oxide layer 5 on the HfO 2 layer 4 by adopting an LPCVD method; at the position ofIntroducing O 2 at the temperature, and forming an oxide layer SiO 2 film with the thickness ofÅ。
S5, preparing a filling layer 6 on the oxide layer 5 for filling the netlike groove 2, and etching the edge of the filling layer 6 by second photoetching to form a first window. The filling layer 6 is formed by in-situ growth of doped polysilicon; the doped polysilicon is specifically boron doped polysilicon, and the doping concentration is larger than。
S6, front metal evaporation: and evaporating to form a front metal Al layer on the filling layer 6, and removing the redundant front metal layer 7 by third photoetching to align the edge of the front metal layer 7 with the edge of the filling layer 6.
S7, forming a passivation layer 8 on the first window and the front metal layer 7, performing photoetching for the fourth time, and removing the central area of the passivation layer 8 to form a second window so as to expose the front metal layer 7. The passivation layer 8 can be PI glue, has good insulating property and radiation resistance, can be negatively charged, and the negative charge is beneficial to compensating fixed positive charges frequently existing in thermally grown SiO 2 so as to play a role in surface passivation.
S8, back metal evaporation: and thinning the back of the P-type silicon substrate 1, and evaporating the bottom of the P-type silicon substrate 1 to form a back metal Al layer after light etching treatment.
The method for manufacturing the three-dimensional longitudinal and transverse groove MIS chip capacitor provided by the embodiment adopts the same inventive concept as the three-dimensional longitudinal and transverse groove MIS chip capacitor, and can obtain the same beneficial effects, and is not described herein again.
In the description of the present invention, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
Claims (7)
1. A three-dimensional crossbar trench MIS chip capacitor, comprising:
a P-type silicon substrate, wherein a net-shaped groove is formed on the P-type silicon substrate;
the thin oxygen layer is arranged on the P-type silicon substrate;
A HfO 2 layer disposed on the thin oxygen layer;
An oxide layer disposed on the HfO 2 layer;
The filling layer is arranged on the oxide layer and used for filling the reticular groove, the edge of the filling layer is removed to form a first window, and the filling layer is boron-doped polysilicon; the boron-doped polysilicon serves as a conductive layer to fill the reticular groove, and holes of the boron-doped polysilicon are compounded with electrons on the front metal layer when reverse voltage is applied, so that electrons are prevented from migrating to the insulating layer, and breakdown failure is avoided;
the front metal layer is arranged on the filling layer, and the edge of the front metal layer is aligned with the edge of the filling layer;
The passivation layer is arranged on the first window and the front metal layer, and the central area of the passivation layer is removed to form a second window so that the front metal layer is exposed;
and the back metal layer is arranged at the bottom of the P-type silicon substrate.
2. The three-dimensional crossbar trench MIS chip capacitor of claim 1, wherein the P-type silicon substrate has a crystal orientation of < 10 > and a resistivity of < 0>。
3. The three-dimensional crossbar trench MIS chip capacitor of claim 2 wherein the width of the mesh trench isDepth of。
4. The three-dimensional crossbar trench MIS chip capacitor of claim 1 or 3, wherein the thin oxygen layer has a thickness ofA, the thickness of the HfO 2 layer isNm, the thickness of the oxide layer isÅ。
5. The three-dimensional crossbar trench MIS chip capacitor of claim 1 wherein the doping concentration of the filling layer is greater than。
6. The three-dimensional crossbar trench MIS chip capacitor of claim 1 wherein the passivation layer is PI glue.
7. The preparation method of the three-dimensional longitudinal and transverse groove MIS chip capacitor is characterized by comprising the following steps:
s1, forming a reticular groove on a P-type silicon substrate;
s2, forming a thin oxygen layer on the P-type silicon substrate;
S3, depositing an HfO 2 layer on the thin oxygen layer;
S4, depositing an oxide layer on the HfO 2 layer;
S5, preparing a filling layer on the oxide layer for filling the reticular groove, and etching the edge of the filling layer to form a first window; the filling layer is formed by growing boron-doped polysilicon in situ; the boron-doped polysilicon serves as a conductive layer to fill the reticular groove, and holes of the boron-doped polysilicon are compounded with electrons on the front metal layer when reverse voltage is applied, so that electrons are prevented from migrating to the insulating layer, and breakdown failure is avoided;
S6, evaporating the filling layer to form a front metal layer, wherein the edge of the front metal layer is aligned with the edge of the filling layer;
s7, forming a passivation layer on the first window and the front metal layer, and removing the central area of the passivation layer to form a second window so that the front metal layer is exposed;
s8, thinning the back surface, and evaporating the back surface of the P-type silicon substrate to form a back metal layer.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310997A (en) * | 2019-05-20 | 2019-10-08 | 中国电子科技集团公司第五十五研究所 | A kind of MIS chip capacity of high capacitance density |
| CN110943164A (en) * | 2018-09-21 | 2020-03-31 | 台湾积体电路制造股份有限公司 | Capacitor and forming method thereof |
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| CN109003962A (en) * | 2018-07-16 | 2018-12-14 | 无锡中微晶园电子有限公司 | A kind of manufacturing method of high frequency silicon capacitor |
| CN208767297U (en) * | 2018-09-29 | 2019-04-19 | 长鑫存储技术有限公司 | Capacitance structure |
| US11749661B2 (en) * | 2021-06-30 | 2023-09-05 | Qualcomm Incorporated | Package comprising a substrate and a multi-capacitor integrated passive device |
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| CN110943164A (en) * | 2018-09-21 | 2020-03-31 | 台湾积体电路制造股份有限公司 | Capacitor and forming method thereof |
| CN110310997A (en) * | 2019-05-20 | 2019-10-08 | 中国电子科技集团公司第五十五研究所 | A kind of MIS chip capacity of high capacitance density |
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