CN1172541A

CN1172541A - Programmable controller

Info

Publication number: CN1172541A
Application number: CN 96190259
Authority: CN
Inventors: 中井大
Original assignee: Matsushita Electric Works Ltd
Current assignee: Panasonic Electric Works Co Ltd
Priority date: 1996-03-06
Filing date: 1996-03-06
Publication date: 1998-02-04
Anticipated expiration: 2016-03-06
Also published as: CN1114160C

Abstract

A clock signal generated from timer is outputted to interruption controller and dedicated CPU. When the clock signal is inputted while the CPU is executing a specific arithmetic processing, the CPU stops the processing and causes a main CPU to return to an operating state from a hold state. Namely, the CPU returns the control to the main CPU at every period (500 'mu's) of the clock signal the period of the clock signal is shroter than the time interval of data transferring interruption requests from a serial controller. Hence data can be transferred to a memory without any DMA controller which has been conventionally used, and the cost of a programmable controller can be reduced.

Description

Programmable controller

Technical field

The present invention relates to have go forward side by side host CPU that row operation handles and carry out in the calculation process functioning in an acting capacity of the programmable controller of the dedicated cpu that certain operations handles of executive routine according to the instruction of above-mentioned host CPU at above-mentioned host CPU.

Background technology

In the past, for the burden of host CPU alleviates and the shortening time, provide a kind of and carry out having in the calculation process programmable controller of the dedicated cpu that the certain operations functioned in an acting capacity of handles at host CPU, Fig. 6 is the block scheme of the so existing example structure of expression.Dedicated cpu 11 is CPU that high-speed computation is used, and carries out specific calculation process and replaces host CPU 10.Here, go up the certain operations of setting CPU10 at dedicated cpu 11 all registers (not shown) and handle necessary various parameter, make dedicated cpu 11 startings, 10 outputs of 11 pairs of host CPUs of dedicated cpu keep (HOLD) signal.Host CPU 10 is exported to dedicated cpu 11 with the signal (ACK) of response when the input of this holding signal, make this operation become halted state (hold mode).And dedicated cpu 11 carries out calculation process during this, finishes as this processing, and the signal of the hold mode of CPU10 is removed in dedicated cpu 11 outputs.Thus, remove the hold mode of host CPU 10, host CPU 10 carries out other computing.And, in carrying out calculation process, the occasion dedicated cpu 11 of reading the occasion of own inexecutable order (can only host CPU 10 carry out order) or dedicated cpu 11 being stopped request signal from the outside input at dedicated cpu 11 is Interrupt Process and remove the hold mode of host CPU 10 also.

And, in above-mentioned existing example, input to the interrupting channel int and the dedicated cpu 11 of host CPU 10 from the internal timing clock signal (hereinafter to be referred as " clock signal ") of timing portion 12.Promptly, because host CPU 10 is not accepted interrupt request in the occasion of hold mode, in order to measure the elapsed time of the timer command that host CPU 10 carries out, clock signal is inputed to dedicated cpu 11 as stopping request signal, on host CPU 10, carry out the interrupt request that causes by clock signal after the hold mode of CPU10 in case remove, must carry out increment to the count value of counter (not shown) and handle (regularly Interrupt Process).For example, for elapsed time, cycle of clock signal is set at 2.5ms (with reference to Fig. 7) in above-mentioned existing example with the timer command of 1/4th precision determination 10ms.

, in order to carry out the data communication with the surrounding devices (external unit) of programming device etc., the Serial Control portion 13 of communication usefulness is connected with dedicated cpu 11 grades with host CPU 10 by address data bus 14 in above-mentioned existing example.DMA (direct access) control part (hereinafter to be referred as " DMA portion 16 ") that above-mentioned address data bus 14 is connecting the memory section 15 that is made of the RAM storer of cancellation (write /) and replacing the data between host CPU 10 control store portions 15 and the Serial Control portion 13 to transmit sends reading of memory of data portion 15 and writes all by 16 controls of DMA portion to the memory section 15 that receives external data to the outside.Like this, because the programs of using to the Interrupt Process of host CPU 10 from Serial Control portion 13 with the data transmission 1 between control Serial Control portions 13 of DMA portion 16 and the memory section 15 etc. are just unnecessary, so can improve the burden of software and all processing time and treatment effeciencies.

,, there are DMA portion 16 prices of various advantages higher, so exist cost to reduce difficult, somewhat expensive problem in the occasion of as above-mentioned existing example, using DMA portion 16.

Opening of invention shown

The objective of the invention is to address the above problem, a kind of programmable controller that treatment effeciency does not reduce, cost is low again that data are transmitted is provided.

In order to achieve the above object, the invention of claim 1 has the executive routine host CPU that row operation handles of going forward side by side, with the dedicated cpu of functioning in an acting capacity of specific calculation process in the calculation process of carrying out according to the instruction of above-mentioned host CPU at above-mentioned host CPU, above-mentioned dedicated cpu makes above-mentioned host CPU be in operation stop condition during carrying out above-mentioned specific calculation process, in the time of when above-mentioned specific calculation process finishes, maybe must carrying out the calculation process beyond the above-mentioned specific calculation process or have when the outside input stops request signal, just should remove the operation stop condition of above-mentioned host CPU, forming thus in the programmable controller, also has the Serial Control portion that in the data communication of carrying out with external unit, on the above-mentioned host CPU of a partition data that receives each regulation, carries out interrupt request, with in the clock signal that produces above-mentioned host CPU operation usefulness, this clock signal is stopped the timing portion that request signal is exported to above-mentioned dedicated cpu as above-mentioned, with transmit control and storage by the above-mentioned host CPU of accepting the interrupt request that above-mentioned Serial Control portion comes from memory of data portion that external unit receives, set the cycle of above-mentioned clock signal with the value of above-mentioned Serial Control portion below the desired time of reception of the above-mentioned partition data of reception, so in the execution that the certain operations of dedicated cpu is handled, also synchronously remove the operation stop condition of host CPU with above-mentioned clock signal.And, the time interval of the interrupt request that generation comes from Serial Control portion promptly by Serial Control portion than receive the short time interval of the desired time of reception of an above-mentioned partition data host CPU is become can mode of operation, can transmit by the data that host CPU is controlled between Serial Control portion and the storer.That is, do not resemble the dma controller that uses high price the existing example, also can carry out data between Serial Control portion and memory section and transmit in the calculation process of dedicated cpu is carried out, the treatment effeciency that data are transmitted does not descend and is low-cost.

The invention of claim 2 is in the invention of claim 1, cycle of above-mentioned clock signal is set on the approximate number of timing of the timer command that above-mentioned host CPU carries out, make host CPU become can mode of operation cycle consistent with the cycle of the timing of timer command, can easily carry out the mensuration of this time with the precision of stipulating.

The invention of claim 3 is in the invention of claim 2, the communication speed of the data communication of above-mentioned Serial Control portion is set as 19,200 bps, the data length of establishing an above-mentioned partition data simultaneously is more than 10 bits, and the cycle of establishing above-mentioned clock signal is 500 μ s, the about 500 μ s of host CPU return the energy mode of operation, so carry out in the such above-mentioned communication format of interrupt request at the shortest per approximately 520.8 μ s of Serial Control portion, also can carry out data transfer process efficiently without dma controller.

Fig. 1 is the block scheme of expression one embodiment of the invention;

Fig. 2 is the process flow diagram of the same operation of explanation;

Fig. 3 is the process flow diagram of the same operation of explanation;

Fig. 4 is the process flow diagram of the same operation of explanation;

Fig. 5 is the process flow diagram of the same operation of explanation;

Fig. 6 is the block scheme of the existing example of expression;

Fig. 7 is the process flow diagram of the same operation of explanation.

The optimal morphology that carries out an invention

Below, explain embodiments of the invention with reference to accompanying drawing.

Fig. 1 is the block scheme of programmable controller basic structure of expression present embodiment, has the executive routine host CPU 1 that row operation handles of going forward side by side, carry out functioning in an acting capacity of according to the instruction of host CPU 1 in the calculation process dedicated cpu 2 of specific calculation process at host CPU 1, in the data communication of carrying out with external unit, on the above-mentioned host CPU 1 of a partition data that receives each regulation, carry out the Serial Control portion 3 of interrupt request, produce the timing portion 4 of the clock signal of host CPU 1 operation usefulness, transmit control and storage from memory of data portion 5 that external unit receives with the host CPU 1 of interrupt request by accepting above-mentioned Serial Control portion 3.Also have, these each ones are connected with dedicated cpu 2 with host CPU 1 respectively by address data bus 6.And, the interrupt request singal of the clock signal of timing portion 4 and Serial Control portion 3 is transfused to interrupt control portion 7, the specified bit of the register that interrupt control portion 7 is all changes according to clock signal and interrupt request singal, so host CPU 1 can be discerned the interrupt request of timing portion 4 and Serial Control portion 3 severally.

Dedicated cpu 2 is as existing example is illustrated, be to replace host CPU 1 to carry out specific calculation process, host CPU 1 becomes hold mode (shut-down operation state) during dedicated cpu 2 carries out calculation process, when the calculation process of dedicated cpu 2 finishes or dedicated cpu 2 read the occasion of the order that will carry out by host CPU 1 such must carry out the calculation process of certain operations beyond handling the time, or when the outside input stops request signal, remove the hold mode of CPU1.Also have, when host CPU 1 is in hold mode, do not accept the interrupt request of interrupt control portion 7.

The memory section 5 that is connected with address bus 6 is made of the semiconductor memory of such the writing of for example RAM/cancellation.As described later, do not possess dma controller in the occasion of present embodiment, the data between Serial Control portion 3 and the memory section 5 transmit by host CPU 1 control.

Serial Control portion 3 and the external unit of programming device etc. between carry out data communication, the impact damper that 1 byte is for example arranged, in impact damper, the data of every reception 1 byte are carried out interrupt request, the data of per 1 bit are exported to address data bus 6, or extract the data of per 1 bit.

Timing portion 4 produces the clock signal of being made up of the pulse signal of some cycles, exports to interrupt control portion 7 and dedicated cpu 2.Here, the clock signal that inputs to dedicated cpu 2 becomes and stops request signal, and for example clock signal dedicated cpu 2 when each rising of H level interrupts executory calculation process, removes the hold mode of host CPU 1 simultaneously.In addition, by at interrupt control portion 7 input clock signals, carry out the interrupt request (below be called " regularly interrupt request ") of timing portion 4 at the host CPU 1 of having removed hold mode.But aforesaid operations is an occasion of being carried out specific calculation process by dedicated cpu 2, in dedicated cpu 2 inoperation and host CPU 1 is carried out the occasion of calculation process, only carries out the timing interrupt request.

Below, with reference to the process flow diagram of Fig. 2～Fig. 5, the operation of present embodiment is described.

At first, Fig. 2 is all process flow diagrams of operation of expression, identical with the generality operation of programmable controller, after energized is carried out the initialization of various hardware and parameter etc., carry out the execution of user program, I/O regeneration, calculation process, communications command repeatedly and handle.

Fig. 3 is illustrated in the calculation process of host CPU 1 the host CPU 1 when carrying out the specific calculation process of must ultrahigh-speed handling by dedicated cpu 2 and the process flow diagram of operation separately of dedicated cpu 2.At first, host CPU 1 is set various parameters at the register of dedicated cpu 2 when reading the order of being handled by CPU2 (コマ Application De), makes dedicated cpu 2 startings.

In addition, export the HOLD signal from the dedicated cpu 2 of starting to host CPU 1, host CPU 1 becomes hold mode.As the response of accepting the HOLD signal, export ack signals (acknowledge signal) to dedicated cpu 2 from host CPU 1.And, dedicated cpu 2 just carries out calculation process when the order of reading is the order that can carry out, interrupt calculation process in the occasion of reading inexecutable order (for example order that will carry out by host CPU 1), remove the hold mode of host CPU 1, make control return host CPU 1.Carry out in the calculation process as the outside clock signal that stops request signal or timing portion 4 of input at dedicated cpu 2, similarly remove the hold mode of host CPU 1.On the contrary,, proceeding specific calculation process until end during this period, finishing the hold mode that host CPU 1 is removed in the back, making control return host CPU 1 as not defeated request signal and the clock signal of stopping.

In contrast, host CPU 1 is investigated the reason of its releasing when removing hold mode, if the fill order of host CPU 1 is then carried out this calculation process.At this moment, host CPU 1 investigation have or not the timing interrupt request of interrupt control portion 7 or the interrupt request of serialization controller 3 (below, this is called " data transmission interrupt request "), carry out various programs according to interrupt request, i.e. timing interrupt handling routine or data transfer process program.And the processing of each program by restarting dedicated cpu 2, is proceeded dedicated cpu 2 discontinued calculation process after finishing.

Fig. 4 is regularly the process flow diagram of interrupt handling routine.Host CPU 1 makes auxiliary counter (not shown) decrement, if this count value is not zero, then the stop timing Interrupt Process is returned original processing.In addition, if the count value of auxiliary counter is zero, when auxiliary counter is set initial value (=5), make 2.5ms counter (not shown) increment after, the stop timing interrupt handling routine returns original processing.Promptly, in the present embodiment owing to set the clock signal period of timing portion 5 for 500 μ s, so host CPU 1 is synchronously carried out regularly interrupt handling routine with the cycle (500 μ s) of clock signal, the count value that in carrying out timing interrupt handling routine each time, makes auxiliary counter from initial value (=5) decrement until 0.Its result, host CPU 1 carries out the timing of 500 μ s * 5=2.5ms, and energy and existing example are similarly carried out the mensuration in the elapsed time of 10ms timer command with 1/4th precision.

Fig. 5 is the process flow diagram of data transfer process program.Host CPU 1 in the data transfer process program branches, is read the directive of also reading reception buffer (not shown) in Serial Control portion 3 reception data on 1 byte ground when having data to transmit interrupt request.This directive is represented the address of storer 5, and host CPU 1 receives data by adjusting on the address of the directive of reading, will receive data storage at storage part 5.Then, prepare the next adjustment that receives data, host CPU 1 makes the data transfer process finished program behind the directive increment that receives, and returns original processing.

Here, the form that externally carries out data communication between equipment and the Serial Control portion 3 for example is the start-stop synchronous communication, with start bit be long 8 bits of 1 bit, data, odd even to test odd number, position of rest be that the communication speed of 1 bit format is 19,200bps.At this moment, Serial Control portion 3 is from receiving data of cutting apart to the time interval of receiving next data of cutting apart, and promptly the time of origin from the data interruption request of Serial Control portion 3 becomes 1 ÷, 19,200 * (1+8+1+1)=572.9 μ s at interval.In the occasion of other form (start bit is that 1 bit, data length are that 7 bits, parity checking odd number, position of rest are 1 bits), this time interval becomes 1 ÷, 19,200 * (1+7+1+1)=520.8 μ s.

Therefore, in communication speed is 19, the data that 200bps, is cut apart are occasions of the above communication form of 10 bits, can not carry out in the short time interval than 520.8 μ s from the data interruption request of Serial Control portion 3, so if make host CPU 1 return operable state than this short time interval, do not use dma controller even do not resemble the existing example, the data that host CPU 1 also can be controlled between Serial Control portion 3 and the memory section 5 transmit, do not use the dma controller of high price, just can reduce cost.Therefore, present embodiment is set the cycle of the clock signal of timing portion 4 for 500 μ s, with the request signal that stops of clock signal as dedicated cpu 2.Because the cycle of establishing clock signal is 500 μ s, it is to measure the approximate number of gate time (2.5ms) of 2.5ms counter in elapsed time of 10ms timer command and the mensuration that existing example is similarly carried out the timer command elapsed time that the cycle of clock signal becomes.

As described above, receiving the needed time of reception of data of cutting apart at present embodiment by Serial Control portion 3 is below (520.8 μ s), and because the cycle of clock signal that will timing portion 4 is set at approximate number (highest common factor) the i.e. 500 μ s of timing (2.5ms) of the timer command of host CPU 1 execution, even so in the calculation process that dedicated cpu 2 causes is carried out, host CPU 1 returns to the energy mode of operation from hold mode with the cycle synchronisation ground of clock signal, during this if the data interruption request of Serial Control portion 3 is arranged, then just carry out data processor, can transmit to memory section 5 from Serial Control portion 3 receiving data.That is, not using dma controller when reducing cost, the interruption times of software is made as minimum, so also can reduce the load of host CPU 1.

The possibility of industrial utilization

The invention of claim 1 is as noted above, has the performing a programme host CPU that row operation processes of going forward side by side , and in the calculation process that above-mentioned host CPU carries out, function in an acting capacity of specific computing according to the instruction of above-mentioned host CPU The dedicated cpu of processing, above-mentioned dedicated cpu is carrying out making above-mentioned host CPU during the above-mentioned specific calculation process Be in operation stop condition, when above-mentioned specific calculation process finishes, maybe must carry out above-mentioned specific Calculation process beyond the calculation process or have from the outside input stop request signal the time, just should remove the master The operation stop condition of CPU, in the programmable controller that forms thus, also have carry out and outside Enterprising at the above-mentioned host CPU of a partition data that receives each regulation in the time of the data communication of section's equipment The serialization controller of row interrupt requests and in the clock signal that produces above-mentioned host CPU operation usefulness This clock signal is exported to the timing section of above-mentioned dedicated cpu and logical as the above-mentioned request signal that stops The above-mentioned host CPU of crossing the interrupt requests of accepting above-mentioned Serial Control section carry out transfer control and storage from outside The data storage section that section equipment receives, with above-mentioned Serial Control section in the above-mentioned partition data of reception institute The following value of the time of reception of wanting is set the cycle of above-mentioned clock signal, so in the specific fortune of dedicated cpu Calculate the operation stop condition of also removing host CPU in the execution of processing with above-mentioned clock signal synchronization ground. And And, the time interval that produces the interrupt requests of coming from Serial Control section namely by Serial Control section than reception The short time interval of the desired time of reception of an above-mentioned partition data makes host CPU become energy mode of operation, energy Transmitted by the data between host CPU control Serial Control section and the storage part, do not resemble and use height the existing example The dma controller of valency also can be at Serial Control section and memory in the calculation process of dedicated cpu is carried out Carry out data between the section and transmit, have the effect that treatment effeciency does not descend and cost is low that the data of making transmit.

The invention of claim 2 is established at the approximate number of the timing of the timer command of above-mentioned host CPU execution In the cycle of fixed above-mentioned clock signal, institute is so that host CPU becomes cycle of energy mode of operation and timer command The cycle of timing is consistent, has the effect that can carry out easily with the precision of regulation this timing.

The invention of claim 3 is set as 19200 with the communication speed of the data communication of above-mentioned Serial Control section Bps the time establish an above-mentioned partition data data length be more than 10 bits, and establish above-mentioned clock The cycle of signal is 500 μ s, and the approximately per 500 μ s of host CPU return the energy mode of operation, so in Serial Control The shortest approximately per 520.8 μ s of section carry out having without DMA also in the such above-mentioned communication format of interrupt requests Can carry out efficiently the effect of data transfer process.

Claims

1. programmable controller, the host CPU that has executive routine and handle, with the dedicated cpu of functioning in an acting capacity of specific calculation process in the calculation process of carrying out according to the instruction of above-mentioned host CPU at above-mentioned host CPU, above-mentioned dedicated cpu makes above-mentioned host CPU be in operation stop condition during carrying out above-mentioned specific calculation process, in the time of when above-mentioned specific calculation process finishes, maybe must carrying out the calculation process beyond the above-mentioned specific calculation process or have when the outside input stops request signal, just should remove the operation stop condition of above-mentioned host CPU, it is characterized in that, also has the Serial Control portion that in the data communication of carrying out with external unit, on the above-mentioned host CPU of a partition data that receives each regulation, carries out interrupt request, with in the clock signal that produces above-mentioned host CPU operation usefulness, this clock signal is stopped the timing portion that request signal is exported to above-mentioned dedicated cpu as above-mentioned, transmit control and storage from the memory of data portion that external unit receives with the above-mentioned host CPU of interrupt request by accepting above-mentioned Serial Control portion, set the cycle of above-mentioned clock signal with the value of above-mentioned Serial Control portion below the desired time of reception of the above-mentioned partition data of reception.

2. programmable controller as claimed in claim 1 is characterized in that, sets the cycle of above-mentioned clock signal on the approximate number of the timing of the timer command that above-mentioned host CPU is carried out.

3. programmable controller as claimed in claim 2, it is characterized in that, be made as 19 in communication speed with the data communication of above-mentioned Serial Control portion, data length with above-mentioned one data of cutting apart in the time of 200 bps is made as more than 10 bits, and the cycle of above-mentioned clock signal is made as about 500 μ s.