KR19990004231A - Memory access device in computer system using PI6 bus - Google Patents

Abstract

The present invention stores the line data for the next address through the temp buffer in advance and transmits the data to the P6 bus, thereby reducing the memory access time and improving the I / O performance of the system. It is about.

In the related art, holding the P6 bus without using the P6 bus at all during the memory waiting time not only decreases the utilization rate of the P6 bus but also causes a significant decrease in I / O performance when the memory waiting time is long.

In order to solve this problem, the present invention relates to a temp buffer 106 which prefetches and stores the next cache line data from the memory unit 104 in the cache line read operation generated by the I / O agent 102 on the P6 bus. It consists of a memory controller 103 which sends data stored in the temp buffer 106 onto the P6 bus in the next cache line read request.

Description

Memory access device in computer system using PI6 bus

The present invention relates to a computer system using a P6 bus, and in particular, in the Cache Line Read operation generated by an input / output agent on the P6 bus, the next cache line data is previously obtained from the memory. Memory access devices in a computer system using the P6 bus, which are stored in the Temp Buffer and sent on the P6 bus on the next cache line read request to improve system I / O performance by reducing memory access time. It is about.

In general, the Intel PCI Bridge is commercially available as an I / O agent on the P6 bus in a computer system using the P6 bus, and I / O operations are performed in blocks.

However, conventionally, the next cache line read operation cannot be requested on the P6 bus until the cache line read operation currently generated when the cache line read is performed on the P6 bus for processing block I / O occurring on the PCI bus is completed. .

Therefore, holding the P6 bus unused during the memory latency (the time from the address sent until the data is transmitted) not only reduces the utilization of the P6 bus but also increases the memory latency. There was a problem that / O performance is significantly reduced.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and in the cache line read operation generated by the I / O agent on the P6 bus, the next cache line data is previously taken from the memory and stored in the temp buffer and the address thereof When the cache line read request for the next cache line address is maintained, the data stored in the temp buffer is sent on the P6 bus, and the next cache line data is prefetched from the memory and stored in the temp buffer as well as maintaining the address thereof. By doing so, the time required for memory access is significantly reduced, thereby increasing the utilization of the P6 bus, and reducing the memory latency, thereby improving the I / O performance of the system and improving the overall performance.

In order to achieve the above object, the present invention provides a method for requesting cache line data on a P6 bus when a multi-line read operation is requested through a PCI bus to process a block I / O read in a PCI device. PCI I / O Agent; A memory controller which transmits the line data onto the P6 bus by causing the requested cache line data and the next cache line data to be output from the memory unit when cache line data is requested through the PCI bus; When cache line data is requested through the PCI bus, the next cache line data is stored in a ready state and then maintained in a valid state, and when the next cache line data is requested on the P6 bus, the stored line data is stored. It characterized in that the configuration as a temp buffer for transmitting to the memory controller.

1 is a block diagram of a memory access device in a computer system using a P6 bus according to the present invention;

Explanation of symbols for the main parts of the drawings

101: PCI device 102: PCI I / O agent

103: memory controller 104: memory unit

105: buffer control logic 106: temp buffer

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a memory access device in a computer system using a P6 bus according to the present invention, in which a multi-line read operation is requested through a PCI bus to process block I / O reads in the PCI device 101. PCI I / O agent 102, which makes the BPRI # signal active, generates memory line read operations on the P6 bus, and requests cache line data to memory controller 103. When the agent 102 detects that a task generated on the P6 bus is a memory line read operation and that the BPRI # signal is active, the temp buffer 106 remains ready to store the next cache line data. When the buffer control logic 105 and the cache line data are requested, the requested cache line data and the next cache line data are output from the memory unit 104 so that the line data is P6. The memory controller 103 which transmits on the bus and the memory unit 104 output the next cache line data after storing it and maintains it in a valid state. When the next cache line data is requested on the P6 bus, the stored line data is stored in the memory. It consists of the temp buffer 106 which transmits to the controller 103. As shown in FIG.

Referring to Figure 1 attached to the operation and effect of the present invention configured as described above is as follows.

First, the PCI device 101 requests a multi-line read operation from the PCI I / O agent 102 using the PCI bus to process block I / O reads.

In this case, the I / O operation is performed in units of blocks. Although the block size is somewhat different depending on the system, the cache line read operation must be performed 16 times because it is about 152 bytes and the cache line size is 32 bytes.

The PCI I / O agent 102 then pulls the BPRI # signal low to process the job and then generates a memory line read (hereinafter referred to as MLR) operation on the P6 bus to generate cache line data. (Assuming this address is AA.)

Next, the buffer control logic 105 prepares the state of the temp buffer 106 if the operation occurring on the P6 bus is MLR and the BPRI # signal is low and the next line address (AA + 32) of the currently requested address. Will be saved.

The memory controller 103 then sends the requested address AA and the next address AA + 32 to the memory unit 104.

Thus, when the line data for the AA address is transferred to the memory controller 103 in the memory unit 104, and the line data for the AA + 32 address is transmitted in succession, the buffer control logic 105 sends the temp buffer ( After storing in 106, the state of the temp buffer 106 is kept valid.

Thereafter, the memory controller 103 transmits the line data for the AA address to the PCI I / O agent 102, and the PCI I / O agent 102 has completed the requested operation, so that the next line address AA + 32 is used. MLR work on the P6 bus. At this time, the BPRI # signal remains low until the multi-line read operation is completed.

Next, the buffer control logic 105 checks the state of the temp buffer 106 and the address stored in the buffer control logic 105 and the address currently requested on the P6 bus since the BPRI # signal is low and the MLR operation is detected. do.

In addition, the memory controller 103 sends the requested address AA + 32 and the next address AA + 64 to the memory unit 104.

Then, the buffer control logic 105 determines that the state of the temp buffer 106 is valid and the address (AA + 32) previously stored and the requested address (AA + 32) on the current P6 bus are the same. The line data in the temp buffer 106 is transferred to the memory controller 103 so that the line data is transferred to the P6 bus.

At this time, when the line data in the temp buffer 106 is transferred to the memory controller 103, the temp buffer 106 is in a ready state.

Then, the line data for the AA + 32 address requested from the memory controller 103 is transmitted from the memory unit 104 to the memory controller 103, which is invalidated because it has already been transmitted through the temp buffer 106.

On the other hand, the line data for the AA + 64 address and the line data for the AA + 64 address which are transmitted in succession are stored in the temp buffer 106, and the temp buffer 106 is kept in a valid state.

That is, the above operation is continuously repeated until the multi-line read is completed.

As described above, the present invention stores the line data for the next address in advance through the temp buffer and transfers the data to the P6 bus, thereby significantly reducing the time required for memory access, thereby improving the utilization of the P6 bus. By reducing memory latency, the system's I / O performance is improved.

Claims (1)

When a multiple-line read operation is requested through the PCI bus to process block input / output (I / O) reads from the PCI device 101, the cache line data is requested on the P6 bus. When cache line data is requested through the PCI I / O agent 102 and the PCI bus, the requested cache line data and the next cache line data are output from the memory unit 104 to transmit the line data onto the P6 bus. When the cache line data is requested through the memory control channel 103 and the PCI bus, the next cache line data is stored in a ready state and then maintained in a valid state after being stored in a valid state. When the cache line data is requested, the P6 bus is configured to include a temp buffer 106 that transmits the stored line data to the memory controller 103. Memory access device in computer system.