CN117220817A - Method and system for time synchronization monitoring of multi-core processor - Google Patents
Method and system for time synchronization monitoring of multi-core processor Download PDFInfo
- Publication number
- CN117220817A CN117220817A CN202311471402.5A CN202311471402A CN117220817A CN 117220817 A CN117220817 A CN 117220817A CN 202311471402 A CN202311471402 A CN 202311471402A CN 117220817 A CN117220817 A CN 117220817A
- Authority
- CN
- China
- Prior art keywords
- ntp
- monitoring
- core
- time
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012544 monitoring process Methods 0.000 title claims abstract description 132
- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000006870 function Effects 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 8
- 238000012545 processing Methods 0.000 description 3
- 238000012806 monitoring device Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002255 enzymatic effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Landscapes
- Computer And Data Communications (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention discloses a time synchronization monitoring method and a time synchronization monitoring system for a multi-core processor, which intercept NTP monitoring request messages and reply messages in bare core interruption, and re-mark the messages by matching with a nanosecond timer of an FPGA, thereby improving the accuracy of the messages, avoiding the influence of links such as the load level of an operation core of the NTP monitoring application and protocol stack buffer, and finally realizing the purpose of improving the accuracy of the NTP synchronization monitoring.
Description
Technical Field
The invention belongs to the technical field of time synchronization of power systems, and particularly relates to a method and a system for time synchronization monitoring of a multi-core processor.
Background
NTP (Network Time Procotol, network time protocol) is a protocol used to synchronize computer time, which allows a computer to synchronize its server or clock source (e.g., quartz clock, GPS, etc.), and has a number of applications in power systems. Besides the application of time synchronization, the identifier is fixed as "TSSM" by using Reference Identifier field of the NTP message, and the NTP message can be used for the purpose of time synchronization monitoring of the power system. In the power system, the number of running devices, equipment, servers and the like is more, so that the load of a time synchronization monitoring task is higher, and meanwhile, because the NTP protocol works at an application layer of an OSI model, the accuracy of a time stamp can be influenced by the system load, a protocol stack buffer and a receiving and transmitting packet interrupt time sequence, so that the monitoring precision is lower.
The following schemes are adopted for optimizing the NTP precision at present:
the patent CN115801170A discloses a clock timing method, a control device, a storage medium and a system, wherein the scheme adopts a multi-core CPU, selects two CPU cores with the lowest load, and is respectively used for binding a packet receiving interrupt thread and a packet sending thread of a network card, so that the problem of unstable time caused by packet sending delay caused by the interruption of the packet receiving interrupt flow in the execution process of the packet sending flow is avoided, and the timing precision is improved. This scheme has a limit on the load of the CPU core, and may not fully achieve the desired effect at high loads of the CPU full core.
The patent CN216526795U discloses an interface circuit of a time service equipment network time precision monitoring method, and the scheme utilizes a master control FPGA to realize the NTP protocol stack function, and cooperates with a master control MCU to realize hardware time mark writing and improve the monitoring precision. The scheme can realize higher-precision time scale writing, but because the FPGA is required to realize the function of a protocol stack, the number of logic gates of the FPGA is higher, the expansibility of the protocol stack is limited, and the cost is increased when the FPGA device is selected.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a method and a system for time synchronization monitoring of a multi-core processor, which can perform high-precision NTP time synchronization monitoring on a large number of devices.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a method for time synchronization monitoring of a multi-core processor, comprising:
enabling the multi-core CPU to operate in an AMP mode, wherein two cores are selected to operate as a bare core and a system core respectively; the bare core is communicated with the FPGA and operates in an interrupt mode, and the system core runs NTP monitoring application and has a protocol stack function; sharing content between different cores;
when the message is sent, the NTP monitoring application sends an NTP monitoring request message, the bare core acquires and monitors the Ethernet packet through the shared content, intercepts the NTP monitoring request message, updates the sending time mark of the NTP monitoring request message by using the current time maintained by the bare core and sends the sending time mark to the FPGA;
when the message is received, the expansion network port of the FPGA receives the Ethernet packets, records the nanosecond time t0 received by each Ethernet packet, packages the nanosecond time and the Ethernet packets and transmits the packaged nanosecond time and the packaged Ethernet packets to the bare core; the bare core monitors the received Ethernet packet, intercepts the NTP monitoring reply message, reads the nanosecond time t1 from the FPGA, pushes back the complete time t1-t0, updates the receiving time mark of the NTP monitoring reply message by the complete time after pushing back, and then sends the NTP monitoring reply message to the system core; the NTP monitoring application calculates the monitored time difference using the relevant fields in the received NTP monitoring reply message.
As a preferred embodiment, the bare core communicates with the FPGA over a gigabit ethernet.
As a preferred embodiment, the NTP monitoring application sends an NTP monitoring request packet, and after passing through the system core protocol stack, sends an ethernet packet to the bare core through the shared memory.
As a preferred embodiment, the current time maintained by the bare core is replaced with the Transmit Timestamp field in the NTP monitoring request message, so as to update the transmission time stamp of the NTP monitoring request message.
As a preferred embodiment, after updating the transmission time stamp of the NTP monitoring request message, the UDP checksum of the NTP monitoring request message is recalculated and filled into the message.
As a preferred embodiment, the complete time after the push-back is filled in the Reference Timestamp field of the NTP monitoring reply message, so as to update the reception time stamp of the NTP monitoring reply message.
As a preferred embodiment, after updating the received time stamp of the NTP monitoring reply message, the UDP checksum of the NTP monitoring reply message is recalculated and filled into the message.
As a preferred implementation, the NTP monitoring reply message after updating the receiving time mark is transmitted to the system core through the shared memory, and is transmitted to the NTP monitoring application after being processed by the protocol stack.
As a preferred embodiment, the NTP monitoring application calculates the monitored time difference based on the following formula for the relevant fields in the NTP monitoring reply message received:
in the method, in the process of the invention,T0 is the Origin Timestamp field Timestamp,T1 is the Receive Timestamp field time stamp,T2 is the Transmit Timestamp field time stamp,T3 is the Reference Timestamp field time stamp.
Another object of the present invention is to provide a time synchronization monitoring system of a multi-core processor, including an FPGA module, an embedded multi-core CPU module, and a network interface module;
the FPGA module maintains a nanosecond timer, the embedded multi-core CPU module operates in an AMP mode, and any two cores in the embedded multi-core function as a bare core and a system core respectively; the bare core is communicated with the FPGA and operates in an interrupt mode, and the system core runs NTP monitoring application and has a protocol stack function; sharing content between different cores;
when the message is sent, the NTP monitoring application sends an NTP monitoring request message, the bare core acquires and monitors the Ethernet packet through the shared content, intercepts the NTP monitoring request message, updates the sending time mark of the NTP monitoring request message by using the current time maintained by the bare core and sends the sending time mark to the FPGA;
when the message is received, the expansion network port of the FPGA receives the Ethernet packets, records the nanosecond time t0 received by each Ethernet packet, packages the nanosecond time and the Ethernet packets and transmits the packaged nanosecond time and the packaged Ethernet packets to the bare core; the bare core monitors the received Ethernet packet, intercepts the NTP monitoring reply message, acquires nanosecond time t1 read from the FPGA, pushes back the complete time t1-t0, updates the receiving time mark of the NTP monitoring reply message by the complete time after pushing back, and then sends the NTP monitoring reply message to the system core; the NTP monitoring application calculates the monitored time difference using the relevant fields in the received NTP monitoring reply message. The two cores respectively operate as a bare core and a system core; the bare core is communicated with the FPGA, and the system core runs NTP monitoring application and has a protocol stack function; sharing content between different cores;
after the NTP monitoring application sends an NTP monitoring reply message, the bare core acquires and monitors the Ethernet packet through the shared content, intercepts the NTP monitoring reply message, updates the sending time mark of the NTP monitoring reply message by using the current time maintained by the bare core, and sends the sending time mark to the FPGA.
The invention provides a method and a system for time synchronization monitoring of a multi-core processor, which can realize high-precision NTP time monitoring. The FPGA does not need to realize a network protocol stack, and the resource requirement of a logic gate for device type selection is reduced. The system core in the multi-core CPU runs the operating system, can conveniently realize the expansion of the protocol stack, and has smaller limitation on hardware resources. The bare core runs in an interrupt mode, and meanwhile, the nanosecond timer maintained by the FPGA is read, so that the time precision is high. The method has the advantages that the time marks of the monitoring request message and the reply message are processed by the bare core, the influence of the CPU core load and the protocol stack buffer memory where the NTP monitoring application is located can be effectively eliminated, the accuracy of the time marks of the monitoring request message sending and the reply message receiving is greatly improved, the number of monitoring devices can be further improved, and the accuracy and the performance of NTP monitoring are finally improved.
Drawings
FIG. 1 is a diagram of a method of the present invention.
Fig. 2 is a flow chart of a monitoring request message transmission process.
Fig. 3 is a flow chart of a process for receiving a monitoring reply message.
Description of the embodiments
The technical scheme of the invention is further described below with reference to the attached drawings and specific embodiments.
In the examples, the complete time refers to the year, month, day, minute, second, and microsecond below second; the nanosecond time is recorded by a nanosecond timer maintained by the FPGA and is a part of the complete time which is accurate to nanoseconds.
The time synchronization monitoring device comprises an FPGA module, an embedded multi-core CPU module and a network interface module.
The FPGA module realizes the expansion of a network interface, the maintenance of a nanosecond timer and the suppression of a network storm. The nanosecond timer is realized by FPGA programming, is accurate time below second, and can be updated in real time and read by the bare core.
The embedded Multi-core CPU module uses an AMP (enzymatic Multi-processing) mode, optionally with two cores. One core operates as a bare core, communicates with an FPGA through GMAC (gigabit Ethernet), and is responsible for time management of the whole device and message interception and time scale updating of NTP monitoring. The other core runs an operating system (e.g., the winged SylixOS) as a system core with complete protocol stack functionality. The NTP monitoring application runs on the system core. And the shared memory is used among different cores to realize high-speed and reliable inter-core interaction.
The network interface module realizes network physical connection with external equipment.
In this embodiment, the format of the NTP monitoring message (including the monitoring reply message and the monitoring request message) is the same as that of the NTP message, except that a "TSSM" character is filled in the Reference Identifier field, which indicates that the message is used for monitoring clock skew.
The NTP monitoring application at least realizes the calculation of clock difference of NTP monitoring, and can also increase the NTP time service function, or only has the clock difference monitoring function, and the NTP time service is completed in other modules.
The time synchronization monitoring method of the invention respectively carries out time correction on the message sending flow and the message receiving flow.
The request message sending processing flow is as follows:
(1) The NTP monitoring application sends an NTP monitoring request message, and after passing through a system core protocol stack, sends an Ethernet packet to the bare core through the shared memory;
(2) The bare core monitors an Ethernet packet to be sent, and intercepts an NTP monitoring request message when the message is screened;
(3) Acquiring the current Time Time0 maintained by the bare core, and filling the current Time as a transmission Time mark into an NTP monitoring request message (replacing the transmission Time in the original message, namely Transmit Timestamp field);
re-calculating UDP checksum of the NTP monitoring request message and filling the message;
(4) And transmitting the NTP monitoring request message with the modified transmission time mark and UDP checksum to the FPGA through GMAC, and transmitting the message from an expanded network port of the FPGA.
The reply message receiving processing flow is as follows:
(1) The FPGA expansion network port receives the Ethernet packets, the FPGA records the nanosecond moment received by each Ethernet packet, and the nanosecond moment and the Ethernet packet content are packaged and then transmitted to the bare core through GMAC;
(2) The bare core monitors the received Ethernet packet, and intercepts the NTP monitoring reply message when the message is screened;
(3) Acquiring nanosecond Time t0 recorded by the FPGA, reading the nanosecond Time t1 from the FPGA, reading the complete Time Time1 at the moment, and pushing the Time1 back forward (t 1-t 0) for nanoseconds, namely receiving the accurate Time Time2 of the NTP monitoring reply message, and replacing the original reply message receiving Time;
(4) Filling Time2 into Reference Timestamp field of NTP monitoring reply message (this field is not used in NTP monitoring), recalculating UDP check of monitoring reply message and filling message;
(5) The NTP monitoring reply message modified with the received time mark and UDP checksum is transmitted to a system core through a shared memory, and is transmitted to an NTP monitoring application after being processed by an operating system protocol stack;
(6) The NTP monitoring application parses the received reply message, the Origin Timestamp field is a Timestamp T0 (Transmit Timestamp field of the device 1 that sends the NTP monitoring request message), the Receive Timestamp field is a Timestamp T1 (time when the device 2 receives the NTP monitoring request message sent by the device 1), the Transmit Timestamp field is a Timestamp T2 (time when the NTP monitoring reply message is sent), and the Reference Timestamp field is a Timestamp T3;
(7) According to the formulaThe monitored time difference is calculated.
Claims (10)
1. A method for time synchronization monitoring of a multi-core processor, comprising:
enabling the multi-core CPU to operate in an AMP mode, wherein two cores are selected to operate as a bare core and a system core respectively; the bare core is communicated with the FPGA and operates in an interrupt mode, and the system core runs NTP monitoring application and has a protocol stack function; sharing content between different cores;
when the message is sent, the NTP monitoring application sends an NTP monitoring request message, the bare core acquires and monitors the Ethernet packet through the shared content, intercepts the NTP monitoring request message, updates the sending time mark of the NTP monitoring request message by using the current time maintained by the bare core and sends the sending time mark to the FPGA;
when the message is received, the expansion network port of the FPGA receives the Ethernet packets, records the nanosecond time t0 received by each Ethernet packet, packages the nanosecond time and the Ethernet packets and transmits the packaged nanosecond time and the packaged Ethernet packets to the bare core; the bare core monitors the received Ethernet packet, intercepts the NTP monitoring reply message, reads the nanosecond time t1 from the FPGA, pushes back the complete time t1-t0, updates the receiving time mark of the NTP monitoring reply message by the complete time after pushing back, and then sends the NTP monitoring reply message to the system core; the NTP monitoring application calculates the monitored time difference using the relevant fields in the received NTP monitoring reply message.
2. The method of claim 1, wherein the bare core communicates with the FPGA over a gigabit ethernet.
3. The method of claim 1 wherein the NTP monitoring application sends the NTP monitoring request message, after passing through a system core protocol stack, to send the ethernet packet to the bare core via the shared memory.
4. The method of claim 1 wherein the current time maintained by the bare core is substituted for a Transmit Timestamp field in the NTP monitoring request message to update the transmission time stamp of the NTP monitoring request message.
5. The method of claim 1 wherein after updating the transmission time stamp of the NTP monitoring request message, the UDP checksum of the NTP monitoring request message is recalculated and filled in.
6. The method of claim 1 wherein the pushed back complete time is filled into a Reference Timestamp field of the NTP monitoring reply message to update a receive timestamp of the NTP monitoring reply message.
7. The method of claim 1 wherein after updating the receive time stamp of the NTP monitoring reply message, the UDP checksum of the NTP monitoring reply message is recalculated and filled in.
8. The method of claim 1 wherein the NTP monitoring reply message after updating the receive time stamp is transmitted to the system core via the shared memory, processed by the protocol stack, and transmitted to the NTP monitoring application.
9. The method of claim 1 wherein the NTP monitoring application receives relevant fields in the NTP monitoring reply message and calculates the monitored time difference based on the following equation:
；
in the method, in the process of the invention,T0 is the Origin Timestamp field Timestamp,T1 is the Receive Timestamp field time stamp,T2 is the Transmit Timestamp field time stamp,T3 is the Reference Timestamp field time stamp.
10. The time synchronization monitoring system of the multi-core processor is characterized by comprising an FPGA module, an embedded multi-core CPU module and a network interface module;
the FPGA module maintains a nanosecond timer, the embedded multi-core CPU module operates in an AMP mode, and any two cores in the embedded multi-core function as a bare core and a system core respectively; the bare core is communicated with the FPGA and operates in an interrupt mode, and the system core runs NTP monitoring application and has a protocol stack function; sharing content between different cores;
when the message is sent, the NTP monitoring application sends an NTP monitoring request message, the bare core acquires and monitors the Ethernet packet through the shared content, intercepts the NTP monitoring request message, updates the sending time mark of the NTP monitoring request message by using the current time maintained by the bare core and sends the sending time mark to the FPGA;
when the message is received, the expansion network port of the FPGA receives the Ethernet packets, records the nanosecond time t0 received by each Ethernet packet, packages the nanosecond time and the Ethernet packets and transmits the packaged nanosecond time and the packaged Ethernet packets to the bare core; the bare core monitors the received Ethernet packet, intercepts the NTP monitoring reply message, acquires nanosecond time t1 read from the FPGA, pushes back the complete time t1-t0, updates the receiving time mark of the NTP monitoring reply message by the complete time after pushing back, and then sends the NTP monitoring reply message to the system core; the NTP monitoring application calculates the monitored time difference by utilizing the relevant fields in the received NTP monitoring reply message; the two cores respectively operate as a bare core and a system core; the bare core is communicated with the FPGA, and the system core runs NTP monitoring application and has a protocol stack function; sharing content between different cores;
after the NTP monitoring application sends an NTP monitoring reply message, the bare core acquires and monitors the Ethernet packet through the shared content, intercepts the NTP monitoring reply message, updates the sending time mark of the NTP monitoring reply message by using the current time maintained by the bare core, and sends the sending time mark to the FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311471402.5A CN117220817B (en) | 2023-11-07 | 2023-11-07 | Method and system for time synchronization monitoring of multi-core processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311471402.5A CN117220817B (en) | 2023-11-07 | 2023-11-07 | Method and system for time synchronization monitoring of multi-core processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117220817A true CN117220817A (en) | 2023-12-12 |
| CN117220817B CN117220817B (en) | 2024-01-05 |
Family
ID=89039272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311471402.5A Active CN117220817B (en) | 2023-11-07 | 2023-11-07 | Method and system for time synchronization monitoring of multi-core processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117220817B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949129A (en) * | 2006-11-27 | 2007-04-18 | 杭州华为三康技术有限公司 | Time synchronizing method and device |
| US20140019793A1 (en) * | 2011-03-29 | 2014-01-16 | Claudio Luis De Amorim | Strictly increasing virtual clock for high-precision timing of programs in multiprocessing systems |
| US8762951B1 (en) * | 2007-03-21 | 2014-06-24 | Oracle America, Inc. | Apparatus and method for profiling system events in a fine grain multi-threaded multi-core processor |
| CN108667547A (en) * | 2018-08-10 | 2018-10-16 | 电信科学技术第五研究所有限公司 | A kind of Network Time Protocol conversion method and system |
| CN111107586A (en) * | 2019-12-24 | 2020-05-05 | 广东机电职业技术学院 | Processing method and system for BBU forward-transmitted data |
| CN111726185A (en) * | 2019-03-20 | 2020-09-29 | 北京米文动力科技有限公司 | Method for synchronizing system clocks of external device and local computing device |
| CN216526795U (en) * | 2021-10-14 | 2022-05-13 | 上海泰坦通信工程有限公司 | Interface circuit of network time precision monitoring method of time-service equipment |
| CN114546680A (en) * | 2022-02-18 | 2022-05-27 | 江苏金智科技股份有限公司 | Method and system for logging bare-core program of relay protection device |
| US20220179446A1 (en) * | 2020-12-03 | 2022-06-09 | Syng, Inc. | Heterogeneous Computing Systems and Methods for Clock Synchronization |
| CN115150223A (en) * | 2022-06-24 | 2022-10-04 | 广西电网有限责任公司电力科学研究院 | Efficient multi-core heterogeneous system data synchronization method |
| CN115801170A (en) * | 2022-11-02 | 2023-03-14 | 北京东土科技股份有限公司 | Clock time synchronization method, control device, storage medium and system |
| CN116346272A (en) * | 2023-01-12 | 2023-06-27 | 中国电子科技集团公司第五十八研究所 | IEEE802.1AS clock synchronization system based on cooperation of PS end and PL end of Xilinx |
| CN116566533A (en) * | 2023-05-24 | 2023-08-08 | 北京无线电计量测试研究所 | Nanosecond NTP network time synchronization method and system |
-
2023
- 2023-11-07 CN CN202311471402.5A patent/CN117220817B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1949129A (en) * | 2006-11-27 | 2007-04-18 | 杭州华为三康技术有限公司 | Time synchronizing method and device |
| US8762951B1 (en) * | 2007-03-21 | 2014-06-24 | Oracle America, Inc. | Apparatus and method for profiling system events in a fine grain multi-threaded multi-core processor |
| US20140019793A1 (en) * | 2011-03-29 | 2014-01-16 | Claudio Luis De Amorim | Strictly increasing virtual clock for high-precision timing of programs in multiprocessing systems |
| CN108667547A (en) * | 2018-08-10 | 2018-10-16 | 电信科学技术第五研究所有限公司 | A kind of Network Time Protocol conversion method and system |
| CN111726185A (en) * | 2019-03-20 | 2020-09-29 | 北京米文动力科技有限公司 | Method for synchronizing system clocks of external device and local computing device |
| CN111107586A (en) * | 2019-12-24 | 2020-05-05 | 广东机电职业技术学院 | Processing method and system for BBU forward-transmitted data |
| US20220179446A1 (en) * | 2020-12-03 | 2022-06-09 | Syng, Inc. | Heterogeneous Computing Systems and Methods for Clock Synchronization |
| CN216526795U (en) * | 2021-10-14 | 2022-05-13 | 上海泰坦通信工程有限公司 | Interface circuit of network time precision monitoring method of time-service equipment |
| CN114546680A (en) * | 2022-02-18 | 2022-05-27 | 江苏金智科技股份有限公司 | Method and system for logging bare-core program of relay protection device |
| CN115150223A (en) * | 2022-06-24 | 2022-10-04 | 广西电网有限责任公司电力科学研究院 | Efficient multi-core heterogeneous system data synchronization method |
| CN115801170A (en) * | 2022-11-02 | 2023-03-14 | 北京东土科技股份有限公司 | Clock time synchronization method, control device, storage medium and system |
| CN116346272A (en) * | 2023-01-12 | 2023-06-27 | 中国电子科技集团公司第五十八研究所 | IEEE802.1AS clock synchronization system based on cooperation of PS end and PL end of Xilinx |
| CN116566533A (en) * | 2023-05-24 | 2023-08-08 | 北京无线电计量测试研究所 | Nanosecond NTP network time synchronization method and system |
Non-Patent Citations (3)
| Title |
|---|
| SHUBHAM KUMAR等: ""A Method and System for Time Synchronization in Nanoseconds Order, by Multi-Core Satellite Receiver Architecture"", 《2023 INTERNATIONAL CONFERENCE ON NETWORK, MULTIMEDIA AND INFORMATION TECHNOLOGY (NMITCON)》 * |
| 刘岩等: ""基于多核处理器的NTP服务器设计"", 《时间频率学报》, vol. 43, no. 1 * |
| 马涛等: ""电力信息化系统时间同步技术研究与应用"", 《电力信息与通信技术》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117220817B (en) | 2024-01-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10862601B1 (en) | Bridges including physical layer devices for indicating transmission times of synchronization frames by modifying previously generated corresponding follow up frames | |
| CN101404618B (en) | System, apparatus and method for implementing transparent transmission clock in accurate clock synchronization protocol | |
| US8370675B2 (en) | Precise clock synchronization | |
| US8738792B2 (en) | Server time protocol messages and methods | |
| EP2448168A1 (en) | Method and system for bearing time synchronization protocol in optical transport network | |
| JP6449430B2 (en) | Time synchronization method, device and time synchronization server for network device | |
| JP2009182659A (en) | Timing synchronizing method, synchronization device, synchronization system, and synchronization program | |
| US20220360350A1 (en) | Method and apparatus for acquiring timestamp of data stream, storage medium, and electronic apparatus | |
| CN103647614A (en) | Method for reliably improving time synchronization precision based on IEEE1588 protocol | |
| CN104243079A (en) | Microsecond clock synchronization method for real-time Ethernet | |
| CN113489563B (en) | Clock synchronization method of virtual machine and cloud platform | |
| CN117220817B (en) | Method and system for time synchronization monitoring of multi-core processor | |
| CN104202137A (en) | IEEE1588 clock synchronization method, system and device based on E1 link | |
| CN101420281B (en) | Method and arrangement for transferring a time of day value between network elements | |
| CN106656395A (en) | Improved system and method for synchronous time measurement in power grid based on self-learning | |
| CN113573403B (en) | Slave clock synchronization system and method for 5G RRU | |
| CN113381832B (en) | Precise time synchronization method based on FPGA platform | |
| CN102571252B (en) | Timing method of high-precision NTP (Network Time Protocol) timing system | |
| CN102394740B (en) | Time synchronization method and device | |
| CN214480655U (en) | Embedded equipment compatible with definable deterministic communication Ethernet | |
| WO2020132834A1 (en) | Method and device for stamping processing | |
| CN116961808A (en) | Clock synchronization method and related equipment | |
| WO2022028716A1 (en) | Ue based time synchronization in 5gs with gm clock on the ue side | |
| CN111865467A (en) | Clock synchronization system and method between distributed chassis board cards for time delay test | |
| CN116208289B (en) | Time synchronization method and device based on white box switch and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |