CN116566533A - Nanosecond NTP network time synchronization method and system - Google Patents
Nanosecond NTP network time synchronization method and system Download PDFInfo
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- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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Abstract
The invention discloses a nanosecond NTP network time synchronization method and a system, comprising a client and a server, wherein the client and the server are marked with NTP time stamps in a hardware mode, the client sends a time request message to the server, the server responds with a time response message, the time which the client sends the message to the server and the time which the server responds to the client calculate the clock deviation t between the client and the server, and the clock of the client is adjusted by the clock deviation t so that the time is consistent with the time of the server. The high-speed PHY chip unit provides Ethernet data packets on all physical layer function cables required for transmission and reception; a first processor unit for acquiring MAC layer data; a second processor unit marks the NTP time source hardware timestamp. In the NTP time synchronization process, the nanosecond NTP time synchronization is realized by marking the hardware time stamp, so that the precision is improved to the nanosecond level, and the influence of errors of an operating system and a network layer on the NTP synchronization precision is avoided.
Description
Technical Field
The invention relates to the technical field of nanosecond NTP network time synchronization, in particular to a nanosecond NTP network time synchronization method and system.
Background
NTP is a network time protocol (Network Time Protocol), which was originally used to synchronize the time of individual computers in a network, with conventional NTP network time synchronization accuracy on the order of milliseconds. However, with the rapid development of time-frequency technology, the time synchronization system is widely applied to the fields of aviation, aerospace, electric power and the like, and the time synchronization system has higher and higher requirements on time synchronization precision, and has reached nanosecond level. Thus, there is a need for achieving higher accuracy time synchronization within a system using nanosecond NTP time source generation techniques.
In network time protocol transmission, there are two timestamp marking modes: software time stamps and hardware time stamps. Compared with the hardware time stamp, in the traditional NTP network time synchronization implementation process, four time stamps are marked on a software layer, namely the software time stamp, and the software time stamp has lower precision and is in a subtle order. The reasons are two: first, there is a bus clock inside the processor, and this clock is usually driven by a common passive crystal oscillator, and the aging rate drift rate of the passive crystal oscillator is in a subtle level. Secondly, the uncertainty of software interrupt processing results in the inability to process in real time, often resulting in a significant difference between the time stamp placed and the actual time.
In summary, the hardware timestamp is adopted in the network time protocol transmission, so that the time synchronization precision of the NTP network is improved to nanosecond level, and the nanosecond time synchronization requirement of the time synchronization system is met. Meets the requirement of high precision of a synchronous system.
Disclosure of Invention
The invention aims to solve the problem of how to realize higher-precision time synchronization in a system in a nanosecond NTP time source generation technology, and provides a nanosecond NTP network time synchronization method and system, which are used for realizing the purpose of improving the NTP network time synchronization precision to the nanosecond level and meeting the requirement of the high precision of a synchronization system.
In order to achieve the technical purpose, the invention provides a nanosecond NTP network time synchronization method, which comprises a client and a server for marking NTP time stamps by using a hardware mode,
s1, the client sends a time request message to the server,
s2, the server responds with a time response message,
s3, calculating clock deviation t between the client and the server according to the time of the client sending the message to the server and the time of the server responding to the client,
and S4, adjusting the clock of the client by using the clock deviation t so as to enable the time of the clock to be consistent with the time of the server.
Preferably, S1, the client sends an NTP request message containing the client sending time stamp T1 to the server,
when the server receives the NTP request message, the receiving time stamp T2 of the server is filled in the message;
s2, the server sends a response message containing a sending time stamp T3 of the server to the client,
the client records a return timestamp T4 when receiving the response message;
s3, calculating the time d of NTP round trip delay and the clock deviation T between the client and the server according to T1, T2, T3 and T4:
and S4, adjusting the clock of the client by using the clock deviation t so as to enable the time of the clock to be consistent with the time of the server.
Preferably, a nanosecond NTP network time synchronization system, the network time synchronization system is composed of at least one network time source generating system,
the network time source generation system comprises:
a high-speed PHY chip unit in charge of NTP communication with the client, which provides Ethernet data packets on all physical layer function cables required for transmission and reception;
the first processor unit is used for realizing the MAC function of hardware NTP synchronization and acquiring MAC layer data;
the second processor unit is used for realizing protocol stack data analysis and marking an NTP time source hardware time stamp, and comprises a UDP protocol stack and an NTP protocol stack;
and a power supply unit responsible for supplying power to the device.
Preferably, it comprises:
in the receiving chain of the wireless communication system,
the high-speed PHY chip unit acquires an NTP synchronous request data packet of the client, and the first processor unit receives the data packet acquired by the high-speed PHY chip unit; the data packet entering the first processor unit acquires MAC layer data, then the data is sent to the second processor unit for data analysis and processing, and the receiving time stamp of the NTP time source is marked;
in the transmission link,
the second processor unit completes framing operation of NTP layer data, marks a sending time stamp of an NTP time source, and then completes framing of UDP, IP and MAC layers; after multiplexing the data with the MAC data of the first processor unit, the data is sent to an MAC interface, and the high-speed PHY chip unit completes the sending of the NTP synchronous response data packet.
Preferably, the method comprises the steps of,
in the receiving chain of the wireless communication system,
the high-speed PHY chip unit acquires an NTP synchronous request data packet of an NTP client through a bus RJ45 network port, the first processor unit receives the data packet acquired by the high-speed PHY chip unit through a GMII/RGMII interface, the data packet after entering the first processor unit acquires MAC layer data through an MAC interface, and then the data is sent to the second processor unit through the bus to carry out UDP protocol stack data analysis and NTP protocol stack data processing, and the receiving timestamp of an NTP time source is marked;
in the transmission link,
the second processor unit completes framing operation of NTP layer data in an NTP protocol stack, marks a sending time stamp of an NTP time source, and then completes framing of UDP, IP and MAC layers in a UDP protocol stack; after multiplexing with the MAC data of the first processor unit, the data is sent to the MAC interface, and the transmission of the NTP synchronous response packet is completed by the high-speed PHY chip unit 101.
Preferably, the time stamps of the NTP time sources are marked on a hardware processor that marks the NTP time stamps in hardware, so that the MAC function is implemented on the hardware processor.
Preferably, the reference time of the hardware processor is 245MHz to 255MHz, so that the NTP protocol stack can restore the reception timestamp and the transmission timestamp of the NTP time source to 1PPS pulse signals, and the accuracy of the reception timestamp 1PPS of the NTP time source and the transmission timestamp 1PPS of the NTP time source are both in nanosecond order.
Preferably, the reference time of the hardware processor is 248MHz to 252MHz, the corresponding clock period is 4ns, and the NTP message sent by the client is analyzed, so that the time stamp accuracy of the NTP network time source reaches nanosecond level, the time stamp is maximally close to the physical layer, and the errors caused by delay of other operating systems and other network layers are reduced.
Preferably, the nanosecond NTP network time synchronization system is composed of two nanosecond NTP network time source generating systems, and comprises a first NTP network time source unit and a second NTP network time source unit for performing data interaction on the two nanosecond NTP network time source generating systems.
Preferably, the first NTP network time source unit and the second NTP network time source unit perform NTP communication through a network, so that nanosecond NTP time synchronization accuracy is realized.
The invention discloses the following technical effects:
the invention utilizes the technology of marking the NTP time stamp in a hardware mode, realizes nanosecond NTP time synchronization in the NTP time synchronization process in the mode of marking the hardware time stamp, avoids the influence of errors of an operating system and a network layer on the NTP synchronization precision, and improves the NTP time synchronization precision to the nanosecond level.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a time synchronization method of a nanosecond NTP network according to the present invention;
fig. 2 is a schematic diagram of a nanosecond NTP network time source generation system according to the present invention;
fig. 3 is a schematic diagram of a nanosecond NTP network time synchronization system according to the present invention.
The system comprises a 101 high-speed PHY chip unit, a 102 first processor unit, a 103 second processor unit, a 104 power supply unit, a 201 first NTP network time source unit and a 202 second NTP network time source unit.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
As shown in fig. 1-3, the present invention provides a nanosecond NTP network time synchronization method, which includes a client and a server for marking NTP time stamps by hardware,
s1, the client sends a time request message to the server,
s2, the server responds with a time response message,
s3, calculating clock deviation t between the client and the server according to the time of the client sending the message to the server and the time of the server responding to the client,
and S4, adjusting the clock of the client by using the clock deviation t so as to enable the time of the clock to be consistent with the time of the server.
Further preferably, S1, the client sends an NTP request message containing the client sending time stamp T1 to the server,
when the server receives the NTP request message, the receiving time stamp T2 of the server is filled in the message;
s2, the server sends a response message containing a sending time stamp T3 of the server to the client,
the client records a return timestamp T4 when receiving the response message;
s3, calculating the time d of NTP round trip delay and the clock deviation T between the client and the server according to T1, T2, T3 and T4:
and S4, adjusting the clock of the client by using the clock deviation t so as to enable the time of the clock to be consistent with the time of the server.
Further preferably, a nanosecond NTP network time synchronization system, the network time synchronization system is comprised of at least one network time source generation system,
the network time source generation system comprises:
a high-speed PHY chip unit in charge of NTP communication with the client, which provides Ethernet data packets on all physical layer function cables required for transmission and reception;
the first processor unit is used for realizing the MAC function of hardware NTP synchronization and acquiring MAC layer data;
the second processor unit is used for realizing protocol stack data analysis and marking an NTP time source hardware time stamp, and comprises a UDP protocol stack and an NTP protocol stack;
and a power supply unit responsible for supplying power to the device.
Further preferably, the method comprises:
in the receiving chain of the wireless communication system,
the high-speed PHY chip unit acquires an NTP synchronous request data packet of the client, and the first processor unit receives the data packet acquired by the high-speed PHY chip unit; the data packet entering the first processor unit acquires MAC layer data, then the data is sent to the second processor unit for data analysis and processing, and the receiving time stamp of the NTP time source is marked;
in the transmission link,
the second processor unit completes framing operation of NTP layer data, marks a sending time stamp of an NTP time source, and then completes framing of UDP, IP and MAC layers; after multiplexing the data with the MAC data of the first processor unit, the data is sent to an MAC interface, and the high-speed PHY chip unit completes the sending of the NTP synchronous response data packet.
It is further preferred that the composition comprises,
in the receiving chain of the wireless communication system,
the high-speed PHY chip unit acquires an NTP synchronous request data packet of an NTP client through a bus RJ45 network port, the first processor unit receives the data packet acquired by the high-speed PHY chip unit through a GMII/RGMII interface, the data packet after entering the first processor unit acquires MAC layer data through an MAC interface, and then the data is sent to the second processor unit through the bus to carry out UDP protocol stack data analysis and NTP protocol stack data processing, and the receiving timestamp of an NTP time source is marked;
in the transmission link,
the second processor unit completes framing operation of NTP layer data in an NTP protocol stack, marks a sending time stamp of an NTP time source, and then completes framing of UDP, IP and MAC layers in a UDP protocol stack; after multiplexing with the MAC data of the first processor unit, the data is sent to the MAC interface, and the transmission of the NTP synchronous response packet is completed by the high-speed PHY chip unit 101.
Further preferably, the NTP time source timestamps are marked on a hardware processor that marks the NTP time stamps in hardware, so that the MAC function is implemented on the hardware processor.
Further preferably, the reference time of the hardware processor is 245MHz to 255MHz, so that the NTP protocol stack can restore the reception timestamp and the transmission timestamp of the NTP time source to 1PPS pulse signals, and the accuracy of the reception timestamp 1PPS of the NTP time source and the transmission timestamp 1PPS of the NTP time source are both in nanosecond order.
Further preferably, the reference time of the hardware processor is 248MHz to 252MHz, the corresponding clock period is 4ns, and the NTP message sent by the client is analyzed, so that the time stamp accuracy of the NTP network time source reaches nanosecond level, the time stamp is maximally close to the physical layer, and the errors caused by delay of other operating systems and other network layers are reduced.
Further preferably, the nanosecond NTP network time synchronization system is composed of two nanosecond NTP network time source generating systems, and the nanosecond NTP network time source generating systems comprise a first NTP network time source unit and a second NTP network time source unit for performing data interaction on the two nanosecond NTP network time source generating systems.
Further preferably, the first NTP network time source unit and the second NTP network time source unit perform NTP communication through a network, so that nanosecond NTP time synchronization accuracy is achieved.
Through research and analysis, the traditional NTP network time synchronization precision cannot break through the millisecond order, because the time stamp is marked on the software protocol layer, and the uncertainty of the software time stamp is too large due to the error influence of an operating system and a network layer, so that the NTP time stamp marking precision is low. Therefore, the present solution is intended to provide a method for implementing nanosecond NTP time synchronization using hardware timestamp technology.
In order to achieve the above purpose, the scheme is as follows:
in a first aspect, the present solution provides a method based on nanosecond NTP network time source generation technology, where the method marks four timestamps T1, T2, T3, T4 in NTP time synchronization in a hardware manner.
In a second aspect, the present solution provides a device based on nanosecond NTP network time source generation technology, where the device uses hardware time stamp technology to generate NTP network time source, and the device mainly includes a processor, a high-speed PHY chip, and a power supply.
In a third aspect, the present solution provides a nanosecond NTP network time synchronization system, including: network time source (server side) based on nanosecond NTP network time generation technology, nanosecond NTP network time synchronization client.
The following describes in detail a method and a system for generating a nanosecond NTP network time source according to the present embodiment with reference to fig. 1, fig. 2, and fig. 3. The method can comprise the following steps:
step S1, receiving an NTP message of a client, wherein the NTP message comprises a sending time stamp T1 of the client;
step S2, realizing the MAC function on the hardware processor, analyzing the NTP message sent by the client, and marking a receiving time stamp T2 on the hardware processor;
step S3, a response message is sent to the client, and a sending timestamp T3 is marked on the hardware processor;
step S4, the client receives the response message and marks a receiving time stamp T4.
In the scheme, the step S2 and the step S3 are realized on an NTP network time source, the related time stamps are marked on a hardware processor, the physical layer is maximally close to the time stamps, and errors caused by delays of other operating systems and other network layers are reduced. The reference clock on the hardware processor is 250MHz, and the corresponding clock period is 4ns, so that the time stamp is marked on the hardware processor, and the time stamp precision of the NTP network time source can reach nanosecond level.
With reference to fig. 2, the present solution further provides a system implemented in conjunction with the above-mentioned nanosecond NTP network time source generation method, where the system includes:
a high-speed PHY chip unit 101, which is responsible for NTP communication with clients, and which can provide ethernet packets on all physical layer function cables required for transmission and reception;
a first processor unit 102, which implements the MAC function of hardware NTP synchronization, and acquires MAC layer data;
a second processor unit 103, which includes a UDP protocol stack and an NTP protocol stack, implements protocol stack data parsing, and marks an NTP time source hardware timestamp;
a power supply unit 104, which is responsible for powering the system.
In the receiving link, the high-speed PHY unit 101 acquires, through a bus, an NTP synchronization request packet of an NTP client received by an RJ45 network port. The first processor unit 102 receives data packets of the high speed PHY chip unit 101 via the GMII/RGMII interface. After the data packet enters the first processor unit 102, the data packet obtains the MAC layer data through the MAC interface, and then the data packet is sent to the second processor unit 103 through the bus to perform UDP protocol stack data analysis and NTP protocol stack data processing, and marks a reception timestamp of the NTP time source.
In the transmission link, the second processor unit 103 first completes the framing operation of the NTP layer data in the NTP protocol stack, marks the transmission time stamp of the NTP time source, and then sends the transmission time stamp to the UDP protocol stack to complete the framing of the UDP, IP and MAC layers. After multiplexing with the MAC data of the first processor unit 102, the data is sent to the MAC interface, and the transmission of the NTP synchronous response packet is completed by the high-speed PHY chip unit 101.
In particular, the NTP protocol stack of the second processor unit 103 may restore the reception timestamp and the transmission timestamp of the NTP time source to a 1PPS pulse signal. Because the timestamps of the NTP time sources are all marked on the hardware processor, the reference time of the hardware processor is 250MHz, and thus the accuracy of the NTP time source receiving timestamp 1PPS and the accuracy of the NTP time source transmitting timestamp 1PPS are both in the order of nanoseconds.
On the basis of the implementation mode of the nanosecond NTP network time source generation method, the scheme further provides a nanosecond NTP network time synchronization system. The NTP time synchronization system shown in fig. 3 is only an example, and should not impose any limitation on the functions and scope of use of the embodiment of the present solution.
Referring to fig. 3, the nanosecond NTP network time synchronization system is composed of two nanosecond NTP network time source generating devices, and NTP communication is performed between a first NTP network time source unit 201 and a second NTP network time source unit 202 through a network, so that nanosecond NTP time synchronization accuracy can be realized.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, third, etc. do not denote any order. These words may be interpreted as names.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (10)
1. A nanosecond NTP network time synchronization method is characterized in that:
including clients and servers that mark NTP timestamps in hardware,
s1, the client sends a time request message to the server,
s2, the server responds with a time response message,
s3, calculating clock deviation t between the client and the server according to the time of the client sending the message to the server and the time of the server responding to the client,
and S4, adjusting the clock of the client by using the clock deviation t so as to enable the time of the clock to be consistent with the time of the server.
2. The nanosecond NTP network time synchronization method of claim 1, wherein the steps of:
s1, the client sends an NTP request message containing a client sending time stamp T1 to the server,
when the server receives the NTP request message, the receiving time stamp T2 of the server is filled in the message;
s2, the server sends a response message containing a sending time stamp T3 of the server to the client,
the client records a return timestamp T4 when receiving the response message;
s3, calculating the time d of NTP round trip delay and the clock deviation T between the client and the server according to T1, T2, T3 and T4:
and S4, adjusting the clock of the client by using the clock deviation t so as to enable the time of the clock to be consistent with the time of the server.
3. A nanosecond NTP network time synchronization system, which is applied to a nanosecond NTP network time synchronization method as claimed in any one of claims 1-3, characterized in that the network time synchronization system is composed of at least one network time source generating system,
the network time source generation system comprises:
a high-speed PHY chip unit in charge of NTP communication with the client, which provides Ethernet data packets on all physical layer function cables required for transmission and reception;
the first processor unit is used for realizing the MAC function of hardware NTP synchronization and acquiring MAC layer data;
the second processor unit is used for realizing protocol stack data analysis and marking an NTP time source hardware time stamp, and comprises a UDP protocol stack and an NTP protocol stack;
and a power supply unit responsible for supplying power to the device.
4. A nanosecond NTP network time synchronization system as claimed in claim 3, comprising:
in the receiving chain of the wireless communication system,
the high-speed PHY chip unit acquires an NTP synchronous request data packet of the client, and the first processor unit receives the data packet acquired by the high-speed PHY chip unit; the data packet entering the first processor unit acquires MAC layer data, then the data is sent to the second processor unit for data analysis and processing, and the receiving time stamp of the NTP time source is marked;
in the transmission link,
the second processor unit completes framing operation of NTP layer data, marks a sending time stamp of an NTP time source, and then completes framing of UDP, IP and MAC layers; after multiplexing the data with the MAC data of the first processor unit, the data is sent to an MAC interface, and the high-speed PHY chip unit completes the sending of the NTP synchronous response data packet.
5. The nanosecond NTP network time synchronization system of claim 4 wherein:
in the receiving chain of the wireless communication system,
the high-speed PHY chip unit acquires an NTP synchronous request data packet of an NTP client through a bus RJ45 network port, the first processor unit receives the data packet acquired by the high-speed PHY chip unit through a GMII/RGMII interface, the data packet after entering the first processor unit acquires MAC layer data through an MAC interface, and then the data is sent to the second processor unit through the bus to carry out UDP protocol stack data analysis and NTP protocol stack data processing, and the receiving timestamp of an NTP time source is marked;
in the transmission link,
the second processor unit completes framing operation of NTP layer data in an NTP protocol stack, marks a sending time stamp of an NTP time source, and then completes framing of UDP, IP and MAC layers in a UDP protocol stack; after multiplexing with the MAC data of the first processor unit, the data is sent to the MAC interface, and the transmission of the NTP synchronous response packet is completed by the high-speed PHY chip unit 101.
6. The nanosecond NTP network time synchronization system of claim 5 wherein: the time stamp of the NTP time source is marked on a hardware processor which marks the NTP time stamp in a hardware mode, so that the MAC function is realized on the hardware processor.
7. The nanosecond NTP network time synchronization system of claim 6 wherein: the reference time of the hardware processor is 245MHz to 255MHz, so that the NTP protocol stack can restore the receiving time stamp and the transmitting time stamp of the NTP time source into 1PPS pulse signals, and the precision of the receiving time stamp 1PPS of the NTP time source and the transmitting time stamp 1PPS of the NTP time source are both in nanosecond level.
8. The nanosecond NTP network time synchronization system of claim 7 wherein:
the reference time of the hardware processor is 248MHz to 252MHz, the corresponding clock period is 4ns, and the NTP message sent by the client is analyzed, so that the time stamp accuracy of the NTP network time source reaches nanosecond level, the time stamp accuracy is maximally close to the physical layer, and the errors caused by the delay of other operating systems and other network layers are reduced.
9. The nanosecond NTP network time synchronization system of claim 8 wherein: the nanosecond NTP network time synchronization system is composed of two nanosecond NTP network time source generating systems and comprises a first NTP network time source unit and a second NTP network time source unit which perform data interaction on the two nanosecond NTP network time source generating systems.
10. The nanosecond NTP network time synchronization system of claim 9 wherein: the first NTP network time source unit and the second NTP network time source unit carry out NTP communication through a network, and nanosecond NTP time synchronization accuracy is realized.
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| CN202310596086.8A CN116566533A (en) | 2023-05-24 | 2023-05-24 | Nanosecond NTP network time synchronization method and system |
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| CN202310596086.8A CN116566533A (en) | 2023-05-24 | 2023-05-24 | Nanosecond NTP network time synchronization method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117220817A (en) * | 2023-11-07 | 2023-12-12 | 江苏金智科技股份有限公司 | Method and system for time synchronization monitoring of multi-core processor |
| CN117560110A (en) * | 2024-01-12 | 2024-02-13 | 深圳市太铭科技有限公司 | NTP time service method and system for high access request |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117220817A (en) * | 2023-11-07 | 2023-12-12 | 江苏金智科技股份有限公司 | Method and system for time synchronization monitoring of multi-core processor |
| CN117220817B (en) * | 2023-11-07 | 2024-01-05 | 江苏金智科技股份有限公司 | Method and system for time synchronization monitoring of multi-core processor |
| CN117560110A (en) * | 2024-01-12 | 2024-02-13 | 深圳市太铭科技有限公司 | NTP time service method and system for high access request |
| CN117560110B (en) * | 2024-01-12 | 2024-04-26 | 深圳市太铭科技有限公司 | NTP time service method and system for high access request |
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