CN117200785A - NOR gate circuit with symmetrical upper and lower edges - Google Patents
NOR gate circuit with symmetrical upper and lower edges Download PDFInfo
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- CN117200785A CN117200785A CN202210604158.4A CN202210604158A CN117200785A CN 117200785 A CN117200785 A CN 117200785A CN 202210604158 A CN202210604158 A CN 202210604158A CN 117200785 A CN117200785 A CN 117200785A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 6
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 6
- 230000000630 rising effect Effects 0.000 claims description 19
- 238000010586 diagram Methods 0.000 description 4
- 238000000342 Monte Carlo simulation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
The application provides a nor gate circuit with symmetrical upper and lower edges, which comprises: the pull-up circuit is a circuit which is formed by connecting PMOS (P-channel metal oxide semiconductor) tubes in series with each other and then connecting the PMOS tubes in parallel, and comprises two PMOS tubes of a first series circuit which are respectively marked as PM1 and PM2; the two PMOS tubes of the second series circuit are respectively marked as PM6 and PM7, and the first series circuit and the second series circuit are connected in parallel; the pull-down circuit is a circuit connected with two NMOS tubes in parallel and is respectively marked as NM1 and NM2; the pull-up circuit is connected with the pull-down circuit; the first series circuit and the second series circuit are connected in parallel through one end of the first series circuit and the second series circuit which are connected with VDD through wires, and the other end of the first series circuit and the second series circuit are connected with Y through wires; one end of the pull-down circuit is connected with the pull-up circuit through a wire, and the other end of the pull-down circuit is connected with VSS through a wire.
Description
Technical Field
The application relates to the technical field of standard unit circuits in the field of integrated circuit design, in particular to a nor gate circuit with symmetrical upper and lower edges.
Background
Generally, a fab will provide a standard cell library developed based on its process, which contains some of the most basic and most common circuit cells, such as nand gates, nor gates, adders, inverters, registers, etc. However, different chip design manufacturers often need to make custom modifications based on this to adapt to the special requirements of their designs.
As shown in fig. 1, the conventional nor gate has a pull-up circuit with two PMOS (fully: positive channel Metal Oxide Semiconductor) connected in series and a pull-down circuit with two NMOS (fully: N-Metal-Oxide-Semiconductor) connected in parallel, which causes a phenomenon: the rising edge of the circuit is relatively slow and the falling edge is relatively fast. This asymmetry results in severe inconsistencies in rising and falling edge times, resulting in some circuits that have high requirements for rising and falling edge consistency being unusable. If performance differences between NMOS and PMOS are not taken into account, the falling edge time of the circuit is about half the rising edge time.
That is, in the prior art, the standard nor gate circuit easily causes a large difference between the rising edge time and the falling edge time of the output thereof due to the asymmetry of the structure of the pull-up circuit and the structure of the pull-down circuit. This gap is unacceptable in some use cases, such as clock generation circuits, where asymmetrical rising and falling edges can cause the duty cycle of the clock to deviate.
In addition, the standard nor gate circuit has a problem of too high OCV when operating at an ultra-low voltage because the pull-up circuit is weak.
Furthermore, the prior art includes the following terms:
OCV (open circuit voltage): and the MOS tube characteristics of all parts on the chip cannot be completely the same due to the manufacturing process, the environment and the like, so that the deviation is caused. The deviation is mainly reflected in the speed of the MOS transistor, and the deviation is larger as the working voltage is reduced. Therefore, if the circuit is to be operated at ultra low voltages, the OCV must be reduced from the circuit design.
Monte Carlo simulation: the method is characterized in that parameters of the MOS tube are used as random variables, and different output results are generated through multiple random inputs. The OCV size of the circuit can be known by observing the consistency of the results.
Ultra low voltage: the power consumption of the chip is proportional to the square of the operating voltage, so the most effective way to reduce the power consumption of the chip is to reduce the operating voltage. However, the OCV of the MOS transistor becomes very large under the ultra-low voltage, so that if the chip is required to operate under the ultra-low voltage, the problem of the OCV under the ultra-low voltage must be overcome.
The rising edge and the falling edge are symmetrical: the rising and falling edge speeds of cells of standard logic, if asymmetric, can cause the slew rate of the circuit to be too high, resulting in increased power consumption. In addition, since the clock generation circuit has a higher duty ratio, the rising edge speed and the falling edge speed are required to be as symmetrical as possible.
Disclosure of Invention
In order to solve the above problems, the present application aims to solve the technical problems: by adopting a special structure, the rising edge time and the falling edge time of the NOR gate output are quite symmetrical, and the requirements of use under some special scenes are met. Meanwhile, the OCV of the pull-up circuit is reduced, so that the pull-up circuit has better robustness when working under ultralow voltage.
Specifically, the application provides a nor gate circuit with symmetrical upper and lower edges, which comprises:
the pull-up circuit (100) is a circuit which is formed by connecting PMOS (P-channel metal oxide semiconductor) tubes in series with each other and then connecting the PMOS tubes in parallel with each other, and comprises two PMOS tubes of a first series circuit (101) which are respectively marked as PM1 and PM2; the two PMOS tubes of the second series circuit (102) are respectively marked as PM6 and PM7, and the first series circuit (101) and the second series circuit (102) are connected in parallel; and
a pull-down circuit (110) which is a circuit connected with two NMOS tubes in parallel and is respectively marked as NM1 and NM2;
the pull-up circuit (100) and the pull-down circuit (110) are directly connected through a wire;
the first series circuit (101) and the second series circuit (102) are connected in parallel through one end of the first series circuit and one end of the second series circuit are connected with VDD through wires, the other end of the second series circuit is connected with Y through wires, and an output signal Y is connected with a pull-up circuit and a pull-down circuit; when the PMOS is switched on and the NMOS is switched off, the pull-up circuit is turned on, and the pull-down circuit is turned off, wherein Y=VDD; conversely, when the PMOS is turned off and the NMOS is turned on, the pull-up circuit is turned off, and the pull-down circuit is turned on, y=vss;
one end of the pull-down circuit (110) is connected with the pull-up circuit (100) through a wire, and the other end of the pull-down circuit is connected with VSS through a wire.
In the first series circuit (101), one end of the PM1 is connected with VDD through a wire, A of the PM1 is a logic input signal, and the value of an output signal Y is determined together with a logic input signal B of the PM2; the VNW of the PM1 is an input voltage signal and is used for supplying power to an N well of the PMOS tube, and the other end of the VNW is connected with the PM2 through a wire;
b of the PM2 is a logic input signal, and the value of an output signal Y is determined together with a logic input signal A of the PM 1; VNW is an input voltage signal for supplying power to the N-well of the PMOS tube, and the other end is connected with Y through a wire and is connected with the second series circuit (102) and the pull-down circuit (110), namely Y is a logic output signal with the value equal to A or B, namely-! (A|B));
in the second series circuit (102), one end of the PM7 is connected with VDD through a wire, A of the PM7 is used as an input end, and the other end of the PM7 is connected with the PM6 through a wire; the B of the PM6 is used as an input end, the other end of the PM6 is connected with Y through a wire, and is connected with the first series circuit (101) and the pull-down circuit (110), wherein A is a logic input signal, and the value of an output signal Y is determined together with the other logic input signal B; the VNW is an input voltage signal, which is used to power the N-well of the PMOS transistor.
The pull-down circuit is connected in parallel with two NMOS tubes in pairs, and is respectively marked as NM1 and NM2.
One end of the NM1 is connected with the pull-up circuit (100) through a wire, A, VPW is used as an input end, and the other end of the NM1 is grounded at the VSS source end;
one end of the NM2 is connected with the pull-up circuit (100) through a wire, B, VPW is used as an input end, and the other end of the NM2 is grounded at the VSS source end;
the NM1 and the NM2 are connected in parallel through wires to form a pull-down circuit (110).
The nor gate circuit can ignore, i.e. be considered equal, the difference between the rising edge time and the falling edge time when the difference between the performances of the NMOS and the PMOS is not considered.
The circuit is applied to an integrated circuit chip operating at ultra-low voltages.
Thus, the present application has the advantages that: the NOR gate circuit is simple in structure, can work under ultra-low voltage and is good in robustness, and the up-down edge symmetry can be achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and together with the description serve to explain the application.
Fig. 1 is a schematic diagram of a nor gate circuit in the prior art.
Fig. 2 is a schematic diagram of the nor gate circuit of the present application.
FIG. 3 is a schematic diagram comparing simulation results of a conventional NOR gate circuit and a circuit of the present application.
Fig. 4 is a diagram showing the simulation results of monte carlo comparing a conventional nor gate circuit with the circuit of the present application.
Detailed Description
In order that the technical content and advantages of the present application may be more clearly understood, a further detailed description of the present application will now be made with reference to the accompanying drawings.
The application mainly designs a NOR gate circuit which can work under ultra-low voltage and has good robustness, and standard units in a chip are built through PMOS (P-channel metal oxide semiconductor) tubes and NMOS (N-channel metal oxide semiconductor) tubes.
The application provides a special NOR gate, as shown in FIG. 2, wherein A, B, VNW, VPW, VDD, VSS is an input signal, Y is an output signal, VNW is the voltage of an N-well, and VPW is the voltage of a P-type substrate. Similar to VDD and VSS, VNW and VPW are input voltage signals, which are physically wired. The pull-up circuit 100 of the circuit is a circuit of two-to-two strings, and the pull-up speed is improved by nearly one time due to the addition of one parallel circuit. While pull-down circuit 101 is still a parallel connection of two NMOS transistors. The NOR gate is characterized in that the rising edge time and the falling edge time are basically equal if the performance difference of NMOS and PMOS is not considered because the pull-up speed is doubled. This can be used in many circuits where symmetry requirements for rising and falling edges are high.
Specifically, as shown in fig. 2, a nor gate circuit with symmetrical upper and lower edges includes:
the pull-up circuit 100 is a circuit of two PMOS tubes connected in series and then connected in parallel, and comprises a first series circuit 101 and a second series circuit 102; two PMOS transistors of the first series circuit 101 are respectively denoted as PM1 and PM2; in the first series circuit 101, one end of the PM1 is connected to VDD via a wire, A, VNW is an input signal, and the other end is connected to the PM2 via a wire; one end of the PM2 is connected to the PM1, B, VNW is an input signal, and the other end is connected to the second series circuit 102 and the pull-down circuit 110 through Y; two PMOS transistors of the second series circuit 102 are respectively denoted as PM6 and PM7, in the second series circuit 102, one end of the PM7 is connected with VDD through a wire, a is used as an input end, and the other end is connected with the PM6 through a wire; one end of the PM6 is connected to the PM7, B, VNW is an input signal, and the other end is connected to the first series circuit 101 and the pull-down circuit 110 through Y;
the first series circuit 101 and the second series circuit 102 are connected in parallel; the first series circuit 101 and the second series circuit 102 are connected in parallel through one end of the two circuits and are connected with VDD through a wire, wherein VDD is not only a power supply voltage, but also is connected with a source electrode of the MOS transistor (called a drain electrode can also be used, because the MOS transistor is not divided into source and drain electrodes), and the other end of the first series circuit and the second series circuit are connected with Y through a wire; wherein A is a logic input signal, and the value of the output signal Y is determined together with another logic input signal B; the VNW is an input voltage signal and is used for supplying power to an N well of the PMOS tube; and
the pull-down circuit 110 is a circuit connected with two NMOS tubes in parallel and is respectively marked as NM1 and NM2;
the pull-up circuit 100 is connected with the pull-down circuit 110 through a wire;
one end of the pull-down circuit 110 is connected to the pull-up circuit 100 through a wire, and the other end is connected to VSS, which is both ground and the source (drain) of the MOS transistor, similar to the description of VDD above.
The pull-down circuit is connected in parallel with two NMOS tubes in pairs, and is respectively marked as NM1 and NM2.
One end of the NM1 is connected with the pull-up circuit 100 through a wire, A, VPW is used as an input end, and the other end of the NM1 is grounded at the source end of VSS;
one end of the NM2 is connected with the pull-up circuit 100 through a wire, B, VPW is used as an input end, and the other end of the NM2 is grounded at the source end of VSS;
the pull-down circuit 110 is configured by connecting the NM1 and the NM2 in parallel via a wire.
The nor gate circuit can ignore, i.e. be considered equal, the difference between the rising edge time and the falling edge time when the difference between the performances of the NMOS and the PMOS is not considered.
The circuit is applied to an integrated circuit chip operating at ultra-low voltages. The circuit is designed specifically for an ultra-low voltage operating scenario.
As shown in fig. 3, the simulation results of the conventional nor gate circuit and the circuit of the present application are compared. Y0 is the output of a conventional NOR gate, and Y1 is the output of the circuit of the present application. It can be seen that the rising edge time of Y0 is 43.45ps, while the rising edge time of Y1 is only 21.73ps, which increases the speed by nearly a factor of two. In addition, the falling edge time of Y0 is 18.73ps, and the difference between the rising edge time and the falling edge time is large. While the falling edge time of Y1 is 19.79ps, very similar to the rising edge time thereof, substantially close.
In addition, the enhancement of the pull-up circuit also reduces the OCV, so that the pull-up circuit works at ultralow voltage and has better robustness. As shown in fig. 4, Y0 is still the monte carlo simulation result of the conventional nor gate, and Y1 is the monte carlo simulation result of the circuit of the present application. It can be seen that the OCV of Y0 is 63.46ps, while that of Y1 is only 28.80ps, and that the OCV is greatly reduced.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations can be made to the embodiments of the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (6)
1. A nor gate circuit with symmetrical upper and lower edges, comprising:
the pull-up circuit (100) is a circuit which is formed by connecting PMOS (P-channel metal oxide semiconductor) tubes in series with each other and then connecting the PMOS tubes in parallel with each other, and comprises two PMOS tubes of a first series circuit (101) which are respectively marked as PM1 and PM2; the two PMOS tubes of the second series circuit (102) are respectively marked as PM6 and PM7, and the first series circuit (101) and the second series circuit (102) are connected in parallel; and
a pull-down circuit (110) which is a circuit connected with two NMOS tubes in parallel and is respectively marked as NM1 and NM2;
the pull-up circuit (100) and the pull-down circuit (110) are directly connected through a wire;
the first series circuit (101) and the second series circuit (102) are connected in parallel through one end of the first series circuit and one end of the second series circuit are connected with VDD through wires, the other end of the second series circuit is connected with Y through wires, and an output signal Y is connected with a pull-up circuit and a pull-down circuit; when the PMOS is switched on and the NMOS is switched off, the pull-up circuit is turned on, and the pull-down circuit is turned off, wherein Y=VDD; conversely, when the PMOS is turned off and the NMOS is turned on, the pull-up circuit is turned off, and the pull-down circuit is turned on, y=vss;
one end of the pull-down circuit (110) is connected with the pull-up circuit (100) through a wire, and the other end of the pull-down circuit is connected with VSS through a wire.
2. A nor gate with symmetrical top and bottom edges according to claim 1, wherein in the first series circuit (101), one end of PM1 is connected to VDD by a wire, a of PM1 is a logic input signal, and the value of the output signal Y is determined together with the logic input signal B of PM2; the VNW of the PM1 is an input voltage signal and is used for supplying power to an N well of the PMOS tube, and the other end of the VNW is connected with the PM2 through a wire;
b of the PM2 is a logic input signal, and the value of an output signal Y is determined together with a logic input signal A of the PM 1; VNW is an input voltage signal for supplying power to the N-well of the PMOS tube, and the other end is connected with Y through a wire and is connected with the second series circuit (102) and the pull-down circuit (110), namely Y is a logic output signal with the value equal to A or B, namely-! (A|B)); in the second series circuit (102), one end of the PM7 is connected with VDD through a wire, A of the PM7 is used as an input end, and the other end of the PM7 is connected with the PM6 through a wire; the B of the PM6 is used as an input end, the other end of the PM6 is connected with Y through a wire, and is connected with the first series circuit (101) and the pull-down circuit (110), wherein A is a logic input signal, and the value of an output signal Y is determined together with the other logic input signal B; the VNW is an input voltage signal, which is used to power the N-well of the PMOS transistor.
3. The nor gate circuit of claim 1, wherein the pull-down circuit is connected in parallel two NMOS transistors, denoted NM1 and NM2, respectively.
4. A nor gate with symmetrical upper and lower edges according to claim 3, wherein one end of said NM1 is connected to said pull-up circuit (100) through a wire, A, VPW is used as an input end, and the other end VSS source is grounded;
one end of the NM2 is connected with the pull-up circuit (100) through a wire, B, VPW is used as an input end, and the other end of the NM2 is grounded at the VSS source end;
the NM1 and the NM2 are connected in parallel through wires to form a pull-down circuit (110).
5. The nor gate circuit of claim 1, wherein the nor gate circuit is configured such that the difference between the rising edge time and the falling edge time is negligible, i.e., equal, when the difference between NMOS and PMOS performance is not considered.
6. The nor gate circuit of claim 1, wherein the circuit is applied to an integrated circuit chip operating at ultra low voltages.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210604158.4A CN117200785A (en) | 2022-05-30 | 2022-05-30 | NOR gate circuit with symmetrical upper and lower edges |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210604158.4A CN117200785A (en) | 2022-05-30 | 2022-05-30 | NOR gate circuit with symmetrical upper and lower edges |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117200785A true CN117200785A (en) | 2023-12-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210604158.4A Pending CN117200785A (en) | 2022-05-30 | 2022-05-30 | NOR gate circuit with symmetrical upper and lower edges |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117200785A (en) |
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2022
- 2022-05-30 CN CN202210604158.4A patent/CN117200785A/en active Pending
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