CN117199063A - 3D transparent light sensor packaging structure - Google Patents
3D transparent light sensor packaging structure Download PDFInfo
- Publication number
- CN117199063A CN117199063A CN202311137129.2A CN202311137129A CN117199063A CN 117199063 A CN117199063 A CN 117199063A CN 202311137129 A CN202311137129 A CN 202311137129A CN 117199063 A CN117199063 A CN 117199063A
- Authority
- CN
- China
- Prior art keywords
- adhesive layer
- chip
- substrate
- gold wire
- packaging adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 74
- 239000012790 adhesive layer Substances 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 239000010410 layer Substances 0.000 claims abstract description 46
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 102
- 239000010931 gold Substances 0.000 claims description 22
- 229910052737 gold Inorganic materials 0.000 claims description 22
- 239000003292 glue Substances 0.000 claims description 15
- 230000003287 optical effect Effects 0.000 abstract description 13
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- 238000005538 encapsulation Methods 0.000 description 16
- 241000218202 Coptis Species 0.000 description 11
- 235000002991 Coptis groenlandica Nutrition 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Light Receiving Elements (AREA)
Abstract
The invention discloses a 3D transparent light sensor packaging structure, which comprises a substrate, an ASIC chip, a Vcsel chip, a first packaging adhesive layer, a second packaging adhesive layer, a 3D transparent adhesive layer and a conducting cushion layer, wherein the substrate is provided with a first packaging adhesive layer and a second packaging adhesive layer; the ASIC chip is attached to the top surface of the substrate and packaged through the first packaging adhesive layer; the Vcsel chip is packaged at the top of the ASIC chip through the 3D transparent adhesive layer to form a stacked chip structure, the Vcsel chip is packaged through the second packaging adhesive layer, and the top surface of the 3D transparent adhesive layer extends to the upper part of the top surface of the second packaging adhesive layer; the conducting cushion layer is arranged between the first packaging adhesive layer and the second packaging adhesive layer, and is electrically connected with the Vcsel chip and the substrate, and the Vcsel chip is electrically connected with the substrate. The invention relates to the technical field of optical sensors, and can solve the problems of large volume and poor heat dissipation performance of an optical sensor in the prior art.
Description
Technical Field
The invention relates to the technical field of optical sensors, in particular to a 3D transparent light sensor packaging structure.
Background
Referring to fig. 1, the optical sensor of the prior art includes a substrate 1, a cover 2, a first chip 3 and a second chip 4; the cover body 2 is arranged on the base plate 1 to form two cavities, and the first chip 3 and the second chip 4 are respectively packaged in the two cavities and are electrically connected with the base plate 1 through wire bonding.
The optical sensor in the prior art needs to be provided with two accommodating cavities, the transverse occupied space is larger, a certain wire bonding height is required for gold wires in the vertical space, a certain space is required to be reserved in the vertical direction, the whole optical sensor is larger in size, and meanwhile, the optical sensor does not have good heat dissipation performance. Therefore, it is necessary to provide a 3D transparent light sensor package structure, which can solve the problems of large volume and poor heat dissipation performance of the optical sensor in the prior art.
Disclosure of Invention
The invention aims to provide a 3D transparent light sensor packaging structure which can solve the problems of large volume and poor heat dissipation performance of an optical sensor in the prior art.
The invention is realized in the following way:
A3D transparent light sensor packaging structure comprises a substrate, an ASIC chip, a Vcsel chip, a first packaging adhesive layer, a second packaging adhesive layer, a 3D transparent adhesive layer and a conducting cushion layer; the ASIC chip is attached to the top surface of the substrate and packaged through the first packaging adhesive layer; the Vcsel chip is packaged at the top of the ASIC chip through the 3D transparent adhesive layer to form a stacked chip structure, the Vcsel chip is packaged through the second packaging adhesive layer, and the top surface of the 3D transparent adhesive layer extends to the upper part of the top surface of the second packaging adhesive layer; the conducting cushion layer is arranged between the first packaging adhesive layer and the second packaging adhesive layer, and is electrically connected with the Vcsel chip and the substrate, and the Vcsel chip is electrically connected with the substrate.
The Vcsel chip and the photosensitive area on the ASIC chip are staggered, the top of the Vcsel chip and the photosensitive area are covered by the 3D transparent adhesive layer, and a gap between the top of the Vcsel chip and the photosensitive area is filled by the second packaging adhesive layer.
The top surface of 3D transparent glue film be cambered surface structure.
The first encapsulation glue layer in be formed with first conduction through-hole along thickness direction, first gold thread sets up in first conduction through-hole, the upper end and the conduction bed course electricity of first gold thread are connected, the lower extreme and the base plate electricity of first gold thread are connected.
And the Vcsel chip is internally wired to form a second gold wire and a third gold wire, the second gold wire is positioned in the second packaging adhesive layer and is electrically connected with the conducting cushion layer, and the third gold wire is positioned in the first packaging adhesive layer and is electrically connected with the substrate.
The diameters of the second gold wire and the third gold wire are smaller than those of the first gold wire.
A plurality of second conducting through holes are formed in the substrate along the thickness direction, a fourth gold wire and a fifth gold wire are respectively arranged in the plurality of second conducting through holes, the upper end of the fourth gold wire is electrically connected with the first gold wire, the upper end of the fifth gold wire is electrically connected with the third gold wire, and the lower ends of the fourth gold wire and the fifth gold wire are respectively led out to the bottom surface of the substrate.
The diameters of the fourth gold wire and the fifth gold wire are larger than those of the third gold wire.
The conducting cushion layer is positioned at the interface of the first packaging adhesive layer and the second packaging adhesive layer, and is higher than the bottom surface of the 3D transparent adhesive layer.
The substrate is a laminated substrate.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the invention, the ASIC chip and the Vcsel chip are arranged in a stacking manner, and meanwhile, the conductive cushion layer is arranged between the two layers of packaging adhesive layers, so that the electric connection between the stacked ASIC chip and the Vcsel chip and the substrate can be met, and two cavities are not required to be arranged for respectively packaging the ASIC chip and the Vcsel chip, thereby effectively reducing the transverse occupied space of the packaging structure and further reducing the volume of the packaging structure.
2. According to the invention, the first gold wire is arranged in the first packaging adhesive layer through the first through hole, the fourth gold wire and the fifth gold wire are arranged in the substrate through the second through hole, the electric connection with the Vcsel chip can be realized through the gold wires through the through cushion layer, the diameter of the gold wires in the through holes is larger, the functional requirements of high current and high heat dissipation can be met, and the through holes arranged along the thickness direction enable the gold wires to have good stress adhesion, and simultaneously enable the wiring of the gold wires to be shortest, so that the cost is reduced.
3. According to the invention, as the bonding positions of the second gold wire and the third gold wire are moved to the inside of the chip by bonding in the Vcsel chip, the vertical space required by bonding can be effectively reduced, so that the thickness of the packaging structure is reduced, and the volume of the packaging structure is further reduced.
4. According to the invention, the ASIC chip and the Vcsel chip are covered by the 3D transparent adhesive, and the Vcsel chip and the photosensitive area of the ASIC chip are staggered, so that the photosensitive area of the ASIC chip can be ensured to receive light and the emitted light of the Vcsel chip, and the optical performance of the optical sensor is ensured; meanwhile, a separation is formed by filling a gap between the top of the Vcsel chip and the photosensitive area through the second packaging adhesive layer, so that the Vcsel chip and the ASIC chip are ensured not to cross-talk with each other.
Drawings
FIG. 1 is a schematic diagram of a prior art photosensor package;
FIG. 2 is a schematic structural diagram of a 3D transparent photosensor package structure according to the present invention;
FIG. 3 is a top view of a stack of ASIC chips and Vcsel chips in a 3D transparent light sensor package structure according to the present invention;
fig. 4 is a front view of a stack of ASIC chips and Vcsel chips in a 3D transparent light sensor package structure of the present invention.
In the figure, 1 substrate, 101 fourth gold wire, 102 fifth wire, 2 cover, 3 first chip, 4 second chip, 5ASIC chip, 6Vcsel chip, 601 second gold wire, 602 third gold wire, 7 first encapsulation glue layer, 701 first gold wire, 8 second encapsulation glue layer, 9 3D transparent glue layer, 10 photosensitive area, 11 conductive cushion layer.
Detailed Description
The invention will be further described with reference to the drawings and the specific examples.
Referring to fig. 2, a 3D transparent optical sensor package structure includes a substrate 1, an ASIC (Application Specific Integrated Circuit, i.e., application specific integrated circuit) chip 5, a Vcsel (Vertical-Cavity Surface-Emitting Laser) chip 6, a first encapsulation adhesive layer 7, a second encapsulation adhesive layer 8, a 3D transparent adhesive layer 9, and a conductive pad layer 11; the ASIC chip 5 is attached to the top surface of the substrate 1 and packaged by the first packaging adhesive layer 7; the Vcsel chip 6 is packaged on the top of the ASIC chip 5 through the 3D transparent adhesive layer 9 to form a stacked chip structure, the Vcsel chip 6 is packaged through the second packaging adhesive layer 8, and the top surface of the 3D transparent adhesive layer 9 extends to be above the top surface of the second packaging adhesive layer 8; the conducting pad layer 11 is arranged between the first packaging adhesive layer 7 and the second packaging adhesive layer 8, the conducting pad layer 11 is electrically connected with the Vcsel chip 6 and the substrate 1, and the Vcsel chip 6 is electrically connected with the substrate 1.
The ASIC chip 5 and the Vcsel chip 6 are arranged in a stacking mode, two cavities are not required to be arranged for respectively packaging the ASIC chip 5 and the Vcsel chip 6, and occupation of transverse space can be effectively reduced. The ASIC chip 5 is attached to the substrate 1 by means of conductive silver paste and the like, and the Vcsel chip 6 is connected with the substrate 1 by means of wire bonding, so that the electric connection requirement is met.
The packaging adhesive layer can adopt a two-layer black packaging adhesive structure, namely a first packaging adhesive layer 7 and a second packaging adhesive layer 8, and the first packaging adhesive layer 7 and the second packaging adhesive layer 8 are electrically connected through a conducting cushion layer 11, so that the electric connection between the ASIC chip 5 and the Vcsel chip 6 and the substrate 1 is satisfied. The conductive pad layer 11 may preferably be a metal pad layer.
The 3D transparent adhesive layer 9 is directly formed on the ASIC chip 5 and the Vcsel chip 6 by the 3D transparent adhesive, and the 3D transparent adhesive has a light transmission function, so that the light receiving and transmitting requirements of the ASIC chip 5 and the Vcsel chip 6 can be met. The packaging is filled with black packaging glue at other positions, and the 3D transparent glue layer 9 extends to the upper portion of the top surface of the second packaging glue layer 8, so that the second packaging glue layer 8 is guaranteed not to block the transceiving light rays of the ASIC chip 5 and the Vcsel chip 6.
Referring to fig. 3 and fig. 4, the Vcsel chip 6 is staggered with the photosensitive area 10 on the ASIC chip 5, the 3D transparent adhesive layer 9 covers the top of the Vcsel chip 6 and the photosensitive area 10, and the gap between the top of the Vcsel chip 6 and the photosensitive area 10 is filled by the second encapsulation adhesive layer 8.
The stacked arrangement of the Vcsel chips 6 does not block the light received by the photosensitive area 10 on the ASIC chip 5, and covers the Vcsel chips 6 and the ASIC chip 5 through the 3D transparent adhesive layer 9, so that the packaging effect is ensured while the light received by the photosensitive area 10 and the light emitted by the Vcsel chip 6 are ensured. The separation is formed by the second encapsulation glue layer 8 filling in the gap between the top of the Vcsel chip 6 and the photosensitive area 10, ensuring that the Vcsel chip 6 and the ASIC chip 5 do not cross-talk with each other.
Referring to fig. 4, the top surface of the 3D transparent adhesive layer 9 is an arc surface structure, and light rays can be refracted and transmitted through the arc surface structures with different sizes, so that the light receiving and transmitting requirements of the Vcsel chip 6 and the ASIC chip 5 are met, parasitic light interference is reduced, and the optical performance of the packaging structure is ensured.
Referring to fig. 2, a first through hole (not shown) is formed in the first encapsulation adhesive layer 7 along the thickness direction, a first gold wire 701 is disposed in the first through hole, an upper end of the first gold wire 701 is electrically connected to the conductive pad layer 11, and a lower end of the first gold wire 701 is electrically connected to the substrate 1.
By the arrangement of the first via hole and the first gold wire 701, the electrical connection between the substrate 1 and the via pad 11 is ensured. And the first through hole and the first gold thread 701 are vertically arranged, so that the length of the first gold thread 701 is shortest, and the stress adhesion is ensured.
Referring to fig. 2, the Vcsel chip 6 is internally wired to form a second gold wire 601 and a third gold wire 602, the second gold wire 601 is located in the second encapsulation adhesive layer 8 and is electrically connected to the conductive pad layer 11, and the third gold wire 602 is located in the first encapsulation adhesive layer 7 and is electrically connected to the substrate 1.
The second gold thread 601 and the third gold thread 602 of the Vcsel chip 6 are arranged in an internal wiring mode, the wiring positions of the second gold thread 601 and the third gold thread 602 are moved to the inside of the chip, the vertical height required by wiring can be effectively reduced, the vertical occupied space is saved, and the volume of the packaging structure is reduced.
Referring to fig. 2, the second gold wire 601 and the third gold wire 602 have diameters smaller than those of the first gold wire 701.
Preferably, the diameter of the first gold wire 701 may be twice or more than that of the second gold wire 601 and the third gold wire 602, so as to satisfy the functional requirements of high current and high heat dissipation.
Referring to fig. 2, a plurality of second through holes (not shown) are formed in the substrate 1 along the thickness direction, the fourth gold wires 101 and the fifth gold wires 102 are respectively disposed in the plurality of second through holes, the upper ends of the fourth gold wires 101 are electrically connected with the first gold wires 701, the upper ends of the fifth gold wires 102 are electrically connected with the third gold wires 602, and the lower ends of the fourth gold wires 101 and the fifth gold wires 102 are respectively led out to the bottom surface of the substrate 1.
Through the setting of second through-hole and fourth gold thread 101, fifth wire 102, can satisfy ASIC chip 5 and Vcsel chip 6 and the electric connection of packaging structure external component, simultaneously, can outwards dispel the inside heat of packaging structure through fourth gold thread 101, fifth wire 102, satisfy high current and high radiating functional demand.
Referring to fig. 2, the diameters of the fourth gold wire 101 and the fifth gold wire 102 are larger than the diameter of the third gold wire 602.
Preferably, the diameters of the fourth gold wire 101 and the fifth gold wire 102 may be twice or more than the diameter of the third gold wire 602, satisfying the functional requirements of high current and high heat dissipation.
Referring to fig. 2, the conducting pad layer 11 is located at the interface between the first encapsulation adhesive layer 7 and the second encapsulation adhesive layer 8, and the conducting pad layer 11 is slightly higher than the bottom surface of the 3D transparent adhesive layer 9.
The height of the conducting pad layer 11 can be adaptively adjusted according to the routing position of the Vcsel chip 6, so that the second gold wire 601 is electrically connected with the conducting pad layer 11, and the arrangement of the conducting pad layer 11 cannot interfere with the routing of the third gold wire 602.
The substrate 1 is a laminated substrate, and is composed of a base material, a laminated board, a solder mask and silk screen printing, and is produced by adopting a PCB (printed Circuit Board) manufacturing lamination process.
Referring to fig. 2 to 4, the production process of the present invention is as follows:
the substrate 1 can complete the layout of the fourth gold wires 101 and the fifth wires 102 in a production factory according to the circuit design requirement. The ASIC chip 5 is mounted on the substrate 1 through conductive silver adhesive, the Vcsel chip 6 is packaged on a non-photosensitive area of the ASIC chip 5 through a 3D transparent adhesive layer 9, and the Vcsel chip is staggered with the photosensitive area 10.
A first encapsulation glue layer 7 is encapsulated on the substrate 1 for encapsulating the ASIC chip 5 and the bottom of the Vcsel chip 6, and a conductive pad layer 11 is attached to the top surface of the first encapsulation glue layer 7. When the first packaging adhesive layer 7 is packaged, a first conducting through hole is reserved and used for arranging a first gold wire 701, so that the first gold wire 701 forms electrical connection between the fourth gold wire 101 of the substrate 1 and the conducting pad layer 11; the bottom of the Vcsel chip 6 is internally wired to form a third gold wire 602, and the third gold wire 602 is electrically connected to the fifth gold wire 102 of the substrate 1.
The Vcsel chip 6 is internally wired at the upper part to form a second gold wire 601, and the second gold wire 601 is electrically connected with the conductive pad layer 11. A second encapsulation glue layer 8 is encapsulated on the first encapsulation glue layer 7 for encapsulating the Vcsel chip 6 and filling in the gap between the Vcsel chip 6 and the photosensitive area 10 for isolating the interference of the received light. The top surface of the second packaging adhesive layer 8 is slightly lower than the top surface of the 3D transparent adhesive layer 9 when packaging.
The foregoing description of the preferred embodiments of the invention is not intended to limit the scope of the invention, and therefore, any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A3D transparent light sensor packaging structure is characterized in that: the packaging structure comprises a substrate (1), an ASIC chip (5), a Vcsel chip (6), a first packaging adhesive layer (7), a second packaging adhesive layer (8), a 3D transparent adhesive layer (9) and a conducting cushion layer (11); the ASIC chip (5) is attached to the top surface of the substrate (1) and packaged through the first packaging adhesive layer (7); the Vcsel chip (6) is packaged at the top of the ASIC chip (5) through a 3D transparent adhesive layer (9) to form a stacked chip structure, the Vcsel chip (6) is packaged through a second packaging adhesive layer (8), and the top surface of the 3D transparent adhesive layer (9) extends to the position above the top surface of the second packaging adhesive layer (8); the conducting cushion layer (11) is arranged between the first packaging adhesive layer (7) and the second packaging adhesive layer (8), the conducting cushion layer (11) is electrically connected with the Vcsel chip (6) and the substrate (1), and the Vcsel chip (6) is electrically connected with the substrate (1).
2. The 3D transparent light sensor package of claim 1, wherein: the Vcsel chip (6) and the photosensitive area (10) on the ASIC chip (5) are staggered, the 3D transparent adhesive layer (9) covers the top of the Vcsel chip (6) and the photosensitive area (10), and a gap between the top of the Vcsel chip (6) and the photosensitive area (10) is filled by the second packaging adhesive layer (8).
3. The 3D transparent light sensor package according to claim 1 or 2, characterized in that: the top surface of 3D transparent glue film (9) be cambered surface structure.
4. The 3D transparent light sensor package of claim 1, wherein: a first conducting through hole is formed in the first packaging adhesive layer (7) along the thickness direction, a first gold wire (701) is arranged in the first conducting through hole, the upper end of the first gold wire (701) is electrically connected with the conducting cushion layer (11), and the lower end of the first gold wire (701) is electrically connected with the substrate (1).
5. The 3D transparent light sensor package of claim 1, wherein: the Vcsel chip (6) is internally wired to form a second gold wire (601) and a third gold wire (602), the second gold wire (601) is positioned in the second packaging adhesive layer (8) and is electrically connected with the conducting cushion layer (11), and the third gold wire (602) is positioned in the first packaging adhesive layer (7) and is electrically connected with the substrate (1).
6. The 3D transparent light sensor package of claim 5, wherein: the diameters of the second gold wire (601) and the third gold wire (602) are smaller than those of the first gold wire (701).
7. The 3D transparent light sensor package of claim 5, wherein: a plurality of second conducting through holes are formed in the substrate (1) along the thickness direction, fourth gold wires (101) and fifth gold wires (102) are respectively arranged in the plurality of second conducting through holes, the upper ends of the fourth gold wires (101) are electrically connected with the first gold wires (701), the upper ends of the fifth gold wires (102) are electrically connected with the third gold wires (602), and the lower ends of the fourth gold wires (101) and the fifth gold wires (102) are respectively led out to the bottom surface of the substrate (1).
8. The 3D transparent light sensor package of claim 7, wherein: the diameters of the fourth gold wire (101) and the fifth gold wire (102) are larger than those of the third gold wire (602).
9. The 3D transparent light sensor package of claim 1, wherein: the conducting cushion layer (11) is positioned at the interface of the first packaging adhesive layer (7) and the second packaging adhesive layer (8), and the conducting cushion layer (11) is higher than the bottom surface of the 3D transparent adhesive layer (9).
10. The 3D transparent light sensor package of any one of claims 1, 4, 5, 7, wherein: the substrate (1) is a laminated substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311137129.2A CN117199063A (en) | 2023-09-05 | 2023-09-05 | 3D transparent light sensor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311137129.2A CN117199063A (en) | 2023-09-05 | 2023-09-05 | 3D transparent light sensor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117199063A true CN117199063A (en) | 2023-12-08 |
Family
ID=88982871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311137129.2A Pending CN117199063A (en) | 2023-09-05 | 2023-09-05 | 3D transparent light sensor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117199063A (en) |
-
2023
- 2023-09-05 CN CN202311137129.2A patent/CN117199063A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100480437B1 (en) | Semiconductor chip package stacked module | |
| CN103632988B (en) | Package-on-package structure and preparation method thereof | |
| US7893528B2 (en) | Package structure of compound semiconductor device and fabricating method thereof | |
| US7495327B2 (en) | Chip stacking structure | |
| KR100809702B1 (en) | Semiconductor package | |
| CN102160197A (en) | Optoelectronic device submount | |
| CN210167054U (en) | LED lamp bead and transparent LED display screen | |
| KR20080027586A (en) | Semiconductor die module and package and fabricating method of semicondctor package | |
| CN102176450B (en) | High-density system-in-package structure | |
| US8049244B2 (en) | Package substrate and light emitting device using the same | |
| KR100664796B1 (en) | Side braze package | |
| CN220821567U (en) | 3D transparent light sensor packaging structure | |
| CN117199063A (en) | 3D transparent light sensor packaging structure | |
| CN214956944U (en) | Light emitting package module | |
| CN102157502B (en) | System-in-package structure | |
| CN213304137U (en) | LED light source structure and display device | |
| CN201994292U (en) | High-density system-level packaging structure | |
| KR20110055985A (en) | Stack package | |
| JP2004134414A (en) | Package structure of surface mount light emitting diode and method for manufacturing the same | |
| KR20040048818A (en) | Circuit device | |
| KR101625253B1 (en) | Surface-mountable apparatus | |
| KR100447894B1 (en) | Dual stacked package for increasing mount density and fabricating method thereof | |
| KR20140106278A (en) | Light emitting device package and method for manufacturing the same | |
| CN219163395U (en) | 3D stacks up packaging structure | |
| CN217643858U (en) | Structure for reducing chip paster combination height |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |