CN117133806A - Natural super-junction GaN HEMT device and preparation method thereof - Google Patents
Natural super-junction GaN HEMT device and preparation method thereof Download PDFInfo
- Publication number
- CN117133806A CN117133806A CN202311374634.9A CN202311374634A CN117133806A CN 117133806 A CN117133806 A CN 117133806A CN 202311374634 A CN202311374634 A CN 202311374634A CN 117133806 A CN117133806 A CN 117133806A
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode
- barrier layer
- gan
- channel layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 96
- 229910052751 metal Inorganic materials 0.000 claims description 42
- 239000002184 metal Substances 0.000 claims description 42
- 238000005530 etching Methods 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 18
- 239000004047 hole gas Substances 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 15
- 239000003989 dielectric material Substances 0.000 claims description 13
- 229910004205 SiNX Inorganic materials 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000227 grinding Methods 0.000 claims description 5
- 229910002704 AlGaN Inorganic materials 0.000 abstract description 31
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000009286 beneficial effect Effects 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 249
- 238000000206 photolithography Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 5
- 239000010980 sapphire Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- -1 siC Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
Compared with the traditional design, the device introduces a back barrier layer below a GaN channel layer to form a double heterojunction structure, and the interfaces of the barrier layer and the channel layer and the interface of the channel layer and the back barrier layer respectively generate 2DEG and 2DHG, which are similar to the natural super junction structure. When the device is turned off, the drain electrode is electrified, the 2DEG and the 2DHG are simultaneously exhausted through the electric field in the vertical direction, an additional field plate is not required to be added, and the withstand voltage of the device is improved by overlapping the vertical component on the original basis. The p-i-n diode is formed by the back barrier layer AlGaN/the channel layer GaN/the barrier layer AlGaN, and the parasitic pin diode can be used for reverse conduction, thereby being beneficial to reducing reverse conduction voltage drop, reducing switching loss and improving working efficiency.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a natural super-junction GaN HEMT device and a preparation method thereof.
Background
The GaN material series has low heat generation rate and high breakdown electric field, and is an important material for developing high-temperature high-power electronic devices and high-frequency microwave devices. At present, with the progress of MBE technology in GaN material application and the breakthrough of key film growth technology, a plurality of GaN heterostructures are successfully grown. Novel devices such as a metal field effect transistor (MESFET), a Heterojunction Field Effect Transistor (HFET), a modulation doped field effect transistor (MODFET) and the like are prepared by adopting a GaN material. The modulated doped AlGaN/GaN structure has high electron mobility (2000 cm < 2 >/v.s), high saturation velocity (1X 107 cm/s) and lower dielectric constant, and is a preferential material for manufacturing microwave devices; gaN has a wider forbidden bandwidth (3.4 eV), and sapphire and other materials are used as substrates, so that the GaN-based semiconductor device has good heat dissipation performance and is beneficial to the operation of the device under a high-power condition.
The GaN power device generally adopts a transverse device structure based on AlGaN/GaN heterojunction due to substrate heteroepitaxy, and the electron mobility of a channel and a drift region is improved due to the existence of heterojunction Two-dimensional electron gas (Two-Dimensional Electron Gas,2 DEG), but the drift region 2DEG has larger depletion difficulty under the off state due to concentrated electron distribution and high density in the 2DEG and no PN junction structure, and the electric field distribution is concentrated, so that the depletion region area is enlarged by designing a complex field plate structure, the uniformity of the electric field distribution is improved, the process complexity is increased, and the yield of finished products is reduced.
Disclosure of Invention
The application aims to overcome the problems in the prior art and provides a natural super-junction GaN HEMT device and a preparation method thereof.
The aim of the application is realized by the following technical scheme: the utility model provides a natural super junction GaN HEMT device, this device specifically includes substrate, buffer layer, channel layer, barrier layer, P-GaN layer and the gate electrode that from bottom to top grows, and active electrode and drain electrode are grown relatively to the channel layer both sides, and the gate electrode is P-GaN schottky contact electrode, its characterized in that: a back barrier layer is introduced between the buffer layer and the channel layer, the back barrier layer, the channel layer and the barrier layer form a double heterojunction structure, and two-dimensional electron gas and two-dimensional hole gas are respectively generated at the interface between the barrier layer and the channel layer and the interface between the channel layer and the back barrier layer;
and a body electrode grows on the back barrier layer, the body electrode forms ohmic contact with the two-dimensional hole gas, and the source electrode, the drain electrode and the two-dimensional electron gas form ohmic contact.
In one example, a dielectric layer is grown in the channel layer between the body electrode and the source electrode.
In one example, the dielectric layer is SiNx, siO 2 And any one of high-k dielectric materials, wherein the dielectric constant k is more than 3.9.
In an example, the buffer layer is any one or any combination of a plurality of AlN, alGaN, gaN, siN.
In one example, the double heterojunction structure is formed based on a group III-nitride based material.
It should be further noted that the technical features corresponding to the examples above may be combined with each other or replaced to form a new technical solution.
The application also comprises a preparation method of the natural super-junction GaN HEMT device, which is used for preparing the GaN HEMT device formed by any one or more examples, and comprises the following steps:
sequentially growing a buffer layer, a back barrier layer, a channel layer, a barrier layer and a P-GaN layer on a substrate;
depositing gate metal on the P-GaN layer, photoetching to form a gate region, etching to remove the gate metal outside the gate region, and removing the photoresist and the P-GaN layer outside the metal region to form a gate electrode;
forming a source ohmic contact region and a drain ohmic contact region on the channel layer by photoetching the barrier layer, depositing a metal layer on the channel layer, forming a source electrode and a drain electrode by photoetching stripping, and carrying out annealing treatment to enable the source electrode and the drain electrode to form ohmic contact with two-dimensional electron gas;
photoetching to form a body electrode etching window;
and depositing body electrode metal on the back barrier layer, removing the metal layer outside the body electrode area, and carrying out annealing treatment to enable the body electrode and the two-dimensional hole gas to form ohmic contact.
In one example, after lithographically forming the bulk electrode etch window, the method further comprises, prior to depositing the bulk electrode metal:
and etching to remove the barrier layer and part of the channel layer, removing the photoresist, depositing a dielectric layer on the etched surface of the channel layer, and removing the dielectric material outside the dielectric region.
In one example, the annealing process to form ohmic contact between the bulk electrode and the two-dimensional hole gas further comprises:
depositing insulating layers on the source electrode, the drain electrode and the gate electrode, grinding, etching the insulating layers above the source electrode, the drain electrode and the gate electrode to form a through hole, depositing interconnection metal, and manufacturing a source electrode PAD, a drain electrode PAD and a gate electrode PAD.
It should be further noted that the technical features corresponding to the examples of the above method may be combined with each other or replaced to form a new technical scheme.
The application also comprises a depletion type natural super-junction GaN HEMT device, the depletion type natural super-junction GaN HEMT device (enhanced device) formed by combining any one or more examples has the same application conception, the device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a gate dielectric layer and a gate electrode which are grown from bottom to top, wherein active electrodes and drain electrodes are oppositely grown on two sides of the channel layer, and the gate electrode is an MIS structure;
and a body electrode grows on the back barrier layer, the body electrode forms ohmic contact with the two-dimensional hole gas, and the source electrode, the drain electrode and the two-dimensional electron gas form ohmic contact.
In one example, a dielectric layer is grown in the channel layer between the body electrode and the source electrode.
In one example, the dielectric layer is SiNx, siO 2 And any one of high-k dielectric materials, wherein the dielectric constant k is more than 3.9.
In one example, the gate dielectric layer is SiNx, siO 2 Any one of the high-k dielectric materials, wherein the dielectric constant k is more than 3.9; optionally, the gate dielectric layer has a laminated structure, which may include multiple sub-gate dielectric layers, and may also have a single-layer structure.
In an example, the buffer layer is any one or any combination of a plurality of AlN, alGaN, gaN, siN.
In one example, the double heterojunction structure is formed based on a group III-nitride based material.
The application also discloses a preparation method of the depletion type natural super-junction GaN HEMT device, which comprises the following steps:
sequentially growing a buffer layer, a back barrier layer, a channel layer, a barrier layer and a gate dielectric layer on a substrate;
depositing gate metal on the gate dielectric layer, photoetching to form a gate region, etching to remove the gate metal outside the gate region, and annealing to form a gate electrode;
forming a source ohmic contact region and a drain ohmic contact region on the channel layer by photoetching the barrier layer, etching to remove gate dielectric layers of the source ohmic contact region and the drain ohmic contact region, depositing a metal layer on the channel layer, photoetching and stripping to form a source electrode and a drain electrode, and performing annealing treatment to enable the source electrode, the drain electrode and two-dimensional electron gas to form ohmic contact;
photoetching to form a body electrode etching window;
and depositing body electrode metal on the back barrier layer, removing the metal layer outside the body electrode area, and carrying out annealing treatment to enable the body electrode and the two-dimensional hole gas to form ohmic contact.
In one example, after lithographically forming the bulk electrode etch window, the method further comprises, prior to depositing the bulk electrode metal:
etching to remove the gate dielectric layer, the barrier layer and part of the channel layer, removing the photoresist, depositing the dielectric layer on the etched surface of the channel layer, and removing the dielectric material outside the dielectric region.
In one example, the annealing process to form ohmic contact between the bulk electrode and the two-dimensional hole gas further comprises:
depositing insulating layers on the source electrode, the drain electrode and the gate electrode, grinding, etching the insulating layers above the source electrode, the drain electrode and the gate electrode to form a through hole, depositing interconnection metal, and manufacturing a source electrode PAD, a drain electrode PAD and a gate electrode PAD.
Compared with the prior art, the application has the beneficial effects that:
according to the application, a back barrier layer is introduced to form a double heterojunction structure, the double heterojunction structure is similar to a natural super junction structure, a body electrode in ohmic contact with 2DHG is combined, when the device is turned off, the drain electrode is high in voltage, two-dimensional electron gas (Two-Dimensional Electron Gas,2 DEG) and Two-dimensional hole gas (Two-dimensional hole gas,2 DHG) are firstly exhausted through an electric field in the vertical direction at the same time, an additional field plate is not required to be added, and the withstand voltage of the device is improved by superposing a vertical component on the original basis; when the device is on, the device current is determined by the 2DEG, and the 2DHG does not participate in conduction because no current path exists. Furthermore, the p-i-n diode is formed by the back barrier layer AlGaN/the channel layer GaN/the barrier layer AlGaN, and the parasitic pin diode can be used for reverse conduction, has lower reverse conduction voltage drop compared with the traditional GaN HEMT, is beneficial to reducing the switching loss of a power supply system and improves the efficiency.
Drawings
The following detailed description of the present application is provided in connection with the accompanying drawings, which are included to provide a further understanding of the application, and in which like reference numerals are used to designate like or similar parts throughout the several views, and in which are shown by way of illustration of the application and not limitation thereof.
Fig. 1 is a schematic diagram of a HEMT device according to an example of the present application;
fig. 2 is a schematic diagram of a HEMT device incorporating a dielectric layer in an example of the present application;
fig. 3 is a schematic view of a HEMT device according to an example of the present application, where the HEMT device is obtained in step S1;
fig. 4 is a schematic view of a HEMT device according to an example of the present application, where the HEMT device is obtained in step S2;
fig. 5 is a schematic view of a HEMT device according to an example of the present application, where the HEMT device is prepared in step S3;
fig. 6 is a schematic view of a HEMT device according to an example of the present application, where the HEMT device is prepared in step S4;
fig. 7 is a schematic view of a HEMT device according to an example of the present application, where the HEMT device is prepared in step S5;
fig. 8 is a schematic diagram of a device obtained after a dielectric layer is prepared in step S4 according to a HEMT device preparation method in an example of the present application;
fig. 9 is a schematic diagram of a depletion mode HEMT device according to an example of the present application;
fig. 10 is a schematic diagram of a depletion mode HEMT device incorporating a dielectric layer in an example of the present application;
fig. 11 is a schematic view of a device obtained in step S1' of a preparation method of a depletion mode HEMT device in an example of the present application;
fig. 12 is a schematic view of a device obtained in step S2' of the preparation method of a depletion mode HEMT device in an example of the present application;
fig. 13 is a schematic view of a device obtained in step S3' of the preparation method of a depletion mode HEMT device in an example of the present application;
fig. 14 is a schematic view of a device obtained in step S4' of the preparation method of a depletion mode HEMT device in an example of the present application;
fig. 15 is a schematic view of a device obtained in step S5' of the preparation method of a depletion mode HEMT device according to an example of the present application;
fig. 16 is a schematic diagram of a device obtained after a dielectric layer is prepared in step S4' according to the preparation method of a depletion mode HEMT device in an example of the present application.
In the figure: 1-substrate, 2-buffer layer, 3-back barrier layer, 4-channel layer, 5-barrier layer, 6-P-GaN layer, 7-gate electrode, 8-source electrode, 9-drain electrode, 10-body electrode, 11-dielectric layer;
a 1' -substrate, a 2' -buffer layer, a 3' -back barrier layer, a 4' -channel layer, a 5' -barrier layer, a 6' -gate dielectric layer, a 7' -gate electrode, an 8' -source electrode, a 9' -drain electrode, a 10' -body electrode and an 11' -dielectric layer.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully understood from the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that directions or positional relationships indicated as being "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are directions or positional relationships described based on the drawings are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. Further, ordinal words (e.g., "first and second," "first through fourth," etc.) are used to distinguish between objects, and are not limited to this order, but rather are not to be construed to indicate or imply relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
In an example, as shown in fig. 1, a natural super-junction GaN HEMT device includes, from bottom to top, a substrate 1, a buffer layer 2, a back barrier layer 3, a channel layer 4, a barrier layer 5, a P-GaN layer 6, and a gate electrode 7, where an active electrode 8 and a drain electrode 9 are grown on two sides of the channel layer 4, and the gate electrode 7 is a P-GaN schottky contact electrode; the back barrier layer 3, the channel layer 4 and the barrier layer 5 form a double heterojunction structure, and the interfaces of the barrier layer 5 and the channel layer 4 and the interfaces of the channel layer 4 and the back barrier layer 3 respectively generate 2DEG and 2DHG; a body electrode 10 grows on the back barrier layer 3, the body electrode 10 forms ohmic contact with two-dimensional hole gas, and a source electrode 8 and a drain electrode 9 form ohmic contact with two-dimensional electron gas.
Wherein, the material of the substrate is any one of Si, diamond, siC, sapphire and GaN, and the example is sapphire. The buffer layer is any one or combination of AlN, alGaN, gaN, siN, and is AlGaN in this example, and the thickness is 5 μm. The double heterojunction structure is formed based on group III-nitride materials, that is, the back barrier layer, the channel layer and the barrier layer are all group III-nitride materials, for example, two or more of GaN, alGaN, inN, alN, inGaN, inAlGaN are combined, and the channel layer is different from the back barrier layer and the barrier layer, so that the double heterojunction can be AlGaN/GaN/AlGaN, alInN/GaN/AlInN, alGaN/InGaN/GaN, and the like, and the back barrier layer is AlGaN layer, the channel layer is GaN layer, and the barrier layer is AlGaN layer. More specifically, the channel layer was 300nm, the AlGaN barrier layer was 12nm, and the Al component was 25%. Further, any one or more of Source electrode and Drain electrode Ti, al, ni, au, in this example, the Source electrode (Source) and Drain electrode (Drain) are sequentially Ti/Al/Ni/Au, where the Ti thickness is 20nm, the Al thickness is 120nm, the Ni thickness is 45nm, and the Au thickness is 55nm. Furthermore, the source electrode is a composite electrode of a traditional source electrode and a body electrode, namely, the ohmic contact formed by adopting metal Ti/Al/Ni/Au or Ti/Al/TiN and 2DEG is used as the traditional source electrode, and meanwhile, the ohmic contact formed by using Pd and other metals and 2DHG is used as the body electrode.
The back barrier layer is introduced between the buffer layer and the channel layer to form a double heterojunction structure of the back barrier layer/the channel layer/the barrier layer, in particular an AlGaN/GaN/AlGaN double heterojunction structure, which is similar to a natural super junction structure, and is combined with a body electrode which forms ohmic contact with 2DHG, when the device is turned off, the drain electrode is high in voltage, the 2DEG and the 2DHG are simultaneously depleted through an electric field in the vertical direction, an additional field plate is not required to be added, and the withstand voltage of the device is improved by superposing a vertical component on the original basis; when the device is on, the device current is determined by the 2DEG, and the 2DHG does not participate in conduction because no current path exists. Furthermore, the p-i-n diode is formed by the back barrier layer AlGaN/the channel layer GaN/the barrier layer AlGaN, and the parasitic pin diode can be used for reverse conduction, has lower reverse conduction voltage drop compared with the traditional GaN HEMT, is beneficial to reducing the switching loss of a power supply system and improves the efficiency.
In one example, as shown in FIG. 2An insulating dielectric layer 11 is grown in the channel layer 4, that is, the bottom of the dielectric layer 11 extends into the channel layer 4, and the dielectric layer 11 is located between the body electrode 10 and the source electrode 8, so as to prevent the body electrode from being in direct contact with the 2DEG to form schottky contact, and the concentration of the 2DEG near the source electrode is reduced, so that the on-resistance of the device is increased. Optionally, the dielectric layer is SiNx, siO 2 Any of the high k (k > 3.9) dielectric materials, in this example SiO 2 A layer.
The application also discloses a preparation method of the natural super-junction GaN HEMT device, which comprises the following steps:
s1: as shown in fig. 3, a buffer layer 2, a back barrier layer 3, a channel layer 4, a barrier layer 5, and a P-GaN layer 6 are sequentially grown on a substrate 1; wherein the buffer layer is 1 μm-3 μm; the thickness of the channel layer is 300nm; the barrier layer is 10nm-15nm. When the P-GaN layer is prepared, a layer of Mg-doped GaN layer is grown on the barrier layer by using an MOCVD process, and the Mg-doped GaN cap layer is annealed, so that the P-GaN layer is manufactured.
S2: as shown in fig. 4, a gate metal is deposited on the P-GaN layer 6, a gate (gate) region is formed by photolithography, the gate metal outside the gate region is removed by etching, the photoresist is removed, and the P-GaN layer outside the metal region is removed by etching to form a gate electrode 7;
s3: as shown in fig. 5, the photolithographic barrier layer 5 further forms a source ohmic contact region and a drain ohmic contact region on the channel layer 4, a metal layer is deposited on the channel layer 4, a source electrode 8 and a drain electrode 9 are formed by photolithographic lift-off (lift-off), and annealing treatment is performed to form ohmic contact between the source electrode and the drain electrode and the two-dimensional electron gas;
s4: as shown in fig. 6, the body electrode 10 is formed by photolithography to etch a window extending to the surface of the back barrier layer 3;
s5: as shown in fig. 7, a bulk electrode metal is deposited on the back barrier layer 3, a metal layer outside the bulk electrode region is removed by photolithography and etching, and an annealing treatment is performed to form ohmic contact between the bulk electrode 10 and the two-dimensional hole gas.
In an example, after the body electrode etching window is formed by photolithography in step S4, the method further includes:
as shown in fig. 8, the barrier layer 5 and part of the channel layer 4 are etched and removed, photoresist is removed, a dielectric layer 11 between the bulk electrode 10 and the source electrode 8 is deposited on the etched surface (upper middle portion of the channel layer) of the channel layer 4, and the dielectric material in the area except the side wall of the electrode is removed by using the photolithography etching technology, and then the bulk electrode 10 is prepared again, so as to obtain the HEMT device of the preferred example shown in fig. 2.
In an example, step S5 further includes:
s6: depositing an insulating layer on the source electrode, the drain electrode and the gate electrode, grinding, etching the insulating layer above the source-drain gate metal by photoetching to form a through hole, depositing interconnection metal, and manufacturing PAD (bonding PAD) of the source electrode, the drain electrode and the gate electrode.
According to the application, by referring to the structural characteristics of the Si super-junction device, an AlGaN back barrier layer is introduced between a buffer layer and a GaN channel layer on the basis of a traditional GaN HEMT, so that an AlGaN/GaN/AlGaN double-heterojunction structure is formed, and 2EDG and 2DHG are respectively generated at the interfaces of AlGaN/GaN and GaN/AlGaN heterojunctions, and the structure is similar to a natural super-junction structure. Ohmic contact is formed between the 2DHG and the body electrode on the basis of the traditional GaN HEMT, the body electrode is connected with the source electrode, when the device is turned off, the drain electrode is electrified, the 2DEG and the 2DHG are simultaneously exhausted through an electric field in the vertical direction, an additional field plate is not required to be added, and the withstand voltage of the device is improved by overlapping a vertical component on the original basis; when the device is on, the device current is determined by the 2DEG, and the 2DHG does not participate in conduction because no current path exists.
The application also comprises a depletion type natural super-junction GaN HEMT device, which has the same technical conception as the natural super-junction GaN HEMT device formed by combining any one or more examples, and as shown in fig. 9, the depletion type natural super-junction GaN HEMT device sequentially comprises a substrate 1', a buffer layer 2', a back barrier layer 3', a channel layer 4', a barrier layer 5', a gate dielectric layer 6' and a gate electrode 7', wherein active electrodes 8' and drain electrodes 9' are oppositely grown on two sides of the channel layer 4', and the gate electrode 7' is of an MIS structure; the back barrier layer 3', the channel layer 4', the barrier layer 5' form a double heterojunction structure, and the interfaces of the barrier layer 5' and the channel layer 4' and the interfaces of the channel layer 4' and the back barrier layer 3' respectively generate 2DEG and 2DHG; a bulk electrode 10' is grown on the back barrier layer 3', the bulk electrode 10' forms ohmic contact with the two-dimensional hole gas, and the source electrode 8', the drain electrode 9' form ohmic contact with the two-dimensional electron gas.
Wherein, the material of the substrate is any one of Si, diamond, siC, sapphire and GaN, and the example is sapphire. The buffer layer is any one or combination of AlN, alGaN, gaN, siN, in this example AlGaN, with a thickness of 5 μm. The double heterojunction structure is formed based on group III-nitride materials, i.e., the back barrier layer, the channel layer, and the barrier layer are group III-nitride materials, for example, a combination of two or more of GaN, alGaN, inN, alN, inGaN, inAlGaN, and the channel layer is different from the back barrier layer and the barrier layer, where the double heterojunction may be AlGaN/GaN/AlGaN, alInN/GaN/AlInN, alGaN/InGaN/GaN, and the like, and the back barrier layer is AlGaN layer, the channel layer is GaN layer, and the barrier layer is AlGaN layer. More specifically, the channel layer was 300nm, the AlGaN barrier layer was 20nm, and the Al component was 25%. Further, any one or more of Source electrode and Drain electrode Ti, al, ni, au, in this example, the Source electrode (Source) and Drain electrode (Drain) are sequentially Ti/Al/Ni/Au, where the Ti thickness is 20nm, the Al thickness is 120nm, the Ni thickness is 45nm, and the Au thickness is 55nm. Furthermore, the source electrode is a composite electrode of a traditional source electrode and a body electrode, namely, the ohmic contact formed by adopting metal Ti/Al/Ni/Au or Ti/Al/TiN and 2DEG is used as the traditional source electrode, and meanwhile, the ohmic contact formed by using Pd and other metals and 2DHG is used as the body electrode. Further, the gate dielectric layer is SiNx, siO 2 Any of the high-k dielectric material layers, this example is preferably SiNx; optionally, the gate dielectric layer is a stacked structure and includes a plurality of overlapped sub-gate dielectric layers.
The back barrier layer is introduced between the buffer layer and the channel layer to form a double heterojunction structure of the back barrier layer/the channel layer/the barrier layer, in particular an AlGaN/GaN/AlGaN double heterojunction structure, which is similar to a natural super junction structure, and is combined with a body electrode which forms ohmic contact with 2DHG, when the device is turned off, the drain electrode is high in voltage, the 2DEG and the 2DHG are simultaneously depleted through an electric field in the vertical direction, an additional field plate is not required to be added, and the withstand voltage of the device is improved by superposing a vertical component on the original basis; when the device is on, the device current is determined by the 2DEG, and the 2DHG does not participate in conduction because no current path exists. Furthermore, the p-i-n diode is formed by the back barrier layer AlGaN/the channel layer GaN/the barrier layer AlGaN, and the parasitic pin diode can be used for reverse conduction, has lower reverse conduction voltage drop compared with the traditional GaN HEMT, is beneficial to reducing the switching loss of a power supply system and improves the efficiency.
In an example, as shown in fig. 10, an insulating dielectric layer 11' is grown in the channel layer 4', that is, the bottom of the dielectric layer 11' extends into the channel layer 4', and the dielectric layer 11' is located between the body electrode 10' and the source electrode 8', so as to prevent the body electrode from being in direct contact with the 2DEG to form schottky contact, which causes the concentration of the 2DEG near the source to decrease, resulting in an increase in on-resistance of the device. Optionally, the dielectric layer is SiNx, siO 2 Any of the high k (k > 3.9) dielectric materials, in this example SiO 2 A layer.
The application also discloses a preparation method of the depletion type natural super-junction GaN HEMT device, which comprises the following steps:
s1': as shown in fig. 11, a buffer layer 2', a back barrier layer 3', a channel layer 4', a barrier layer 5', and a gate dielectric layer 6 'are sequentially grown on a substrate 1'; wherein the buffer layer is 1 μm-3 μm; the thickness of the channel layer is 300nm; the barrier layer is 20nm-25nm. When the gate dielectric layer is prepared, a layer of SiNx layer is grown on the barrier layer in situ by using an MOCVD process, or SiO2 is grown by using a PECVD method, or a high-k dielectric is grown by using an atomic layer deposition method, or multiple dielectrics are overlapped, so that the gate dielectric layer is manufactured.
S2': as shown in fig. 12, a gate metal is deposited on the gate dielectric layer 6', a gate (gate) region is formed by photolithography, the gate metal outside the gate region is removed by etching, photoresist is removed, and a gate electrode 7 is formed by annealing;
s3': as shown in fig. 13, the photoetching barrier layer 5' further forms a source ohmic contact region and a drain ohmic contact region on the channel layer 4', etches and removes the gate dielectric layers of the source ohmic contact region and the drain ohmic contact region, deposits a metal layer on the channel layer 4', forms a source electrode 8' and a drain electrode 9' by photoetching stripping (lift-off), and performs annealing treatment to form ohmic contact between the source electrode and the drain electrode and the two-dimensional electron gas;
s4': as shown in fig. 14, the body electrode 10 'is formed by photolithography to etch a window extending to the surface of the back barrier layer 3';
s5': as shown in fig. 15, a bulk electrode metal is deposited on the back barrier layer 3', the metal layer outside the bulk electrode region is removed by photolithography and etching, and an annealing process is performed to form ohmic contact between the bulk electrode 10' and the two-dimensional hole gas.
In an example, after the body electrode etching window is formed by photolithography in step S4', the method further includes:
as shown in fig. 16, the gate dielectric layer 6', the barrier layer 5' and a part of the channel layer 4 'are etched and removed, photoresist is removed, a dielectric layer 11' between the bulk electrode 10 'and the source electrode 8' is deposited on the etched surface (upper middle portion of the channel layer) of the channel layer 4', and the dielectric material in the area except the side wall of the electrode is removed by using the photolithography etching technology, and then the bulk electrode 10' is prepared, so as to obtain the depletion type HEMT device of the preferred example shown in fig. 2.
In an example, step S5' further includes:
s6': depositing an insulating layer on the source electrode, the drain electrode and the gate electrode, grinding, etching the insulating layer above the source-drain gate metal by photoetching to form a through hole, depositing interconnection metal, and manufacturing PAD of the source electrode, the drain electrode and the gate electrode.
The foregoing detailed description of the application is provided for illustration, and it is not to be construed that the detailed description of the application is limited to only those illustration, but that several simple deductions and substitutions can be made by those skilled in the art without departing from the spirit of the application, and are to be considered as falling within the scope of the application.
Claims (8)
1. The utility model provides a natural super junction GaN HEMT device, includes substrate, buffer layer, channel layer, barrier layer, P-GaN layer and the gate electrode that from bottom to top grows, and active electrode and drain electrode are grown relatively to the channel layer both sides, and the gate electrode is P-GaN schottky contact electrode, its characterized in that: a back barrier layer is introduced between the buffer layer and the channel layer, the back barrier layer, the channel layer and the barrier layer form a double heterojunction structure, and two-dimensional electron gas and two-dimensional hole gas are respectively generated at the interface between the barrier layer and the channel layer and the interface between the channel layer and the back barrier layer;
and a body electrode grows on the back barrier layer, the body electrode forms ohmic contact with the two-dimensional hole gas, and the source electrode, the drain electrode and the two-dimensional electron gas form ohmic contact.
2. The natural super-junction GaN HEMT device of claim 1, wherein: and a dielectric layer is grown in the channel layer and is positioned between the body electrode and the source electrode.
3. The natural super-junction GaN HEMT device of claim 2, wherein: the dielectric layer is SiNx, siO 2 And any one of high-k dielectric materials, wherein the dielectric constant k is more than 3.9.
4. The natural super-junction GaN HEMT device of claim 1, wherein: the buffer layer is any one or any combination of a plurality of AlN, alGaN, gaN, siN.
5. The natural super-junction GaN HEMT device of claim 1, wherein: the double heterojunction structure is formed based on a group III-nitride based material.
6. A preparation method of a natural super-junction GaN HEMT device is characterized by comprising the following steps: the method comprises the following steps:
sequentially growing a buffer layer, a back barrier layer, a channel layer, a barrier layer and a P-GaN layer on a substrate;
depositing gate metal on the P-GaN layer, photoetching to form a gate region, etching to remove the gate metal outside the gate region, and removing the photoresist and the P-GaN layer outside the metal region to form a gate electrode;
forming a source ohmic contact region and a drain ohmic contact region on the channel layer by photoetching the barrier layer, depositing a metal layer on the channel layer, forming a source electrode and a drain electrode by photoetching stripping, and carrying out annealing treatment to enable the source electrode and the drain electrode to form ohmic contact with two-dimensional electron gas;
photoetching to form a body electrode etching window;
and depositing body electrode metal on the back barrier layer, removing the metal layer outside the body electrode area, and carrying out annealing treatment to enable the body electrode and the two-dimensional hole gas to form ohmic contact.
7. The method for manufacturing the natural super-junction GaN HEMT device according to claim 6, is characterized in that: after the etching window of the bulk electrode is formed by photoetching, the method further comprises the following steps:
and etching to remove the barrier layer and part of the channel layer, removing the photoresist, depositing a dielectric layer on the etched surface of the channel layer, and removing the dielectric material outside the dielectric region.
8. The method for manufacturing the natural super-junction GaN HEMT device according to claim 6, is characterized in that: the annealing treatment is carried out to enable the bulk electrode and the two-dimensional hole gas to form ohmic contact, and then the method further comprises the following steps:
depositing insulating layers on the source electrode, the drain electrode and the gate electrode, grinding, etching the insulating layers above the source electrode, the drain electrode and the gate electrode to form a through hole, depositing interconnection metal, and manufacturing a source electrode PAD, a drain electrode PAD and a gate electrode PAD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311374634.9A CN117133806B (en) | 2023-10-23 | 2023-10-23 | Natural super-junction GaN HEMT device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311374634.9A CN117133806B (en) | 2023-10-23 | 2023-10-23 | Natural super-junction GaN HEMT device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117133806A true CN117133806A (en) | 2023-11-28 |
| CN117133806B CN117133806B (en) | 2024-01-26 |
Family
ID=88854812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311374634.9A Active CN117133806B (en) | 2023-10-23 | 2023-10-23 | Natural super-junction GaN HEMT device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117133806B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013222800A (en) * | 2012-04-16 | 2013-10-28 | Sharp Corp | Nitride semiconductor device and manufacturing method of the same |
| US20150155273A1 (en) * | 2012-06-20 | 2015-06-04 | National Institute Of Advanced Industrial Science And Technology | Semiconductor device |
| CN105118859A (en) * | 2015-07-29 | 2015-12-02 | 电子科技大学 | Tunneling enhancement type HEMT device |
| US20190280093A1 (en) * | 2018-03-06 | 2019-09-12 | Infineon Technologies Austria Ag | High Electron Mobility Transistor with Deep Charge Carrier Gas Contact Structure |
| US20220029007A1 (en) * | 2020-07-24 | 2022-01-27 | Vanguard International Semiconductor Corporation | Semiconductor structure and semiconductor device |
| WO2023014351A1 (en) * | 2021-08-03 | 2023-02-09 | Analog Devices, Inc. | Impurity reduction techniques in gallium nitride regrowth |
| CN116682853A (en) * | 2022-02-23 | 2023-09-01 | 北京大学 | Gallium nitride device, manufacturing method thereof and semiconductor integrated platform |
-
2023
- 2023-10-23 CN CN202311374634.9A patent/CN117133806B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013222800A (en) * | 2012-04-16 | 2013-10-28 | Sharp Corp | Nitride semiconductor device and manufacturing method of the same |
| US20150155273A1 (en) * | 2012-06-20 | 2015-06-04 | National Institute Of Advanced Industrial Science And Technology | Semiconductor device |
| CN105118859A (en) * | 2015-07-29 | 2015-12-02 | 电子科技大学 | Tunneling enhancement type HEMT device |
| US20190280093A1 (en) * | 2018-03-06 | 2019-09-12 | Infineon Technologies Austria Ag | High Electron Mobility Transistor with Deep Charge Carrier Gas Contact Structure |
| US20220029007A1 (en) * | 2020-07-24 | 2022-01-27 | Vanguard International Semiconductor Corporation | Semiconductor structure and semiconductor device |
| WO2023014351A1 (en) * | 2021-08-03 | 2023-02-09 | Analog Devices, Inc. | Impurity reduction techniques in gallium nitride regrowth |
| CN116682853A (en) * | 2022-02-23 | 2023-09-01 | 北京大学 | Gallium nitride device, manufacturing method thereof and semiconductor integrated platform |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117133806B (en) | 2024-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11362205B2 (en) | Group III nitride enhancement-mode HEMT based on composite barrier layer structure and manufacturing method thereof | |
| US7508014B2 (en) | Field effect transistor including a gate electrode and an additional electrode | |
| US20210320199A1 (en) | Enhancement-mode semiconductor device and preparation method therefor | |
| US7339206B2 (en) | Field effect transistor including a group III-V compound semiconductor layer | |
| TWI543366B (en) | Compound semiconductor device and method for fabricating the same | |
| KR20070032701A (en) | A method of manufacturing a nitride transistor having a regrown ohmic contact region and a nitride transistor having a regrown ohmic contact region | |
| US9755045B2 (en) | Rectifier structures with low leakage | |
| KR102080745B1 (en) | Nitride semiconductor and method thereof | |
| JP2006253559A (en) | Field-effect transistor and its manufacturing method | |
| CN111900203B (en) | GaN-based high-hole mobility transistor and preparation method thereof | |
| JP5546104B2 (en) | GaN-based field effect transistor | |
| US20170125545A1 (en) | Compound semiconductor device and manufacturing method thereof | |
| CN110429127B (en) | Gallium nitride transistor structure and preparation method thereof | |
| CN112820648B (en) | Gallium nitride metal oxide semiconductor transistor and preparation method thereof | |
| CN111755330A (en) | Semiconductor structure and manufacturing method thereof | |
| CN117133806B (en) | Natural super-junction GaN HEMT device and preparation method thereof | |
| CN114899227A (en) | Enhanced gallium nitride-based transistor and preparation method thereof | |
| KR102067596B1 (en) | Nitride semiconductor and method thereof | |
| CN113628962A (en) | III-nitride enhanced HEMT device and manufacturing method thereof | |
| JP2022016950A (en) | Semiconductor device | |
| US20230231045A1 (en) | Semiconductor device, method for manufacturing semiconductor device, and electronic device | |
| CN116741635A (en) | HEMT device manufacturing method based on maskless regrowth low-resistance extension layer | |
| CN115831744A (en) | Method for manufacturing GaN HEMT device by adopting selective epitaxy process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |