CN117118422A

CN117118422A - Power supply selection switch circuit, chip and radio frequency front end module

Info

Publication number: CN117118422A
Application number: CN202311210322.4A
Authority: CN
Inventors: 高天宝; 倪建兴
Original assignee: Radrock Shenzhen Technology Co Ltd
Current assignee: Radrock Shenzhen Technology Co Ltd
Priority date: 2023-09-19
Filing date: 2023-09-19
Publication date: 2023-11-24

Abstract

The application discloses a power supply selection switch circuit, a chip and a radio frequency front end module, wherein the power supply selection switch circuit comprises a power supply selection switch and a boost circuit, the power supply selection switch is an N-type field effect transistor, the drain electrode of the power supply selection switch is used for receiving power supply voltage, the source electrode of the power supply selection switch is used for connecting a power amplifier, and the power amplifier is powered through the power supply voltage when the power amplifier is conducted; the input end of the booster circuit is used for receiving the power supply voltage, the output end of the booster circuit is connected with the grid electrode of the N-type field effect transistor, and the booster circuit is used for outputting the received power supply voltage after lifting by a preset amplitude value; the preset amplitude is larger than the conduction threshold voltage of the N-type field effect transistor and smaller than 1.1 times of the withstand voltage value of the N-type field effect transistor. The application adopts the N-type field effect transistor as a power supply selection switch, has smaller parasitic capacitance, and controls the grid-drain voltage difference of the N-type field effect transistor within a preset range through the booster circuit, so that the N-type field effect transistor has small on-resistance, thereby meeting the requirements of small on-resistance and small parasitic capacitance.

Description

Power supply selection switch circuit, chip and radio frequency front end module

Technical Field

The present application relates to the field of radio frequency technologies, and in particular, to a power supply selection switch circuit, a chip, and a radio frequency front end module.

Background

Power amplifiers are widely used in the fields of communication, broadcasting, radar, industrial processing, medical instruments, scientific research, and the like. In different operating modes or scenarios, the power amplifier needs to be powered by different power supplies, and therefore, a power selection switch is typically provided between the power amplifier and the power supply to select whether to turn on the power supply to power the power amplifier.

With the technical development of the power amplifier, the working mode of the power amplifier is increased, and in certain working modes, the power supply voltage required by the power amplifier can be changed within a certain range, but the current power supply selection switch on the market cannot meet the requirement that the on-resistance and parasitic capacitance are still kept small under the condition of changing the power supply.

Disclosure of Invention

The application provides a power supply selection switch circuit, a chip and a radio frequency front-end module, which can meet the requirements of small on-resistance and small parasitic capacitance of the power supply selection switch.

In a first aspect, the present application provides a power supply selection switch circuit comprising: the power supply selection switch is an N-type field effect transistor, the drain electrode of the N-type field effect transistor is used for receiving power supply voltage, the source electrode of the N-type field effect transistor is used for connecting the power amplifier, and the power amplifier is supplied with power through the power supply voltage when the power amplifier is conducted; the input end of the boosting circuit is used for receiving the power supply voltage, the output end of the boosting circuit is connected with the grid electrode of the N-type field effect transistor, and the boosting circuit is used for outputting the received power supply voltage after the power supply voltage is lifted by a preset amplitude value; the preset amplitude is larger than the conduction threshold voltage of the N-type field effect transistor and smaller than 1.1 times of the withstand voltage value of the N-type field effect transistor.

As one embodiment, the predetermined magnitude is at least twice the on threshold voltage of the N-type field effect transistor.

As one embodiment, the on threshold voltage of the N-type field effect transistor is less than or equal to 1V, and the preset amplitude is greater than or equal to 3V.

As one implementation mode, the withstand voltage value of the N-type field effect transistor is 5V, and the preset amplitude value is smaller than or equal to 5.5V.

As one implementation, the preset amplitude is equal to the withstand voltage of the N-type field effect transistor.

As one implementation mode, the withstand voltage value of the N-type field effect transistor is 5V, and the preset amplitude value is 5V.

As one embodiment, the booster circuit includes: the voltage-current conversion circuit is used for converting the power supply voltage into a first current, wherein the ratio of the power supply voltage to the first current is a first resistance value; the current mirror circuit is used for mirroring the first current according to a preset current proportion to obtain a second current; the current-voltage conversion circuit is used for receiving the second current and the third current, converting the sum of the second current and the third current into a first voltage and outputting the first voltage to the grid electrode of the N-type field effect transistor; the sum of the second current and the third current is a fourth current, the ratio of the first voltage to the fourth current is a second resistance, the ratio of the preset amplitude to the third current is equal to the second resistance, and the ratio of the first resistance to the second resistance is equal to the current ratio.

As one embodiment, a voltage-to-current conversion circuit includes an operational amplifier, a first transistor, and a first resistor, wherein: the first electrode of the first transistor is used for receiving the power supply voltage of the booster circuit, the first input end of the operational amplifier is used for receiving the power supply voltage, the second input end of the operational amplifier is connected with the second electrode of the first transistor, and the output end of the operational amplifier is connected with the control electrode of the first transistor; one end of the first resistor is connected with the second pole of the first transistor, and the other end of the first resistor is grounded; wherein, the resistance value of the first resistor is equal to the first resistance value.

As one implementation mode, the current-voltage conversion circuit comprises a second resistor, one end of the second resistor is respectively connected with the current source and the output end of the current mirror circuit, and the other end of the second resistor is used for grounding; the current source is used for outputting a third current, and the resistance value of the second resistor is equal to the second resistance value.

As one embodiment, the current ratio is 1, and the second resistance value is equal to the first resistance value.

As one embodiment, the boost circuit includes a first bootstrap switch circuit and a second bootstrap switch circuit; the first bootstrap switch circuit and the second bootstrap switch respectively receive a power supply voltage and a second voltage with a preset amplitude, and generate a third voltage based on the power supply voltage and the second voltage, wherein the amplitude of the third voltage is equal to the sum of the amplitude of the power supply voltage and the preset amplitude; the output ends of the first bootstrap switch circuit and the second bootstrap switch circuit are respectively connected with the grid electrode of the N-type field effect transistor; the second bootstrap switch circuit is used for outputting a third voltage in a first time period, the first bootstrap switch circuit is used for outputting the third voltage in a second time period, and the first time period is connected with the second time period.

As an embodiment, the first bootstrapped switch circuit includes a first capacitor, wherein: in a first time period, a first end of the first capacitor is used for receiving a second voltage, and a second end of the first capacitor is used for being grounded; in a second time period, the first end of the first capacitor is used for being connected with the grid electrode of the N-type field effect transistor, and the second end of the first capacitor is used for receiving the power supply voltage.

As an embodiment, the first bootstrap switching circuit further comprises a first switch, a second switch, a third switch and a fourth switch, wherein: the first end of the first switch is used for grounding, and the second end of the first switch is connected with the second end of the first capacitor; the first end of the second switch is used for being connected with a voltage source to receive second voltage output by the voltage source, and the second end of the second switch is connected with the first end of the first capacitor; the first end of the third switch is used for receiving the power supply voltage, and the second end of the third switch is connected with the second end of the first capacitor; the first end of the fourth switch is connected with the first end of the first capacitor, and the second end of the fourth switch is connected with the grid electrode of the N-type field effect transistor; the first switch and the second switch are turned on in a first time period and turned off in a second time period; the third switch and the fourth switch are turned off for a first period of time and turned on for a second period of time.

As an embodiment, the second bootstrapped switch circuit includes a second capacitor, wherein: in the first time period, the first end of the second capacitor is used for being connected with the grid electrode of the N-type field effect transistor, and the second end of the second capacitor is used for receiving the power supply voltage; the first end of the second capacitor is used for receiving a second voltage during a second period, and the second end of the second capacitor is used for being grounded.

As an embodiment, the second bootstrap switching circuit further includes a fifth switch, a sixth switch, a seventh switch and an eighth switch, wherein: the first end of the fifth switch is used for grounding, and the second end of the fifth switch is connected with the second end of the second capacitor; the first end of the sixth switch is used for being connected with the voltage source to receive the second voltage output by the voltage source, and the second end of the sixth switch is connected with the first end of the second capacitor; the first end of the seventh switch is used for receiving the power supply voltage, and the second end of the seventh switch is connected with the second end of the first capacitor; the first end of the eighth switch is connected with the first end of the second capacitor, and the second end of the eighth switch is connected with the grid electrode of the N-type field effect transistor; the fifth switch and the sixth switch are turned off in a first time period and turned on in a second time period; the seventh switch and the eighth switch are turned on for a first period of time and turned off for a second period of time.

As one embodiment, the boost circuit includes a charge pump, an input terminal of the charge pump is used for receiving a power supply voltage, and an output terminal of the charge pump is connected with a gate of the N-type field effect transistor.

As one embodiment, the amplitude of the clock signal of the charge pump at a high level is 1/N of a preset amplitude, where N is a positive integer.

In a second aspect, the application provides a chip comprising the power supply selection switch circuit of any one of the first aspects.

As one implementation mode, the chip comprises at least two power supply selection switch circuits, wherein the drain electrode of the N-type field effect transistor in each power supply selection switch circuit is respectively connected with a corresponding power supply module so as to receive the power supply voltage output by the corresponding power supply module, and the source electrode of the N-type field effect transistor in each power supply selection switch circuit is connected with the power supply end of the power amplifier; the chip further comprises an enabling circuit for enabling the at least one power supply selection switch circuit.

As an embodiment, the chip further comprises a power amplifier.

In a third aspect, the present application provides a radio frequency front end module comprising a power amplifier and a power supply selection switch circuit as in the first aspect.

As an implementation mode, the radio frequency front end module further comprises a substrate, a first chip and a second chip, wherein the first chip and the second chip are arranged on the substrate, the power amplifier is integrated in the first chip, and the power supply selection switch circuit is integrated in the second chip.

As an implementation mode, the radio frequency front end module further comprises a third chip and a control circuit, wherein the control circuit is integrated in the third chip, and the control circuit is connected with the power amplifier and used for controlling the power amplifier to work.

As an implementation manner, the radio frequency front end module further comprises a substrate and a fourth chip arranged on the substrate, and the power amplifier and the power supply selection switch circuit are integrated in the fourth chip.

The power supply selection switch circuit adopts the N-type field effect transistor as a power supply selection switch, and can have smaller parasitic capacitance. The voltage boosting circuit is utilized to enable the grid voltage of the N-type field effect transistor to change along with the power supply voltage, the voltage difference of the grid and the drain is kept to be a preset amplitude value, and the voltage interval of the preset amplitude value is ingeniously set, so that the NMOS transistor is kept to have smaller on-resistance Ron on the premise of not being broken down. Compared with the related art, the power supply selection switch circuit provided by the embodiment of the application can simultaneously reduce the parasitic capacitance and the on-resistance of the power supply selection switch, is beneficial to reducing the loss on a power supply path, improves the power efficiency of the power amplifier, and can be suitable for more application scenes and higher-requirement power supply modes.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows a schematic diagram of a power supply selection switch circuit according to an embodiment of the present application.

Fig. 2 shows an application schematic diagram of a power supply selection switch circuit according to an embodiment of the present application.

Fig. 3 shows a schematic circuit structure of a boost circuit according to an embodiment of the present application.

Fig. 4 is a schematic circuit diagram of another boost circuit according to an embodiment of the present application.

Fig. 5 shows a schematic circuit structure of a boost circuit according to an embodiment of the present application.

Fig. 6 shows a schematic circuit structure of a first bootstrap switching circuit provided in an embodiment of the present application.

Fig. 7 is a schematic circuit diagram of a second bootstrap switching circuit according to an embodiment of the present application.

Fig. 8 is a schematic circuit diagram of a further boost circuit according to an embodiment of the present application.

Fig. 9 shows a schematic circuit structure of a charge pump unit according to an embodiment of the present application.

Fig. 10 shows a schematic diagram of a chip structure according to an embodiment of the present application.

Fig. 11 shows another schematic chip structure provided in an embodiment of the present application.

Fig. 12 is a schematic structural diagram of a radio frequency front end module according to an embodiment of the present application.

Fig. 13 is a schematic structural diagram of another rf front-end module according to an embodiment of the present application.

Fig. 14 is a schematic structural diagram of another rf front-end module according to an embodiment of the present application.

Fig. 15 is a schematic structural diagram of another rf front-end module according to an embodiment of the present application.

Detailed Description

In order to enable those skilled in the art to better understand the present application, a clear and complete description of the technical solution in the present embodiment will be provided below with reference to the accompanying drawings in the present embodiment. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Because some performance indexes such as energy efficiency of the power amplifier are related to the power supply voltage thereof, under different working modes or scenes, the power amplifier needs to be powered by different power supplies, and therefore, a power supply selection switch is usually arranged between the power amplifier and the power supplies to select whether to conduct the power supplies to supply power for the power amplifier. In the semiconductor field, the switch can be realized by using a field effect transistor.

The on condition of the N-type field effect transistor is that the gate voltage is greater than the source/drain voltage, and when the drain receives the power supply voltage Vcc, a voltage higher than the power supply voltage Vcc needs to be provided to the gate to turn on the N-type field effect transistor. However, if the power supply voltage Vcc is large, the difference between the gate voltage of the N-type field effect transistor and the power supply voltage Vcc is too small, so that the on-resistance Ron of the N-type field effect transistor is too large, and may not be even turned on; if the supply voltage Vcc is small, it may cause the NFET to breakdown. Accordingly, the related art generally selects a P-type field effect transistor or a transmission gate as a power selection switch.

In one related art, a power select switch typically employs a P-type field effect transistor. The on condition of the P-type field effect transistor is that the gate voltage is smaller than the source/drain voltage, so that the source of the P-type field effect transistor receives the power voltage Vcc, and a low level is applied to the gate of the P-type field effect transistor, so that the P-type field effect transistor can be turned on. The parasitic capacitance of the P-type field effect transistor can meet the requirement of isolation, but the size and the on-resistance Ron of the P-type field effect transistor are larger than those of the N-type field effect transistor, and the switching speed is slower. In addition, in the scene of the variation of the power supply voltage Vcc, when the power supply voltage Vcc is smaller, the voltage difference between the gate and the source is smaller, the on-resistance Ron is further increased, and the use requirement cannot be satisfied.

In another related art, a transmission gate formed by connecting a P-type field effect transistor and an N-type field effect transistor in parallel is used as a power supply selection switch. Because the N-type field effect transistor has smaller on-resistance and the resistance has the characteristic of reduced resistance after being connected in parallel, the on-resistance of the N-type field effect transistor and the P-type field effect transistor after being connected in parallel is smaller, and the requirement of low on-resistance Ron can be met. However, due to the characteristic of increasing the capacitance of the capacitor in parallel connection, the parasitic capacitance of the N-type field effect transistor and the P-type field effect transistor in parallel connection is increased, the isolation of the power supply selection switch to the radio frequency signal is reduced, and the two tubes in parallel connection can cause the increase of the switch area and the increase of the cost.

With the development of the fifth generation mobile communication technology (5G), compared with the previous 4G or 3G technology, a radio frequency front end with higher frequency, larger bandwidth and higher order QAM modulation is required, and more stringent requirements are put on various performance indexes such as efficiency, power consumption, isolation and the like of a power amplifier in the radio frequency front end, so that the power supply mode, loss on a power supply path, isolation and the like of the power amplifier are required to be improved. However, in some power supply modes, the power supply selection switch of the power amplifier is required to have both a small on-resistance and a very small parasitic capacitance, and the related technologies can only make a compromise between the two, so that the requirements cannot be met at the same time.

In order to still meet the requirement that on-resistance and parasitic capacitance are small under the condition of power supply variation, the application provides a power supply selection switch circuit, which adopts an N-type field effect transistor as a power supply selection switch and has small parasitic capacitance; the grid voltage of the N-type field effect transistor is controlled to follow the change of the power supply voltage, so that the N-type field effect transistor can keep smaller on-resistance on the premise of not being broken down, and the problem that a power supply selection switch with small on-resistance and small parasitic capacitance cannot be provided under the condition of power supply change in the prior art is solved.

Referring to fig. 1, fig. 1 is a schematic diagram illustrating a power selection switch circuit according to an embodiment of the application. As shown in fig. 1, the power selection switch circuit 10 includes a power selection switch 101 and a boost circuit 102, an input end of the boost circuit 102 is used for receiving a power voltage Vcc, an output end of the boost circuit 102 is connected to the power selection switch 101, and the boost circuit 102 is used for raising the received power voltage Vcc by a preset magnitude Δv to obtain a control voltage Vg, that is, the control voltage vg=vcc+Δv. The booster circuit 102 outputs a control voltage Vg to the power selection switch 101 to control the power selection switch 101 to be turned on.

In the embodiment of the application, the power supply selection switch 101 is implemented by using an N-type field effect transistor NM1, wherein a gate of the N-type field effect transistor NM1 is connected with an output end of the booster circuit 102, so as to receive the control voltage Vg, a drain of the N-type field effect transistor NM1 is used for receiving the power supply voltage Vcc, and a source of the N-type field effect transistor NM1 is used for connecting the power amplifier PA, and when the N-type field effect transistor NM1 is turned on under the action of the control voltage Vg, the power supply voltage Vcc is transmitted to the power amplifier PA through the turned-on N-type field effect transistor NM1 to supply power to the power amplifier PA.

In the embodiment of the present application, the drain voltage Vd of the N-type field effect transistor NM1 is the power supply voltage Vcc, and the received power supply voltage Vcc is raised by the booster circuit 102 by a preset magnitude Δv and then used for controlling the N-type field effect transistor NM1, so that the gate voltage of the N-type field effect transistor NM1 is vg=vcc+Δv, and the voltage difference vgd=vg-vd=Δv between the gate and the drain. Thus, the gate-drain voltage difference of the N-type field effect transistor NM1 can be maintained at the preset magnitude Δv regardless of whether the power supply voltage Vcc is changed or not and the magnitude of the change. The preset amplitude Δv is larger than the turn-on threshold voltage Vth of the N-type field effect transistor NM1, i.e. the gate-drain voltage difference of the N-type field effect transistor NM1 is larger than the threshold voltage thereof, so that the N-type field effect transistor NM1 can maintain a smaller turn-on resistance Ron, thereby being capable of being turned on quickly, and having smaller insertion loss after being turned on. In addition, the breakdown voltage of the field effect tube is usually larger than or equal to 1.1 times of the voltage withstand value of the field effect tube, and the preset amplitude delta V is smaller than 1.1 times of the voltage withstand value of the N-type field effect tube NM1, so that the voltage difference between any two poles of the N-type field effect tube NM1 can be ensured to be smaller than the breakdown voltage of the N-type field effect tube NM1, the N-type field effect tube NM1 is prevented from being broken down, and the reliability of a power supply selection switch is improved.

Based on the above, the power supply selection switch circuit provided by the embodiment of the application adopts the N-type field effect transistor as the power supply selection switch, and has small parasitic capacitance, so that the power supply selection switch circuit has good isolation to radio frequency signals when being turned off. The voltage boosting circuit is utilized to enable the grid voltage of the N-type field effect transistor to change along with the power supply voltage, the voltage difference of the grid and the drain is kept to be a preset amplitude value, and the voltage interval of the preset amplitude value is ingeniously set, so that the NMOS transistor is kept to have smaller on-resistance Ron on the premise of not being broken down. Compared with the related art, the power supply selection switch circuit of the embodiment of the application can simultaneously reduce the parasitic capacitance and the on-resistance of the power supply selection switch, is beneficial to reducing the loss on a power supply path, improves the power efficiency of the power amplifier, can be suitable for more application scenes and higher-requirement power supply modes, for example, can be applied to the power amplifier adopting an APT (Average power tracking ) power supply mode and can also be applied to the power amplifier adopting an ET (envelope tracking ) power supply mode.

Optionally, the N-type field effect transistor in the embodiment of the present application may be an N-channel semiconductor field effect transistor or an N-channel metal oxide semiconductor field effect transistor (NMOS).

As an embodiment, as shown in fig. 2, the power selection switch circuit 10 is applied to a radio frequency front end module, and the radio frequency front end module further includes a power supply module and a power amplifier PA, where the power supply voltage Vcc is generated by the power supply module. The power supply module may be, for example, a direct current switching power supply (DC-DC) in order to generate a fixed or varying supply voltage Vcc according to the supply mode requirements of the power amplifier PA. The power supply selection switch circuit 10 is connected between the power supply module and the power amplifier PA, and transmits the power supply voltage output by the corresponding power supply module to the power amplifier PA when the power supply module is turned on to supply power to the power amplifier PA.

It should be understood that, in the power supply selection switch circuit 10, the drain of the N-type field effect transistor NM1 and the input terminal of the booster circuit may be directly connected to the output terminal of the power supply module, or may be indirectly connected to the output terminal of the power supply module through a circuit element such as a resistor, a transistor, or the like, as long as the power supply voltage can be obtained. In other words, the power supply voltage Vcc obtained by the drain of the N-fet NM1 and the input terminal of the booster circuit may be the output voltage of the power supply module, or may be a voltage obtained by dividing or other processing the output voltage of the power supply module, which is not limited in the present application.

As an embodiment, the preset amplitude Δv is at least twice the on threshold voltage of the N-type field effect transistor NM 1. In other words, the gate-drain voltage difference of the N-type field effect transistor is at least twice the on threshold voltage. Illustratively, when the on threshold voltage of the N-type field effect transistor is 1V, the preset amplitude Δv is greater than or equal to 2V, and the gate-drain voltage difference Vgd of the N-type field effect transistor is greater than or equal to 2V.

The N-type field effect transistor can be conducted when the gate-drain voltage difference is larger than the conducting threshold voltage, but when the gate voltage difference is close to the conducting threshold voltage, the N-type field effect transistor has higher conducting resistance, and the switching speed and the insertion loss after conducting are affected. According to the embodiment, the preset amplitude is set to be at least 2 times of the conduction threshold voltage of the N-type field effect transistor, so that the gate-drain voltage difference of the N-type field effect transistor is at least 1 time greater than the conduction threshold voltage, the conduction resistance of the N-type field effect transistor can be reduced, the switching speed of the N-type field effect transistor is increased, the insertion loss after conduction is reduced, and the N-type field effect transistor can meet the requirements of small conduction resistance and small parasitic capacitance.

As one embodiment, the on threshold voltage Vth of the N-type field effect transistor NM1 is less than or equal to 1V, and the preset amplitude Δv is greater than or equal to 3V. Therefore, the gate-drain voltage difference of the N-type field effect transistor NM1 is at least 2V greater than the turn-on threshold voltage Vth thereof, which can further reduce the turn-on resistance of the N-type field effect transistor NM1, speed up the switching speed thereof, further deepen the turn-on degree of the N-type field effect transistor NM1, and reduce the insertion loss after turn-on thereof to a greater extent. The N-type field effect transistor NM1 is an NMOS transistor, and has a turn-on threshold voltage Vth of 0.7V, and a preset amplitude Δv greater than or equal to 3V, which is at least 2.3V greater than the turn-on threshold voltage Vth, so that the NMOS transistor can be turned on deeply.

As an implementation manner, the N-type field effect transistor NM1 is a 5V device, that is, the withstand voltage of the N-type field effect transistor NM1 is 5V, when the voltage difference of any two poles of the N-type field effect transistor NM1 exceeds 10% of the withstand voltage (that is, the voltage difference of any two poles exceeds 5.5V), the N-type field effect transistor NM1 has a risk of breakdown, and then the preset amplitude Δv can be set to be less than or equal to 5.5V, so as to reduce the risk of breakdown of the N-type field effect transistor NM1, and ensure the reliability of the power supply selection switch circuit 10.

As an embodiment, the preset amplitude Δv is set to be equal to the withstand voltage value of the N-type field effect transistor NM1, for example, when the withstand voltage value of the N-type field effect transistor NM1 is 5V, the preset amplitude Δv=5v may be set. Thus, the N-type field effect transistor NM1 can obtain the minimum on-resistance Ron on the premise of not being broken down, so that the switching speed of the N-type field effect transistor NM1 is accelerated to the maximum extent, and the insertion loss after the N-type field effect transistor NM1 is conducted is reduced.

In the embodiment of the present application, the booster circuit 102 may have various embodiments, and the preset amplitude Δv of the booster circuit 102 raised on the basis of the power supply voltage Vcc may be flexibly set as required. Illustratively, the following examples describe some implementations of the boost circuit 102 in connection with FIGS. 3-8.

In some embodiments, as shown in fig. 3, the boost circuit 102 includes a voltage-to-current conversion circuit 1021, a current mirror circuit 1022, and a current-to-voltage conversion circuit 1023, where the voltage-to-current conversion circuit 1021 is configured to convert a power supply voltage Vcc into a first current I1, and a ratio of the power supply voltage Vcc to the first current I1 is denoted as a first resistance r1, and r1=vcc/I1. The current mirror circuit 1022 is configured to mirror the first current I1 according to a preset current ratio k to obtain a second current I2, i.e. i2=kχi1. The current-voltage conversion circuit 1023 is configured to receive the second current I2 and the third current I3, and convert the sum of the second current and the third current into the first voltage V1, and if the sum of the second current I2 and the third current I3 is denoted as the fourth current I4, and the ratio of the first voltage V1 and the fourth current I4 is denoted as the second resistance r2, i4=i2+i3, and r2=v1/I4.

In this embodiment, the third current I3 is set according to the required preset amplitude Δv and the second resistance r2, so that the ratio of the preset amplitude Δv to the third current I3 is equal to the second resistance r2, and Δv=r2×i3. The above formulas are converted to obtain:

V1＝r2*I4

＝r2*(I2+I3)

＝r2*I2+r2*I3

＝r2*I2+ΔV

＝r2*k*I1+ΔV

＝r2*k*(Vcc/r1)+ΔV

＝Vcc*k*r2/r1+ΔV

in this embodiment, by setting circuit parameters of the voltage-current conversion circuit 1021, the current mirror circuit 1022, and the current-voltage conversion circuit 1023 such that the ratio of the first resistance value r1 to the second resistance value r2 is equal to the current ratio k, k=r1/r 2, the above expression can be obtained: v1=vcc+Δv, and a first voltage V1 raised by a predetermined magnitude Δv on the basis of the power supply voltage Vcc can be obtained.

The output end of the current-voltage conversion circuit 1023 is connected to the gate of the N-type field effect transistor NM1, so that the first voltage V1 is output to the gate of the N-type field effect transistor NM1, and is used as the gate voltage Vg of the NM1, so that the gate-drain voltage difference of the N-type field effect transistor NM1 is equal to the preset amplitude Δv. By combining the above embodiments, the N-type field effect transistor can simultaneously meet the requirements of small on-resistance and small parasitic capacitance by skillfully setting the value of the preset amplitude Δv.

The boost circuit of the embodiment of the application can quickly generate the first voltage V1 with the preset amplitude delta V higher than the power supply voltage Vcc along with the change of Vcc in real time, and has the advantage of real-time response. The first voltage V1 is utilized to control the on or off of the N-type field effect transistor NM1, so that the N-type field effect transistor can simultaneously meet the requirements of small on resistance and small parasitic capacitance, the switching speed of the N-type field effect transistor NM1 is accelerated, the on resistance and insertion loss of the N-type field effect transistor NM1 are reduced, and the efficiency of the power amplifier is improved.

As an embodiment, the conversion between current and voltage may be achieved using a resistive element based on ohm's law. Specifically, the voltage-current conversion circuit 1021 may include a first resistor R1, and the power supply voltage Vcc is applied across the first resistor R1 having a resistance R1, so as to generate a current I1 flowing through the first resistor R1. The current-voltage conversion circuit 1023 may include a second resistor R2, where the resistance of the second resistor R2 is R2, so that the fourth current I4 flows through the second resistor R2, a voltage difference with the magnitude of I4R 2 is generated at two ends of the second resistor R2, one end of the second resistor R2 is grounded, and the voltage at the other end is the first voltage v1=i4R 2.

Illustratively, as shown in fig. 4, the voltage-to-current conversion circuit 1021 includes an operational amplifier A1, a first transistor M1, and a first resistor R1, wherein: the first electrode of the first transistor is used for receiving the power supply voltage Vdd of the boost circuit, the first input end of the operational amplifier A1 is used for receiving the power supply voltage Vcc, the second input end of the operational amplifier A1 is connected with the second electrode of the first transistor M1, and the output end of the operational amplifier is connected with the control electrode of the first transistor M1; one end of the first resistor R1 is connected with the second pole of the first transistor M1 and the second input end of the operational amplifier A1, and the other end of the first resistor R1 is used for grounding; the resistance value of the first resistor R1 is equal to the first resistance value R1, so that the power supply voltage Vdd of the booster circuit is greater than the output voltage V1 thereof, i.e. the difference between Vdd and Vcc is at least greater than the preset amplitude Δv.

Optionally, the first transistor M1 may be a field effect transistor or a triode, and if the first transistor M1 is a field effect transistor, the first pole and the second pole of the first transistor M1 are a source and a drain respectively; if the first transistor M1 is a triode, the first and second poles of the first transistor M1 are collector and emitter, respectively.

Based on the principle of the operational amplifier being short, the voltages at the two input ends of the operational amplifier A1 are the same during normal operation, so that the voltage at the second input end of the operational amplifier A1, that is, the voltage at one end of the first resistor R1 is equal to the power supply voltage Vcc received by the first input end of the operational amplifier A1. Since the other end of the first resistor R1 is grounded, the voltage difference between the two ends of the first resistor R1 is Vcc. The current flowing through the first resistor is i1=vcc/r 1 according to ohm's law. Since the first transistor M1 is connected in series with the first resistor R1, the current flowing through the source and drain of the first transistor M1 is also I1. The first transistor M1 further includes a third electrode, which is a gate or a base, and is configured to be connected to the current mirror circuit, so that the current mirror circuit can mirror the current I1 flowing through the first transistor M1, thereby obtaining the second current I2.

Illustratively, as shown in fig. 4, the current mirror circuit includes a second transistor M2, the second transistor M2 being of the same type as the first transistor M1, and both being connected in a current mirror manner, thereby mirroring the first current I1. The second transistor M2 also includes a first pole, a second pole, and a third pole, which are the same as the first transistor M1, wherein the third pole of the second transistor M2 is connected to the third pole of the first transistor M1, the first pole of the second transistor M2 is configured to receive the supply voltage Vdd of the boost circuit, and the second pole of the second transistor M2 is configured to output the second current I2.

The ratio of the second current I2 to the first current I1 (i.e., the preset current ratio) is related to the sizes of the second transistor M2 and the first transistor M1. Taking a field effect transistor as an example, the current ratio k is equal to the ratio of the width-to-length ratio of the second transistor M2 to the width-to-length ratio of the first transistor M1. If the second transistor M2 and the first transistor M1 are the same size, the current ratio k=1.

For example, as shown in fig. 4, the third current I3 may be generated by a current source. In order to generate the first voltage V1 with the amplitude equal to vcc+Δv at one end of the second resistor R2, the magnitude of the required third current is determined according to the required preset amplitude Δv and the resistance R2 of the second resistor R2, and a suitable current source is selected to obtain the third current. For example, when Δv=5v and v1=vcc+5v are required, a current source having an output current of 5V/r2 may be selected. Alternatively, the current source may be implemented using a circuit structure similar to the voltage-to-current conversion circuit 1021, and may also be implemented using a digital current source. If the current source is a digital current source, determining a value of the required third current I3 according to the required amplitude of the DeltaV and the resistance value of the second resistor r2, and inputting a corresponding code value into the digital current source to obtain the required third current I3. If the current source adopts a circuit structure similar to the voltage-current conversion circuit 1021, a voltage with the amplitude equal to DeltaV is input at the input end of the circuit structure, and a resistor with the resistance value equal to r2 is adopted in the circuit structure, so that a third current I3 with the amplitude equal to DeltaV/r 2 can be obtained. It should be appreciated that other implementations of the current source are possible, and the application is not limited to the specific implementation, as long as the third current I3 having a magnitude equal to Δv/r2 can be generated.

As shown in fig. 4, the second pole of the second transistor M2 and the output terminal of the current source are both connected to one terminal of the second resistor R2, and the other terminal of the second resistor R2 is grounded, so that the fourth current I4 flowing through the second resistor R2 is the sum of the second current I2 output by the second transistor M2 and the third current I3 output by the current source, and the fourth current passes through the resistor R2 and generates a voltage difference with an amplitude equal to I4R 2 at both terminals of the second resistor R2, thereby obtaining the first voltage v1=i4×r2=vcc+Δv at the non-grounded terminal of the second resistor R2. One end of the second resistor R2 is connected to the grid electrode of the N-type field effect tube NM1, namely, the first voltage V1 can be utilized to control the on or off of the N-type field effect tube NM1, so that the grid-drain voltage difference of the N-type field effect tube NM1 is maintained to be a preset amplitude delta V, and the requirements of small on-resistance and small parasitic capacitance of a power supply selection switch are met.

As an embodiment, the resistance of the first resistor R1 and the resistance of the second resistor R2 may be equal, and at this time, the current mirror circuit may have a mirror ratio k=1 of the first current, and the second transistor M2 and the first transistor M1 with the same size may be used so that the preset current ratio is 1.

In some embodiments, the boost circuit 102 may also be implemented with a bootstrap switch. Illustratively, as shown in fig. 5, the boost circuit 102 includes a first bootstrap switch circuit 1024 and a second bootstrap switch circuit 1025; the first bootstrap switch circuit 1024 and the second bootstrap switch 1025 each receive the power supply voltage Vcc and the second voltage V2 having a preset magnitude Δv, and generate a third voltage V3 based on the power supply voltage Vcc and the second voltage V2, the magnitude of the third voltage V3 being equal to the sum of the magnitude of the power supply voltage Vcc and the preset magnitude Δv, that is, v3=vcc+Δv.

The first bootstrap switch circuit 1024 is configured to output the third voltage V3 during the second period T2, and the second bootstrap switch circuit 1025 is configured to output the third voltage V3 during the first period T1, where the first period T1 and the second period T2 are connected. The output ends of the first bootstrap switch circuit 1024 and the second bootstrap switch circuit 1025 are respectively connected to the gate of the N-type field effect transistor NM1, so as to control the N-type field effect transistor NM1 to be turned on through the third voltage V3.

The bootstrap switch circuit works on the principle that the voltage on the capacitor plate is raised by using the charge transfer of the capacitor. Since the capacitor requires a certain time to charge, a single bootstrap switch circuit can only generate the required third voltage V3 for a fraction of a cycle. According to the embodiment of the application, by arranging the two bootstrap switch circuits which are alternately output, the second bootstrap switch circuit can output the third voltage V3 in the process of charging the internal capacitor of the first bootstrap switch circuit; in the process of charging the internal capacitor of the second bootstrap switch circuit, the first bootstrap switch circuit may output the third voltage V3, so that the third voltage V3 can be obtained in a complete period, so that the gate voltage of the N-type field effect transistor NM1 is maintained to be equal to vcc+Δv all the time during the period of gating the power supply module corresponding to the power supply selection switch circuit 10, and the gate-drain voltage difference of the N-type field effect transistor NM1 is maintained to be Δv unchanged no matter how the power supply voltage Vcc changes. By combining the magnitude of Δv set in the foregoing embodiment, the N-type field effect transistor NM1 can maintain a small on-resistance Ron during the on period, thereby reducing the insertion loss of the power supply selection switch.

As an embodiment, the first bootstrap switch circuit 1024 and the second bootstrap switch circuit 1025 are both periodically operated, and the period duration of operation of the first bootstrap switch circuit 1024 and the second bootstrap switch circuit 1025 are the same, and the operation timing sequences are opposite. In other words, during one working period of the boost circuit 102, if the first bootstrap switch circuit 1024 outputs the third voltage V3 during the first half period and charges during the second half period, the second bootstrap switch circuit 1025 charges during the first half period and outputs the third voltage V3 during the second half period; conversely, if the first bootstrap switch circuit 1024 charges in the first half-period and the second half-period outputs the third voltage V3, the second bootstrap switch circuit 1025 outputs the third voltage in the first half-period and charges in the second half-period.

As an embodiment, as shown in fig. 6, the first bootstrap switch circuit 1024 includes a first capacitor C1, where, during a first period T1, a first end of the first capacitor C1 is used to receive the second voltage V2, and a second end of the first capacitor C1 is used to be grounded; in the second period T2, the first end of the first capacitor C1 is connected to the gate of the N-type field effect transistor NM1, and the second end of the first capacitor C1 is configured to receive the power supply voltage Vcc.

In the first period T1, the second voltage V2 charges the first capacitor C1, so that the voltage of the first end of the first capacitor gradually rises to the second voltage V2; at the beginning of the second period T2, the second terminal of the first capacitor C1 is switched from the ground to the receiving power voltage Vcc, the second terminal voltage of the first capacitor C1 is raised by Vcc, and the voltage across the capacitor cannot be suddenly changed, so that the first terminal voltage of the first capacitor C1 is raised by Vcc and becomes v2+vcc, thereby obtaining the required third voltage v3=v2+vcc=vcc+Δv. The voltage at the first end of the first capacitor C1 can be maintained at V3 for the second period T2 based on the charge storage effect of the capacitor. When the second period T2 is over, the first capacitor C1 is recharged, and the above process is repeated. Therefore, the first terminal of the first capacitor C1 can output the third voltage V3 for the second period T2 of each cycle.

The second bootstrap switch circuit 1025 includes a second capacitor C2, where, in the first period T1, a first end of the second capacitor C2 is used to connect to the gate of the N-type field effect transistor NM1, and a second end of the second capacitor is used to receive the power supply voltage Vcc; in the second period T2, the first end of the second capacitor C2 is configured to receive the second voltage V2, and the second end of the second capacitor is configured to be grounded.

The second bootstrap switch circuit 1025 operates in the same manner as the first bootstrap switch circuit 1024, but with opposite timing sequences, and will not be described again here.

In the present embodiment, the first terminal of the second capacitor C2 outputs the third voltage during the first period T1 of each cycle, and the first terminal of the first capacitor C1 outputs the third voltage during the second period T2 of each cycle, thereby enabling the booster circuit to maintain outputting the third voltage V3 throughout the cycle.

The two ends of the first capacitor C1 and the second capacitor C2 can be respectively switched to different signal ends through different switches to selectively switch and receive, for example, the power supply voltage Vcc or the gate electrode of the N-type field effect transistor NM 1.

Illustratively, as shown in fig. 6, the first bootstrap switch circuit 1024 further includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4, wherein: the first end of the first switch S1 is used for being grounded, and the second end of the first switch S1 is connected with the second end of the first capacitor C1; the first end of the second switch S2 is used for being connected with a voltage source to receive a second voltage V2 output by the voltage source, and the second end of the second switch S2 is connected with the first end of the first capacitor C1; the first end of the third switch S3 is used for receiving the power supply voltage Vcc, and the second end of the switch S3 is connected with the second end of the first capacitor C1; the first end of the fourth switch S4 is connected with the first end of the first capacitor C1, and the second end of the fourth switch S4 is connected with the grid electrode of the N-type field effect transistor NM 1; the first switch S1 and the second switch S2 are turned on in a first period T1 and turned off in a second period T2; the third switch S3 and the fourth switch S4 are turned off during the first period T1 and turned on during the second period T2.

In the first period T1, the first switch S1 and the second switch S2 are turned on, the third switch S3 and the fourth switch S4 are turned off, the first end of the first capacitor C1 receives the second voltage V2 output by the voltage source, the second end is grounded, the first capacitor C1 is charged by the second voltage V2, and the voltage at the first end of the first capacitor C1 is gradually increased to V2.

At the beginning of the second period T2, the first switch S1 and the second switch S2 are turned off, the third switch S3 and the fourth switch S4 are turned on, the second terminal of the first capacitor C1 is switched from ground to receive the power voltage Vcc, the voltage is raised by Vcc, and the first terminal voltage of the first capacitor C1 is raised by Vcc on the basis of V2 to be v2+vcc, thereby obtaining the required third voltage v3=v2+vcc=vcc+Δv. The voltage at the first end of the first capacitor C1 can be maintained at V3 for the second period T2 based on the charge storage effect of the capacitor. When the second period T2 ends and the next first period T1 begins, the first capacitor C1 is recharged, and the above process is repeated. Therefore, the first terminal of the first capacitor C1 can output the third voltage V3 for the second period T2 of each cycle.

Illustratively, as shown in fig. 7, the second bootstrap switch circuit 1025 further includes a fifth switch S5, a sixth switch S6, a seventh switch S7 and an eighth switch S8, wherein: the first end of the fifth switch S5 is used for grounding, and the second end of the fifth switch S5 is connected with the second end of the second capacitor C2; the first end of the sixth switch S6 is connected to the voltage source to receive the second voltage V2 output by the voltage source, and the second end of the sixth switch S6 is connected to the first end of the second capacitor C2; the first end of the seventh switch S7 is configured to receive the power supply voltage Vcc, and the second end of the seventh switch S7 is connected to the second end of the second capacitor C2; the first end of the eighth switch S8 is connected with the first end of the second capacitor C2, and the second end of the eighth switch S8 is connected with the grid electrode of the N-type field effect transistor NM 1; wherein the fifth switch S5 and the sixth switch S6 are turned off in the first period T1 and turned on in the second period T2; the seventh switch S7 and the eighth switch S8 are turned on for the first period T1 and turned off for the second period T2.

The operation principle of the circuit shown in fig. 7 is similar to that of fig. 6, except that the timing is reversed, and the description thereof is omitted.

As an implementation manner, the second voltage may be obtained by using a bandgap reference circuit and a low dropout regulator (LDO) in the chip, that is, the voltage source may reuse the bandgap reference circuit and the low dropout regulator (LDO) in the chip, thereby saving circuit area and reducing circuit cost.

As another embodiment, the voltage source may also be implemented by a digital-to-analog converter (DAC) capable of generating a voltage signal of a desired amplitude based on the input digital signal.

For example, when the voltage v3=vcc+5v needs to be output, the parameter of the LDO circuit may be set to output the voltage with the amplitude of 5V as the second voltage, and other 5V voltage sources may be selected to generate the second voltage V2 with the amplitude of 5V.

According to the bootstrap switch circuit structure shown in fig. 6 and 7, the boost circuit can maintain and output the third voltage V3 in the whole period through two capacitors and a plurality of switches, and the circuit structure is simple and has low cost; the third voltage V3 changing along with the power supply voltage Vcc is utilized to control the on or off of the N-type field effect transistor NM1, so that the power supply selection switch can simultaneously meet the requirements of small on resistance and small parasitic capacitance, the switching speed of the N-type field effect transistor NM1 is accelerated, the on resistance and insertion loss of the N-type field effect transistor NM1 are reduced, and the efficiency of the power amplifier is improved.

In some embodiments, the boost circuit 102 may also be implemented with a charge pump. Illustratively, as shown in fig. 8, the boost circuit 102 includes a charge pump 1026, an input terminal of the charge pump 1026 is configured to receive a power supply voltage Vcc, and an output terminal of the charge pump 1026 is connected to a gate of the N-type field effect transistor NM 1.

After the charge pump 1026 is enabled, the output voltage Vout thereof can gradually rise on the basis of the input voltage Vcc, and when the magnitude of the rise of the output voltage Vout is equal to the set magnitude, i.e., Δv, the output voltage Vout of the charge pump will stabilize at vcc+Δv. Illustratively, when Vcc is used as the input signal of the charge pump 1026 and a square wave signal with a high level of 5V and a low level of 0V is used as the clock signal of the charge pump 1026, the output voltage Vout of the charge pump 1026 will rise from Vcc and stabilize after vout=vcc+5v is reached.

The output end of the charge pump 1026 is connected to the gate of the N-type field effect transistor NM1, i.e. the on/off of the N-type field effect transistor NM1 can be controlled by the voltage vcc+Δv, so that the gate-drain voltage difference of the N-type field effect transistor NM1 is maintained to be Δv regardless of the variation of the power supply voltage Vcc. By combining the magnitude of Δv set in the foregoing embodiment, the N-type field effect transistor NM1 can maintain a small on-resistance Ron during the on period, thereby meeting the requirements of small parasitic capacitance and small on-resistance at the same time.

As one embodiment, the charge pump 1026 includes at least one charge pump unit, and the output voltage of each charge pump unit is the sum of its input voltage and the high level amplitude of the clock signal clk. The amplitude of the clock signal of the charge pump 1026 at the high level is 1/N of the preset amplitude Δv, and after the N charge pump units are cascaded, the power supply voltage Vcc may be raised to vcc+Δv, where N is a positive integer. For example, N may be equal to 1, that is, the magnitude of the clock signal clk of the charge pump 1026 at the high level is equal to the preset magnitude Δv, where the charge pump 1026 may include only one charge pump unit.

For example, the charge pump unit may employ a circuit configuration as shown in fig. 9, in which the magnitudes at the high levels of ClkA and ClkB are each 1/N times Δv, and the high levels of ClkA and ClkB do not overlap each other. Alternatively, the charge pump unit may also have other circuit structures, which is not limited in the present application.

According to the embodiment of the application, the power supply voltage Vcc is raised to Vcc+DeltaV through the charge pump, and the circuit has the advantages of simple structure and low cost.

Embodiments of the present application also provide a chip, as shown in fig. 10, where the chip 90 may include one or more of the power selection switch circuits 10 described in any of the embodiments above.

The chip 90 may be applied to a radio frequency front end module, and the radio frequency front end module further includes a power supply module and a power amplifier PA, where the power supply selection switch circuit 10 is connected between the power supply module and the power amplifier PA, so that when the power supply is turned on, a power supply voltage Vcc output by the power supply module is transmitted to the power amplifier PA to supply power to the power amplifier PA.

In some embodiments, the power amplifier PA needs a plurality of power supply modules to supply power to the power amplifier PA, and then a plurality of power supply selection switch circuits 10 are correspondingly needed, and each power supply module is connected to a power supply end of the power amplifier PA through a corresponding power supply selection switch circuit 10 respectively. Alternatively, a plurality of power supply selection switch circuits 10 may be integrated in one chip, or may be integrated in different chips, respectively.

The chip 90 includes at least two power selection switch circuits 10, wherein the drain electrode of the N-type field effect transistor in each power selection switch circuit 10 is respectively connected to the corresponding power supply module to receive the power supply voltage output by the corresponding power supply module, and the source electrode of the N-type field effect transistor in each power selection switch circuit is connected to the power supply end of the power amplifier PA, so that the corresponding power supply module is gated to supply power to the power amplifier PA when the N-type field effect transistor is turned on.

The chip 90 of the embodiment of the application adopts the power selection switch circuit 10, can simultaneously meet the requirements of small parasitic capacitance and small on-resistance of the power selection switch, accelerates the switching speed of the power selection switch and reduces the insertion loss of the power selection switch.

As an embodiment, as shown in fig. 11, the chip 90 further includes an enabling circuit 901, where the enabling circuit 901 is configured to enable at least one power supply selection switch circuit 10. For example, when a plurality of power supply modules are disposed in the rf front-end module, only one of the power supply modules is needed to supply power to the power amplifier at the same time, the enabling circuit 901 selects the power supply selection switch circuit 10 corresponding to the currently required power supply module from the plurality of power supply selection switch circuits 10 to enable, and the other power supply selection switch circuits 10 are turned off, so that the plurality of power supply modules supply power to the power amplifier PA simultaneously and interfere with each other.

Alternatively, the power supply selection switch circuit 10 and the power amplifier PA may be integrated in the same chip, or may be separately provided in different chips.

When the power supply selection switch circuit 10 is integrated with the power amplifier PA in the same chip, the power amplifier PA is also included in the chip 90. The power selection switch circuit 10 and the power amplifier PA are integrated together, which is beneficial to improving the integration level of the chip and enabling the radio frequency front-end module to be more miniaturized.

When the power selection switch circuit 10 and the power amplifier are disposed in different chips, the chip 90 does not include the power amplifier PA, and the power amplifier PA may be integrated in other chips of the rf front-end module. At this time, different chip processes may be adopted for the power selection switch circuit 10 and the power amplifier PA, for example, the power selection switch circuit 10 may select a CMOS (Complementary Metal-Oxide-Semiconductor) process, and the power amplifier PA may select an HBT (Heterojunction bipolar transistor) process, so that the production process of the rf front-end module is more flexible.

The embodiment of the present application further provides a radio frequency front end module, which includes a power amplifier PA and the power selection switch circuit 10 according to any of the foregoing embodiments.

Optionally, the radio frequency front end module further comprises at least one power supply module for supplying power to the power amplifier PA, and the power supply selection switch circuit 10 is connected between the corresponding power supply module and the power amplifier PA. Alternatively, the power supply module may be disposed outside the rf front-end module and electrically connected to the power selection switch circuit 10 in the rf front-end module.

As an embodiment, as shown in fig. 12, the rf front-end module further includes a substrate 110, and a first chip 111 and a second chip 112 disposed on the substrate, wherein the power amplifier PA is integrated in the first chip 111, and the power selection switch circuit 10 is integrated in the second chip 112. In this embodiment, the power selection switch circuit 10 and the power amplifier PA are independently disposed in different chips, so that the power selection switch circuit 10 and the power amplifier PA can flexibly employ different chip processes according to different circuit parameters, for example, the power selection switch circuit 10 can select a CMOS (Complementary Metal-Oxide-Semiconductor) process, and the power amplifier PA can select an HBT (Heterojunction bipolar transistor) process, so that the production process of the rf front-end module is more flexible.

As an embodiment, the radio frequency front-end module further comprises a control circuit 15, and the control circuit 15 is connected to the power amplifier PA and is used for controlling the power amplifier PA to work, for example, controlling a power supply mode, an operation mode, an output power and the like of the power amplifier PA. The control circuit 15 may be implemented in CMOS process, for example.

Alternatively, as shown in fig. 13, the control circuit 15 may be integrated in the second chip 112, and at this time, the power selection switch circuit 10 and the control circuit 15 are integrated in the second chip 112 together, so that the integration level of the second chip 112 can be improved, and the area of the radio frequency front end module can be reduced. Optionally, the enabling circuit may also be integrated in the second chip 112 to further improve the integration level of the second chip 112.

Alternatively, the control circuit 15 may be independent of the second chip 112, for example, as shown in fig. 14, and the rf front-end module further includes a third chip 113, where the control circuit 15 is integrated into the third chip 113. In this way, the power supply selection switch circuit 10 and the control circuit 15 are independently arranged in different chips, so that the structure of the control circuit 15 is not affected, and the power supply selection switch circuit 10 can be conveniently matched with the traditional chip product with the control circuit 15. At this time, the enable circuit of the power supply selection switch circuit 10 may be integrated in the third chip 113 together with the control circuit 15, or may be integrated in the second chip 112 together with the power supply selection switch circuit 10.

As an embodiment, as shown in fig. 15, the rf front-end module includes a substrate 110 and a fourth chip 114 disposed on the substrate 110, and the power amplifier PA and the power selection switch circuit 10 are integrated in the fourth chip 114. In this embodiment, the power selection switch circuit 10 and the power amplifier PA are integrated together, which is beneficial to improving the integration level of the chip and miniaturizing the rf front-end module.

In the above embodiments, each chip may be packaged on the substrate 110 by the same or different packaging processes, and electrical connection between different chips is achieved through traces on the substrate 110.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be appreciated by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not drive the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A power supply selection switch circuit, comprising:

the power supply selection switch is an N-type field effect transistor, the drain electrode of the N-type field effect transistor is used for receiving power supply voltage, the source electrode of the N-type field effect transistor is used for connecting with the power amplifier, and the power amplifier is supplied with power through the power supply voltage when the power amplifier is conducted;

the input end of the boosting circuit is used for receiving the power supply voltage, the output end of the boosting circuit is connected with the grid electrode of the N-type field effect transistor, and the boosting circuit is used for outputting the received power supply voltage after being lifted by a preset amplitude value;

The preset amplitude is larger than the conduction threshold voltage of the N-type field effect transistor and smaller than 1.1 times of the withstand voltage of the N-type field effect transistor.

2. The power selection switch circuit of claim 1, wherein the predetermined magnitude is at least twice the turn-on threshold voltage of the N-type field effect transistor.

3. The power selection switch circuit of claim 2, wherein the on threshold voltage of the N-type field effect transistor is less than or equal to 1V and the preset magnitude is greater than or equal to 3V.

4. The power selection switch circuit of claim 1, wherein the withstand voltage of the N-type field effect transistor is 5V, and the preset amplitude is less than or equal to 5.5V.

5. The power selection switch circuit of claim 1, wherein the predetermined magnitude is equal to a withstand voltage of the N-type field effect transistor.

6. The power selection switch circuit of claim 4, wherein the N-type field effect transistor has a withstand voltage of 5V and the predetermined magnitude is 5V.

7. The power supply selection switch circuit according to any one of claims 1 to 6, wherein the booster circuit includes:

A voltage-current conversion circuit for converting the power supply voltage into a first current, wherein the ratio of the power supply voltage to the first current is a first resistance value;

the current mirror circuit is used for mirroring the first current according to a preset current proportion to obtain a second current;

a current-voltage conversion circuit for receiving the second current and the third current, converting the sum of the second current and the third current into a first voltage, and outputting the first voltage to the gate of the N-type field effect transistor;

the sum of the second current and the third current is a fourth current, the ratio of the first voltage to the fourth current is a second resistance, the ratio of the preset amplitude to the third current is equal to the second resistance, and the ratio of the first resistance to the second resistance is equal to the current ratio.

8. The power supply selection switch circuit of claim 7, wherein the voltage-to-current conversion circuit comprises an operational amplifier, a first transistor, and a first resistor, wherein:

the first electrode of the first transistor is used for receiving the power supply voltage of the boost circuit, the first input end of the operational amplifier is used for receiving the power supply voltage, the second input end of the operational amplifier is connected with the second electrode of the first transistor, and the output end of the operational amplifier is connected with the control electrode of the first transistor;

One end of the first resistor is connected with the second pole of the first transistor, and the other end of the first resistor is grounded; wherein, the resistance value of the first resistor is equal to the first resistance value.

9. The power supply selection switch circuit according to claim 8, wherein the current-voltage conversion circuit includes a second resistor, one end of the second resistor is connected to the current source and the output end of the current mirror circuit, respectively, and the other end of the second resistor is connected to ground; the current source is used for outputting the third current, and the resistance value of the second resistor is equal to the second resistance value.

10. The power selection switch circuit of claim 9, wherein the current ratio is 1 and the second resistance value is equal to the first resistance value.

11. The power supply selection switch circuit of any of claims 1-6, wherein the boost circuit comprises a first bootstrap switch circuit and a second bootstrap switch circuit;

the first bootstrap switch circuit and the second bootstrap switch each receive the power supply voltage and a second voltage having the preset magnitude, and generate a third voltage based on the power supply voltage and the second voltage, the magnitude of the third voltage being equal to a sum of the magnitude of the power supply voltage and the preset magnitude;

The output ends of the first bootstrap switch circuit and the second bootstrap switch circuit are respectively connected with the grid electrode of the N-type field effect transistor;

the second bootstrap switch circuit is used for outputting the third voltage in a first time period, the first bootstrap switch circuit is used for outputting the third voltage in a second time period, and the first time period is connected with the second time period.

12. The power selection switch circuit of claim 11, wherein the first bootstrap switch circuit comprises a first capacitance, wherein:

during the first period, a first end of the first capacitor is used for receiving the second voltage, and a second end of the first capacitor is used for being grounded;

and in the second time period, the first end of the first capacitor is used for being connected with the grid electrode of the N-type field effect transistor, and the second end of the first capacitor is used for receiving the power supply voltage.

13. The power selection switch circuit of claim 12, wherein the first bootstrap switch circuit further comprises a first switch, a second switch, a third switch, and a fourth switch, wherein:

the first end of the first switch is used for grounding, and the second end of the first switch is connected with the second end of the first capacitor;

The first end of the second switch is used for being connected with a voltage source to receive the second voltage output by the voltage source, and the second end of the second switch is connected with the first end of the first capacitor;

the first end of the third switch is used for receiving the power supply voltage, and the second end of the third switch is connected with the second end of the first capacitor;

the first end of the fourth switch is connected with the first end of the first capacitor, and the second end of the fourth switch is connected with the grid electrode of the N-type field effect transistor;

wherein the first switch and the second switch are turned on in the first period of time and turned off in the second period of time;

the third switch and the fourth switch are turned off in the first period and turned on in the second period.

14. The power supply selection switch circuit of claim 11, wherein the second bootstrap switch circuit includes a second capacitor, wherein:

in the first time period, a first end of the second capacitor is used for being connected with a grid electrode of the N-type field effect transistor, and a second end of the second capacitor is used for receiving the power supply voltage;

during the second period, a first end of the second capacitor is configured to receive the second voltage, and a second end of the second capacitor is configured to be grounded.

15. The power supply selection switch circuit of claim 14, wherein the second bootstrap switch circuit further comprises a fifth switch, a sixth switch, a seventh switch and an eighth switch, wherein:

the first end of the fifth switch is used for being grounded, and the second end of the fifth switch is connected with the second end of the second capacitor;

the first end of the sixth switch is used for being connected with a voltage source to receive the second voltage output by the voltage source, and the second end of the sixth switch is connected with the first end of the second capacitor;

the first end of the seventh switch is used for receiving the power supply voltage, and the second end of the seventh switch is connected with the second end of the first capacitor;

the first end of the eighth switch is connected with the first end of the second capacitor, and the second end of the eighth switch is connected with the grid electrode of the N-type field effect transistor;

wherein the fifth switch and the sixth switch are turned off in the first period and turned on in the second period;

the seventh switch and the eighth switch are turned on for the first period and turned off for the second period.

16. The power selection switch circuit according to any one of claims 1 to 6, wherein the boost circuit comprises a charge pump, an input terminal of the charge pump is configured to receive the power supply voltage, and an output terminal of the charge pump is connected to a gate of the N-type field effect transistor.

17. The power selection switch circuit of claim 16, wherein the magnitude of the clock signal of the charge pump at a high level is 1/N of the preset magnitude, where N is a positive integer.

18. A chip comprising a power supply selection switch circuit as claimed in any one of claims 1 to 17.

19. The chip of claim 18, wherein the chip comprises at least two power selection switch circuits, the drain electrode of the N-type field effect transistor in each power selection switch circuit is respectively used for being connected with a corresponding power supply module so as to receive the power supply voltage output by the corresponding power supply module, and the source electrode of the N-type field effect transistor in each power selection switch circuit is used for being connected with a power supply end of a power amplifier;

the chip further comprises an enabling circuit for enabling at least one of the power supply selection switch circuits.

20. The chip of claim 18, wherein the chip further comprises the power amplifier.

21. A radio frequency front end module comprising a power amplifier and a power supply selection switch circuit as claimed in any one of claims 1 to 17.

22. The rf front-end module of claim 21, further comprising a substrate and first and second chips disposed on the substrate, the power amplifier being integrated within the first chip and the power selection switch circuit being integrated within the second chip.

23. The rf front-end module of claim 22, further comprising a third chip and a control circuit integrated within the third chip, the control circuit coupled to the power amplifier and configured to control operation of the power amplifier.

24. The rf front-end module of claim 23, further comprising a substrate and a fourth chip disposed on the substrate, the power amplifier and the power supply selection switch circuit being integrated within the fourth chip.