CN112637999B

CN112637999B - Constant current control circuit and chip

Info

Publication number: CN112637999B
Application number: CN202110248850.3A
Authority: CN
Inventors: 李瑞平; 刘彬; 王建虎
Original assignee: Shanghai Xinlong Semiconductor Technology Co ltd
Current assignee: Shanghai Xinlong Semiconductor Technology Co ltd
Priority date: 2021-03-08
Filing date: 2021-03-08
Publication date: 2021-05-28
Anticipated expiration: 2041-03-08
Also published as: CN112637999A

Abstract

The invention discloses a constant current control circuit and a chip, which comprise a sampling module, a ramp voltage generating module and a comparing module, wherein the sampling module comprises a voltage comparing unit and a voltage regulating unit, and the voltage regulating unit outputs a first voltage; the ramp voltage generation module outputs a second voltage; and the comparison module compares the first voltage with the second voltage to obtain a control signal which is changed along with the first voltage, and the control signal is used for controlling the state of the external power tube so as to control the average current flowing through the external energy storage element. According to the invention, the average current flowing through the external energy storage element is controlled by comparing the sampling voltage of the sampling resistor end with the preset threshold voltage, so that constant current output is realized.

Description

Constant current control circuit and chip

Technical Field

The invention relates to the field of constant current control, in particular to a constant current control circuit and a chip.

Background

A Light Emitting Diode (LED) is a solid-state semiconductor device that can convert electrical energy into visible light, and has the advantages of high light emitting efficiency and long life. The LED has a diode characteristic, and a constant current source driving module is required to control the LED.

The constant current source driving module is usually manufactured by using a constant current control chip, and the conventional constant current control chip has a complicated internal circuit structure and needs an error amplifier, an oscillator and a complicated control logic circuit. The power tube in the constant current control chip is controlled to be switched on and switched off after the difference value between the voltage at the sampling resistor and the reference voltage is amplified, so that the current flowing through the LED is kept stable, and constant current is realized. The constant current control chip with the structure needs an error amplifier and an oscillator with high precision, the circuit structure is complex, and the requirements on the process and the cost are high.

Disclosure of Invention

The invention provides a constant current control circuit and a chip, wherein a power tube in the chip is controlled to be switched on and off after the sampling voltage of a sampling resistor end is compared with a preset threshold voltage, so that the average current of an external energy storage element connected with an LED is controlled, and the constant current output is finally realized.

The embodiment of the invention provides a constant current control circuit, which comprises a sampling module, a ramp voltage generating module and a comparing module, wherein: the sampling module comprises a voltage comparison unit and a voltage regulation unit, wherein the voltage comparison unit comprises a first input end, a second input end, a third input end and a first output end, the first input end receives a first reference voltage, the second input end receives a second reference voltage smaller than the first reference voltage, the third input end receives a sampling voltage corresponding to the current flowing through the external energy storage element, wherein the first output terminal of the voltage comparing unit outputs a voltage adjusting signal to the voltage adjusting unit according to a comparison result of the sampled voltage and the second reference voltage during a period when the sampled voltage is less than the first reference voltage, the voltage regulating unit controls a first voltage storage element of the voltage regulating unit to be charged and discharged according to the voltage regulating signal, so that the voltage regulating unit outputs a first voltage; the ramp voltage generation module is used for controlling the charging and discharging of a second voltage storage unit of the ramp voltage generation module according to the state of an external power tube, so that the ramp voltage generation module outputs a second voltage; and the comparison module is used for comparing the first voltage with the second voltage to obtain a control signal which is changed along with the first voltage, and the control signal is used for controlling the state of an external power tube so as to control the average current flowing through an external energy storage element.

Further, the voltage regulating signal controls the first voltage storage element to charge during the period when the sampling voltage is less than the second reference voltage, and controls the first voltage storage element to discharge when the sampling voltage is greater than the second reference voltage and less than the first reference voltage.

Further, the second reference voltage is set to be greater than a difference between the first reference voltage and the second reference voltage.

Further, when the sampling voltage is smaller than the first reference voltage, the external power tube is turned on, so that the second voltage storage unit of the ramp voltage generation module is charged, and when the sampling voltage is larger than the first reference voltage, the external power tube is turned off, so that the second voltage storage unit of the ramp voltage generation module is discharged.

Further, when the sampling voltage is greater than the first reference voltage, a second output end of the voltage comparison unit outputs a signal to an external logic control module to control an external power tube to be cut off, the first voltage output by the voltage adjustment unit is maintained at a voltage at a time before the external power tube is cut off, and meanwhile the second voltage storage unit of the ramp voltage generation module discharges to reduce a second voltage.

Further, before the current flowing through the external energy storage element is reduced to zero, when the second voltage is reduced to be smaller than the first voltage, the comparison module outputs a control signal to control the external power tube to be conducted.

Further, the charging time of the first voltage storage element is increased, and the first voltage is increased, so that the cut-off time of the external power tube is reduced.

Further, before the current flowing through the external energy storage element drops to zero, the second voltage is always greater than the first voltage, and then the comparison module outputs a control signal to keep the external power tube off.

Further, the constant current control circuit further includes a power-on reset module connected to the first voltage storage element, and configured to provide a power-on reset signal to the first voltage storage element to perform discharging and zeroing on the first voltage storage element.

The embodiment of the invention also provides a constant current control chip which comprises the constant current control circuit provided by any embodiment of the invention.

The invention provides a constant current control circuit and a chip, wherein a power tube in the chip is controlled to be switched on and off after the sampling voltage of a sampling resistor end is compared with a preset threshold voltage, so that the average current flowing through an external energy storage element is controlled, and the constant current output is finally realized. Compared with a constant current control circuit and a chip with a traditional structure, the constant current control circuit and the chip provided by the invention have the advantages that an error amplifier and an oscillator are not arranged in the internal circuit structure, the internal circuit structure is simple, the requirement on the performance of a comparator is not high, the circuit structure is simple and stable, the area of the chip is small, the cost is low, and a peripheral circuit is simple, so that the cost of the LED constant current source driving module can be reduced.

Drawings

The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.

Fig. 1 is a schematic connection diagram of a constant current control system according to an embodiment of the present invention.

Fig. 2 is a block diagram of a constant current control circuit of the constant current control chip according to the embodiment of the present invention.

Fig. 3 is a schematic connection diagram of a constant current control circuit of the constant current control chip according to the embodiment of the present invention.

Fig. 4 is a schematic connection diagram of an internal module of a constant current control chip according to an embodiment of the present invention.

Fig. 5 is an exemplary detailed connection diagram of the constant current control circuit shown in fig. 3.

Fig. 6 is a simulation diagram of a constant current control system using the exemplary constant current control circuit shown in fig. 5.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The terms "first," "second," and the like in the description and in the claims, and in the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein.

Specifically, referring to fig. 1, fig. 1 is a connection schematic diagram of a constant current control system 2000 according to an embodiment of the present invention, where the constant current control system 2000 includes a constant current control chip 1000, a sampling resistor RCS, an inductor L1, a capacitor C3, a capacitor C4, a capacitor C5, a schottky diode D1, a power source VIN, and LEDs (such as an exemplary LED 1 and an exemplary LED 2). When the power transistors NM1 and NM2 (as shown in fig. 4) in the constant current control chip 1000 are turned on, the power source VIN passes through the LED, the inductor L1, the constant current control chip 1000, the sampling resistor RCS, and then to the ground, thereby forming a current loop. Therefore, the average current flowing through the inductor L1 is equal to the average current flowing through the LED, and the current (IL) flowing through the inductor L1 increases with a certain slope, while the current flowing through the sampling resistor RCS is equal to the current flowing through the inductor L1, so the voltage of the sampling resistor RCS also increases with a certain slope. Therefore, the change of the current on the inductor L1 can be obtained by acquiring the voltage change of the sampling resistor RCS; in addition, the on and off of the internal power tube NM2 are controlled according to the voltage change of the sampling resistor RCS, so that the current change on the inductor L1 can be controlled, the average current of the inductor L1 is controlled to reach the target average current, and constant current output is realized.

Specifically, as shown in fig. 1, the power source VIN is a power source of the whole constant current control system 2000, and is connected to the T1 pin of the constant current control chip 1000, the first end of the capacitor C4, the cathode of the schottky diode D1, the anode of the LED 1, and the first end of the capacitor C5. The second terminal of the capacitor C4 is connected to ground. The capacitor C4 is an output end capacitor and is used for realizing energy storage and filtering functions. The T2 pin of the constant current control chip 1000 is connected to the positive electrode of the schottky diode D1 and the first end of the inductor L1. The second end of the inductor L1 is connected to the cathode of the LED 2. And the cathode of the LED 1 is connected with the anode of the LED 2. The second end of the capacitor C5 is connected to the cathode of the LED 2 and the second end of the inductor L1, respectively. The capacitor C5 is the output capacitor of LED 1 and LED 2, i.e. the filter capacitor. A T5 pin of the constant current control chip 1000 is connected to one end of the sampling resistor RCS, and the other end of the sampling resistor RCS is grounded. Specifically, the sampling resistor RCS is a current sampling resistor, when the internal power transistors NM1 and NM2 (as shown in fig. 4) of the constant current control chip 1000 are turned on, the output currents of the LED 1 and the LED 2 flow through the internal power transistors NM1 and NM2 from the T2 pin through the inductor L1 and then flow through the sampling resistor RCS to the reference ground, a sampling voltage VCS is generated at the T5, and the constant current control system 2000 controls the on and off of the internal power transistor NM2 according to the sampling voltage VCS, so that the average output current of the constant current control system 2000 is stable, that is, the constant current state is achieved. In application, the magnitude of the regulating resistor RCS is usually selected to regulate the constant current value of the constant current control system 2000, so as to be suitable for different constant current application occasions. The schottky diode D1 provides a freewheeling loop for the inductor L1 when the internal power transistor NM2 is turned off. In addition, the T3 pin of the constant current control chip 1000 is connected to a first end of a capacitor C3, and the other end of the capacitor C3 is grounded. The capacitor C3 is used for energy storage filtering. The T4 pin of the constant current control chip 1000 is grounded.

Fig. 2 is a block diagram of a constant current control circuit 400 of the constant current control chip 1000 according to the embodiment of the present invention. The constant current control circuit 400 comprises a sampling module 401, a ramp voltage generating module 402 and a comparing module 403, wherein the sampling module 401 comprises a voltage comparing unit 4001 and a voltage adjusting unit 4002 connected with the voltage comparing unit 4001. The comparing module 403 receives the first voltage and the second voltage from the sampling module 401 and the ramp voltage generating module 402, respectively, and outputs a control signal to control the state of the power tube NM2, so as to control the average current flowing through the energy storage element (i.e., the inductor L1 shown in fig. 1).

Fig. 3 is a connection diagram of the constant current control circuit 400 of the constant current control chip 1000 shown in fig. 1. Specifically, the voltage comparing unit 4001 includes a first input terminal a, a second input terminal B, a third input terminal C, and a first output terminal D, the first input terminal a and the second input terminal B respectively receive a first reference voltage V1 and a second reference voltage V2 smaller than the first reference voltage V1, the third input terminal C receives a sampling voltage VCS corresponding to a current flowing through an energy storage element (i.e., an inductor L1 shown in fig. 1), when the sampling voltage VCS is smaller than the first reference voltage V1, the first output terminal D of the voltage comparing unit 4001 outputs a voltage adjusting signal to the voltage adjusting unit 4002 according to a comparison result between the sampling voltage VCS and the second reference voltage V2, the voltage adjusting unit 4002 controls charging and discharging of the first voltage storage element C1 of the voltage adjusting unit 4002 according to the voltage adjusting signal, so that the voltage adjusting unit 4002 outputs the first voltage VC 1. The ramp voltage generating module 402 controls the second voltage storage unit C2 of the ramp voltage generating module 402 to charge and discharge according to the state of the power tube NM2 (shown in fig. 4), so that the ramp voltage generating module 402 outputs a second voltage VC2, wherein the second voltage VC2 is a ramp voltage; and the comparing module 403 compares the first voltage VC1 with the second voltage VC2 to obtain a control signal varying with the first voltage VC1, and the control signal is used to control the state of the power tube NM2, so as to control the average current flowing through the external energy storage element (i.e., the inductor L1 shown in fig. 1).

The voltage regulation signal controls the first voltage storage element C1 to charge during the time when the sampled voltage VCS is less than the second reference voltage V2, and controls the first voltage storage element C1 to discharge during the time when the sampled voltage VCS is greater than the second reference voltage V2 and less than the first reference voltage V1. The second reference voltage V2 is set to be greater than the difference between the first reference voltage V1 and the second reference voltage V2, i.e., V2> V1-V2.

When the sampled voltage VCS is less than the first reference voltage V1, the power transistor NM2 (shown in fig. 4) is turned on, so that the second voltage storage unit C2 of the ramp voltage generation module 402 is charged, and when the sampled voltage VCS is greater than the first reference voltage V1, the power transistor NM2 is turned off, so that the second voltage storage unit C2 of the ramp voltage generation module 402 is discharged.

The voltage comparing unit 4001 further includes a second output terminal E, when the sampled voltage VCS is greater than the first reference voltage V1, the second output terminal E of the voltage comparing unit 4001 outputs an OCP signal to the logic control module 300 (shown in fig. 4) to control the power transistor NM2 (shown in fig. 4) to turn off, the first voltage VC1 output by the voltage adjusting unit 4002 is maintained at the voltage at the moment before the power transistor NM2 turns off, and the second voltage storage unit C2 of the ramp voltage generating module 402 discharges to decrease the second voltage VC 2. When the second voltage VC2 drops to be less than the first voltage VC1 before the current flowing through the external energy storage element drops to zero, the comparing module 403 outputs a control signal to control the power transistor NM2 to be turned on. The charging time period of the first voltage storage element C1 increases, and the first voltage VC1 increases, so that the off-time of the power transistor NM2 decreases. When the second voltage VC2 is always greater than the first voltage VC1 before the current flowing through the external energy storage element (i.e., the inductor L1 shown in fig. 1) drops to zero, the comparing module 403 outputs a control signal to keep the power transistor NM2 turned off.

The constant current control circuit 400 in this embodiment further includes a power-on reset module connected to the first voltage storage element C1, where the power-on reset module includes a switch K5. The power-on reset module is configured to provide a power-on reset signal POR to the first voltage storage element C1 to discharge and zero the first voltage storage element C1.

The operation principle of the constant current control circuit 400 will be specifically described below with reference to fig. 1 to 3.

As shown in fig. 3, V1, V2, and V3 are three reference voltages provided by the reference voltage generation module 404 (shown in fig. 5) inside the constant current control circuit 400. The second reference voltage V2 is set to be greater than the difference between the first reference voltage V1 and the second reference voltage V2, and the third reference voltage V3 is set to make the current mirror, which charges and discharges the first voltage storage element C1, have a proper operating region. The ON signal, DRN signal, and OCP signal are logic control signals, where the DRN signal and the OCP signal are used to control the ON and off of the power transistor NM2 (shown in fig. 4) inside the constant current control chip 1000, and the ON signal and the aforementioned voltage adjustment signal are used to control the opening and closing of the switches K1, K2, K3, and K4 in the constant current control circuit 400. In the present embodiment, the switches K1, K3 and K4 are (P-type metal-oxide-semiconductor transistors, i.e., PMOS transistors), and K2 is (N-type metal-oxide-semiconductor transistors, i.e., NMOS transistors). The ON signal is high during the ON period of the power transistor NM2 and low during the off period of the power transistor NM 2. The DRN signal is a signal for forcing the power transistor NM2 to be turned on, when the DRN signal is at a high level, the power transistor NM2 is forced to be turned on, and when the DRN signal is at a low level, the power transistor NM2 of the constant current control chip 1000 is no longer controlled (i.e., the current on or off state of the power transistor NM2 is maintained), but the power transistor NM2 is turned off by the OCP signal, that is, when the OCP signal is at a high level, the power transistor NM2 of the constant current control chip 1000 is turned off, and when the OCP signal is at a low level, the power transistor NM2 of the constant current control chip 1000 is not controlled to be turned off. The third input terminal C is a current sampling terminal that receives a sampling voltage VCS generated by a current flowing through a sampling resistor RCS. In this embodiment, the sampling voltage VCS is a voltage VCS generated by the current IL of the inductor L1 flowing through the sampling resistor RCS, i.e., VCS = IL RCS. The average output current of the constant current control system 2000 within the on-time of the power tube NM2 can be sampled by the variation of the sampling voltage VCS of the current sampling end, the average output current is controlled by adjusting the on-time and the off-time of the power tube NM2, and the purpose of constant current output is finally achieved.

The basic principle of the invention is to control the average current of the inductor L1 to realize constant current output by setting the threshold voltage points (i.e. the first reference voltage V1 and the second reference voltage V2) of two comparators (i.e. the comparator COMP1 and the comparator COMP 2). The first reference voltage V1 and the second reference voltage V2 correspond to a peak current and a center current of the inductor L1, respectively (the center current is a target average current). Note that specific functions and connection relationships of the comparators COMP1, COMP2 and other components shown in fig. 3 will be described in detail below with reference to fig. 5. Specifically, referring to fig. 1 to 3, when the constant current control chip 1000 is powered ON, the constant current control chip 1000 steps down a voltage VIN1 of a power source VIN to a voltage VDD, and supplies power to other internal modules, after the voltage is stabilized, there is no current at an output terminal, and a sampling voltage VCS is smaller than V2 and smaller than V1, that is, a current of an inductor L1 is smaller than a central current and a peak current, an OCP signal outputs a low level, the logic control module 300 (shown in fig. 4) outputs a DRIVE signal to control a power tube NM2 (shown in fig. 4) to be turned ON, and at this time, an ON signal is a high level, and the power source VIN forms a current loop via an LED (LED 1 and LED 2) and an inductor L1, a power tube NM1 (shown in fig. 4) and an NM2, and then through a current sampling terminal (third input terminal C) and a sampling resistor RCS to a. The current in the inductor L1 increases with a slope, and the current in the sampling resistor RCS is equal to the current in the inductor L1, and the voltage in the sampling resistor RCS also increases with a slope, i.e., the sampling voltage VCS increases with a slope. During the period when the sampled voltage VCS is less than V2, the switch K1 of the sampling module 401 is closed, K2 is open, and the reference current module 405 (shown in fig. 5) charges the first voltage storage element C1 with a constant current, I1; meanwhile, during the ON signal is high, the switch K3 of the ramp voltage generating module 402 is closed, the switch K4 is opened, and the voltage of the second voltage storage unit C2 is rapidly charged to V3 (non-constant current charging). When the sampling voltage VCS rises to be greater than V2 and less than V1, i.e., the current of the inductor L1 is greater than the center current and less than the peak current, the switch K1 of the sampling module 401 is open, K2 is closed, the first voltage storage element C1 discharges at the constant current I2, and I1= I2. When the sampling voltage VCS is slightly larger than V1, that is, when the current of the inductor L1 is larger than the peak current, the OCP signal outputs a high level, the power tube NM2 is controlled to be turned off, the current of the inductor L1 stops rising, and starts to fall according to a certain slope; when the power tube NM2 is turned off, no current flows through the sampling resistor RCS, and the sampling voltage VCS is equal to zero.

In the initial power-up stage, the voltage of the second voltage storage unit C2 is quickly charged to V3, and then the periodic constant current I3 discharge is performed, i.e. when the OCP signal triggers the power transistor NM2 (as shown in fig. 4) to turn off, the second voltage storage unit C2 discharges at the constant current I3, the second voltage VC2 ramps down, and when the next period power transistor NM2 is turned on, the voltage of the second voltage storage unit C2 is quickly charged to V3, which is cycled periodically. It should be noted that the second voltage storage unit C2 is charged using the fixed voltage V3, and thus its process of being charged to V3 is not constant current charging; in addition, the current for charging the second voltage storage unit C2 is much larger than the discharging current I3. As described above, the charging current I1 of the first voltage storage element C1 is equal to the discharging current I2, so that the voltage VC1 (i.e., the first voltage) of the first voltage storage element C1 continuously rises only when the charging duration is longer than the discharging duration, and when the voltage VC1 of the first voltage storage element C1 is continuously less than the voltage VC2 of the second voltage storage unit C2, the constant current control chip 1000 operates in the critical point mode (BCM). When the constant current control chip 1000 operates in the critical point mode, the zero-crossing detection module 200 (shown in fig. 4) inside the constant current control chip 1000 detects that the current of the inductor L1 drops to zero, and then the power tube NM2 of the constant current control chip 1000 is turned on. Since the current of the inductor L1 is zero before the power transistor NM2 is turned on, the current of the inductor L1 increases with a certain slope from zero after the power transistor NM2 is turned on, and therefore, when the constant current control chip 1000 operates in the critical point mode, the sampling voltage VCS rises from zero, the first voltage storage element C1 is charged during the period from zero to V2, and the first voltage storage element C1 is discharged during the period from V2 to V1. In the present embodiment, the relationship between V2 and V1 is reasonably set to realize that V2> V1-V2, so that when the constant current control chip 1000 operates in the critical point mode, the time t1 for the sampling voltage VCS to rise from zero to V2 is greater than the time t2 for the sampling voltage VCS to rise from V2 to V1, that is, the time period t1 for charging the first voltage storage element C1 is greater than the discharge time period t2, and that the voltage VC1 of the first voltage storage element C1 can be continuously raised.

When the voltage VC1 of the first voltage storage element C1 is greater than the voltage VC2 of the second voltage storage unit C2 once at a certain off time of the power tube NM2 after a number of charging cycles, the operation mode of the constant current control chip 1000 is changed to a continuous mode (CCM), and the voltage VC1 of the first voltage storage element C1 fluctuates periodically up and down to a small range. In this mode, the power transistor NM2 is turned on (as shown in fig. 4) when the current of the inductor L1 does not drop to zero, i.e., in this mode, the valley current (initial current) of the inductor L1 is greater than zero, i.e., the sampling voltage VCS does not rise from zero, and the time for charging the first voltage storage element C1 is gradually reduced and finally stabilizes at the time t1 for charging the first voltage storage element C1 being equal to the discharge time t 2. Specifically, after the constant current control chip 1000 enters the continuous mode, when the power transistor NM2 is turned off, the ON signal is at a low level, and both the switches K1 and K2 are in an off state, so that the voltage VC1 of the first voltage storage element C1 remains unchanged, i.e., is equal to the voltage value corresponding to the last moment before the power transistor NM2 is turned off; meanwhile, the second voltage storage unit C2 discharges through the constant current I3, the voltage VC2 thereof decreases according to a certain slope, when the voltage VC2 decreases to be less than the voltage VC1 of the first voltage storage element C1, the comparison module 403 (i.e., the comparator COMP 3) outputs a DRN signal at a high level, at this time, the power tube NM2 is forced to be turned on, the current flowing through the inductor L1 continuously increases from the valley current (non-zero), and the sampling voltage VCs continuously increases accordingly. When the sampling voltage VCS generated on the sampling resistor RCS by the current flowing through the inductor L1 is greater than V1, i.e., when the current flowing through the inductor L1 reaches the peak current, the OCP signal is output at a high level to turn off the power transistor NM 2. The power tube NM2 is thus periodically turned on and off, and the average current flowing through the inductor L1 is finally constant to the target average current. It should be appreciated that the average current of the inductor L1 is half the sum of the peak current and the valley current. In this embodiment, the peak current is constant (i.e., corresponds to the current when the sampled voltage VCS reaches V1). It can be deduced that, when the constant current control chip 1000 operates in the continuous mode, and the average current of the inductor L1 in the previous off-time of the power transistor NM2 is smaller than the target average current, that is, the initial value of the sampling voltage VCS is smaller in the current on-time of the power transistor NM2, the time t1 of charging the first voltage storage element C1 in the current on-time is increased (i.e., t1> t 2), the voltage VC1 is increased, and the time for the voltage VC2 (the peak of VC2 is fixed to V3) to fall to be smaller than the voltage VC1 in the current off-time is shortened, that is, the off-time of the power transistor NM2 is shortened, so that the average current in the current off-time is increased. Similarly, when the average current of the inductor L1 of the power transistor NM2 in the previous off-time is greater than the target average current, that is, the initial value of the sampled voltage VCS is greater in the current on-time, the time t1 for charging the first voltage storage element C1 in the current on-time is shortened (i.e., t1< t 2), the voltage VC1 is decreased, the time for the voltage VC2 to decrease to be less than the voltage VC1 in the current off-time is increased, that is, the off-time of the power transistor NM2 is increased, so as to decrease the average current in the current off-time. In this way, the charging time of the first voltage storage element C1 is adjusted by the variation of the sampling voltage VCS to increase or decrease the voltage VC1, so as to continuously adjust the average current flowing through the inductor L1 to reach the target average current, and finally achieve a constant current output (i.e., reach a steady state).

In the embodiment, as shown in fig. 3, the POR signal is a power-on reset signal of the constant current control chip 1000, and the POR signal closes the switch K5 for a short time to reset the level signal of the first voltage storage element C1 each time the constant current control chip 1000 is powered on.

As described above, the calculation process and the calculation formula of the switching period (T), the on-Time (TON) and the off-Time (TOFF) of the power tube NM2 (shown in fig. 4) when the constant current control chip 1000 reaches the steady state are:

1. when the power transistor NM2 is turned on, the charging time t1 of the first voltage storage element C1 is equal to the discharging time t2, and the discharging time t2 is used to calculate the on-time TON of the power transistor NM2, and the discharging time t2 of the first voltage storage element C1 is determined by the time when the sampled voltage VCS rises from V2 to V1.

Specifically, when the power transistor NM2 is turned on, the calculation formula of the induced voltage across the inductor L1 is:

△VL1=L*△I/△t

where Δ t is the on-time TON of the power tube NM2, Δ VL1= VIN1-VOUT, VIN1 is the input voltage of the power supply VIN, VOUT is the voltage across the output terminals LED (i.e. the sum of the voltages across LED 1 and LED 2), and L is the inductance of the inductor L1. Therefore, by obtaining the current change amount Δ I of the inductor L1, Δ t, that is, TON can be calculated.

During the on period (TON period) of the power tube NM2, the current variation Δ I of the inductor L1 corresponds to the voltage variation generated on the sampling resistor RCS, i.e. 2 × (V1-V2), because the first voltage storage element C1 has two states of charging and discharging during the on period of the power tube NM2, and in the steady state, the time t1 of charging is equal to the time t2 of discharging. At the time of discharge t2, the voltage variation is equal to V1-V2, so the variation of the sampling voltage VCS during charging is also equal to V1-V2, and the voltage variation during the conduction period of the power tube NM2 is equal to 2 (V1-V2), so the current variation Δ I is calculated to be equal to 2 (V1-V2)/RCS, and finally the conduction Time (TON) of the power tube NM2 when the steady state is reached is derived as:

TON=2*t1=L*△I/△VL1=L*2*(V1-V2)/RCS/(VIN1-VOUT)

2. during the off period (TOFF period) of the power tube NM2, the current of the inductor L1 decreases with a certain slope, and during the TOFF period, the absolute value of the change of the current of the inductor L1 is actually equal to the absolute value of the change of the current during the TON period, so that the change of the current Δ I' during the TOFF period is equal to 2 × (V1-V2)/RCS; during TOFF, the induced voltage Δ VL 1' across the inductor is approximately equal to VOUT (negligible tube drop for schottky diode D1). Therefore, the cut-off Time (TOFF) of the power tube NM2 when reaching the steady state can be derived as:

TOFF=L*△I’/△VL1’=L*2*(V1-V2)/RCS/VOUT

therefore, the switching period T of the power tube NM2 when the steady state is reached can be obtained by the formula T = TON + TOFF.

Since the change in the value of the sampling resistor RCS corresponds to the change in the current of the inductor L1, the switching period of the constant current control chip 1000 is related to the change in the current of the inductor L, the input voltage VIN1, the output voltage VOUT, and the inductor L1.

The sampling voltage VCS is a voltage generated by the current of the inductor L1 flowing through the sampling resistor RCS, and when the second reference voltage V2 is set to a voltage corresponding to the target average current of the inductor L1, the average current is V2/RCS.

Fig. 4 is a schematic diagram illustrating connection of internal modules of the constant current control chip 1000 (including pins T1-T5) shown in fig. 1. The constant current control chip 1000 includes an internal power supply and reference module 100, a zero-crossing detection module 200, a logic control module 300, a constant current control circuit 400, and power transistors NM1 and NM 2. In this embodiment, both the power transistors NM1 and NM2 are NMOS transistors.

The internal power and reference module 100 receives an input voltage VIN1 from a power source VIN through a pin T1, and a low-dropout linear regulator module (not shown) of the internal power and reference module 100 steps down the input voltage VIN1 from the power source VIN to VDD to supply power to the zero-crossing detection module 200, the constant-current control circuit 400, and a G terminal (gate) of the high-voltage power tube NM1 in the constant-current control chip 1000. The source voltage of the high voltage power transistor NM1 is limited to VDD-VTHNM1 (VTHNM 1 is the conducting voltage drop of the power transistor NM 1), so the power transistor NM2 can use a low voltage power transistor with very low cost. In this embodiment, as shown in fig. 4, the logic control module 300 outputs the DRIVE signal to turn on the power tube NM2, so as to complete the switching operation of the constant current control chip 1000; compared with the power transistor NM1, the parasitic capacitance of the gate (G terminal) of the power transistor NM2 is much smaller, so that the requirement on the driving capability of the constant current control chip 1000 is not high. The internal power supply and reference module 100 also supplies a reference voltage VREF, which is set to 1.25V in the present embodiment, to the internal circuit module (e.g., the constant current control circuit 400). The internal power and reference block 100 further provides a power-on reset signal POR to the constant current control circuit 400, where the POR signal is a voltage that is temporarily set high at each power-on, and is used to discharge and zero the first voltage storage element C1 of the constant current control circuit 400.

The constant current control chip 1000 further includes a zero crossing detection module 200, and as shown in fig. 3 and 4, the zero crossing detection module 200 receives the current of the inductor L1 through a T2 pin. When the power supply is just powered on, the voltage VC1 of the first voltage storage element C1 is much smaller than the voltage VC2 of the second voltage storage unit C2, and the DRN signal output by the comparator COMP3 is always at a low level, so the power transistor NM2 is not controlled to be turned on; at this time, the zero-crossing detection module 200 can implement: during TOFF, when the current of the inductor L1 is detected to be zero, the zero crossing detection module 200 outputs a ZCD signal to the logic control module 300, and controls the power transistor NM2 to be turned on again. When the current of the inductor L1 rises from zero, the charging time of the first voltage storage element C1 is longer than the discharging time, so that the voltage VC1 of the first voltage storage element C1 is continuously increased, and after a certain time, the voltage VC1 of the first voltage storage element C1 is higher than the voltage VC2 of the second voltage storage unit C2 during TOFF, the constant current control chip 1000 enters the continuous mode from the critical point mode, and at this time, the zero-cross detection module 200 does not control the internal logic of the constant current control chip 1000, i.e., does not control the conduction of the power tube NM2, but controls the conduction of the power tube NM2 according to the comparison result of the voltages VC1 and VC2 by the DRN signal. The OCP signal is used to control the NM2 to be turned off, whether in critical-point mode or continuous mode. In the continuous mode, the constant current control chip 1000 gradually stabilizes the on and off time of the power tube NM2, and finally reaches a constant current stable state.

The logic control module 300 receives control signals (e.g., DRN signal, OCP signal, ZCD signal) from the zero-cross detection module 200 and the constant current control circuit 400, processes the control signals of the zero-cross detection module 200 and the constant current control circuit 400, controls the ON and off of the power tube NM2 through the DRIVE signal, and controls the switching of the sampling module 401 (shown in fig. 3) of the constant current control circuit 400 through the ON signal.

The constant current control circuit 400 receives signals from the internal power supply and reference module 100 and the logic control module 300, and receives a sampling voltage VCS generated by the current of the inductor L1 flowing through the sampling resistor RCS through a pin T5, when the constant current control circuit 400 detects that the current of the inductor L1 is higher than a set peak current (i.e., the sampling voltage VCS is greater than a first reference voltage V1), the constant current control circuit 400 outputs an OCP signal to the logic control module 300, and the logic control module 300 turns off the power transistor NM 2. When in the continuous mode, the length of the off time of the power tube NM2 is controlled by the constant current control circuit 400, and when the constant current control circuit 400 outputs the DRN signal to the logic control module 300 as a high level, the power tube NM2 can be turned on. Therefore, the invention controls the cut-off and the conduction of the power tube by limiting the maximum inductance current, sampling the average inductance current in each conduction time of the power tube, and adjusting the average inductance current to realize the constant current control.

Fig. 5 is an exemplary detailed connection diagram of the constant current control circuit 400 shown in fig. 3. As shown in fig. 5, the constant current control circuit 400 includes a sampling module 401, a ramp voltage generating module 402, a comparing module 403, a reference voltage generating module 404, and a reference current module 405. Wherein the sampling module 401 comprises a voltage comparison unit 4001 and a voltage adjustment unit 4002.

The reference current module 405 includes a bias current source IBIAS, which provides corresponding capacitor charging and discharging currents for the sampling module 401 and the ramp voltage generation module 402. Wherein I1 is the charging current of the sampling capacitor C1 (i.e., the first voltage storage element), I2 is the discharging current of the sampling capacitor C1, and I3 is the discharging current of the ramp capacitor C2 (i.e., the second voltage storage unit).

The reference voltage generating module 404 includes an operational amplifier OP1, a PMOS transistor M1, a resistor R1, a resistor R2, a resistor R3, and a resistor R4. A first input terminal of the operational amplifier OP1 receives the reference voltage VREF, an output terminal of the operational amplifier OP1 is connected to the gate of M1, a source of M1 receives the voltage VDD, a drain of M1 and one end of the resistor R1 form a first common terminal, and the first common terminal outputs a third reference voltage (e.g., 3.2V) to the ramp voltage generating module 402. The other end of the resistor R1 and one end of the resistor R2 form a second common terminal, and the second common terminal is connected to the second input terminal of the operational amplifier OP 1. The other end of the resistor R2 and one end of the resistor R3 form a third common terminal, which outputs a first reference voltage (e.g., 300 mv) to the voltage comparison unit 4001 of the sampling module 401. The other end of the resistor R3 and one end of the resistor R4 form a fourth common terminal, which outputs a second reference voltage (e.g., 200 mv) to the voltage comparison unit 4001 of the sampling module 401. The other end of the resistor R4 is grounded.

The reference voltage generating module 404 provides a first reference voltage (e.g., 300 mv), a second reference voltage (e.g., 200 mv) and a third reference voltage (e.g., 3.2V) to the voltage comparing unit 4001 and the ramp voltage generating module 402, and the voltage of the second common terminal between the resistors R1 and R2 is equal to the reference voltage VREF according to the principle of the operational amplifier, so that three different constant voltage reference voltages can be obtained by adjusting the ratio of the resistors R1, R2, R3 and R4, and the reference voltages can be provided to other modules.

The voltage comparison unit 4001 of the sampling module 401 includes comparators COMP1 and COMP 2. A first input terminal of COMP1 receives a first reference voltage (e.g., 300 mv), a second input terminal of COMP1 and a first input terminal of COMP2 receive a sampled voltage VCS, and a second input terminal of COMP2 receives a second reference voltage (e.g., 200 mv). The output of COMP1 outputs the OCP signal to logic control module 300 (shown in FIG. 4). An output terminal of COMP2 outputs a voltage regulation signal to the voltage regulation unit 4002.

The voltage regulation unit 4002 of the sampling module 401 includes a NAND gate NAND1, a NAND gate NAND2, a not gate INV1, a PMOS transistor K1, an NMOS transistor K2, a capacitor C1, and an NMOS transistor K5. A first input of the NAND1 receives the voltage regulation signal from the COMP2, a second input of the NAND1 receives the ON signal from the logic control module 300 (shown in FIG. 4), an output of the NAND1 is connected to a first input of the NAND2 and an input of the INV1, respectively, and a second input of the NAND2 receives the ON signal. The output terminal of the NAND2 is connected to the gate of K1, and the source of K1 receives the charging current I1 provided by the reference current module 405. The output terminal of the INV1 is connected to the gate of K2, and the source of K2 outputs the discharge current I2 to the reference current module 405. The drain of the K1 and the drain of the K2 form a common terminal, the common terminal is connected to a first end of a capacitor C1, a first end of the capacitor C1 is further connected to a first input terminal of a comparator COMP3 of the comparison module 403, and is used for outputting a first voltage VC1, and the other end of the capacitor C1 is grounded. The gate of K5 receives the POR signal from the internal power and reference block 100 (shown in FIG. 4), the drain of K5 is connected to the first terminal of the capacitor C1, and the source of K5 is grounded.

With reference to fig. 4 and 5, the basic operation principle of the sampling module 401 is: when the power transistor NM2 is turned off, that is, the ON signal is low, the INV1 output is low, K2 is turned off, the NAND2 output is high, K1 is turned off, the capacitor C1 has no charge-discharge path, and the capacitor C1 is in a sample-and-hold state. When the power transistor NM2 is turned ON, that is, the ON signal is at a high level, if the sampling voltage VCS is less than 200mv, COMP1 and COMP2 output a low level, that is, the COMP1 outputs an OCP signal at a low level, the COMP2 outputs a voltage regulation signal at a low level, and at the same time, both NAND2 and INV1 output a low level, so that K1 is turned ON, K2 is turned off, the capacitor C1 starts to be charged, and the charging current is I1; when the sampling voltage VCS is greater than 200mv and less than 300mv, the voltage regulation signal output by COMP2 is at a high level, the OCP signal output by COMP1 is still at a low level, and at the same time, NAND2 and INV1 output a high level, at this time, K1 is turned off, K2 is turned on, the capacitor C1 starts to discharge, and the discharge current is I2 (I2 = I1). When the sampling voltage VCS is greater than 300mv, COMP1 and COMP2 output a high level, and the OCP signal (over-current detection signal) outputs a high level to the logic control module 300 to control the cutoff of the power tube NM2, so that the inductor L1 enters a freewheeling state through the schottky diode D1, at this time, the ON signal transitions to a low level, at this time, K1 and K2 are cut off, and the sampling module 401 enters a sample-and-hold state. Wherein 300mv is the maximum value of the set sampling voltage VCS (i.e. the peak current corresponding to the inductor L1), and 200mv is the central value of the set sampling voltage VCS (i.e. the target average current corresponding to the inductor L1), i.e. the average current of the inductor L1 is 0.2V/RCS when the whole system is operated in the steady state of the continuous mode. The POR signal is a power-on reset signal of the constant current control chip 1000, and the logic signal control module 300 outputs a signal with a high level for a short time to the sampling module 401 every time power is turned on, so as to discharge the residual charge on the capacitor C1, thereby preventing the residual charge from affecting the whole system.

The ramp voltage generating module 402 includes an operational amplifier OP2, an inverter INV2, an inverter INV3, a PMOS transistor K3, a PMOS transistor K4, and a capacitor C2. The first input terminal of the operational amplifier OP2 receives the third reference voltage (e.g., 3.2V) from the reference voltage generating module 404. A second input terminal of the operational amplifier OP2 is connected to an output terminal thereof. The input terminal of the INV2 receives the ON signal from the logic control module 300 (shown in fig. 4), and the output terminal of the INV2 is connected to the input terminal of INV3 and the gate of K3, respectively. The source of K3 is connected with the output end of operational amplifier OP2, the output end of INV3 is connected with the gate of K4, the source of K4 and the drain of K3 are connected and form a common end, the common end is connected with the first end of capacitor C2, and the second end of capacitor C2 is grounded. The drain of K4 outputs a discharge current I3 to the reference current module 405. The first end of the capacitor C2 is further connected to a second input end of the comparator COMP3 of the comparing module 403, for outputting a second voltage VC 2.

The operational amplifier OP2 of the ramp voltage generation module 402 is used as a voltage follower, which considers that the ramp voltage generation module 402 needs to rapidly charge the capacitor C2 to the third reference voltage (e.g., 3.2V), and if the third reference voltage of the reference voltage generation module 404 is directly used, the reference voltage of the reference voltage generation module 404 may fluctuate, thereby affecting the accuracy and reliability of the whole system. When the power transistor NM2 (shown in fig. 4) is turned ON, i.e. the ON signal is high, the INV2 outputs low, K3 is turned ON, K4 is turned off, and the capacitor C2 is charged to 3.2V. When the power tube NM2 is turned off, that is, when the ON signal is at a low level, K3 is turned off, K4 is turned ON, the capacitor C2 starts to discharge, the discharge current is I3, and the second voltage VC2 output by the capacitor C2 is in a downward slope.

The comparing module 403 comprises a comparator COMP3, a first input terminal of which receives the first voltage VC1 outputted by the sampling module 401, a second input terminal of which receives the second voltage VC2 outputted by the ramp voltage generating module 402, and an output terminal of which outputs a DRN signal to the logic control module 300 (shown in fig. 4) for controlling the power transistor NM2 (shown in fig. 4) to be turned on. When the constant current control chip 1000 operates in the critical point mode, that is, the second voltage VC2 (i.e., the ramp voltage) is always greater than the first voltage VC1, the DRN signal is at a low level, which does not control the conduction of the power transistor NM2, but the zero-crossing detection module 200 (shown in fig. 4) controls the conduction of the power transistor NM 2. When the power transistor NM2 is turned off, the second voltage VC2 is less than the first voltage VC1 at a certain time, the constant current control chip 1000 operates in the continuous mode, and the DRN signal changes from low level to high level, and the control logic control module 300 turns on the power transistor NM2, that is, the time from the turn-off time of the power transistor NM2 to the time when the second voltage VC2 drops to VC1 is the turn-off time of the power transistor NM2 in the current cycle. When the first voltage VC1 increases, the off-time of the power transistor NM2 decreases, and the average current of the inductor L1 in the current period increases. By controlling the off-time of the power tube NM2, the average current of the inductor L1 in the current cycle can be controlled.

Fig. 6 is a simulation diagram of the constant current control system 2000 using the exemplary constant current control circuit 400 shown in fig. 5, in which the variation processes of the first voltage VC1, the second voltage VC2, the LED current (output current of the constant current control system 2000), and the inductor current in the critical-point mode (during the t0 period) and the continuous mode (during the t01 period) are shown. Referring to fig. 1 to 5, in the constant current control system 2000 in the present embodiment, the sampling resistor RCS is set to 571 mq, and the first reference voltage V1 is set to 300mv, the second reference voltage V2 is set to 200mv, and the third reference voltage V3 is set to 3.2V. In other embodiments, the sampling resistor RCS may be set to different values to achieve different constant current values. As shown in fig. 6, after the constant current control system 2000 is powered on, it operates in the critical point mode in the time period t0, that is, when the current of the inductor L1 reaches the current limiting value (VCS is greater than V1), the power tube NM2 is turned off, and when the current of the inductor L1 passes through zero, the power tube NM2 is turned on. In each on and off period of the power tube NM2, the voltage VC1 of the sampling capacitor C1 rises in a step shape, and when VC1 approaches 3.2V, the system enters a continuous mode (t 01 time period), in which the constant current control system 2000 gradually adjusts the current of the inductor L1 to a target average current, and the constant current control system 2000 enters a steady state.

In this embodiment, when the constant current control system 2000 operates in the critical point mode, the power transistor NM2 is turned on after the current IL of the inductor L1 is set to zero, and the power transistor NM2 is turned off when the current reaches the peak value, so that the sampling voltage VCS (VCS = RCS × IL) varies from 0 to V1 (0-300 mv). Since the current IL of the inductor L1 is linear, the average current Ibcm of the inductor L1 in the critical point mode is half of the sum of the peak current and the valley current in the on period, i.e., the average current Ibcm = [ (300mv +0)/RCS ] × 0.5, when the peak current corresponds to the current when the sampling voltage VCS is the peak voltage V1 (i.e., 300 mv), and the valley current corresponds to the current when the sampling voltage VCS is the valley voltage 0V.

As described above, if the target average current of the inductor L1 is set to be the current when the sampling voltage VCS is equal to the second reference voltage (e.g., 200 mv), and the current of the inductor L1 tends to be in a steady state after reaching the target average current, the constant current control system 2000 may turn off the power transistor NM2 when receiving the sampling voltage VCS of 300mv, and turn on the power transistor NM2 when the sampling voltage VCS is 100mv, so that the average current of the inductor L1 reaches the target average current I = [ (300mv +100mv)/RCS ] × 0.5.

In practical operation, when the constant current control system 2000 operates in the continuous mode, if the power transistor NM2 is turned on, the received initial sampling voltage VCS1 is less than 100mv, which means that the average current of the inductor L1 in the last off period is less than the target average current I. Since the time for the sample voltage to rise from 100mv to 200mv is equal to the time for the sample voltage to rise from 200mv to 300mv (the inductor current varies linearly), the time for the sample voltage VCS1 to rise from less than 100mv to 200mv will be greater than the time for the sample voltage to rise from 200mv to 300 mv. That is, the charging time t1 of the capacitor C1 is greater than the discharging time t2, thereby increasing the first voltage VC1 of the current off period. Therefore, after VC1 increases, its intersection point with the second voltage VC2 moves forward in the off period of NM2, i.e. the time when the second voltage VC2 drops to less than VC1 moves forward, so the off time of NM2 is reduced, and the change of the inductor current is linear, so reducing the off time is equivalent to increasing the average current.

Similarly, if the initial sampling voltage VCS2 received by the power transistor NM2 at the turn-on time is greater than 100mv, it means that the average current of the inductor L1 in the last turn-off period is greater than the target average current I. As described above, since the time for the sample voltage to rise from 100mv to 200mv is equal to the time for the sample voltage to rise from 200mv to 300mv (the inductor current varies linearly), the time for the sample voltage VCS2 to rise from greater than 100mv to 200mv will be less than the time for the sample voltage to rise from 200mv to 300 mv. That is, the charging time t1 of the capacitor C1 is less than the discharging time t2, thereby reducing the first voltage VC1 of the current off period. Therefore, after VC1 is decreased, its intersection point with the second voltage VC2 in the off period of NM2 is shifted backward, that is, the time when the second voltage VC2 is decreased to be less than VC1 is shifted backward, so the off time of NM2 is increased, and the change of the inductor current is linear, so increasing the off time is equivalent to decreasing the average current.

Working according to the above principle, the constant current control system 2000 will finally stabilize the average current of the inductor L1 at the target average current I = [ (300mv +100mv)/RCS ] × 0.5, and realize constant current output (i.e. reach a stable state).

According to the constant current control circuit and the chip, provided by the invention, the sampling voltage VCS at the sampling resistor end is compared with the preset threshold voltages V1 and V2, and the charging time of the first voltage storage element C1 is adjusted, so that the average current flowing through the inductor L1 is continuously adjusted to reach the target average current, and finally, constant current output (namely, a stable state is achieved). Compared with the constant current control circuit and the chip with the traditional structures, the constant current control circuit and the chip have the advantages that the error amplifier and the oscillator are not arranged in the internal circuit structure, the internal circuit structure is simple, the requirement on the performance of the comparator is not high, the circuit structure is simple and stable, the area of the chip is small, the cost is low, and the peripheral circuit is simple, so that the cost of the LED constant current source driving module can be reduced.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The constant current control circuit and the chip provided by the embodiment of the invention are described in detail, a specific example is applied in the description to explain the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the technical scheme and the core idea of the invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. The constant-current control circuit is characterized by comprising a sampling module, a ramp voltage generating module and a comparing module, wherein:

the sampling module comprises a voltage comparison unit and a voltage regulation unit, wherein the voltage comparison unit comprises a first input end, a second input end, a third input end and a first output end, the first input end receives a first reference voltage, the second input end receives a second reference voltage smaller than the first reference voltage, the third input end receives a sampling voltage, the sampling voltage reflects the current flowing through an external energy storage element when an external power tube is conducted, the first output end of the voltage comparison unit outputs a voltage regulation signal to the voltage regulation unit according to the comparison result of the sampling voltage and the second reference voltage during the period when the sampling voltage is smaller than the first reference voltage, and the voltage regulation unit controls the charging and discharging of a first voltage storage element of the voltage regulation unit according to the voltage regulation signal, causing the voltage regulating unit to output a first voltage, wherein the voltage regulating signal controls the first voltage storage element to be charged during a period when the sampled voltage is less than the second reference voltage, and controls the first voltage storage element to be discharged during a period when the sampled voltage is greater than the second reference voltage and less than the first reference voltage;

the ramp voltage generation module is used for controlling the charging and discharging of a second voltage storage unit of the ramp voltage generation module according to the state of an external power tube, so that the ramp voltage generation module outputs a second voltage; and

the comparison module is used for comparing the first voltage with the second voltage to obtain a control signal which changes along with the first voltage, and the control signal is used for controlling the state of an external power tube so as to control the average current flowing through an external energy storage element.

2. The constant current control circuit according to claim 1, wherein the second reference voltage is set to be greater than a difference between the first reference voltage and the second reference voltage.

3. The constant current control circuit according to claim 1, wherein during a period when the sampling voltage is less than the first reference voltage, the external power transistor is turned on, so that the second voltage storage unit of the ramp voltage generation module is charged, and during a period when the sampling voltage is greater than the first reference voltage, the external power transistor is turned off, so that the second voltage storage unit of the ramp voltage generation module is discharged.

4. The constant current control circuit according to claim 1, wherein when the sampled voltage is greater than the first reference voltage, the second output terminal of the voltage comparison unit outputs a signal to an external logic control module to control an external power transistor to be turned off, the first voltage output by the voltage adjustment unit is maintained at a voltage at a time before the external power transistor is turned off, and the second voltage storage unit of the ramp voltage generation module discharges to reduce a second voltage.

5. The constant current control circuit according to claim 4, wherein the comparison module outputs a control signal to control the external power transistor to conduct when the second voltage decreases to be less than the first voltage before the current flowing through the external energy storage element decreases to zero.

6. The constant current control circuit according to claim 5, wherein a charging period of the first voltage storage element increases, and the first voltage increases, so that an off-time of an external power transistor decreases.

7. The constant current control circuit of claim 4, wherein the comparison module outputs a control signal to maintain the external power transistor off when the second voltage is always greater than the first voltage before the current flowing through the external energy storage element drops to zero.

8. The constant current control circuit of claim 1, further comprising a power-on reset module coupled to the first voltage storage element for providing a power-on reset signal to the first voltage storage element to discharge zero to the first voltage storage element.

9. A constant current control chip characterized by comprising the constant current control circuit according to any one of claims 1 to 8.