CN113467566B

CN113467566B - Ramp voltage generating circuit, chip and electronic equipment

Info

Publication number: CN113467566B
Application number: CN202110901822.7A
Authority: CN
Inventors: 李念龙
Original assignee: Shanghai Awinic Technology Co Ltd
Current assignee: Shanghai Awinic Technology Co Ltd
Priority date: 2021-08-06
Filing date: 2021-08-06
Publication date: 2022-10-11
Anticipated expiration: 2041-08-06
Also published as: CN113467566A

Abstract

The application discloses ramp voltage produces circuit and chip and electronic equipment including this circuit, this circuit includes: the circuit comprises a current control circuit and a capacitor, wherein the far end of the capacitor outputs a ramp voltage, and when the ramp voltage is smaller than a reference voltage, the current control circuit outputs a first current to charge the capacitor, so that the rising slope of the ramp voltage is smaller than a preset slope, and the output voltage of the electronic equipment gradually rises along with the ramp voltage at the moment to realize soft start; when the ramp voltage is greater than the reference voltage, the current control circuit outputs a second current greater than the first current to charge the capacitor, so that the probability that the ramp voltage is pulled down due to electric leakage caused by damage of the capacitor is reduced, the ramp voltage is kept not less than the reference voltage, and the reference voltage is not less than the reference voltage, so that the ramp voltage at the moment is not less than the reference voltage, and the output voltage of the electronic equipment works normally along with the reference voltage.

Description

Ramp voltage generating circuit, chip and electronic equipment

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a ramp voltage generating circuit, a chip, and an electronic device.

Background

Many electronic devices, such as Low Dropout regulators (LDOs), need to have a soft start function when they are started in order to prevent the risk of surge caused by the output voltage thereof building up too fast. The soft start function generally needs to be implemented by a ramp voltage, so that the output voltage of the electronic device gradually rises along with the ramp voltage when the electronic device is started.

Specifically, the ramp voltage is generally generated by charging a capacitor with a small current, so that the ramp voltage gradually rises and is finally maintained at a high potential. However, since the capacitor has a certain risk of damage and is prone to leakage, and when the capacitor has damage, the leakage becomes more serious as the voltages at two ends of the capacitor increase, therefore, when the capacitor leaks electricity due to damage, the ramp voltage is likely to be pulled down and cannot be kept at a high potential, and since the output voltage of the electronic device can work along with the smaller voltage of the reference voltage and the ramp voltage, if the ramp voltage decreases to be less than the reference voltage, the output voltage of the electronic device can work along with the ramp voltage, thereby affecting the function of the electronic device, and even causing quality accidents of the client. How to reduce the influence of the damage of the capacitor on the ramp voltage is an urgent technical problem to be solved by those skilled in the art.

Disclosure of Invention

In order to solve the above technical problem, embodiments of the present application provide a ramp voltage generation circuit, a chip, and an electronic device, so as to reduce an influence of a damage of a capacitor on a ramp voltage.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

a ramp voltage generating circuit applied to an electronic device having a soft start function, the electronic device having a first input terminal to which a ramp voltage outputted from the ramp voltage generating circuit is inputted and a second input terminal to which a reference voltage is inputted, an output voltage of which operates following a smaller one of the reference voltage and the ramp voltage, the ramp voltage generating circuit comprising: a current control circuit and a capacitor, wherein,

the first input end of the current control circuit is connected with the voltage input end of the ramp voltage generating circuit, the second input end of the current control circuit inputs reference voltage, and the output end of the current control circuit is grounded through the capacitor; when the voltage of the far-ground end of the capacitor is smaller than the reference voltage, the output end of the current control circuit outputs a first current, so that the rising slope of the voltage of the far-ground end of the capacitor is smaller than a preset slope; when the voltage of the capacitor far-ground end is greater than the reference voltage, the output end of the current control circuit outputs a second current, so that the voltage of the capacitor far-ground end is kept to be not less than the reference voltage, wherein the second current is greater than the first current, and the reference voltage is not less than the reference voltage;

the far-end of the capacitor is a voltage output end of the ramp voltage generating circuit and outputs the ramp voltage.

Optionally, the current control circuit comprises a current generating circuit and a control circuit, wherein,

the input end of the current generating circuit is connected with the voltage input end of the ramp voltage generating circuit, the control end of the current generating circuit is connected with the output end of the control circuit, and the output end of the current generating circuit is connected with the far-ground end of the capacitor;

the first input end of the control circuit inputs the reference voltage, the second input end of the control circuit is connected with the far-ground end of the capacitor, and the enabling end of the control circuit is connected with the output end of the capacitor;

when the voltage at the second input end of the control circuit is smaller than the voltage at the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the current generation circuit to output the first current; when the voltage of the second input end of the control circuit is larger than the voltage of the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the current generation circuit to output the second current, and the control circuit is turned off through the enable end of the control circuit.

Optionally, the current generating circuit includes: a current source and a current regulating branch, wherein,

the input end of the current source is connected with the voltage input end of the ramp voltage generating circuit and used for generating a preset current based on the voltage input by the voltage input end of the ramp voltage generating circuit;

the control end of the current regulating branch circuit is connected with the output end of the control circuit, and when the voltage of the second input end of the control circuit is smaller than that of the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the current regulating branch circuit to be in a first state; when the voltage at the second input end of the control circuit is larger than the voltage at the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the current regulating branch circuit to be in a second state;

when the current regulating branch circuit is in a first state, the current generating circuit outputs the first current based on the preset current; when the current regulating branch circuit is in a second state, the current generating circuit outputs the second current based on the preset current.

Optionally, the current source includes: a first switch tube, a second switch tube and a DC current source, wherein,

the first end of the first switching tube is connected with the voltage input end of the ramp voltage generating circuit, the second end of the first switching tube is grounded through the direct current source, and the control end of the first switching tube is connected with the second end of the first switching tube;

the first end of the second switch tube is connected with the voltage input end of the ramp voltage generating circuit, the second end of the second switch tube is the output end of the current source, and the control end of the second switch tube is connected with the control end of the first switch tube;

the first switch tube and the second switch tube form a current mirror structure, and the preset current is generated based on the voltage input by the voltage input end of the ramp voltage generation circuit.

Optionally, the current regulating branch includes: a first branch and a second branch, wherein,

the input end of the first branch circuit is connected with the second end of the second switching tube, the control end of the first branch circuit is connected with the output end of the control circuit, and the output end of the first branch circuit is grounded;

the input end of the second branch circuit is connected with the second end of the second switching tube, and the output end of the second branch circuit is connected with the far-end of the capacitor;

the current output by the first branch circuit is K times of the current output by the second branch circuit, and K is not less than 1; when the voltage at the second input end of the control circuit is smaller than the voltage at the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the first branch circuit to be conducted, and the current regulating branch circuit is in a first state; when the voltage of the second input end of the control circuit is larger than the voltage of the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the first branch circuit to be switched off, and the current regulating branch circuit is in a second state.

Optionally, the first branch includes: a third switching tube and a fourth switching tube, wherein,

the first end of the third switching tube is connected with the second end of the second switching tube, and the control end of the third switching tube is connected with the control end of the first switching tube;

the first end of the fourth switching tube is grounded, the second end of the fourth switching tube is connected with the second end of the third switching tube, and the control end of the fourth switching tube is connected with the output end of the control circuit;

the second branch circuit includes: a first end of the fifth switching tube is connected with a second end of the second switching tube, the second end of the fifth switching tube is connected with the far-ground end of the capacitor, and a control end of the fifth switching tube is connected with a control end of the first switching tube;

the width-to-length ratio of the third switching tube is K times of the width-to-length ratio of the fifth switching tube.

Optionally, the fourth switch tube is an NMOS tube, the control circuit is a comparator, the first input end of the comparator is the non-inverting input end of the comparator, the second input end of the comparator is the inverting input end of the comparator, and the comparator is turned off when the enable end of the comparator receives a low level signal.

Optionally, the fourth switching tube is a PMOS tube, the control circuit is a comparator, the first input end of the comparator is the inverting input end of the comparator, the second input end of the comparator is the positive phase input end of the comparator, and the comparator is turned off when the enable end of the comparator receives a high level signal.

Optionally, the current regulating branch includes: the input end of the third branch circuit is connected with the voltage input end of the ramp voltage generating circuit, the control end of the third branch circuit is connected with the output end of the control circuit, and the output end of the third branch circuit is connected with the far-ground end of the capacitor;

when the voltage at the second input end of the control circuit is smaller than the voltage at the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the third branch circuit to be switched off, and the current regulating branch circuit is in a first state; when the voltage of the second input end of the control circuit is larger than the voltage of the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the third branch circuit to be conducted, and the current regulating branch circuit is in a second state.

Optionally, the third branch includes: and a first end of the sixth switching tube is connected with a voltage input end of the ramp voltage generating circuit, a second end of the sixth switching tube is connected with a far-ground end of the capacitor, and a control end of the sixth switching tube is connected with an output end of the control circuit.

Optionally, the sixth switching tube is a PMOS tube, the control circuit is a comparator, the first input end of the comparator is a non-inverting input end of the comparator, the second input end of the comparator is an inverting input end of the comparator, and the comparator is turned off when the enable end of the comparator receives a low level signal.

Optionally, the sixth switching tube is an NMOS tube, the control circuit is a comparator, the first input end of the comparator is the inverting input end of the comparator, the second input end of the comparator is the non-inverting input end of the comparator, and the comparator is turned off when the enable end of the comparator receives a high level signal.

Optionally, the first input end of the control circuit is connected to the control end of the first switching tube, and the reference voltage is input.

A chip comprises the ramp voltage generation circuit of any one of the above.

An electronic device comprising the ramp voltage generation circuit described in any one of the above, wherein the electronic device has a soft start function, a first input terminal of the electronic device inputs the ramp voltage output by the ramp voltage generation circuit, and a second input terminal of the electronic device inputs a reference voltage, and an output voltage of the electronic device operates with the smaller one of the reference voltage and the ramp voltage.

Compared with the prior art, the technical scheme has the following advantages:

the ramp voltage generating circuit provided by the embodiment of the application is applied to electronic equipment with a soft start function, the first input end of the electronic equipment inputs the ramp voltage output by the ramp voltage generating circuit, the second input end of the electronic equipment inputs reference voltage, the output voltage of the reference voltage and the smaller voltage of the ramp voltage follow to work, and the ramp voltage generating circuit comprises: the far-end of the capacitor is a voltage output end of the ramp voltage generating circuit and outputs the ramp voltage; when the voltage of the far-ground end of the capacitor is smaller than the reference voltage, namely the ramp voltage is smaller than the reference voltage, the current control circuit outputs a first current to charge the capacitor, so that the rising slope of the voltage of the far-ground end of the capacitor is smaller than a preset slope, namely the rising slope of the ramp voltage is smaller than the preset slope, and the output voltage of the electronic equipment gradually rises along with the ramp voltage at the moment, so that soft start is realized; when the voltage of the capacitor far-ground end is greater than the reference voltage, namely the ramp voltage is greater than the reference voltage, the current control circuit outputs a second current greater than the first current to charge the capacitor, so that the probability that the ramp voltage is pulled down due to leakage caused by damage of the capacitor is reduced, the voltage of the capacitor far-ground end is not less than the reference voltage, namely the ramp voltage is not less than the reference voltage, and the reference voltage is not less than the reference voltage, so that the ramp voltage at the moment is not less than the reference voltage, and the output voltage of the electronic device can normally work along with the reference voltage. Therefore, the ramp voltage generation circuit provided by the embodiment of the application reduces the influence of the damage of the capacitor on the ramp voltage by increasing the charging current of the capacitor after the ramp voltage rises to the reference voltage, namely after the electronic device completes soft start.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a conventional ramp voltage generating circuit;

fig. 2 to 17 are schematic structural diagrams of ramp voltage generation circuits according to embodiments of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background section, how to reduce the influence of the damage of the capacitor on the ramp voltage becomes a technical problem to be solved by those skilled in the art.

Fig. 1 is a schematic structural diagram of a conventional ramp voltage generating circuit, and as shown in fig. 1, the circuit outputs a ramp voltage Vslope0 at a far end of a capacitor Csst0, where the ramp voltage Vslope0 gradually rises to a high potential as a dc current source IB0 charges the capacitor Csst0, and finally is kept at the high potential by continuously charging the capacitor Csst0 with the dc current source IB 0.

The ramp voltage generating circuit is generally applied to an electronic device with a soft start function, and when the electronic device is in soft start, the output voltage of the electronic device gradually rises along with the ramp voltage output by the ramp voltage generating circuit, so that the surge risk caused by too fast establishment can be avoided. In addition, the electronic equipment can input a reference voltage, and the output voltage of the electronic equipment can work along with the smaller voltage of the reference voltage and the ramp voltage, so that after the electronic equipment enters a normal working state, the output voltage of the electronic equipment works along with the ramp voltage instead of the reference voltage, and the ramp voltage needs to be kept at a high potential higher than the reference voltage at the moment so as to avoid influencing the output voltage of the electronic equipment in the normal working state.

The inventor researches and discovers that since the output voltage of the electronic device gradually rises along with the ramp voltage Vslope0 during soft start, the rising slope of the ramp voltage Vslope0 cannot exceed a certain threshold at this time, which requires that the charging current IB0 of the capacitor Csst0 is small; meanwhile, in order to save the area, the used capacitor Csst0 cannot be too large, and according to a charging formula of the capacitor: csst0 Vslope0= IB0 t, where t is the charging time of the capacitance Csst0, which further requires that the charging current IB0 of the capacitance Csst0 is small, and the charging current IB0 of the capacitance Csst0 may become smaller under certain environmental conditions. Since the current value of the dc current source IB0 is a fixed value, when the ramp voltage Vslope0 rises to the maximum ramp voltage value required by the electronic device to achieve soft start, the capacitor Csst0 is continuously charged by the small fixed current IB0, so that the ramp voltage Vslope0 gradually rises to a high potential, and is finally maintained at the high potential by the small fixed current IB 0. However, since the capacitor Csst0 has a certain risk of damage in the process, the capacitor Csst0 leaks electricity as the usage time length increases, and the leakage of the capacitor Csst0 becomes more serious as the voltages at two ends of the capacitor Csst0 increase in the presence of damage, so that the leakage of the capacitor Csst0 due to damage is more serious when the ramp voltage Vslope0 is at a high potential. If the leakage current of the capacitor Csst0 is larger than the charging current IB0, the ramp voltage Vslope0 is pulled low, and cannot be kept at a high level continuously, or even drops to be smaller than the reference voltage, and then the output voltage of the electronic device works along with the ramp voltage Vslope0, so that the function of the electronic device is affected, and even a quality accident of a client is caused.

Although the charging current of the capacitor Csst0 can be increased by increasing the fixed current of the dc current source IB0, so as to reduce the probability that the ramp voltage Vslope0 is pulled down to be smaller than the reference voltage due to leakage caused by damage to the capacitor Csst0, the rising slope of the ramp voltage Vslope0 is also increased, so that the rising slope of the ramp voltage Vslope0 exceeds a threshold value, and thus the output voltage of the electronic device is still built up too fast following the ramp voltage Vslope0 at the time of starting, which causes a surge risk.

In view of this, embodiments of the present disclosure provide a ramp voltage generating circuit to reduce the influence of the damage of the capacitor on the ramp voltage.

The ramp voltage generating circuit is applied to electronic equipment with a soft start function, the first input end of the electronic equipment inputs the ramp voltage output by the ramp voltage generating circuit, the second input end of the electronic equipment inputs reference voltage, and the output voltage of the electronic equipment works along with the smaller voltage of the reference voltage and the ramp voltage.

Fig. 2 is a schematic structural diagram of a ramp voltage generation circuit according to an embodiment of the present application, and as shown in fig. 2, the ramp voltage generation circuit includes: a current control circuit 100 and a capacitor Csst, wherein,

the first input end of the current control circuit 100 is connected to the voltage input end of the ramp voltage generation circuit, the power supply voltage VDD is input, the reference voltage Vref is input to the second input end, and the output end is grounded through the capacitor Csst; when the voltage of the far-end of the capacitor Csst is smaller than the reference voltage Vref, the output end of the current control circuit 100 outputs a first current, so that the rising slope of the voltage of the far-end of the capacitor Csst is smaller than a preset slope; when the voltage of the far-end of the capacitor Csst is greater than the reference voltage Vref, the output end of the current control circuit 100 outputs a second current, so that the voltage of the far-end of the capacitor Csst is kept to be not less than the reference voltage Vref, wherein the second current is greater than the first current, and the reference voltage Vref is not less than the reference voltage;

the far end of the capacitor Csst is a voltage output end of the ramp voltage generation circuit, and outputs the ramp voltage Vslope.

It should be noted that, when the voltage at the far end of the capacitor Csst is smaller than the reference voltage Vref, that is, the ramp voltage Vslope is smaller than the reference voltage Vref, the current control circuit 100 outputs a first current to charge the capacitor Csst, so that the rising slope of the voltage at the far end of the capacitor Csst is smaller than a preset slope, that is, the rising slope of the ramp voltage Vslope is smaller than the preset slope, so that the output voltage of the electronic device gradually rises along with the current ramp voltage Vslope, and soft start is implemented; when the voltage at the far end of the capacitor Csst is greater than the reference voltage Vref, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the current control circuit 100 outputs a second current greater than the first current to charge the capacitor Csst, so that the probability that the ramp voltage Vslope is pulled down due to leakage caused by damage to the capacitor Csst is reduced, the voltage at the far end of the capacitor Csst is kept not less than the reference voltage Vref, that is, the ramp voltage Vslope is kept not less than the reference voltage Vref, and since the reference voltage Vref is not less than the reference voltage, the ramp voltage Vslope at this time is not less than the reference voltage, and thus the output voltage of the electronic device works normally along with the reference voltage.

It should be further noted that, after the ramp voltage Vslope is greater than the reference voltage Vref, the current control circuit 100 outputs the second current to continue charging the capacitor Csst, which causes the voltage at the far end of the capacitor Csst (i.e., the ramp voltage Vslope) to be pulled to a high potential quickly by the second current, where the high potential is a voltage value close to the power supply voltage VDD, and the rising slope of the ramp voltage Vslope at this time is greater than the rising slope of the ramp voltage Vslope when the current control circuit 100 outputs the first current to charge the capacitor Csst.

Therefore, compared with the conventional ramp voltage generating circuit, after the ramp voltage Vslope0 output by the ramp voltage generating circuit rises to the ramp voltage value required by the electronic device to realize soft start, the ramp voltage Vslope is still pulled to the high potential by a smaller fixed current IB0, and the ramp voltage generating circuit provided by the embodiment of the application increases the charging current of the capacitor Csst by pulling the ramp voltage Vslope to the high potential by a larger current (namely, the second current) after the ramp voltage Vslope rises to the reference voltage Vref, namely after the electronic device finishes soft start, so that the probability that the ramp voltage Vslope is pulled down is greatly reduced under the condition that the capacitor Csst has certain process damage and leaks electricity, and the influence of the damage of the capacitor Csst on the ramp voltage Vslope is reduced, namely the ramp voltage generating circuit provided by the embodiment of the application is a reliable ramp voltage generating circuit capable of resisting the certain process damage risk of the capacitor Csst.

On the basis of the above-mentioned embodiments, in one embodiment of the present application, as shown in fig. 3, the current control circuit 100 includes a current generating circuit 10 and a control circuit 20, wherein,

the input end of the current generating circuit 10 is connected with the voltage input end of the ramp voltage generating circuit, the control end is connected with the output end of the control circuit 20, and the output end is connected with the far-end of the capacitor Csst;

the reference voltage Vref is input to a first input terminal (shown as a terminal 1 of the control circuit 20 in fig. 3) of the control circuit 20, a second input terminal (shown as a terminal 2 of the control circuit 20 in fig. 3) is connected to the far-end terminal of the capacitor Csst, the ramp voltage Vslope is input, and an enable terminal (shown as a terminal 3 of the control circuit 20 in fig. 3) is connected to an output terminal thereof;

when the second input end voltage of the control circuit 20 is smaller than the first input end voltage thereof, the voltage signal VST output by the output end of the control circuit 20 controls the current generation circuit 10 to output the first current; when the second input terminal voltage of the control circuit 20 is greater than the first input terminal voltage thereof, the voltage signal VST output by the output terminal of the control circuit 20 controls the current generating circuit 10 to output the second current, and the enable terminal of the control circuit 20 turns off the control circuit 20.

It should be noted that the input end of the current generating circuit 10 is the first input end of the current control circuit 100, and the power supply voltage VDD is input, the first input end of the control circuit 20 is the second input end of the current control circuit 100, and the reference voltage Vref is input, and the output end of the current generating circuit 10 is the output end of the current control circuit 100.

In the embodiment of the present application, when the voltage at the second input terminal of the control circuit 20 is smaller than the voltage at the first input terminal thereof, that is, the ramp voltage Vslope is smaller than the reference voltage Vref, the voltage signal VST output by the output terminal of the control circuit 20 controls the current generation branch 10 to output the first current to charge the capacitor Csst, so that the voltage at the far end of the capacitor Csst (that is, the ramp voltage Vslope) gradually rises, and the rising slope thereof is smaller than a preset slope; when the voltage at the second input terminal of the control circuit 20 is greater than the voltage at the first input terminal thereof, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output terminal of the control circuit 20 controls the current generation branch 10 to output the second current to charge the capacitor Csst, so that the voltage at the far end of the capacitor Csst (that is, the ramp voltage Vslope) is pulled to a high potential rapidly and is kept not less than the reference voltage Vref.

It should be further noted that, when the second input terminal voltage of the control circuit 20 is greater than the first input terminal voltage thereof, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output terminal of the control circuit 20 also enables the control circuit 20 to be turned off through an enable terminal of the control circuit 20 (as shown by the terminal 3 of the control circuit 20 in fig. 3), so as to avoid adding additional power consumption.

It should be noted that the control circuit 20 may be a comparator, or may be another circuit structure capable of reflecting the voltage magnitude of the two input terminals through the voltage signal output by the output terminal thereof, which is not limited in this application, and is determined as the case may be.

On the basis of the above embodiments, in one embodiment of the present application, the current generation circuit 10 includes: a current source 11 and a current regulating branch 12, wherein,

the input end of the current source 11 is connected to the voltage input end of the ramp voltage generating circuit, and is configured to generate a preset current based on the voltage input by the voltage input end of the ramp voltage generating circuit;

the control end of the current regulating branch 12 is connected to the output end of the control circuit 20, and when the voltage at the second input end of the control circuit 20 is smaller than the voltage at the first input end thereof, the voltage signal VST output by the output end of the control circuit 20 controls the current regulating branch 12 to be in a first state; when the voltage at the second input end of the control circuit 20 is greater than the voltage at the first input end thereof, the voltage signal VST output by the output end of the control circuit 20 controls the current regulating branch 12 to be in the second state;

when the current regulating branch 12 is in the first state, the current generating circuit 10 outputs the first current based on the preset current; when the current regulating branch 12 is in the second state, the current generating circuit 10 outputs the second current based on the preset current.

Fig. 4 and 5 illustrate two connection modes between the current source 11 and the current regulating branch 12, wherein,

as shown in fig. 4, the input terminal of the current source 11 is the input terminal of the current generating circuit 10, and is connected to the voltage input terminal of the ramp voltage generating circuit, and the output terminal is connected to the input terminal of the current regulating branch 12;

the control end of the current regulating branch 12 is the control end of the current generating circuit 10 and is connected to the output end of the control circuit 20, and the output end is the output end of the current generating circuit 10 and is connected to the far-end of the capacitor Csst.

During specific operation, when the voltage at the second input end of the control circuit 20 is smaller than the voltage at the first input end thereof, that is, when the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the current adjusting branch 12 to be in a first state, at this time, the current generating circuit 10 outputs the first current based on the preset current IB, that is, the current adjusting branch 12 outputs the first current based on the preset current IB; when the voltage at the second input terminal of the control circuit 20 is greater than the voltage at the first input terminal thereof, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output terminal of the control circuit 20 controls the current adjusting branch 12 to be in the second state, at this time, the current generating circuit 10 outputs the second current based on the preset current IB, that is, the current adjusting branch 12 outputs the second current based on the preset current IB.

As shown in fig. 5, a common terminal between the input terminal of the current source 11 and the input terminal of the current adjusting branch 12 is an input terminal of the current generating circuit 10, and is connected to a voltage input terminal of the ramp voltage generating circuit, and a power supply voltage VDD is input, a common terminal between the output terminal of the current source 11 and the output terminal of the current adjusting branch 12 is an output terminal of the current generating circuit 10, a current output by the output terminal of the current generating circuit 10 is a sum of a preset current IB output by the current source 11 and a current IB12 output by the current adjusting branch 12 in the first state or the second state, and a control terminal of the current adjusting branch 12 is a control terminal of the current generating circuit 10 and is connected to an output terminal of the control circuit 20.

During specific operation, when the voltage at the second input end of the control circuit 20 is smaller than the voltage at the first input end thereof, that is, when the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the current adjusting branch 12 to be in the first state, at this time, the current generating circuit 10 outputs the first current based on the preset current IB, where the first current is the sum of the preset current IB output by the current source 11 and the current IB12 output by the current adjusting branch 12 in the first state; when the voltage at the second input end of the control circuit 20 is greater than the voltage at the first input end thereof, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the current adjusting branch 12 to be in the second state, at this time, the current generating circuit 10 outputs the second current based on the preset current IB, where the second current is the sum of the preset current IB output by the current source 11 and the current IB12 output by the current adjusting branch 12 in the second state, and the current output by the current adjusting branch 12 in the second state is greater than the current output by the current adjusting branch 12 in the first state.

It should be noted that, fig. 4 and fig. 5 only list two connection manners between the current source 11 and the current regulating branch 12, and in other embodiments of the present application, the connection manner between the current source 11 and the current regulating branch 12 may also be other connection manners capable of implementing that when the current regulating branch 12 is in the first state, the current generating circuit 10 outputs the first current based on the preset current IB; when the current adjusting branch 12 is in the second state, the current generating circuit 10 outputs the connection manner of the second current based on the preset current IB, which is not limited in this application, and is determined as the case may be.

Next, the current source 11 will be described by taking the connection manner between the current source 11 and the current regulating branch 12 shown in fig. 4 and 5 as an example.

Alternatively, in an embodiment of the present application, as shown in fig. 6 and 7, wherein the connection between the current source 11 and the current adjusting branch 12 in fig. 6 and 4 is the same, and the connection between the current source 11 and the current adjusting branch 12 in fig. 5 and 7 is the same, as can be seen from fig. 6 and 7, the current source 11 includes: a first switch tube Q1, a second switch tube Q2 and a direct current source IB1, wherein,

the first end of the first switch tube Q1 is connected with the voltage input end of the ramp voltage generating circuit, the power supply voltage VDD is input, the second end of the first switch tube Q1 is grounded through the direct current power supply IB1, and the control end of the first switch tube Q1 is connected with the second end of the first switch tube Q1;

a first end of the second switch tube Q2 is connected to a voltage input end of the ramp voltage generating circuit, and a power supply voltage VDD is input thereto, a second end is an output end of the current source 11, and a control end is connected to a control end of the first switch tube Q1;

the first switch tube Q1 and the second switch tube Q2 form a current mirror structure, and the preset current is generated based on the voltage input by the voltage input end of the ramp voltage generation circuit.

Optionally, in an embodiment of the present application, the first switching tube Q1 and the second switching tube Q2 are both PMOS tubes, and at this time, the first ends of the switching tubes are both source electrodes, the second ends are both drain electrodes, and the control ends are both gate electrodes.

It should be noted that, a common terminal of the first switching tube Q1 and the first terminal of the second switching tube Q2 is an input terminal of the current source 11, and the current IB flowing through the second switching tube Q2 mirrors the current IB1 flowing through the first switching tube Q1 and is output at the second terminal of the second switching tube Q2.

It should be noted that the preset current output by the current source 11, that is, the current IB output by the second end of the second switching tube Q2, can be set according to the width-to-length ratio of the first switching tube Q1 and the second switching tube Q2 and the magnitude of the dc current source IB1, and therefore, the preset current IB output by the current mirror 11 can be adjusted according to circuit requirements.

It should be noted that, in this embodiment of the present application, only one circuit structure of the current source 11 is listed, and in other embodiments of the present application, the circuit structure of the current source 11 may also be another circuit structure equivalent to a current source, which is not limited in this application and can be selected by a user according to a user's requirement.

Next, the current adjusting branch 12 will be described by taking as an example the connection relationship between the current source 11 and the current adjusting branch 12 shown in fig. 6 and the circuit configuration of the current source 11.

Optionally, in an embodiment of the present application, as shown in fig. 8, the current regulating branch 12 includes: a first branch 1 and a second branch 2, wherein,

the input end of the first branch 1 is connected with the second end of the second switch tube Q2, the control end is connected with the output end of the control circuit 20, and the output end is grounded;

the input end of the second branch 2 is connected with the second end of the second switching tube Q2, and the output end of the second branch 2 is connected with the far-ground end of the capacitor Csst;

the current output by the first branch circuit 1 is K times of the current output by the second branch circuit 2, and K is not less than 1; when the voltage at the second input terminal of the control circuit 20 is smaller than the voltage at the first input terminal thereof, the voltage signal VST output by the output terminal of the control circuit 20 controls the first branch circuit 1 to be turned on, and the current regulating branch circuit 12 is in the first state; when the voltage at the second input terminal of the control circuit 20 is greater than the voltage at the first input terminal thereof, the voltage signal VST output by the output terminal of the control circuit 20 controls the first branch circuit 1 to be turned off, and the current regulating branch circuit 12 is in the second state.

It should be noted that a common end of the input end of the first branch 1 and the input end of the second branch 2 is an input end of the current adjusting branch 12, a control end of the first branch 1 is a control end of the current adjusting branch 12, and an output end of the second branch 2 is an output end of the current adjusting branch 12.

In this embodiment, when a voltage at a second input end of the control circuit 20 is smaller than a voltage at a first input end thereof, that is, when the ramp voltage Vslope is smaller than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the first branch 1 to be turned on, at this time, both the first branch 1 and the second branch 2 are turned on, the current regulating branch 12 is in the first state, and the first branch 1 and the second branch 2 simultaneously shunt the preset current IB output by the second end of the second switching tube Q2, since the current output by the first branch 1 is K times of the current output by the second branch 2 and K is not smaller than 1, the current output by the second branch 2 at this time is IB/(K + 1), that is, the first current is IB/(K + 1), and charges the capacitor Csst, so that the voltage at the far end of the capacitor Csst (that is, the ramp voltage Vslope) gradually rises, and the rising slope thereof is smaller than the preset slope; when the voltage at the second input end of the control circuit 20 is greater than the voltage at the first input end thereof, that is, the slope voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the first branch 1 to be turned off, at this time, the first branch 1 is turned off, the second branch 2 continues to be turned on, the current adjusting branch 12 is in the second state, the second branch 12 carries all the preset current IB output by the second end of the second switching tube Q2, and the current output by the second branch 12 becomes IB, that is, the second current is IB. It can be seen that the charging current of the capacitor Csst changes from IB/(K + 1) to IB, which is increased by K times, so that the voltage at the far end of the capacitor Csst (i.e. the ramp voltage Vslope) is quickly pulled to high potential and remains no less than the reference voltage Vref.

As can be seen from this, in the ramp voltage generating circuit provided in the embodiment of the present application, when the ramp voltage Vslope is smaller than the reference voltage Vref, the first branch circuit 1 branches the preset current IB, so that the current carried by the second branch circuit 2 is 1/(K + 1) of the preset current IB, and the current regulating branch circuit 12 outputs the first current with a magnitude of 1/(K + 1) of the preset current IB; when the ramp voltage Vslope is greater than the reference voltage Vref, the first branch circuit 1 no longer shunts the preset current IB, so that the current carried by the second branch circuit 2 is all the preset current IB, and the current adjusting branch circuit 12 outputs the second current whose magnitude is equal to the preset current IB, that is, the charging current of the capacitor Csst is increased, thereby reducing the probability that the ramp voltage Vslope is pulled down to be less than the reference voltage due to the leakage caused by the damage of the capacitor Csst, and reducing the influence of the damage of the capacitor Csst on the ramp voltage.

It should be noted that, the specific number of the first branches 1 is not limited in the present application, in other embodiments of the present application, there may be a plurality of first branches 1, and when the ramp voltage Vslope is smaller than the reference voltage Vref, the plurality of first branches 1 shunt the preset current IB, so that the current received by the second branch 2 is a part of the preset current IB; when the ramp voltage Vslope is greater than the reference voltage Vref, the plurality of first branches 1 do not shunt the preset current IB, or at least a portion of the first branches 1 do not shunt the preset current IB, so as to increase the current carried by the second branch 2, thereby increasing the charging current of the capacitor Csst.

Specifically, in one embodiment of the present application, as shown in fig. 9, the first branch circuit 1 includes: a third switching tube Q3 and a fourth switching tube Q4, wherein,

the first end of the third switching tube Q3 is connected with the second end of the second switching tube Q2, and the control end is connected with the control end of the first switching tube Q1;

a first end of the fourth switching tube Q4 is grounded, a second end of the fourth switching tube Q4 is connected with a second end of the third switching tube Q3, and a control end of the fourth switching tube Q4 is connected with an output end of the control circuit 20;

the second branch 2 comprises: a fifth switching tube Q5, wherein a first end of the fifth switching tube Q5 is connected to a second end of the second switching tube Q2, a second end of the fifth switching tube Q5 is connected to the far-ground end of the capacitor Csst, and a control end of the fifth switching tube Q5 is connected to the control end of the first switching tube Q1;

the width-to-length ratio of the third switching tube Q3 is K times of the width-to-length ratio of the fifth switching tube Q5.

Optionally, in an embodiment of the present application, the third switching tube Q3 and the fifth switching tube Q5 are both PMOS tubes, and at this time, the first end of each of the switching tubes is a source, the second end is a drain, and the control end is a gate.

It should be noted that a first end of the third switching tube Q3 is an input end of the first branch 1, a first end of the fourth switching tube Q4 is an output end of the first branch 1, and a control end of the fourth switching tube Q4 is a control end of the first branch 1; a first end of the fifth switching tube Q5 is an input end of the second branch 2, and a second end of the fifth switching tube Q5 is an output end of the second branch 2.

In this embodiment of the application, when the voltage at the second input end of the control circuit 20 is smaller than the voltage at the first input end thereof, that is, the ramp voltage Vslope is smaller than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the fourth switching tube Q4 to be turned on, so that the first branch 1 composed of the third switching tube Q3 and the fourth switching tube Q4 is turned on, and the current regulation branch 12 is in the first state, at this time, the third switching tube Q3 and the fifth switching tube Q5 simultaneously shunt the preset current IB output by the second end of the second switching tube Q2, since the aspect ratio of the third switching tube Q3 is K times the aspect ratio of the fifth switching tube Q5, the current flowing through the fifth switching tube Q5 is IB/(K + 1), that is, the first current output by the second branch 2 is IB/(K + 1); when the voltage at the second input end of the control circuit 20 is greater than the voltage at the first input end thereof, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the fourth switching tube Q4 to be turned off, so that the first branch 1 formed by the third switching tube Q3 and the fourth switching tube Q4 is turned off, the current adjusting branch 12 is in the second state, at this time, the fifth switching tube Q5 passes all the preset current IB output by the second end of the second switching tube Q2, the current flowing through the fifth switching tube Q5 is IB, that is, the second current output by the second branch 2 is IB, so that the charging current of the capacitor Csst is changed from IB/(K + 1) to IB, and is increased by K times.

On the basis of the foregoing embodiment, optionally, in an embodiment of the present application, as shown in fig. 10, the fourth switching tube Q4 is an NMOS tube, at this time, a first end of the fourth switching tube Q4 is a source, a second end is a drain, and a control end is a gate; the control circuit 20 is a comparator, a first input end of the comparator 20 is a non-inverting input end of the comparator 20, a second input end of the comparator 20 is an inverting input end of the comparator 20, and the enable end EN of the comparator 20 controls the comparator 20 to turn off when receiving a low level signal, so that when the ramp voltage Vslope is smaller than the reference voltage Vref, that is, when a voltage at the non-inverting input end (a voltage at the first input end) of the comparator 20 is greater than a voltage at the inverting input end (a voltage at the second input end) of the comparator 20, the voltage signal VST output by the output end of the comparator 20 is at a high level, and the fourth switching tube Q4 is controlled to turn on; when the ramp voltage Vslope is greater than the reference voltage Vref, that is, when a voltage at a positive phase input terminal (a first input terminal voltage) of the comparator 20 is less than a voltage at a negative phase input terminal (a second input terminal voltage), the voltage signal VST output by the output terminal of the comparator 20 is at a low level, the fourth switching tube Q4 is controlled to be turned off, and the comparator 20 is controlled to be turned off by the enable terminal EN of the comparator 20.

In another embodiment of the present application, as shown in fig. 11, the fourth switching transistor Q4 is a PMOS transistor, at this time, a first end of the fourth switching transistor Q4 is a drain, a second end thereof is a source, and a control end thereof is a gate; the control circuit 20 is a comparator, a first input terminal of the comparator 20 is an inverting input terminal of the comparator 20, a second input terminal of the comparator 20 is a positive-phase input terminal of the comparator 20, and the enable terminal ENB of the comparator 20 controls the comparator 20 to turn off when receiving a high-level signal, so that when the ramp voltage Vslope is smaller than the reference voltage Vref, that is, when a voltage at the positive-phase input terminal (a voltage at the first input terminal) of the comparator 20 is smaller than a voltage at the inverting input terminal (a voltage at the second input terminal) of the comparator 20, the voltage signal VST output by the output terminal of the comparator 20 is at a low level, and the fourth switching tube Q4 is controlled to turn on; when the ramp voltage Vslope is greater than the reference voltage Vref, that is, when a positive phase input terminal voltage (a first input terminal voltage) of the comparator 20 is greater than an inverse phase input terminal voltage (a second input terminal voltage) thereof, the voltage signal VST output by the output terminal of the comparator 20 is at a high level, the fourth switching tube Q4 is controlled to be turned off, and the comparator 20 is controlled to be turned off by the enable terminal ENB of the comparator 20.

Since the control terminal voltage of the first switch tube Q1 is determined by its width-to-length ratio and the magnitude of the dc current source IB1, and its voltage value is smaller than the power supply voltage VDD, the control terminal voltage of the first switch tube Q1 can be used as the reference voltage Vref. Specifically, on the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 12, the first input terminal of the control circuit 20 is connected to the control terminal of the first switching tube Q1, and the reference voltage Vref is input, so that an additional generation circuit for the reference voltage Vref is not required, and the circuit structure of the ramp voltage generation circuit is simplified.

Next, the current regulation branch 12 will be described by taking the connection relationship between the current source 11 and the current regulation branch 12 shown in fig. 7 and the circuit configuration of the current source 11 as an example.

Optionally, in an embodiment of the present application, as shown in fig. 13, the current regulating branch 12 includes: an input end of the third branch 3 is connected with a voltage input end of the ramp voltage generation circuit, a control end of the third branch 3 is connected with an output end of the control circuit 20, and an output end of the third branch is connected with a far-ground end of the capacitor Csst;

when the voltage at the second input end of the control circuit 20 is smaller than the voltage at the first input end thereof, the voltage signal VST output by the output end of the control circuit 20 controls the third branch 3 to be turned off, and the current regulating branch 12 is in the first state; when the voltage at the second input terminal of the control circuit 20 is greater than the voltage at the first input terminal thereof, the voltage signal VST output by the output terminal of the control circuit 20 controls the third branch circuit to be turned on, and the current regulating branch circuit 12 is in the second state.

It should be noted that the input end of the third branch 3 is the input end of the current adjusting branch 12, and the power supply voltage VDD is input, the control end of the third branch 3 is the control end of the current adjusting branch 12, and the output end of the third branch 3 is the output end of the current adjusting branch 12.

In this embodiment, when the voltage at the second input end of the control circuit 20 is smaller than the voltage at the first input end thereof, that is, the ramp voltage Vslope is smaller than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the third branch 3 to be turned off, the current adjusting branch 12 is in the first state, at this time, the current output by the output end of the current generating circuit 10 is the preset current IB output by the second end of the second switching tube Q2, that is, the first current is the preset current IB, and the current charges the capacitor Csst, so that the voltage at the far end of the capacitor Csst (that is, the ramp voltage Vslope) gradually rises, and the rising slope thereof is smaller than the preset slope; when the voltage at the second input end of the control circuit 20 is greater than the voltage at the first input end thereof, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the third branch 3 to be turned on, and the current regulating branch 12 is in the second state, at this time, the current output by the output end of the current generating circuit 10 becomes the sum (IB + IB 12) of the current IB12 output by the third branch 3 and the preset current IB output by the second end of the second switching tube Q2, that is, the second current is (IB + IB 12). It can be seen that the charging current of the capacitor Csst is increased from IB to (IB + IB 12), so that the voltage at the far end of the capacitor Csst (i.e., the ramp voltage Vslope) is pulled to high rapidly, and remains no less than the reference voltage Vref.

As can be seen, in the ramp voltage generating circuit provided in the embodiment of the present application, when the ramp voltage Vslope is smaller than the reference voltage Vref, the third branch 3 is turned off, so that the first current output by the current generating circuit 10 is the preset current IB; when the ramp voltage Vslope is greater than the reference voltage Vref, the third branch 3 is turned on, so that the second current output by the current generating circuit 10 is the sum (IB + IB 12) of the preset current IB and the current IB12 output by the third branch 3, that is, the charging current of the capacitor Csst is increased, thereby reducing the probability that the ramp voltage Vslope is pulled down to be less than the reference voltage due to leakage caused by damage of the capacitor Csst, and reducing the influence of the damage of the capacitor Csst on the ramp voltage.

It should be noted that, the specific number of the third branches 3 is not limited in the present application, in other embodiments of the present application, a plurality of third branches 3 may also be provided, and when the ramp voltage Vslope is smaller than the reference voltage Vref, the plurality of third branches 3 are turned off, so that the first current output by the current generation circuit 10 is the preset current; when the ramp voltage Vslope is greater than the reference voltage Vref, the third branches 3 are turned on, so that the second current output by the current generation circuit 10 is the sum of the preset current and the currents output by the third branches 3, thereby increasing the charging current of the capacitor Csst.

It should be noted that, in the embodiment of the present application, compared with the embodiments corresponding to fig. 8 to fig. 12, since the current adjusting branch 12 adjusts the current generating circuit 10 to output the first current and the second current based on the preset current IB in a different manner, and the preset current IB output by the current source 11 can be adjusted according to circuit requirements, the preset current IB output by the current source 11 in the embodiments corresponding to the present application and the embodiments corresponding to fig. 8 to fig. 12 is different in magnitude. Specifically, in the embodiment of the present application, the predetermined current IB outputted by the current source 11 is the first current, and in the embodiments corresponding to fig. 8 to 12, the predetermined current IB outputted by the current source 11 is (K + 1) times the first current, but the first current (i.e., the predetermined current IB in this embodiment) in the embodiment of the present application is equivalent to the first current (i.e., 1/(K + 1) of the predetermined current IB in this embodiment) in the embodiments corresponding to fig. 8 to 12, and the second current (i.e., the sum (IB + IB 12) of the predetermined current IB in this embodiment and the current IB12 outputted by the third branch 3 in this embodiment) in this embodiment of the present application is equivalent to the second current (i.e., the predetermined current IB in this embodiment) in the embodiments corresponding to fig. 8 to 12.

Specifically, in an embodiment of the present application, as shown in fig. 14, the third branch 3 includes: a sixth switching tube Q6, where a first end of the sixth switching tube Q6 is connected to the voltage input end of the ramp voltage generating circuit, a power supply voltage VDD is input, a second end of the sixth switching tube Q6 is connected to the far-ground end of the capacitor Csst, and a control end of the sixth switching tube Q6 is connected to the output end of the control circuit 20.

It should be noted that, in the embodiment of the present application, when the voltage at the second input end of the control circuit 20 is smaller than the voltage at the first input end thereof, that is, when the ramp voltage Vslope is smaller than the reference voltage Vref, the voltage signal VST output by the output end of the control circuit 20 controls the sixth switching tube Q6 to turn off, so that the third branch 3 turns off, and thus the current regulating branch 12 is in the first state; when the voltage at the second input terminal of the control circuit 20 is greater than the voltage at the first input terminal thereof, that is, the ramp voltage Vslope is greater than the reference voltage Vref, the voltage signal VST output by the output terminal of the control circuit 20 controls the sixth switching tube Q6 to be turned on, so that the third branch 3 is turned on, and the current regulating branch 12 is in the second state.

On the basis of the foregoing embodiment, optionally, in an embodiment of the present application, as shown in fig. 15, the sixth switching transistor Q6 is a PMOS transistor, at this time, a first end of the fourth switching transistor Q4 is a source, a second end thereof is a drain, and a control end thereof is a gate; the control circuit 20 is a comparator, a first input end of the comparator 20 is a non-inverting input end of the comparator 20, a second input end of the comparator 20 is an inverting input end of the comparator 20, and the enable end EN of the comparator 20 controls the comparator 20 to turn off when receiving a low level signal, so that when the ramp voltage Vslope is smaller than the reference voltage Vref, that is, when a voltage at the non-inverting input end (a voltage at the first input end) of the comparator 20 is greater than a voltage at the inverting input end (a voltage at the second input end), the voltage signal VST output by the output end of the comparator 20 is at a high level, and the sixth switching tube Q6 is controlled to turn off, that is, the third branch 3 is turned off; when the ramp voltage Vslope is greater than the reference voltage Vref, that is, when a voltage at a positive phase input end (a first input end voltage) of the comparator 20 is less than a voltage at a negative phase input end (a second input end voltage), a voltage signal VST output by an output end of the comparator 20 is at a low level, the sixth switching tube Q6 is controlled to be turned on, that is, the third branch 3 is turned on, and the comparator 20 is controlled to be turned off through an enable end EN of the comparator 20.

In another embodiment of the present application, as shown in fig. 16, the sixth switching tube Q6 is an NMOS tube, and at this time, the first end of the sixth switching tube Q6 is a drain, the second end is a source, and the control end is a gate; the control circuit 20 is a comparator, a first input terminal of the comparator 20 is an inverting input terminal of the comparator 20, a second input terminal of the comparator 20 is a non-inverting input terminal of the comparator 20, and the enable terminal ENB of the comparator 20 controls the comparator to turn off when receiving a high level signal, so that when the ramp voltage Vslope is smaller than the reference voltage Vref, that is, when a voltage at a positive phase input terminal (a voltage at the first input terminal) of the comparator 20 is smaller than a voltage at an inverting input terminal (a voltage at the second input terminal) of the comparator 20, the voltage signal VST output by the output terminal of the comparator 20 is at a low level, the sixth switching tube Q6 is controlled to turn off, that is, the third branch 3 is turned off; when the ramp voltage Vslope is greater than the reference voltage Vref, that is, when a voltage at a positive phase input terminal (a first input terminal) of the comparator 20 is greater than a voltage at a negative phase input terminal (a second input terminal), a voltage signal VST output by an output terminal of the comparator 20 is at a high level, the sixth switching tube Q6 is controlled to be turned on, that is, the third branch 3 is turned on, and the comparator 20 is controlled to be turned off by an enable terminal ENB of the comparator 20.

Since the control terminal voltage of the first switch tube Q1 is determined by its width-to-length ratio and the magnitude of the dc current source IB1, and its voltage value is smaller than the power supply voltage VDD, the control terminal voltage of the first switch tube Q1 can be used as the reference voltage Vref. Specifically, on the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 17, the first input terminal of the control circuit 20 is connected to the control terminal of the first switching tube Q1, and the reference voltage Vref is input, so that an additional generation circuit for the reference voltage Vref is not required, and the circuit structure of the ramp voltage generation circuit is simplified.

The embodiment of the present application further provides a chip, where the chip includes the ramp voltage generation circuit provided in any one of the above embodiments, and a specific working process of the ramp voltage generation circuit has been described in detail in any one of the above embodiments, and is not described herein again.

In addition, an embodiment of the present application further provides an electronic device, which includes the ramp voltage generating circuit provided in any of the above embodiments, and the electronic device has a soft start function, where a first input terminal of the electronic device inputs the ramp voltage output by the ramp voltage generating circuit, a second input terminal of the electronic device inputs a reference voltage, and an output voltage of the electronic device operates along with a smaller one of the reference voltage and the ramp voltage.

When the electronic equipment is in specific work, when the electronic equipment is in soft start, the output voltage of the electronic equipment gradually rises along with the ramp voltage output by the ramp voltage generating circuit, so that the surge risk caused by too fast establishment can be avoided; when the electronic equipment enters a normal working state, the ramp voltage output by the ramp voltage generating circuit is not less than the reference voltage, so that the output voltage of the electronic equipment is changed from working along with the ramp voltage to working along with the reference voltage.

Since the specific operation process of the ramp voltage generation circuit has been described in detail in any of the above embodiments, it is not described herein again.

To sum up, the ramp voltage generating circuit provided in the embodiment of the present application is applied to an electronic device having a soft start function, a first input terminal of the electronic device inputs a ramp voltage output by the ramp voltage generating circuit, a second input terminal of the electronic device inputs a reference voltage, and an output voltage of the electronic device operates along with a smaller voltage of the reference voltage and the ramp voltage, and the ramp voltage generating circuit includes: the far-end of the capacitor is a voltage output end of the ramp voltage generation circuit and outputs the ramp voltage; when the ramp voltage is smaller than the reference voltage, the current control circuit outputs a first current to charge the capacitor, so that the rising slope of the ramp voltage is smaller than a preset slope, the output voltage of the electronic equipment gradually rises along with the ramp voltage at the moment, and soft start is realized; when the ramp voltage is greater than the reference voltage, the current control circuit outputs a second current greater than the first current to charge the capacitor, so that the probability that the ramp voltage is pulled down due to leakage caused by damage of the capacitor is reduced, the influence of the damage of the capacitor on the ramp voltage is reduced, the ramp voltage is kept to be not less than the reference voltage, and the reference voltage is not less than the reference voltage, so that the ramp voltage is not less than the reference voltage, and the output voltage of the electronic equipment works normally along with the reference voltage.

All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.

In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A ramp voltage generating circuit applied to an electronic device having a soft start function, the electronic device having a first input terminal to which a ramp voltage outputted from the ramp voltage generating circuit is inputted and a second input terminal to which a reference voltage is inputted, an output voltage of which operates following a smaller one of the reference voltage and the ramp voltage, the ramp voltage generating circuit comprising: a current control circuit and a capacitor, wherein the current control circuit comprises a current generation circuit and a control circuit, the current generation circuit comprises a current source and a current regulation branch circuit, wherein,

the input end of the current generating circuit is connected with the voltage input end of the ramp voltage generating circuit, a current source in the current generating circuit generates preset current based on the voltage input by the voltage input end of the ramp voltage generating circuit, the control end of a current regulating branch in the current generating circuit is connected with the output end of the control circuit, and the output end of the current generating circuit is grounded through the capacitor;

the far-end of the capacitor is a voltage output end of the ramp voltage generating circuit and outputs the ramp voltage;

a first input end of the control circuit inputs reference voltage, a second input end of the control circuit is connected with the far-ground end of the capacitor, and an enabling end of the control circuit is connected with the output end of the capacitor;

when the voltage at the second input end of the control circuit is smaller than the voltage at the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the current regulating branch circuit to be in a first state, so that the current generating circuit outputs a first current based on the preset current, and the rising slope of the voltage at the far end of the capacitor is smaller than the preset slope;

when the voltage at the second input end of the control circuit is greater than the voltage at the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the current regulating branch circuit to be in a second state, so that the current generating circuit outputs a second current based on the preset current, the voltage at the far end of the capacitor is kept to be not less than the reference voltage, and the control circuit is turned off through the enabling end of the control circuit, wherein the second current is greater than the first current, and the reference voltage is not less than the reference voltage.

2. The ramp voltage generating circuit according to claim 1, wherein the current source comprises: a first switch tube, a second switch tube and a DC current source, wherein,

the first end of the first switch tube is connected with the voltage input end of the ramp voltage generating circuit, the second end of the first switch tube is grounded through the direct current source, and the control end of the first switch tube is connected with the second end of the first switch tube;

3. The ramp voltage generating circuit according to claim 2, wherein the current regulating branch comprises: a first branch and a second branch, wherein,

the current output by the first branch circuit is K times of the current output by the second branch circuit, and K is not less than 1; when the voltage of a second input end of the control circuit is smaller than the voltage of a first input end of the control circuit, a voltage signal output by an output end of the control circuit controls the first branch circuit to be conducted, and the current regulating branch circuit is in a first state; when the voltage of the second input end of the control circuit is larger than the voltage of the first input end of the control circuit, the voltage signal output by the output end of the control circuit controls the first branch circuit to be switched off, and the current regulating branch circuit is in a second state.

4. The ramp voltage generating circuit according to claim 3,

the first branch includes: a third switching tube and a fourth switching tube, wherein,

the second branch includes: a first end of the fifth switching tube is connected with a second end of the second switching tube, a second end of the fifth switching tube is connected with the far-ground end of the capacitor, and a control end of the fifth switching tube is connected with the control end of the first switching tube;

the width-length ratio of the third switching tube is K times of the width-length ratio of the fifth switching tube.

5. The ramp voltage generating circuit according to claim 4, wherein the fourth switching transistor is an NMOS transistor, the control circuit is a comparator, the first input terminal of the comparator is a non-inverting input terminal of the comparator, the second input terminal of the comparator is an inverting input terminal of the comparator, and the comparator is turned off when the enable terminal of the comparator receives a low level signal.

6. The ramp voltage generating circuit according to claim 4, wherein the fourth switching transistor is a PMOS transistor, the control circuit is a comparator, the first input terminal of the comparator is an inverting input terminal of the comparator, the second input terminal of the comparator is a non-inverting input terminal of the comparator, and the comparator is turned off when the enable terminal of the comparator receives a high-level signal.

7. The ramp voltage generating circuit according to claim 2, wherein the current regulating branch comprises: the input end of the third branch circuit is connected with the voltage input end of the ramp voltage generating circuit, the control end of the third branch circuit is connected with the output end of the control circuit, and the output end of the third branch circuit is connected with the far-ground end of the capacitor;

8. The ramp voltage generating circuit according to claim 7, wherein the third branch comprises: and a first end of the sixth switching tube is connected with a voltage input end of the ramp voltage generating circuit, a second end of the sixth switching tube is connected with a far-ground end of the capacitor, and a control end of the sixth switching tube is connected with an output end of the control circuit.

9. The ramp voltage generating circuit of claim 8, wherein the sixth switch is a PMOS transistor, the control circuit is a comparator, the first input terminal of the comparator is a non-inverting input terminal of the comparator, the second input terminal of the comparator is an inverting input terminal of the comparator, and the comparator is turned off when the enable terminal of the comparator receives a low level signal.

10. The ramp voltage generating circuit according to claim 8, wherein the sixth switching transistor is an NMOS transistor, the control circuit is a comparator, the first input terminal of the comparator is an inverting input terminal of the comparator, the second input terminal of the comparator is a non-inverting input terminal of the comparator, and the comparator is turned off when the enable terminal of the comparator receives a high signal.

11. The ramp voltage generating circuit according to any one of claims 2 to 10, wherein a first input terminal of the control circuit is connected to the control terminal of the first switch tube, and the reference voltage is input.

12. A chip comprising the ramp voltage generating circuit according to any one of claims 1 to 11.

13. An electronic device comprising the ramp voltage generating circuit according to any one of claims 1 to 11, wherein the electronic device has a soft start function, and a first input terminal thereof inputs the ramp voltage outputted from the ramp voltage generating circuit, and a second input terminal thereof inputs a reference voltage, and an output voltage thereof operates in accordance with the smaller one of the reference voltage and the ramp voltage.