CN110098832B - DCDC conversion circuit for starting double-output at ultralow voltage and implementation method thereof - Google Patents

DCDC conversion circuit for starting double-output at ultralow voltage and implementation method thereof Download PDF

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CN110098832B
CN110098832B CN201910364378.2A CN201910364378A CN110098832B CN 110098832 B CN110098832 B CN 110098832B CN 201910364378 A CN201910364378 A CN 201910364378A CN 110098832 B CN110098832 B CN 110098832B
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output
nmos
tube
voltage
pmos
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CN110098832A (en
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郭家树
陈后鹏
李喜
王倩
雷宇
苗杰
解晨晨
吕艺
刘卫丽
宋志棠
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09421—Diode field-effect transistor logic

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Abstract

The invention provides a DCDC conversion circuit for starting double-path output at ultralow voltage and a realization method thereof, wherein the DCDC conversion circuit comprises: the dual-output module is electrically connected with a high-voltage power-on reset module of the dual-output module, a power tube substrate level selection module which is electrically connected with the high-voltage power-on reset module and the dual-output module, a working mode switching module which is electrically connected with the high-voltage power-on reset module and the dual-output module, a control tube substrate level selection module which is electrically connected with the working mode switching module, a load access module which is electrically connected with the dual-output module and a modulation signal generation module which is electrically connected with the dual-output module, the load access module and the working mode switching module. The invention solves the problems that the existing DCDC conversion circuit can not work under low power voltage, needs an additional clock generation device and has only one output.

Description

DCDC conversion circuit for starting double-output at ultralow voltage and implementation method thereof
Technical Field
The invention belongs to the field of circuit design, and particularly relates to a DCDC conversion circuit for starting double-output at ultralow voltage and an implementation method thereof.
Background
The DCDC conversion circuit is widely applied to various vehicle-mounted chips and Internet of things chips, can reasonably adjust the power supply voltage of the chips according to the application condition, and can generate stable voltage or current supply under the condition of ensuring the fluctuation of the external power supply voltage and the load.
The structure of a classic DCDC conversion circuit is shown in FIG. 1, and in order to ensure the generation of a modulation signal, an input voltage VinMust be greater than 1.4V to 1.8V. The structure of the conventional synchronous DCDC conversion circuit is shown in FIG. 2, and the diode is replaced by a PMOS tube; to ensure the generation of the modulated signal, its input voltage VinOnly one output is needed above the threshold voltage of the PMOS tube and under the control of a modulation signal; since the synchronous DCDC conversion circuit needs additional clock generation devices (such as MEMS switches) in the early stage of operation, this also limits the use condition of the chip and increases the chip cost.
The existing DCDC conversion circuit has the following defects: 1) the DCDC conversion circuit cannot work under low power supply voltage (such as 0.5 times of threshold voltage), 2) an additional clock generation device is needed, and 3) only one output is needed, so that a new DCDC conversion circuit with ultra-low voltage starting and double output and an implementation method thereof are needed to be designed to solve the technical problems.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an ultra-low voltage enabled dual-output DCDC conversion circuit and an implementation method thereof, which are used to solve the problems that the conventional DCDC conversion circuit cannot operate at a low power voltage, needs an additional clock generation device, and has only one output.
To achieve the above and other related objects, the present invention provides an ultra-low voltage enabled dual output DCDC conversion circuit, comprising:
the double-path output module comprises a single-path output unit and a double-path output unit, and is used for generating two paths of output voltages according to the input voltage and is in an oscillator working mode when the output voltage is smaller than a detection threshold value so as to generate two paths of output direct current levels higher than the input voltage; when the output voltage is greater than or equal to the detection threshold value, the circuit is in a closed-loop working mode so as to generate an output direct current level according to a modulation signal;
the high-voltage power-on reset module is electrically connected with the two-way output unit and is used for detecting the output voltage of the two-way output unit, generating a first selection signal when the detection voltage is smaller than the detection threshold value, and generating a second selection signal when the detection voltage is larger than or equal to the detection threshold value;
the power tube substrate level selection module comprises a first power tube substrate level selection unit and a second power tube substrate level selection unit, wherein the first power tube substrate level selection unit is electrically connected with the high-voltage power-on reset module and the one-way output unit, and the second power tube substrate level selection unit is electrically connected with the high-voltage power-on reset module and the two-way output unit and is used for selecting access voltages at the bottom ends of the power tube substrates in the one-way output unit and the two-way output unit according to the first selection signal or the second selection signal;
the working mode switching module is electrically connected with the high-voltage power-on reset module and the dual-path output module, and is used for switching the dual-path output module to an oscillator working mode under the action of the first selection signal and switching the dual-path output module to a closed-loop working mode under the action of the second selection signal;
the control tube substrate level selection module comprises a PMOS control tube substrate level selection unit and an NMOS control tube substrate level selection unit, wherein the PMOS control tube substrate level selection unit is electrically connected to a PMOS tube in the working mode switching module, and the NMOS control tube substrate level selection unit is electrically connected to an NMOS tube in the working mode switching module and is used for adjusting the access voltage of the substrate ends of the PMOS control tube and the NMOS control tube in the working mode switching module; the load access module is electrically connected with the two-way output unit and used for sampling the output voltage and generating a load access signal to control the load access when the sampling voltage is greater than or equal to a reference threshold value;
the modulation signal generation module comprises a first modulation signal generation unit and a second modulation signal generation unit, wherein the first modulation signal generation unit and the second modulation signal generation unit are electrically connected to the two-way output unit, the load access module and the working mode switching module, the first modulation signal generation unit is used for generating the modulation signal under the control of the load access signal, and the second modulation signal generation unit is used for generating the modulation signal when the two-way output module is in a closed-loop working mode.
Optionally, the one-way output unit includes: the power supply comprises a first inductor, a first NMOS power tube, a first diode and a first capacitor, wherein one end of the first inductor is connected to the input voltage, the other end of the first inductor is connected to the drain end of the first NMOS power tube and is simultaneously connected to the anode end of the first diode, the source end of the first NMOS power tube is grounded, the gate end of the first NMOS power tube is connected to the working mode switching module, the substrate end of the first NMOS power tube is connected to the first power tube substrate level selection unit, the cathode end of the first diode is connected to one end of the first capacitor and is simultaneously used as the output end of the output unit, and the other end of the first capacitor is grounded;
the two-way output unit includes: the power supply circuit comprises a second inductor, a second NMOS power tube, a second diode and a second capacitor, wherein one end of the second inductor is connected to the input voltage, the other end of the second inductor is connected to the drain end of the second NMOS power tube and is simultaneously connected to the anode end of the second diode, the source end of the second NMOS power tube is grounded, the gate end of the second NMOS power tube is connected to the working mode switching module, the substrate end of the second NMOS power tube is connected to the substrate level selection unit of the second power tube, the cathode end of the second diode is connected to one end of the second capacitor and is simultaneously used as the output end of the two output units, and the other end of the second capacitor is grounded.
Optionally, the high-voltage power-on reset module includes: the low-voltage power-on reset circuit comprises a low-voltage power-on reset unit, a charge pump, a filter capacitor and a filter resistor, wherein the input end of the low-voltage power-on reset unit is connected with the two-path output unit, the output end of the low-voltage power-on reset unit is connected with the input end of the charge pump, the output end of the charge pump is connected with one end of the filter resistor, the other end of the filter resistor is connected with one end of the filter capacitor and is simultaneously used as the output end of the high-voltage power-on reset module, and the.
Optionally, the first power transistor substrate level selection unit includes: the power supply circuit comprises a first PMOS selection power tube and a first NMOS selection power tube, wherein the source end of the first PMOS selection power tube is connected to the input voltage, the grid end of the first PMOS selection power tube is connected to the grid end of the first NMOS selection power tube and is also connected to the high-voltage power-on reset module, the drain end of the first PMOS selection power tube is connected to the drain end of the first NMOS selection power tube and is also used as the output end of a substrate level selection unit of the first power tube, and the source end of the first NMOS selection power tube is grounded;
the second power tube substrate level selection unit comprises: the power supply circuit comprises a second PMOS selection power tube and a second NMOS selection power tube, wherein the source end of the second PMOS selection power tube is connected to the input voltage, the grid end of the second PMOS selection power tube is connected to the grid end of the second NMOS selection power tube and is also connected to the high-voltage power-on reset module, the drain end of the second PMOS selection power tube is connected to the drain end of the second NMOS selection power tube and is also used as the output end of a substrate level selection unit of the second power tube, and the source end of the second NMOS selection power tube is grounded.
Optionally, the operating mode switching module includes: the high-voltage power-on reset circuit comprises a first PMOS control tube, a second PMOS control tube, a first NMOS control tube and a second NMOS control tube, wherein a gate terminal of the first PMOS control tube, a gate terminal of the second PMOS control tube, a gate terminal of the first NMOS control tube and a gate terminal of the second NMOS control tube are simultaneously connected to the high-voltage power-on reset module; the drain end of the second PMOS control tube is connected to the two paths of output units, the source end of the second PMOS control tube is connected to the one path of output units, and the substrate end of the second PMOS control tube is connected to the substrate level selection unit of the other PMOS control tube; the drain terminal of the first NMOS control tube is connected to the one-way output unit, the source terminal of the first NMOS control tube is connected to the first modulation signal generation unit, and the substrate terminal of the first NMOS control tube is connected to a substrate level selection unit of the NMOS control tube; the drain terminal of the second NMOS control tube is connected to the two-way output unit, the source terminal of the second NMOS control tube is connected to the second modulation signal generation unit, and the substrate terminal of the second NMOS control tube is connected to the other NMOS control tube substrate level selection unit.
Optionally, the PMOS control transistor substrate level selection unit includes: a first PMOS selection control tube, a second PMOS selection control tube, a first inverter, a second inverter and a first comparator, wherein the grid terminal of the first PMOS selection control tube is connected with the output terminal of the first inverter, the source terminal of the first PMOS selection control tube is connected with the first input end of the first comparator, and connected to the working mode switching module, the drain terminal of the first PMOS selection control tube is connected to the drain terminal of the second PMOS selection control tube, the grid terminal of the second PMOS selection control tube is connected with the input terminal of the first phase inverter, and the source terminal of the second PMOS selection control tube is connected with the second input terminal of the first comparator, the input end of the second phase inverter is connected with the output end of the first comparator;
the NMOS control tube substrate level selection unit comprises: a first NMOS selection control transistor, a second NMOS selection control transistor, a third inverter, a fourth inverter and a second comparator, wherein the gate terminal of the first NMOS selection control tube is connected to the output terminal of the third inverter, the drain terminal of the first NMOS selection control tube is connected to the first input end of the second comparator, and is connected to the working mode switching module, the source terminal of the first NMOS selective control tube is connected to the source terminal of the second NMOS selective control tube, the grid terminal of the second NMOS selection control tube is connected with the input terminal of the third inverter, and the second NMOS selection control tube is connected with the output end of the fourth inverter, the drain end of the second NMOS selection control tube is connected with the second input end of the second comparator, and the input end of the fourth phase inverter is connected to the output end of the second comparator.
Optionally, the load access module includes: a first resistor, a second resistor, a hysteresis comparator, a first PMOS load control transistor and a second PMOS load control transistor, wherein one end of the first resistor is connected to the two-way output unit and is also connected to the source terminal of the first PMOS load control tube, the other end of the first resistor is connected to one end of the second resistor, and is connected to the first input terminal of the hysteresis comparator, the other end of the second resistor is grounded, a second input end of the hysteresis comparator is connected with a reference threshold, an output end of the hysteresis comparator is connected with grid ends of the first PMOS load control tube and the second PMOS load control tube at the same time, the drain electrode of the first PMOS load control tube is connected with a first load, the source electrode of the second PMOS load control tube is connected with the two-way output unit, and the drain end of the second PMOS load control tube is connected to the first modulation signal generating unit.
Optionally, the first modulation signal generation unit and the second modulation signal generation unit each include: the load access module is connected with the first input end of the error amplifier, the output end of the error amplifier is connected with the first input end of the modulation comparator, the second input end of the modulation comparator is connected with the output end of the clock signal generator, the output end of the modulation comparator is connected with the R end of the RS latch, the S end of the RS latch is connected with the input end of the clock signal generator, and the Q end of the RS latch serves as the output end.
The invention also provides a method for realizing the ultra-low voltage starting dual-output DCDC conversion circuit, which comprises the following steps:
under the condition of low-level input voltage power supply, the DCDC conversion circuit starts to work and generates two paths of output voltages; the high-voltage power-on reset module detects the output voltage and generates a first selection signal when the detected voltage is smaller than a detection threshold value so as to control the working mode switching module to switch the two-way output module to an oscillator working mode, and therefore two-way output direct-current levels higher than the input voltage are generated;
with the gradual rise of the output voltage, when the detection voltage is equal to the detection threshold value, the high-voltage power-on reset module generates a second selection signal to control the working mode switching module to switch the two-way output module to a closed-loop working mode, and at the moment, a second modulation signal generation unit generates a modulation signal to control the two-way output unit to generate an output direct-current level;
with the continuous rise of the output voltage, when the corresponding sampling voltage rises to a reference threshold value, the load access module generates a load access signal to control the two output units to access the load, and simultaneously controls the first modulation signal generation unit to generate a modulation signal to pull up the output voltage of the one output unit, so that the subsequent load is driven, and the two output modules stably output two output direct current levels higher than the input voltage.
Optionally, the dual output module is in an oscillator operation modeThe output DC level generated by the output unit
Figure BDA0002047746120000051
Figure BDA0002047746120000052
The output DC level generated by the two-way output unit
Figure BDA0002047746120000053
Wherein L is1Is the inductance value of the first inductor, L2Is the inductance value of the second inductor, C1Is the sum of parasitic capacitances of the drain terminal of the first NMOS power tube, the drain terminal of the first PMOS control tube and the anode terminal of the first diode, C2Q is the sum of parasitic capacitances at the drain end of the second NMOS power tube, the drain end of the second PMOS control tube and the anode end of the second diode1Is L1C1Quality factor, Q, of the resonant tank2Is L2C2Quality factor of the resonant tank, VinFor input voltage, Vth1Is the turn-on voltage of the first diode, Vth2Is the turn-on voltage of the second diode.
As described above, the ultra-low voltage start dual-output DCDC conversion circuit and the implementation method thereof of the present invention have the following beneficial effects:
the DCDC conversion circuit can normally work under ultra-low voltage and is suitable for low-voltage working environments such as micro energy collection and the like.
The DCDC conversion circuit does not need an additional clock generation device in the working initial stage, is compatible with a standard CMOS (complementary metal oxide semiconductor) process, is easy to integrate and saves the chip area and the cost.
The DCDC conversion circuit can realize double-path output and improve the application range of the circuit.
Drawings
Fig. 1 is a circuit diagram of a conventional DCDC conversion circuit.
Fig. 2 shows a circuit diagram of a synchronous DCDC conversion circuit.
Fig. 3 is a circuit diagram of the DCDC conversion circuit according to the present invention.
Fig. 4 is a circuit diagram of the high voltage power-on reset module according to the present invention.
FIG. 5 is a circuit diagram of a substrate level selection unit of a PMOS control transistor according to the present invention.
FIG. 6 is a circuit diagram of a substrate level selection unit of an NMOS control transistor according to the present invention.
Fig. 7 is a circuit diagram of the first modulation signal generating unit or the second modulation signal generating unit according to the present invention.
Fig. 8 is a schematic circuit diagram of the dual output module according to the present invention operating in the oscillator mode.
Fig. 9 is a schematic circuit diagram of the dual output module according to the present invention operating in a closed-loop mode.
Fig. 10 is a waveform diagram of a dual output voltage when the input voltage of the DCDC conversion circuit of the present invention is 0.4V.
Description of the element reference numerals
100 double-path output module
101 one-way output unit
102 two-way output unit
200 high-voltage power-on reset module
300 power tube substrate level selection module
301 first power transistor substrate level selection unit
302 second power transistor substrate level selection unit
400 operating mode switching module
500 control tube substrate level selection module
501 PMOS control tube substrate level selection unit
502 NMOS control tube substrate level selection unit
600 load access module
700 modulation signal generating module
701 first modulation signal generating unit
702 second modulation signal generation unit
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 10. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 3, the present embodiment provides an ultra-low voltage enabled dual output DCDC conversion circuit, which includes:
the dual output module 100 includes a single output unit 101 and a dual output unit 102 for outputting a voltage according to an input voltage VinGenerating two output voltages, and operating in oscillator mode when the output voltage is less than the detection threshold to generate a voltage higher than the input voltage VinThe two paths of the output direct current level; when the output voltage is greater than or equal to the detection threshold value, the circuit is in a closed-loop working mode so as to generate an output direct current level according to a modulation signal;
a high-voltage power-on reset module 200, electrically connected to the two-way output unit 102, configured to detect an output voltage of the two-way output unit 102, generate a first selection signal when the detected voltage is smaller than the detection threshold, and generate a second selection signal when the detected voltage is greater than or equal to the detection threshold;
a power tube substrate level selection module 300, including a first power tube substrate level selection unit 301 and a second power tube substrate level selection unit 302, where the first power tube substrate level selection unit 301 is electrically connected to the high-voltage power-on reset module 200 and the one-way output unit 101, and the second power tube substrate level selection unit 302 is electrically connected to the high-voltage power-on reset module 200 and the two-way output unit 102, and is configured to select an access voltage at a bottom end of a power tube substrate in the one-way output unit 101 and the two-way output unit 102 according to the first selection signal or the second selection signal, so as to improve driving capability of power tubes in the one-way output unit 101 and the two-way output unit 102, and simultaneously ensure safety of power tubes in the one-way output unit 101 and the two-way output unit 102;
the working mode switching module 400 is electrically connected to the high-voltage power-on reset module 200 and the dual-path output module 100, and is configured to switch the dual-path output module 100 to an oscillator working mode under the action of the first selection signal and switch the dual-path output module 100 to a closed-loop working mode under the action of the second selection signal;
the control tube substrate level selection module 500 comprises a PMOS control tube substrate level selection unit 501 and an NMOS control tube substrate level selection unit 502, wherein the PMOS control tube substrate level selection unit 501 is electrically connected to a PMOS tube in the working mode switching module 400, and the NMOS control tube substrate level selection unit 502 is electrically connected to an NMOS tube in the working mode switching module 400, and is used for adjusting the access voltages at the substrate ends of the PMOS control tube and the NMOS control tube in the working mode switching module 400, so as to avoid mutual interference between two outputs, and ensure the safety of the PMOS control tube and the NMOS control tube in the working mode switching module 400;
a load access module 600 electrically connected to the two-way output unit 102 for sampling the output voltage and outputting a sampled voltage VsIs greater than or equal to a reference threshold value Vref1Generating Load access signal LoadonTo controlLoad making access;
the modulation signal generating module 700 comprises a first modulation signal generating unit 701 and a second modulation signal generating unit 702, the first modulation signal generating unit 701 and the second modulation signal generating unit 702 are electrically connected to the two-way output unit 102, the Load access module 600 and the operating mode switching module 400, the first modulation signal generating unit 701 is configured to receive the Load access signal Load when the Load access signal Load is detectedonIs controlled to generate the modulation signal, and the second modulation signal generation unit 702 is configured to generate the modulation signal when the dual output module 100 is in the closed-loop operation mode.
As an example, as shown in fig. 3, the one-way output unit 101 includes: first inductance L1A first NMOS power tube NP1A first diode D1And a first capacitor C1Wherein the first inductance L1One end of which is connected to the input voltage VinThe first inductance L1Is connected to the first NMOS power tube NP1Is connected to the first diode D at the same time1The first NMOS power tube NP1The source terminal of the first NMOS power tube N is grounded, and the first NMOS power tube N is connected with the first NMOS power tube NP1The gate terminal of the first NMOS power transistor N is connected to the operating mode switching module 400P1Is connected to the first power tube substrate level selection unit 301, the first diode D1Is connected to the first capacitor C1And the first capacitor C is also used as the output end of the output unit 1011And the other end of the same is grounded.
As an example, as shown in fig. 3, the two-way output unit 102 includes: second inductance L2A second NMOS power tube NP2A second diode D2And a second capacitor C2Wherein the second inductance L2One end of which is connected to the input voltage VinSaid second inductance L2Is connected to the second NMOS power tube NP2While being connected to the second diode D2The anode terminal of (a) a (b),the second NMOS power tube NP2The source terminal of the first NMOS power tube N is grounded, and the second NMOS power tube N is connected with the first NMOS power tube NP2The gate terminal of the second NMOS power transistor N is connected to the operating mode switching module 400P2Is connected to the second power transistor substrate level selection unit 302, the second diode D2Is connected to the second capacitor C2And at the same time, the second capacitor C is used as the output end of the two-way output unit 1022And the other end of the same is grounded.
As an example, as shown in fig. 4, the high voltage power-on reset module 200 includes: low-voltage power-on reset unit, charge pump and filter capacitor CPORAnd a filter resistor RPORWherein the input end of the low-voltage power-on reset unit is connected to the two-way output unit 102, the output end of the low-voltage power-on reset unit is connected to the input end of the charge pump, and the output end of the charge pump is connected to the filter resistor RPOROne terminal of, the filter resistance RPORIs connected to the filter capacitor C at the other endPORAnd the filter capacitor C is also used as the output end of the high-voltage power-on reset module 200PORAnd the other end of the same is grounded. It should be noted that the low-voltage power-on reset unit is any one of the existing circuits capable of implementing low-voltage power-on reset, and this embodiment does not limit the specific circuit structure of the low-voltage power-on reset unit.
In this embodiment, the high-voltage power-on reset module 200 generates a low-level first selection signal (i.e. outputs a low level "0") when the detection voltage is smaller than the detection threshold; when the detection voltage is equal to or greater than the detection threshold, a second selection signal of a high level is generated (i.e., a high level "1" is output).
As an example, as shown in fig. 3, the first power transistor substrate level selection unit 301 includes: first PMOS selection power tube PSP1And the first NMOS selects the power tube NSP1Wherein the first PMOS selects the power transistor PSP1Source terminal of is connected to the input voltage VinThe first PMOS selects the power tube PSP1Is connected to the gate terminalThe first NMOS selects the power tube NSP1The gate terminal of the first PMOS transistor is connected to the high-voltage power-on reset module 200, and the first PMOS transistor selects the power transistor PSP1Drain terminal thereof is connected to the first NMOS selection power tube NSP1And the drain terminal of the first NMOS selection power transistor N is also used as the output terminal of the first power transistor substrate level selection unit 301SP1The source terminal of which is grounded.
As an example, as shown in fig. 3, the second power transistor substrate level selection unit 302 includes: second PMOS selection power tube PSP2And a second NMOS select power transistor NSP2Wherein the second PMOS selects the power transistor PSP2Source terminal of is connected to the input voltage VinThe second PMOS selects the power tube PSP2The grid end of the second NMOS selection power tube N is connected with the second NMOS selection power tube NSP2The gate terminal of the power transistor P is connected to the high-voltage power-on reset module 200, and the second PMOS selects the power transistor PSP2Drain terminal thereof is connected to the second NMOS selection power tube NSP2And the drain terminal of the second NMOS transistor is also used as the output terminal of the second power transistor substrate level selection unit 302, and the second NMOS transistor selects the power transistor NSP2The source terminal of which is grounded.
In this embodiment, the first power transistor substrate level selection unit 301 and the second power transistor substrate level selection unit 302 are controlled by the first selection signal and the second selection signal output by the high-voltage power-on reset module 200: when the high-voltage power-on reset module 200 outputs a low level (i.e. outputs a first selection signal), the first PMOS selection power transistor P in the first power transistor substrate level selection unit 301 selects the first PMOS selection power transistor PSP1Conducting first NMOS selection power tube NSP1Turning off, the second PMOS selection power tube P in the second power tube substrate level selection unit 302SP2Conducting, the second NMOS selects the power tube NSP2Turning off, at this time, the first NMOS power transistor N in the one-way output unit 101P1Is connected to the substrate terminal of the input voltage VinA second NMOS power tube N in the two-way output unit 102P2Is connected to the substrate terminal of the input voltage VinTo reduce the first NMOS powerRate tube NP1And a second NMOS power transistor NP2The driving capability of the threshold voltage under low input voltage is improved; when the high voltage power-on reset module 200 outputs a high level (i.e. outputs a second selection signal), the first PMOS selection power transistor P in the first power transistor substrate level selection unit 301 selects the first PMOS selection power transistor PSP1Turn-off, first NMOS selection power tube NSP1Conducting, the second PMOS selection power transistor P in the second power transistor substrate level selection unit 302SP2Turn off, the second NMOS selects the power tube NSP2Conducting, at this time, the first NMOS power transistor N in the one-way output unit 101P1The substrate end of (1) is grounded, and a second NMOS power tube N in the two-way output unit 102P2To reduce the first NMOS power transistor NP1And a second NMOS power transistor NP2The leakage current of (1).
As an example, as shown in fig. 3, the operation mode switching module 400 includes: first PMOS control tube PC1A second PMOS control tube PC2A first NMOS control tube NC1And a second NMOS control tube NC2Wherein the first PMOS control tube PC1Gate terminal of said second PMOS control transistor PC2Gate terminal of and the first NMOS control tube NC1Gate terminal of and the second NMOS control tube NC2The gate terminal of the first PMOS transistor is connected to the high-voltage power-on reset module 200, and the first PMOS transistor PC1The drain end of the first PMOS control tube P is connected to the one-way output unit 101C1The source terminal of the first PMOS control tube P is connected to the two-way output unit 102C1The substrate end of the PMOS control transistor is connected to a substrate level selection unit 501 of the PMOS control transistor; the second PMOS control tube PC2The drain end of the second PMOS control tube P is connected to the two-way output unit 102C2A source terminal thereof is connected to the one output unit 101, and the second PMOS control transistor PC2The substrate end of the PMOS control transistor is connected to another substrate level selection unit 501 of the PMOS control transistor; the first NMOS control tube NC1The drain end of the first NMOS control tube N is connected to the one-way output unit 101C1Source terminal of is connected toThe first modulation signal generating unit 701, the first NMOS control transistor NC1The substrate end of the NMOS control tube is connected to a substrate level selection unit 502 of the NMOS control tube; the second NMOS control tube NC2The drain end of the second NMOS control tube N is connected to the two-way output unit 102C2Is connected to the second modulation signal generating unit 702, the second NMOS control transistor NC2Is connected to another NMOS control transistor substrate level selection unit 502.
In this embodiment, the working mode switching module 400 is controlled by the first selection signal and the second selection signal output by the high voltage power-on reset module 200, and when the high voltage power-on reset module 200 outputs a low level (i.e. outputs the first selection signal), the first PMOS control transistor P in the working mode switching module 400C1And a second PMOS control tube PC2Conducting, the first NMOS controls the transistor NC1And a second NMOS control tube NC2Turning off, at which time the operation mode switching module 400 switches the dual output module 100 to the oscillator operation mode (as shown in fig. 8); when the high voltage power-on reset module 200 outputs a high level (i.e. outputs a second selection signal), the first PMOS control transistor P in the operating mode switching module 400C1And a second PMOS control tube PC2Turn off, the first NMOS controls the transistor NC1And a second NMOS control tube NC2And when the operation mode switching module 400 is turned on, the dual output module 100 is switched to the closed-loop operation mode (as shown in fig. 9).
As an example, as shown in fig. 5, the PMOS control transistor substrate level selection unit 501 includes: first PMOS selection control tube PSC1A second PMOS selection control tube PSC2A first inverter INV1A second inverter INV2And a first comparator Comp1Wherein the first PMOS selection control tube PSC1Is connected to the first inverter INV1The first PMOS selection control tube PSC1Is connected to said first comparator Comp1Is connected to the operating mode switching module 400,the first PMOS selection control tube Comp1Drain terminal thereof is connected to the second PMOS selection control tube PSC2And a drain terminal connected to the operating mode switching module 400, wherein the second PMOS selection control transistor P selects the second PMOS selection control transistor PSC2Is connected to the first inverter INV1And an input end connected to the second inverter INV2The second PMOS selection control tube PSC2Is connected to said first comparator Comp1And a second input end connected to the operation mode switching module 400, the second inverter INV2Is connected to said first comparator Comp1To the output terminal of (a).
As an example, as shown in fig. 6, the NMOS control transistor substrate level selection unit 502 includes: first NMOS selection control tube NSC1A second NMOS selection control tube NSC2A third inverter INV3And a fourth inverter INV4And a second comparator Comp2Wherein the first NMOS selects the control transistor NSC1Is connected to the third inverter INV3The first NMOS selects the control tube NSC1Is connected to said second comparator Comp2And a first input end connected to the operating mode switching module 400, wherein the first NMOS selects the control transistor NSC1Source terminal of the second NMOS selection control tube NSC2The source terminal of the NMOS transistor is connected to the operating mode switching module 400, and the second NMOS transistor selects the control transistor NSC2Is connected to the third inverter INV3And an input end connected to the fourth inverter INV4The second NMOS selects the control tube NSC2Is connected to said second comparator Comp2And a second input end connected to the operation mode switching module 400, the fourth inverter INV4Is connected to said second comparator Comp2To the output terminal of (a).
In this embodiment, the PMOS control transistor substrate level selection unit 501 controls the first PMOS transistor according to the first PMOS transistor connected theretoPipe PC1Or the second PMOS control tube PC2The source-drain end voltage of the first PMOS control tube P is adjusted to be connected intoC1Or the second PMOS control tube PC2The voltage at the substrate end is large or small to avoid the mutual interference between two paths of outputs and ensure the first PMOS control tube PC1And the second PMOS control tube PC2The safety of (2). The NMOS control tube substrate level selection unit 502 selects the first NMOS control tube N according to the connection thereofC1Or the second NMOS control tube NC2The source-drain end voltage of the first NMOS control tube N is adjusted and connectedC1Or the second NMOS control tube NC2The voltage of the substrate end is large and small so as to avoid the mutual interference between two paths of outputs and ensure the first NMOS control tube NC1And the second NMOS control tube NC2The safety of (2).
As an example, as shown in fig. 3, the load access module 600 includes: a first resistor R1A second resistor R2Hysteresis comparator ComphA first PMOS load control tube PLC1And a second PMOS load control tube PLC2Wherein the first resistor R1Is connected to the two-way output unit 102 and is also connected to the first PMOS load control transistor PLC1The source terminal of, the first resistor R1Is connected to the second resistor R at the other end2Is connected to the hysteresis comparator ComphThe second resistor R, the first input terminal, the second resistor R2Is grounded, said hysteresis comparator ComphSecond input terminal of (2) is connected to a reference threshold value Vref1Said hysteresis comparator ComphIs connected to the first PMOS load control tube PLC1And the second PMOS load control tube PLC2The first PMOS load control tube PLC1Is connected to a first load Rload1The second PMOS load control tube PLC2Is connected to the two-way output unit 102 and is also connected to a second load Rload2The second PMOS load control tube PLC2Is connected to the first modulation signal generationAnd (5) a unit 701.
In this embodiment, the hysteretic comparator samples the first resistor R1Voltage at both ends and at the sampling voltage VsIs greater than or equal to a reference threshold value Vref1Time output Load access signal LoadonTo control the first PMOS load control tube PLC1Is conducted to load Rload1Accessing the DCDC conversion circuit; at the same time, the Load is connected to the signal LoadonControlling the second PMOS load control tube PLC2On to increase the output voltage of the output unit 101 by the modulation signal generated by the first modulation signal generating unit 701, so that the output voltage drives the load Rload2。
As an example, as shown in fig. 7, the first modulation signal generation unit 701 and the second modulation signal generation unit 702 each include: error amplifier EA, modulation comparator CompmA clock signal generator and an RS latch, wherein a first input end of the error amplifier EA is connected with a preset voltage Vref2A second input terminal of the error amplifier EA is connected to the load access module 600, and an output terminal of the error amplifier EA is connected to the modulation comparator CompmSaid modulation comparator CompmIs connected to the output of said clock signal generator, said modulation comparator CompmThe output end of the RS latch is connected to the R end of the RS latch, the S end of the RS latch is connected to the input end of the clock signal generator, and the Q end of the RS latch serves as the output end. It should be noted that this embodiment is only an example of the first modulation signal generation unit 701 and the second modulation signal generation unit 702, and of course, other circuit structures capable of generating modulation signals are also applicable to this embodiment, and this embodiment does not limit the specific circuit structures of the first modulation signal generation unit 701 and the second modulation signal generation unit 702.
In the present embodiment, the preset voltage Vref2And a sampling voltage VsAn error signal is generated after passing through an error amplifier EA, the error signal is compared with a clock signalThe generator generates a triangular wave signal to generate a duty cycle and a sampling voltage VsThe magnitude of the clock signal is related to drive the first NMOS control transistor NC1And a second NMOS control tube NC2To control the first inductor L1And a second inductance L2The charging and discharging time of the power supply so as to ensure that the output load is changed when V is changedsAnd keeping stable.
As shown in fig. 3 to fig. 10, this embodiment further provides an implementation method of the ultra-low voltage enabled dual output DCDC conversion circuit, where the implementation method includes:
under the condition of low-level input voltage power supply, the DCDC conversion circuit starts to work and generates two paths of output voltages; the high-voltage power-on reset module detects the output voltage and generates a first selection signal when the detected voltage is smaller than a detection threshold value so as to control the working mode switching module to switch the double-path output module to an oscillator working mode, and therefore two paths of output direct current levels higher than the input voltage are generated. As shown in fig. 3, when the detection voltage is smaller than the detection threshold, the high-voltage power-on reset module 200 generates a first selection signal (i.e. low level "0") to control the first PMOS selected power transistor P in the first power transistor substrate level selection unit 301SP1Conducting first NMOS selection power tube NSP1Turning off, the second PMOS selection power tube P in the second power tube substrate level selection unit 302SP2Conducting and second NMOS selecting power tube NSP2Turn off, the first PMOS control tube P in the working mode switching module 400C1And a second PMOS control tube PC2Conducting first NMOS control tube NC1And a second NMOS control tube NC2Turning off; at this time, the first inductor L1A second inductor L2A first NMOS power tube NP1A second NMOS power tube NP2The first PMOS control tube PC1A second PMOS control tube PC2And parasitic capacitance Cs1And Cs2Together forming a cross-coupled LC oscillator (as shown in FIG. 8) producing a voltage at node A, B that is higher than the input voltage VinThe oscillation signals are respectively passed through the first and secondPolar tube D1And a first capacitor C1A second diode D2And a second capacitor C2The rectified output is higher than the input voltage VinTwo-way output DC level VF1And VF2。
As an example, when the dual output module is in the oscillator operation mode, the one-way output unit generates an output dc level
Figure BDA0002047746120000131
Figure BDA0002047746120000132
The output DC level generated by the two-way output unit
Figure BDA0002047746120000133
Wherein L is1Is the inductance value of the first inductor, L2Is the inductance value of the second inductor, C1Is the sum of parasitic capacitances of the drain terminal of the first NMOS power tube, the drain terminal of the first PMOS control tube and the anode terminal of the first diode, C2Q is the sum of parasitic capacitances at the drain end of the second NMOS power tube, the drain end of the second PMOS control tube and the anode end of the second diode1Is L1C1Quality factor, Q, of the resonant tank2Is L2C2Quality factor of the resonant tank, VinFor input voltage, Vth1Is the turn-on voltage of the first diode, Vth2Is the turn-on voltage of the second diode.
From the above formula, it can be seen that L is constant with the parasitic capacitance1/L2The larger the value of (A), VF1And VF2The larger the peak value of (a), the higher the output direct current level after being rectified by a diode and a capacitor.
With the gradual rise of the output voltage, when the detection voltage is equal to the detection threshold value, the high-voltage power-on reset module generates a second selection signal to control the working mode switching module to switch the two-way output module to a closed-loop working mode,and at the moment, the second modulation signal generating unit generates a modulation signal, so that the two-way output unit is controlled to generate an output direct current level. As shown in fig. 3, when the detection voltage is equal to the detection threshold, the high-voltage power-on reset module 200 generates a second selection signal (i.e. high level "1") to control the first PMOS selected power transistor P in the first power transistor substrate level selection unit 301SP1Turn-off, first NMOS selection power tube NSP1Conducting, the second PMOS selection power transistor P in the second power transistor substrate level selection unit 302SP2Turn-off and second NMOS selection power tube NSP2On, the first PMOS control tube P in the working mode switching module 400C1And a second PMOS control tube PC2Turn-off, first NMOS control tube NC1And a second NMOS control tube NC2Conducting; at this time, the first inductor L1A second inductor L2A first NMOS power tube NP1A second NMOS power tube NP2A first NMOS control tube NC1A second NMOS control tube NC2A first diode D1A second diode D2A first capacitor C1A second capacitor C2The closed-loop operation mode of the common standard DCDC conversion circuit (as shown in fig. 9) is adopted, and the second modulation signal generating unit 702 generates a stable modulation signal to control the two-way output unit 102 to generate the output dc level.
With the continuous rise of the output voltage, when the corresponding sampling voltage rises to a reference threshold value, the load access module generates a load access signal to control the two output units to access the load, and simultaneously controls the first modulation signal generation unit to generate a modulation signal to pull up the output voltage of the one output unit, so that the subsequent load is driven, and the two output modules stably output two output direct current levels higher than the input voltage. Specifically, as shown in FIG. 3, at a sampling voltage VsRises to a reference threshold Vref1Then, the hysteresis comparator outputs a load access signal to control the first PMOS load control tube PLC1And a second PMOS load control tube PLC2Is conducted to realize the control of the tube P through the first PMOS loadLC1Conducting the load Rload1In the access circuit, the tube P is controlled by a second PMOS loadLC2The first modulation signal generating unit generates modulation signals to enable the output unit to start working and gradually pull up the output direct current level generated by the output unit, so that the load R is drivenload2(ii) a Finally with the load Rload1And Rload2Make the output voltage Vout1And Vout2Gradually becomes stable to realize stable output of voltage V higher than the input voltageinOutputs a direct current level.
FIG. 10 shows the input voltage V of the DCDC conversion circuit of this embodimentinAs shown in fig. 10, the DCDC conversion circuit of the present embodiment can normally operate at an ultra-low voltage, does not need an additional clock generation device in an initial stage of operation, and has a dual output.
In summary, the ultra-low voltage start dual-output DCDC conversion circuit and the implementation method thereof of the present invention have the following beneficial effects: the DCDC conversion circuit can normally work under ultra-low voltage and is suitable for low-voltage working environments such as micro energy collection and the like. The DCDC conversion circuit does not need an additional clock generation device in the working initial stage, is compatible with a standard CMOS (complementary metal oxide semiconductor) process, is easy to integrate and saves the chip area and the cost. The DCDC conversion circuit can realize double-path output and improve the application range of the circuit. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. An ultra-low voltage enabled dual output DCDC conversion circuit, comprising:
the double-path output module comprises a single-path output unit and a double-path output unit, and is used for generating two paths of output voltages according to the input voltage and is in an oscillator working mode when the output voltage is smaller than a detection threshold value so as to generate two paths of output direct current levels higher than the input voltage; when the output voltage is greater than or equal to the detection threshold value, the circuit is in a closed-loop working mode so as to generate an output direct current level according to a modulation signal;
the high-voltage power-on reset module is electrically connected with the two-way output unit and is used for detecting the output voltage of the two-way output unit, generating a first selection signal when the detection voltage is smaller than the detection threshold value, and generating a second selection signal when the detection voltage is larger than or equal to the detection threshold value;
the power tube substrate level selection module comprises a first power tube substrate level selection unit and a second power tube substrate level selection unit, wherein the first power tube substrate level selection unit is electrically connected with the high-voltage power-on reset module and the one-way output unit, and the second power tube substrate level selection unit is electrically connected with the high-voltage power-on reset module and the two-way output unit and is used for selecting access voltages at the bottom ends of the power tube substrates in the one-way output unit and the two-way output unit according to the first selection signal or the second selection signal;
the working mode switching module is electrically connected with the high-voltage power-on reset module and the dual-path output module, and is used for switching the dual-path output module to an oscillator working mode under the action of the first selection signal and switching the dual-path output module to a closed-loop working mode under the action of the second selection signal;
the control tube substrate level selection module comprises a PMOS control tube substrate level selection unit and an NMOS control tube substrate level selection unit, wherein the PMOS control tube substrate level selection unit is electrically connected to a PMOS tube in the working mode switching module, and the NMOS control tube substrate level selection unit is electrically connected to an NMOS tube in the working mode switching module and is used for adjusting the access voltage of the substrate ends of the PMOS control tube and the NMOS control tube in the working mode switching module;
the load access module is electrically connected with the two-way output unit and used for sampling the output voltage and generating a load access signal to control the load access when the sampling voltage is greater than or equal to a reference threshold value;
the modulation signal generation module comprises a first modulation signal generation unit and a second modulation signal generation unit, wherein the first modulation signal generation unit and the second modulation signal generation unit are electrically connected to the two-way output unit, the load access module and the working mode switching module, the first modulation signal generation unit is used for generating the modulation signal under the control of the load access signal, and the second modulation signal generation unit is used for generating the modulation signal when the two-way output module is in a closed-loop working mode.
2. The ultra-low voltage enabled dual output DCDC conversion circuit according to claim 1, wherein the one-way output unit comprises: the power supply comprises a first inductor, a first NMOS power tube, a first diode and a first capacitor, wherein one end of the first inductor is connected to the input voltage, the other end of the first inductor is connected to the drain end of the first NMOS power tube and is simultaneously connected to the anode end of the first diode, the source end of the first NMOS power tube is grounded, the gate end of the first NMOS power tube is connected to the working mode switching module, the substrate end of the first NMOS power tube is connected to the first power tube substrate level selection unit, the cathode end of the first diode is connected to one end of the first capacitor and is simultaneously used as the output end of the output unit, and the other end of the first capacitor is grounded; the two-way output unit includes: the power supply circuit comprises a second inductor, a second NMOS power tube, a second diode and a second capacitor, wherein one end of the second inductor is connected to the input voltage, the other end of the second inductor is connected to the drain end of the second NMOS power tube and is simultaneously connected to the anode end of the second diode, the source end of the second NMOS power tube is grounded, the gate end of the second NMOS power tube is connected to the working mode switching module, the substrate end of the second NMOS power tube is connected to the substrate level selection unit of the second power tube, the cathode end of the second diode is connected to one end of the second capacitor and is simultaneously used as the output end of the two output units, and the other end of the second capacitor is grounded.
3. The ultra-low voltage enabled dual output DCDC conversion circuit of claim 1, wherein the high voltage power-on reset module comprises: the low-voltage power-on reset circuit comprises a low-voltage power-on reset unit, a charge pump, a filter capacitor and a filter resistor, wherein the input end of the low-voltage power-on reset unit is connected with the output ends of the two paths of output units, the output end of the low-voltage power-on reset unit is connected with the input end of the charge pump, the output end of the charge pump is connected with one end of the filter resistor, the other end of the filter resistor is connected with one end of the filter capacitor and is simultaneously used as the output end of the high-voltage power-on reset module.
4. The DCDC conversion circuit of ultra-low voltage enabled dual output according to claim 1, wherein the first power transistor substrate level selection unit comprises: the power supply circuit comprises a first PMOS selection power tube and a first NMOS selection power tube, wherein the source end of the first PMOS selection power tube is connected to the input voltage, the grid end of the first PMOS selection power tube is connected to the grid end of the first NMOS selection power tube and is also connected to the high-voltage power-on reset module, the drain end of the first PMOS selection power tube is connected to the drain end of the first NMOS selection power tube and is also used as the output end of a substrate level selection unit of the first power tube, and the source end of the first NMOS selection power tube is grounded;
the second power tube substrate level selection unit comprises: the power supply circuit comprises a second PMOS selection power tube and a second NMOS selection power tube, wherein the source end of the second PMOS selection power tube is connected to the input voltage, the grid end of the second PMOS selection power tube is connected to the grid end of the second NMOS selection power tube and is also connected to the high-voltage power-on reset module, the drain end of the second PMOS selection power tube is connected to the drain end of the second NMOS selection power tube and is also used as the output end of a substrate level selection unit of the second power tube, and the source end of the second NMOS selection power tube is grounded.
5. The ultra-low voltage enabled dual output DCDC conversion circuit according to claim 2, wherein the operation mode switching module comprises: the high-voltage power-on reset circuit comprises a first PMOS control tube, a second PMOS control tube, a first NMOS control tube and a second NMOS control tube, wherein a gate terminal of the first PMOS control tube, a gate terminal of the second PMOS control tube, a gate terminal of the first NMOS control tube and a gate terminal of the second NMOS control tube are simultaneously connected to the high-voltage power-on reset module; the drain end of the second PMOS control tube is connected to the other end of the second inductor in the two paths of output units, the source end of the second PMOS control tube is connected to the gate end of the first NMOS power tube in the one path of output units, and the substrate end of the second PMOS control tube is connected to the substrate level selection unit of the other PMOS control tube; the drain terminal of the first NMOS control tube is connected to the gate terminal of a first NMOS power tube in the one-way output unit, the source terminal of the first NMOS control tube is connected to the first modulation signal generation unit, and the substrate terminal of the first NMOS control tube is connected to a substrate level selection unit of the NMOS control tube; the drain terminal of the second NMOS control tube is connected to the gate terminal of a second NMOS power tube in the two-way output unit, the source terminal of the second NMOS control tube is connected to the second modulation signal generation unit, and the substrate terminal of the second NMOS control tube is connected to another substrate level selection unit of the NMOS control tube.
6. The DCDC conversion circuit of ultra-low voltage enabled dual output according to claim 1, wherein the PMOS control transistor substrate level selection unit comprises: a first PMOS selection control tube, a second PMOS selection control tube, a first inverter, a second inverter and a first comparator, wherein the grid terminal of the first PMOS selection control tube is connected with the output terminal of the first inverter, the source terminal of the first PMOS selection control tube is connected with the first input end of the first comparator, and connected to the working mode switching module, the drain terminal of the first PMOS selection control tube is connected to the drain terminal of the second PMOS selection control tube, the grid terminal of the second PMOS selection control tube is connected with the input terminal of the first phase inverter, and the source terminal of the second PMOS selection control tube is connected with the second input terminal of the first comparator, the input end of the second phase inverter is connected with the output end of the first comparator;
the NMOS control tube substrate level selection unit comprises: a first NMOS selection control transistor, a second NMOS selection control transistor, a third inverter, a fourth inverter and a second comparator, wherein the gate terminal of the first NMOS selection control tube is connected to the output terminal of the third inverter, the drain terminal of the first NMOS selection control tube is connected to the first input end of the second comparator, and is connected to the working mode switching module, the source terminal of the first NMOS selective control tube is connected to the source terminal of the second NMOS selective control tube, the grid terminal of the second NMOS selection control tube is connected with the input terminal of the third inverter, and the second NMOS selection control tube is connected with the output end of the fourth inverter, the drain end of the second NMOS selection control tube is connected with the second input end of the second comparator, and the input end of the fourth phase inverter is connected to the output end of the second comparator.
7. The ultra-low voltage enabled dual output DCDC conversion circuit of claim 1, wherein the load access module comprises: a first resistor, a second resistor, a hysteresis comparator, a first PMOS load control transistor and a second PMOS load control transistor, wherein one end of the first resistor is connected to the output end of the two-way output unit and is also connected to the source terminal of the first PMOS load control transistor, the other end of the first resistor is connected to one end of the second resistor and is also connected to the first input end of the hysteresis comparator, the other end of the second resistor is grounded, the second input end of the hysteresis comparator is connected to a reference threshold, the output end of the hysteresis comparator is simultaneously connected to the gate terminals of the first PMOS load control transistor and the second PMOS load control transistor, the drain electrode of the first PMOS load control transistor is connected to the first load, the source terminal of the second PMOS load control transistor is connected to the output end of the two-way output unit and is also connected to the second load, and the drain end of the second PMOS load control tube is connected to the first modulation signal generation unit.
8. The DCDC conversion circuit of ultra-low voltage enabled dual output according to claim 1, wherein the first modulation signal generation unit and the second modulation signal generation unit each comprise: the load access module is connected with the first input end of the error amplifier, the output end of the error amplifier is connected with the first input end of the modulation comparator, the second input end of the modulation comparator is connected with the output end of the clock signal generator, the output end of the modulation comparator is connected with the R end of the RS latch, the S end of the RS latch is connected with the input end of the clock signal generator, and the Q end of the RS latch serves as the output end.
9. An implementation method of the ultra-low voltage enabled dual-output DCDC conversion circuit according to any one of claims 1 to 8, wherein the implementation method comprises:
under the condition of low-level input voltage power supply, the DCDC conversion circuit starts to work and generates two paths of output voltages; the high-voltage power-on reset module detects the output voltage and generates a first selection signal when the detected voltage is smaller than a detection threshold value so as to control the working mode switching module to switch the two-way output module to an oscillator working mode, and therefore two-way output direct-current levels higher than the input voltage are generated;
with the gradual rise of the output voltage, when the detection voltage is equal to the detection threshold value, the high-voltage power-on reset module generates a second selection signal to control the working mode switching module to switch the two-way output module to a closed-loop working mode, and at the moment, a second modulation signal generation unit generates a modulation signal to control the two-way output unit to generate an output direct-current level;
with the continuous rise of the output voltage, when the corresponding sampling voltage rises to a reference threshold value, the load access module generates a load access signal to control the two output units to access the load, and simultaneously controls the first modulation signal generation unit to generate a modulation signal to pull up the output voltage of the one output unit, so that the subsequent load is driven, and the two output modules stably output two output direct current levels higher than the input voltage.
10. The implementation method of the DCDC conversion circuit with ultra-low voltage start and dual output as claimed in claim 9, wherein when the dual output module is in the oscillator operation mode, the one output unit generates the output dc level
Figure FDA0002526355200000051
Figure FDA0002526355200000052
Output generated by the two-way output unitOutput DC level
Figure FDA0002526355200000053
Figure FDA0002526355200000054
Wherein L is1Is the inductance value of the first inductor, L2Is the inductance value of the second inductor, C1Is the sum of parasitic capacitances of the drain terminal of the first NMOS power tube, the drain terminal of the first PMOS control tube and the anode terminal of the first diode, C2Q is the sum of parasitic capacitances at the drain end of the second NMOS power tube, the drain end of the second PMOS control tube and the anode end of the second diode1Is L1C1Quality factor, Q, of the resonant tank2Is L2C2Quality factor of the resonant tank, VinFor input voltage, Vth1Is the turn-on voltage of the first diode, Vth2Is the turn-on voltage of the second diode.
CN201910364378.2A 2019-04-30 2019-04-30 DCDC conversion circuit for starting double-output at ultralow voltage and implementation method thereof Active CN110098832B (en)

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CN112564469B (en) * 2019-09-25 2022-05-20 圣邦微电子（北京）股份有限公司 Switch converter and low-voltage starting circuit thereof

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