CN117111859B - Data writing method, device and equipment - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F1/24—Resetting means
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The application discloses a data writing method, a device and equipment, and relates to the technical field of electronics, wherein the method comprises the following steps: the shift register sets a data bit width threshold and a counter threshold according to configuration information, the bit width of the shift register is the same as that of the FIFO memory, and the configuration information is determined based on the bit width of the FIFO memory; when the shift register receives data to be written, the data bit width of which is the data bit width threshold value, the shift register increases the value of a counter in the shift register, and the value increased by the counter is the same each time; when the value of the counter is equal to the counter threshold value, the shift register stops data receiving and writes the received data to be written into the FIFO memory; thereby improving the storage space utilization of the FIFO memory.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a data writing method, device, and equipment.
Background
First-in first-out (First Input First Output, FIFO) memory is a data buffer used for data transmission and interface matching, and is currently widely used in various digital systems. The bit width of the existing FIFO memory is usually fixed, and needs to be strictly matched with the bit widths of the interfaces of the source and the receiving terminals, so that the problem of waste of storage space exists in the application process, and as the complexity of the system increases, the data bit widths between different modules and interfaces may not be consistent, so that the storage space of the FIFO memory cannot be fully utilized.
The phenomenon that the memory space of the FIFO memory is not fully utilized is particularly serious in a field programmable gate array (Field Programmable Gate Array, FPGA) chip with a smaller scale, because the memory resource in the FPGA chip is very precious, and how to improve the memory space utilization of the FIFO memory becomes a problem to be solved.
Disclosure of Invention
In view of the foregoing, it is a primary object of the present application to provide a data writing method, apparatus and device, which aim to improve the storage space utilization efficiency of FIFO memories.
The first aspect of the present application provides a data writing method, which includes:
the shift register sets a data bit width threshold and a counter threshold according to configuration information, the bit width of the shift register is the same as that of the FIFO memory, and the configuration information is determined according to the bit width of the FIFO memory;
when the shift register receives data to be written, the data bit width of which is the data bit width threshold value, the shift register increases the value of a counter in the shift register, and the value increased by the counter is the same each time;
when the value of the counter is equal to the counter threshold value, the shift register stops data reception and writes the received data to be written into the FIFO memory.
In some implementations of the first aspect of the present application, after writing the received data to be written to the FIFO memory, the method further includes:
the shift register is reset so that the shift register waits for receiving new data to be written with the data bit width being the data bit width threshold value, and when the value of the counter after reset is equal to the counter threshold value, the received new data to be written is written into the FIFO memory.
In some implementations of the first aspect of the present application, writing the received data to be written to the FIFO memory includes:
the shift register generates a write enable signal and transmits the write enable signal to the FIFO memory so that the FIFO memory opens a write port of the FIFO memory;
the shift register writes the received data to be written into the FIFO memory in parallel through the write port.
In some implementations of the first aspect of the present application, the configuration information includes: data frame length information, data frame length unit information, counter threshold information, write enable function enable information, configuration information flag bit information.
In some implementations of the first aspect of the present application, setting the data bit width threshold and the counter threshold according to the configuration information includes:
the shift register sets a data bit width threshold according to the data frame length information and the data frame length unit information;
the shift register sets a counter threshold according to the counter threshold information.
In some implementations of the first aspect of the present application, the bit width of the FIFO memory is equal to the product of the data bit width threshold and the counter threshold.
In some implementations of the first aspect of the present application, the shift register includes at least one of the following states: idle state, write state, full state, enable state, and reset state, the state of the shift register is switched by the state machine.
In some implementations of the first aspect of the present application, an idle state is used to indicate that the shift register waits to receive data to be written;
a writing state for indicating the shift register to receive the data to be written;
a full state for instructing the shift register to stop data reception;
an enable state for instructing the shift register to write the received data to be written into the FIFO memory;
and a reset state for indicating a shift register reset.
A second aspect of the present application provides a data writing device, the data writing device belonging to a shift register, the data writing device comprising:
the configuration module is used for setting a data bit width threshold value and a counter threshold value according to configuration information, the bit width of the shift register is the same as that of the FIFO memory, and the configuration information is determined according to the bit width of the FIFO memory;
the counting module is used for increasing the value of a counter in the shift register when the data bit width is received and the data to be written is the data bit width threshold value, and the value increased by the counter is the same each time;
and the writing module is used for stopping data receiving when the value of the counter is equal to the counter threshold value and writing the received data to be written into the FIFO memory.
A third aspect of the present application provides a data writing apparatus, characterized in that the apparatus comprises: comprising a memory and a processor for executing a program stored in the memory, running a data writing method as provided in the first aspect of the present application.
The technical scheme provided by the application has the following beneficial effects:
in the application, a data bit width threshold value and a counter threshold value of a shift register are firstly set based on the bit width of a FIFO memory, and the bit width of the shift register is the same as that of the FIFO memory; then, the value of the counter of the shift register is increased when the shift register receives the data to be written with the data bit width as the data bit width threshold value, and the value of each increase is the same; finally, when the value of the counter is equal to the counter threshold value, the data to be written in the shift register is written into the FIFO memory, and the writing is performed each time when the counter threshold value is reached, so that the utilization efficiency of the FIFO memory space is improved.
Drawings
FIG. 1 is a schematic diagram of conventional FIFO mismatch with data according to an embodiment of the present application;
fig. 2 is a flow chart of a data writing method according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating the working principle of a shift register according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of an overall solution provided by an embodiment of the present application;
FIG. 5 is a flowchart illustrating another data writing method according to an embodiment of the present disclosure;
FIG. 6 is a state switching diagram of a shift register according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a data writing device according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a data writing device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims of this application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described above, the conventional FIFO memory has a problem of low utilization of memory space resources, as shown in fig. 1, in which the bit width of the conventional FIFO memory is generally fixed to 32 bits, and if the bit width of data actually written into a data register or BUFFER (TX BUFFER) for temporarily storing data to be written into the FIFO memory is not considered, the problem of memory space waste is caused. For example, FIFO memories have a bit width of 32 bits, while TX BUFFER data has a bit width of only 8 bits. In this case, each time 8 bits of data are written to the FIFO memory, the depth count of the FIFO is incremented by 1, but the FIFO memory of 32 bits width is not filled. If the counter threshold of the FIFO memory is set to 4, when writing 4 times 8-bit data into the FIFO memory, the central processing unit (Central Processing Unit, CPU) or the direct memory access controller (Direct Memory Access, DMA) is triggered to perform data reading, but the FIFO memory does not fully utilize the memory space and only fills 4 bytes, thereby resulting in inefficient use and waste of FIFO memory resources.
In view of the above, referring to fig. 2, the present application provides a data writing method for improving the storage space utilization efficiency of the FIFO memory, which specifically includes the following steps:
s201: the shift register sets a data bit width threshold and a counter threshold according to configuration information, the bit width of the shift register is the same as that of the FIFO memory, and the configuration information is determined according to the bit width of the FIFO memory.
In the embodiment of the application, the shift register is a device based on a trigger, which works under a plurality of same time pulses, data is input into the shift register in a parallel or serial mode, then each time pulse is sequentially shifted by one bit and output at an output end, and the shift register can be used for collecting and packaging data with different bit widths; FIFO memory refers to a first-in first-out data buffer in which the first-in data is shifted out first; bit width refers to the number of binary bits transmitted and stored in digital circuitry, e.g., 8 bits wide indicates that 8 bits of binary data can be transmitted or stored, 32 bits wide indicates that 32 bits of binary data can be transmitted or stored, and in addition, the bit width is typically fixed, representing the number of binary bits that can be simultaneously stored and transmitted. It should be noted that, the bit width of the shift register is equal to the bit width of the FIFO memory, for example, if the bit width of the FIFO memory is 32 bits, the bit width of the shift register should also be 32 bits. This ensures that the data in the shift register can be written completely into the FIFO memory without data loss or overflow.
The data bit width threshold value refers to how many bits of data to be written are received by the shift register each time, the counter threshold value refers to how much time the value of the counter of the shift register reaches, the data in the shift register is written into the FIFO memory, and the configuration information may refer to information for specifying the operating parameters of the shift register.
The purpose of S201 is to implement dynamic configuration of the shift register, so that the shift register can perform adaptive data collection and packing according to different data bit widths.
In some implementations of the embodiments of the present application, the configuration information specifically includes: data frame length information, data frame length unit information, counter threshold information, write enable function enable information, configuration information flag bit information.
The data frame length information is used for indicating the Bit value of the data written into the shift register each time, the data frame length unit information is used for identifying the unit of the Bit value of the data written into the shift register each time, such as Byte and Bit, and it is noted that the minimum unit written into or shifted into the shift register is 1Byte, and since 1 byte=8 Bit, when the data frame length unit is Byte, the data frame length is 1 or an integral multiple of 1 correspondingly; when the data frame length unit is Bit, the data frame length is 8 or an integer multiple of 8. The counter threshold information is used to indicate how much the value of the counter of the shift register reaches to perform data writing. The write enable function enable information is used to indicate whether or not to enable the write enable function of the shift register, and the write enable function refers to generating a write enable signal when a condition for performing data writing is satisfied in the shift register, and writing data in the shift register into the FIFO memory. For example, if the shift register is instructed to enable the write enable function, the bit is 1; if the shift register is indicated not to enable the write enable function, the bit is 0. The configuration information flag bit information is used for indicating that the information received by the current shift register is configuration information.
In some implementations of the embodiments of the present application, setting the data bit width threshold and the counter threshold according to the configuration information specifically includes: the shift register sets a data bit width threshold according to the data frame length information and the data frame length unit information; the shift register sets a counter threshold according to the counter threshold information. Further described herein in connection with the examples, assume that some of the configuration information is as follows: the data frame length information is 1, the data frame length unit is Byte, the counter threshold is 4, and therefore the data bit width threshold set by the shift register is 1Byte, and the counter threshold is 4.
It should be noted that, the configuration information is determined based on the bit width of the FIFO memory, and the purpose of the configuration information is to make the most of the storage space of the FIFO memory, preferably, setting the data bit width threshold and the counter threshold is performed following the principle that the bit width of the FIFO memory is equal to the product of the data bit width threshold and the counter threshold. For example, assuming that the FIFO stores 32 bits wide, a data bit wide threshold of 8 bits and a counter threshold of 4 may be set; a data bit width threshold of 16 may also be set, with a counter threshold of 2.
S202: when the shift register receives the data to be written, the data bit width of which is the data bit width threshold value, the shift register increases the value of a counter in the shift register, and the value of each increase of the counter is the same.
In the embodiment of the present application, the data to be written specifically refers to a binary data stream to be written into the FIFO memory. When the shift register receives the data to be written which accords with the data bit width threshold value, the data to be written is sequentially written into the shift register and is shifted backwards, and meanwhile, the value of the counter is increased for counting the writing times. Here, the whole multiple of 1 or 1 may be added each time, which does not affect the implementation of the embodiments of the present application, and only needs to ensure that the same value is added each time. It will be appreciated that the selection of each increment will affect the counting mode of the counter and the setting of the counter threshold, and it is assumed here that the shift register performs the subsequent operation after each 4 times of data to be written, the initial value of the counter is 0, the counter threshold is 4 when the value of the counter is incremented by 1, and the counter threshold is 8 when the value of the counter is incremented by 2.
In this embodiment of the present application, as shown in fig. 3, when the shift register receives the first 8 bits of data to be written, the first 8 bits of data are written into the shift register and shifted backward, and meanwhile, the value of the counter is increased by 1, and the counter is 1 at this time; when the shift register receives the second 8-bit data to be written, writing the second 8-bit data into the shift register and shifting the second 8-bit data backwards, and adding 1 to the value of the counter, wherein the counter is 2; when the shift register receives the third 8-bit data to be written, writing the third 8-bit data into the shift register and shifting the third 8-bit data backwards, and adding 1 to the value of the counter, wherein the counter is 3; and so on until the value of the counter reaches the counter threshold.
S203: when the value of the counter is equal to the counter threshold value, the shift register stops data reception and writes the received data to be written into the FIFO memory.
In an embodiment of the present application, stopping data reception specifically means that the data to be written is not received any more until the storing of the received data to be written in the FIFO memory is completed. Before writing to the FIFO memory, the shift register packs the received data to be written with a plurality of data widths corresponding to the data width threshold values together to obtain larger data to be written, for example, packs 4 8-bit data to be written into one 32-bit data to be written.
In the application, the process of writing the received data to be written into the FIFO memory is performed in a parallel writing manner, for example, referring to fig. 4, a RAM is used to represent a data source, a shift register is added between the data source and the FIFO memory to improve the storage space utilization of the FIFO memory, and if the shift register receives 4 8 bits of data to be written from the RAM when the value of the counter is equal to the counter threshold value, the received data can be packed, and one 32 bits of data to be written into the FIFO memory in parallel, thereby completing one round of data writing, and the storage space of the FIFO memory is fully utilized.
In the flow shown in fig. 2, the data bit width threshold and the counter threshold of the shift register are set based on the bit width of the FIFO memory, and the bit width of the shift register is the same as the bit width of the FIFO memory, so that dynamic adjustment of the shift register is realized, and the shift register is adapted to the bit width of the FIFO register; and finally, when the value of the counter is equal to the counter threshold value, the data to be written in the shift register is written into the FIFO memory. Therefore, the width of data received by the shift register can be adjusted based on configuration information determined by the bit width of the FIFO memory, so that the bit width of the FIFO is adaptively matched, the utilization efficiency of the storage space of the FIFO memory is improved, and forward gain can be provided for optimizing the resource occupation and performance improvement of a digital system.
Referring to fig. 5, the embodiment of the present application further provides a data writing method, which further introduces a writing manner of data to be written and adds a step of resetting the shift memory on the basis of the flow shown in fig. 2, and specifically includes the following steps:
s501: the shift register sets a data bit width threshold and a counter threshold according to configuration information, the bit width of the shift register is the same as that of the FIFO memory, and the configuration information is determined according to the bit width of the FIFO memory.
In the embodiment of the present application, the specific implementation manner of S501 is the same as S201, and the description thereof is omitted herein.
S502: when the shift register receives the data to be written, the data bit width of which is the data bit width threshold value, the shift register increases the value of a counter in the shift register, and the value of each increase of the counter is the same.
In the embodiment of the present application, the specific implementation manner of S502 is the same as S202, and the description thereof is omitted herein.
S503: when the value of the counter is equal to the counter threshold, the shift register stops data reception.
In the embodiment of the present application, the specific implementation of S503 is similar to S203, and is not described herein.
S504: the shift register generates a write enable signal and transmits the write enable signal to the FIFO memory to cause the FIFO memory to open a write port of the FIFO memory.
The write port refers to a port in the FIFO memory for receiving data, and can be understood as an input port of the FIFO memory; when the FIFO memory receives the write enable signal from the shift register, the write port is opened according to the signal. When the write port is open, this means that the shift register is allowed to write the data to be written into the FIFO memory; when the write port is closed, this means that the shift register is inhibited from writing data to be written into the FIFO memory.
The write enable signal is a control signal sent to the FIFO memory for controlling the closing and opening of the write port to indicate when the FIFO memory can write data. The principle of operation of the write enable signal is as follows: after the data to be written in the shift register is packaged, a write enable signal is sent to the control logic of the FIFO memory; after receiving the high level of the write enable signal, the FIFO memory opens a write port, allows the data of the shift register to shift and write into the FIFO memory; after the data is written, the write enable signal is pulled low, and the FIFO memory closes the write port.
S505: the shift register writes the received data to be written into the FIFO memory in parallel through the write port.
Here, the shift register completes one round of writing of data to be written into the FIFO memory through the write port of the FIFO memory.
S506: the shift register is reset so that the shift register waits for receiving new data to be written with the data bit width being the data bit width threshold value, and when the value of the counter after reset is equal to the counter threshold value, the received new data to be written is written into the FIFO memory.
In this embodiment of the present application, after the shift register completes one operation of writing the data to be written in the shift register into the FIFO memory, the shift register resets to empty the data to be written that the shift register has received, and at the same time, the value of the counter is restored to the initial value, or the value of the counter is cleared. To wait for receiving a new round of data to be written, i.e. return to step S302, and when the value of the reset counter is equal to the counter threshold, steps S303 to S305 are performed to complete the writing of the new round of data to be written into the FIFO memory.
In some implementations of embodiments of the present application, the shift register includes at least one of an idle state, a write state, a full state, an enable state, and a reset state, the state of the shift register being switched by a state machine.
A state machine, or state machine of a shift register, refers to control logic added to the shift register for controlling the switching between states of the shift register, which may be implemented by logic circuits. Referring to fig. 6, fig. 6 is a state switching diagram of a shift register provided in an embodiment of the present application, where each state is used for:
an idle state for indicating that the shift register is waiting to receive data to be written; the idle state may also be referred to as an initial state of the shift register, when the state machine switches the shift register to the idle state, the shift register waits to receive data to be written, and when the shift register receives data to be written, the state machine switches the shift register to the writing state.
And the writing state is used for indicating the shift register to receive the data to be written. When the state machine switches the shift register to the writing state, the shift register starts to receive data to be written, and each time the shift register receives the data to be written with the data width being the data width threshold value, the data to be written is shifted into the register and is shifted backwards. When the value of the counter is equal to the counter threshold value, it means that the shift register can write the received data to be written to the FIFO memory. At this time, the state machine switches the shift register to the full state.
And a full state for instructing the shift register to stop data reception. When the state machine switches the shift register to the full state, the shift register no longer receives new data to be written, and then the state machine switches the shift register to the enabled state.
And an enable state for instructing the shift register to write the received data to be written into the FIFO memory. When the shift register is switched into an enabling state by the state machine, the shift register generates an enabling signal and transmits the enabling signal to the FIFO memory so that the FIFO memory opens a writing port, after the FIFO memory opens the writing port, data to be written in the shift register are packed and written into the FIFO memory in parallel, and then the shift register is switched into a reset state by the state machine.
And a reset state for indicating a shift register reset. When the state machine switches the shift register to a reset state, the shift register is reset, all modules in the shift register are initialized, and then the state machine switches the shift register to an idle state.
In the flow shown in fig. 5, write control to the FIFO memory is achieved by generating and transmitting a write enable signal to cause the FIFO memory to open its write port; by parallel writing, the data to be written received by the shift register can be converted and adapted to the data with the bit width of the FIFO memory, so that the space of the FIFO memory is effectively utilized, the waste or mismatch of the data is avoided, and the utilization efficiency of the storage space of the FIFO memory is improved. In addition, the data writing efficiency can be improved by parallel writing. And initializing a shift register through resetting to realize the collection and packaging of the data to be written in the next round. By defining different states and using a state machine to control transitions between states of the shift register, precise control of various stages in the data writing process is achieved.
Referring to fig. 7, the embodiment of the present application further provides a data writing device, where the input writing device belongs to a shift register, and the data writing device includes the following modules:
a configuration module 701, configured to set a data bit width threshold and a counter threshold according to configuration information, where the bit width of the shift register is the same as the bit width of the FIFO memory, and the configuration information is determined according to the bit width of the FIFO memory;
a technical module 702, configured to, when data to be written with a data bit width being a data bit width threshold is received, increment a value of a counter in the shift register, where the value incremented by the counter is the same each time;
the writing module 703 is configured to stop data reception when the value of the counter is equal to the counter threshold value, and write the received data to be written into the FIFO memory.
In some implementations of the present application, the apparatus further includes:
and the reset module is used for resetting to enable the shift register to wait for receiving new data to be written of which the data bit width is equal to the data bit width threshold value, and writing the received new data to be written into the FIFO memory when the value of the reset counter is equal to the counter threshold value.
In some implementations of embodiments of the present application, writing received data to be written to FIFO memory includes:
generating a write enable signal and transmitting the write enable signal to the FIFO memory to enable the FIFO memory to open a write port of the FIFO memory;
and writing the received data to be written into the FIFO memory in parallel through the write port.
In some implementations of embodiments of the present application, the configuration information includes: data frame length information, data frame length unit information, counter threshold information, write enable function enable information, configuration information flag bit information.
In some implementations of embodiments of the present application, setting the data bit width threshold and the counter threshold according to the configuration information includes:
setting a data bit width threshold according to the data frame length information and the data frame length unit information;
the shift register sets a counter threshold according to the counter threshold information.
In some implementations of embodiments of the present application, the bit width of the FIFO memory is equal to the product of the data bit width threshold and the counter threshold.
In some implementations of embodiments of the present application, the state of the shift register includes: idle state, write state, full state, enable state, and reset state, the state of the shift register is switched by the state machine.
In some implementations of embodiments of the present application, an idle state is used to indicate that a shift register is waiting to receive data to be written;
a writing state for indicating the shift register to receive the data to be written;
a full state for instructing the shift register to stop data reception;
an enable state for instructing the shift register to write the received data to be written into the FIFO memory;
and a reset state for indicating a shift register reset.
As shown in fig. 8, an embodiment of the present application further provides a data writing device, including: a memory 801 and a processor 802;
wherein the memory 801 is used for storing programs;
the processor 802 is configured to execute a program in a memory to implement a data writing method as described above with reference to fig. 2 or 5.
Finally, it should also be noted that in the embodiments of the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A method of writing data, the method comprising:
the shift register sets a data bit width threshold and a counter threshold according to configuration information, wherein the bit width of the shift register is the same as that of a first-in first-out FIFO memory, the configuration information is determined according to the bit width of the FIFO memory, and the bit width of the FIFO memory is equal to the product of the data bit width threshold and the counter threshold;
when the shift register receives data to be written, wherein the data bit width of the data bit width is the data bit width threshold value, the shift register increases the value of a counter in the shift register, and the value of each increase of the counter is the same;
when the value of the counter is equal to the counter threshold value, the shift register stops data receiving and writes the received data to be written into the FIFO memory;
resetting the shift register to enable the shift register to empty the received data to be written, waiting for receiving new data to be written with the data bit width being the data bit width threshold value, and writing the received new data to be written into the FIFO memory when the value of the reset counter is equal to the counter threshold value;
the shift register includes at least one of the following states: the state of the shift register is switched through a state machine, and the idle state is used for indicating the shift register to wait for receiving the data to be written; the writing state is used for indicating the shift register to receive the data to be written; the full state is used for indicating the shift register to stop data receiving; the enabling state is used for indicating the shift register to write the received data to be written into the FIFO memory; and the reset state is used for indicating the reset of the shift register.
2. The method of claim 1, wherein the writing the received data to be written to the FIFO memory comprises:
the shift register generates a write enable signal and transmits the write enable signal to the FIFO memory so that the FIFO memory opens a write port of the FIFO memory;
and the shift register writes the received data to be written into the FIFO memory in parallel through the write port.
3. The method of claim 1, wherein the configuration information comprises: data frame length information, data frame length unit information, counter threshold information, write enable function enable information, configuration information flag bit information.
4. A method according to claim 3, wherein said setting a data bit width threshold and a counter threshold according to said configuration information comprises:
the shift register sets the data bit width threshold according to the data frame length information and the data frame length unit information;
the shift register sets the counter threshold according to the counter threshold information.
5. A data writing device, wherein the data writing device belongs to a shift register, the data writing device comprising:
the configuration module is used for setting a data bit width threshold value and a counter threshold value according to configuration information, the bit width of the shift register is the same as that of the FIFO memory, the configuration information is determined according to the bit width of the FIFO memory, and the bit width of the FIFO memory is equal to the product of the data bit width threshold value and the counter threshold value;
the counting module is used for increasing the value of a counter in the shift register when receiving data to be written, the data bit width of which is the data bit width threshold value, and the value of each increment of the counter is the same;
a writing module, configured to stop data reception and write the received data to be written into the FIFO memory when the value of the counter is equal to the counter threshold;
the reset module is used for resetting the shift register so that the shift register can empty the received data to be written, wait for receiving new data to be written with the data bit width being the data bit width threshold value, and write the received new data to be written into the FIFO memory when the value of the reset counter is equal to the counter threshold value;
the shift register includes at least one of the following states: the state of the shift register is switched through a state machine, and the idle state is used for indicating the shift register to wait for receiving the data to be written; the writing state is used for indicating the shift register to receive the data to be written; the full state is used for indicating the shift register to stop data receiving; the enabling state is used for indicating the shift register to write the received data to be written into the FIFO memory; and the reset state is used for indicating the reset of the shift register.
6. A data writing device, the device comprising: comprising a memory and a processor for executing a program stored in the memory, running the data writing method according to any one of claims 1 to 4.
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