CN108599908A

CN108599908A - Communication system and semiconductor equipment

Info

Publication number: CN108599908A
Application number: CN201810180487.4A
Authority: CN
Inventors: 真锅安武
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2017-03-07
Filing date: 2018-03-05
Publication date: 2018-09-28
Anticipated expiration: 2038-03-05
Also published as: US20180262896A1; JP2018148438A; CN108599908B; US10575161B2

Abstract

This application involves communication systems and semiconductor equipment.A kind of communication system is provided, emergency notice can be sent with short delay without waiting for currently transmitted completion or retransmission frame until frame.Communication system includes meeting the frame of ethernet standard for generating and sending frames to the sending device of device external and for the receiving device of receiving frame.Emergency notice data are inserted into frame by sending device with scheduled data break.Receiving device obtains emergency notice data with data break identical with sending device from the frame received, and obtains remaining data as the data (normal data) in the Header Area and payload region of the frame.

Description

Communication system and semiconductor equipment

Cross reference to related applications

It is whole by quoting in the disclosure for the Japanese patent application No.2017-042412 that on March 7th, 2017 submits It is incorporated herein, including specification, drawings and abstract.

Technical field

The present invention relates to communication systems and semiconductor equipment.For example, the present invention relates to meet Ethernet for utilizing The technology of the frame publication emergency notice of (Ethernet, registered trademark) standard.

Background technology

For example, the technology described in Japanese Unexamined Patent Application Publication No.2006-67038 reduces the hair of urgent frame Delay in sending.If encountering urgent frame during the transmission of normal frame, currently transmitted normal frame be interrupted and discarded with Send urgent frame.

Invention content

For example, if in ethernet networks, need to send emergency notice when sending frame, then usually require to wait for until The currently transmitted completion of frame.Therefore, when emergency notice to be sent, it may occur that significant delay.Meanwhile it is special using Japanese Unexamined Technology described in the open No.2006-67038 of profit application makes it possible to send emergency notice with extremely short delay.However, this Kind technology so that the normal frame being dropped due to urgent frame must be retransmitted.Therefore, normal frame may for example increase Delay in the case of sent.

In view of the foregoing, it is contemplated that the embodiment described below.From the following description and drawings, other problems and novelty are special Sign will become obvious.

According to an aspect of the invention, there is provided a kind of communication system including sending device and receiving device.It sends Equipment generates the frame for meeting ethernet standard, and the frame of generation is sent to the outside of equipment.Receiving device receives the frame.It sends First data are inserted into frame by equipment with scheduled data break.Receiving device with data break identical with sending device from The first data are obtained in the frame received, and obtain remaining data as the number in the Header Area and payload region of frame According to.

Aforementioned aspect of the present invention allows to send emergency notice with short delay, current until frame without waiting for It is sent completely or retransmits frame.

Description of the drawings

Fig. 1 is the schematic diagram of the example arrangement for the major part for showing communication system according to a first embodiment of the present invention；

Fig. 2 is the flow chart of the summary for the exemplary operations for showing communication system shown in FIG. 1；

Fig. 3 is the circuit block of the example arrangement for the major part for showing the transmission circuit in semiconductor equipment shown in FIG. 1 Figure；

Fig. 4 is the oscillogram for the exemplary operations for showing transmission circuit shown in Fig. 3；

Fig. 5 is the circuit block diagram for the example arrangement for showing Data Synthesis processing circuit shown in Fig. 3；

Fig. 6 is the oscillogram for the exemplary operation for showing Data Synthesis processing circuit shown in fig. 5；

Fig. 7 is the circuit block of the example arrangement for the major part for showing the receiving circuit in semiconductor equipment shown in FIG. 1 Figure；

Fig. 8 is the oscillogram for the exemplary operations for showing receiving circuit shown in Fig. 7；

Fig. 9 is the circuit block diagram for the example arrangement for showing data allocation circuit shown in Fig. 7；

Figure 10 is the oscillogram for the exemplary operations for showing data allocation circuit shown in Fig. 9；

Figure 11 is the schematic diagram of the example arrangement for the major part for showing communication system according to a second embodiment of the present invention；

Figure 12 is the circuit block diagram for the example arrangement for showing the Data Synthesis processing circuit in Fig. 3, Data Synthesis processing Circuit is included in semiconductor equipment according to a third embodiment of the present invention；

Figure 13 is the oscillogram for showing the exemplary operations of Data Synthesis processing circuit shown in Figure 12；

Figure 14 is the circuit block diagram of the example arrangement for the major part for showing the transmission circuit in Fig. 1, the transmission circuit quilt It is included in semiconductor equipment according to a fourth embodiment of the present invention；

Figure 15 is the circuit block diagram for showing the example arrangement of Data Synthesis processing circuit shown in Figure 14；

Figure 16 is to show that data shown in Figure 14 divide the circuit diagram of the example arrangement of circuit；

Figure 17 is the oscillogram for the exemplary operations for showing transmission circuit shown in Figure 14；

Figure 18 is the oscillogram for the exemplary operations for showing Data Synthesis processing circuit shown in figure 15；

Figure 19 is the circuit block diagram of the example arrangement for the major part for showing the receiving circuit in Fig. 1, the receiving circuit quilt It is included in semiconductor equipment according to a fifth embodiment of the present invention；

Figure 20 is the circuit block diagram for the example arrangement for showing data allocation circuit shown in Figure 19；

Figure 21 is the oscillogram for the exemplary operations for showing receiving circuit shown in Figure 19；

Figure 22 is the circuit block diagram of the example arrangement for the major part for showing the transmission circuit in Fig. 1, the transmission circuit quilt It is included in semiconductor equipment according to a sixth embodiment of the present invention；

Figure 23 A are the circuit diagrams for showing the example arrangement of bit termination power shown in Figure 22；

Figure 23 B are the figures for the specific example output and input for showing bit termination power shown in Figure 23 A；

Figure 24 is the oscillogram for the exemplary operations for showing transmission circuit shown in Figure 22；

Figure 25 is the circuit block diagram of the example arrangement for the major part for showing the receiving circuit in Fig. 1, the receiving circuit quilt It is included in semiconductor equipment according to a sixth embodiment of the present invention；

Figure 26 is to show that bit shown in Figure 25 divides the circuit diagram of the example arrangement of circuit；

Figure 27 is the circuit block diagram for the example arrangement for showing data allocation circuit shown in Figure 25；

Figure 28 is the oscillogram for the exemplary operations for showing receiving circuit shown in Figure 25；

Figure 29 is to show to determine spaced exemplary method in communication system according to a seventh embodiment of the present invention Figure；And

Figure 30 is the schematic diagram for the emergency notice sending method for being shown as the comparative example of the present invention.

Specific implementation mode

In the following description of the embodiments, for convenience's sake, when necessary, description of the invention will be divided into multiple Part or embodiment, but unless stated otherwise, otherwise they are not unrelated each other, are in following relationship：One portion Point or embodiment be, for example, modification, detailed description or supplementary explanation to some or all of another part or embodiment.In addition, In embodiment described below, when referring to quantity (including quantity, numerical value, amount, range etc.) of element, the quantity of element is not It is limited to specific quantity, unless for example special statement or being obviously limited to specific quantity in principle.More than or less than certain amount of number Amount is also suitable.

In addition, in embodiment described below, it is obvious that unless for example illustrating or apparent in principle Indispensable, otherwise component (including such as element step) is not always essential.Similarly, the implementation being described below In example, for example, when the shape for referring to component and the position relationship between them, for example, otherwise including base unless stated otherwise Approximate or similar shape in sheet, unless illustrating or being obviously left out in principle.Above-mentioned numerical value and range It is also the same.

In addition, the circuit element for including in each functional block of the present embodiment is not particularly limited, but can use known The integrated circuit technique etc. of CMOS transistor (complementary type MOS transistor) be formed in the semiconductor substrate of monocrystalline silicon etc..

Detailed description of the present invention embodiment with reference to the drawings.It is similar in all attached drawings of description embodiment Element is usually indicated by the same numbers.These similar elements will not be described repeatedly.

First embodiment

<<Emergency notice sending method (comparative example) and its problem>>

First, the method for comparative example being described before explaining based on the method for embodiment.Figure 30 is to be shown as this The schematic diagram of the emergency notice sending method of the comparative example of invention.When needing to send emergency notice, usually currently transmitted Normal frame FRN be fully transmitted the urgent frame FRE for sending include urgent notices information later, such as 1 institute of comparative example of Figure 30 Show.However, in this case, due to needing to wait for being sent completely until normal frame FRN, so it is difficult to very short delay Send emergency notice.In Vehicular communication system, for example, needing sending the same of the image captured by camera in some cases When send emergency notice, so that the fault message about control device is for example presented.In the high system of such security requirement In, emergency notice is for example sent to scheduled error handle component by special requirement as early as possible.

In view of the foregoing, it may be considered that method shown in the comparative example 2 of Figure 30.This method is lost before being sent completely Currently transmitted normal frame FRN is abandoned, and sends urgent frame FRE, then retransmits the normal frame FRN of discarding.But this In the case of, communication efficiency may reduce.More specifically, the retransmission of normal frame FRN may lead to such as normal frame FRN Transmission delay increase and bandwidth cost increase.In addition, when use a urgent frame FRE transmission by low volume data (such as Several bytes) formed emergency notice when, need execute filling to meet the requirement of minimum frame size (64 byte).As a result, example Such as, bandwidth cost may increase due to filling.

<<Communication system is summarized>>

Fig. 1 is the schematic diagram of the example arrangement for the major part for showing communication system according to a first embodiment of the present invention. Communication system shown in FIG. 1 include two semiconductor equipment (semiconductor chip) DEV1, DEV2, PHY (physical layer) circuit PHY1, PHY2 and network N W1.PHY circuit PHY1, PHY2 is respectively coupled to semiconductor equipment DEV1, DEV2.Network N W1 is by PHY circuit PHY, PH2 are coupled.Network N W1 is the cable network for example formed by Ethernet cable such as and IEEE802.11 Compatible wireless lan network.

Semiconductor equipment DEV1, DEV2 include respectively CPU (central processing unit), memory MEM, interrupt control circuit INTC, telecommunication circuit CC and bus interface BSIF for telecommunication circuit CC.CPU, memory MEM and bus interface BSIF with it is total Line BS couplings.

Telecommunication circuit CC includes transmission circuit TXC and receiving circuit RXC.Transmission circuit TXC generations meet ethernet standard Frame, and the frame of generation is sent to the outside of equipment.External receiving frames of the receiving circuit RXC from equipment.In this example, lead to Believe that circuit CC handles MAC (media access control) layer, and PHY circuit PHY1, PHY2 by handling PHY (physics) layer is sent And receiving frame.

For example, PHY circuit PHY1, PHY2 includes respectively the electricity for executing conversion between serial signal and parallel signal Road.In general, may include such as meeting the circuit of IEEE 802.3MII (Media Independent Interface) standard or meeting GMII (gigabits Media Independent Interface) standard circuit known circuit.PHY circuit PHY1, PHY2 is usually only formed by semiconductor chip.So And in some cases, PHY circuit PHY1, PHY2 can be incorporated into telecommunication circuit CC.

CPU (and memory MEM) is generation source or the reception destination of normal data NDT.Interrupt control circuit INTC is The generation source of emergency notice data EDT receives destination.Emergency notice data EDT is in emergency (or priority) higher than just Regular data NDT.In this example, telecommunication circuit CC sends and receives normal data NDT by bus interface BSIF, and directly transmits With reception emergency notice data EDT.

In general, emergency notice data EDT is usually sent and received during interrupt processing.Therefore, interrupt control circuit INTC is used as occurring source or receives destination.However, the generation source or reception destination of emergency notice data EDT can be according to need Change.In addition, the generation source or reception destination of normal data NDT can also change as needed.That is, communication electricity Road CC is configured such that at least normal data NDT and emergency notice data EDT are sent in various in which can be distinguished It portion's circuit and is received with being distinguished from various internal circuits.

Fig. 2 is the flow chart of the summary for the exemplary operations for showing communication system shown in FIG. 1.Here, suppose that semiconductor is set Standby DEV1 is the transmission source (i.e. sending device) of frame, and semiconductor equipment DEV2 is that (i.e. reception is set for the reception destination of the frame It is standby).With reference to figure 2, first, semiconductor equipment DEV1 generates normal data NDT (step S101) in memory MEM.Normal number It can for example be generated by CPU according to NDT, such as partly generated by DMAC (DMA controller).Normal number Include according to NDT such as frame Header Area and payload region in data.

After the generation for completing normal data NDT, setting registers of the CPU to bus interface BSIF and telecommunication circuit CC Various setting operations are executed, and bus interface BSIF (steps will be published to for the transmission of normal data NDT request SR S102).Bus interface BSIF is obtained normal in response to sending request SR according to the content of setting register from memory MEM Data NDT, and the normal data NDT of acquisition is output to transmission circuit TXC (step S103).

Meanwhile independently of the processing in step S101 to S103, interrupt control circuit INTC generates emergency notice data EDT And the emergency notice data EDT of generation is exported to transmission circuit TXC (step S111 and S112).Here, transmission circuit TXC lifes At the frame (frame data DT) for including the normal data NDT inputted in step s 103, and during the process with scheduled number The emergency notice data EDT inputted in step S112 is inserted into frame (frame data DT) (step S100) according to interval.Send electricity Then the emergency notice data EDT frames being periodically inserted into are sent to network N W1 (steps by road TXC by PHY circuit PHY1 S100)。

The frame received is sent to semiconductor by network N W1 from transmission circuit TXC receiving frames, and by PHY circuit PHY2 Equipment DEV2 (step S200).Receiving circuit RXC in semiconductor equipment DEV2 receives the frame (frame data DT), and with it is aforementioned The identical data breaks of transmission circuit TXC in semiconductor equipment DEV1 obtain emergency notice data EDT from the frame received (step S300).In addition, receiving circuit RXC obtains remaining data as normal data NDT (that is, the Header Area of frame and effective Data in load region) (step S300).

The normal data NDT obtained in step S300 is stored in memory MEM (step by bus interface BSIF S301), then reception notice RN (step S302) is sent out to CPU.In addition, concurrently with the processing in step S301 and S302, The emergency notice data EDT obtained in step S300 is output to interrupt control circuit INTC (step S311 by receiving circuit RXC And S312).

<<The details of the major part of transmission circuit>>

Fig. 3 is the circuit block of the example arrangement for the major part for showing the transmission circuit in semiconductor equipment shown in FIG. 1 Figure.Fig. 4 is the oscillogram for the exemplary operations for showing transmission circuit shown in Fig. 3.Transmission circuit TXC as shown in Figure 3 includes number It is effectively sent according to effective input node NDi1, normal data input node NDi2, emergency notice data input node NDi3, data Node NDt1, frame data sending node NDt2, FIFO (first in first out) buffer FIFO_A1, FIFO_A2 and frame generative circuit FRG_A.Transmission circuit TXC sends frame with tranmitting data register cycle synchronisation, and executes the various processing needed for sending.

Data valid signal DV_Ai is input to the effective input node NDi1 of data, and normal number from bus interface BSIF According to NDT_Ai normal data input node NDi2 is input to from bus interface BSIF.Emergency notice data EDT_Ai is controlled from interruption Circuit I NTC is input to emergency notice data input node NDi3.Normal data NDT_Ai and emergency notice data EDT_Ai have There is the bit width of n-bit (for example, 4 bits or 8 bits).

More specifically, as shown in figure 4, normal data NDT_Ai (that is, in the HD of Header Area and the PLD of payload region In data) normal data input node NDi2 is input into during predetermined effectual time, and in addition to effectual time (blank in Fig. 4) inputs data related with idle state during period.Meanwhile data valid signal DV_Ai is input into number According to effective input node NDi1, data valid signal DV_Ai during effectual time in level"1" and except effectual time with Level "0" is in during the outer period.When the normal data NDT_Ai in memory MEM will be output to transmission circuit TXC, Bus interface BSIF is generated and is exported such data valid signal DV_Ai.

Fifo buffer FIFO_A2 holdings will be stored in the Header Area HD and payload region PLD of frame Normal data NDT_Ai.More specifically, fifo buffer FIFO_A2 has the capacity in the tranmitting data register period of predetermined quantity, and And normal data input node NDi2 (including the normal data NDT_ in effectual time is obtained on each tranmitting data register period Ai the data at).Meanwhile fifo buffer FIFO_A1 has the tranmitting data register week of quantity identical as fifo buffer FIFO_A2 The capacity of phase, and the data valid signal DV_ on each tranmitting data register period at the effective input node NDi1 of acquisition data Ai。

Frame generative circuit FRG_A includes interval setting register SREG_A, Data Synthesis processing circuit DSC_A, data choosing Circuit DSEL_A and error-detecging code counting circuit CRCG are selected, and in each tranmitting data register cycle sequences while determining frame data Delta frame in chronological order.Interval setting register SREG_A keeps the interval of CPU settings for example as shown in Figure 1 that M is arranged.Between It is to determine the value for the data break for being periodically inserted emergency notice data EDT_Ai every setting M.

Data Synthesis processing circuit DSC_A includes the data counter that will be described in later.Data counter is with interval The interval that M (cycle count " M+1 ") is defined is set, cycle count is carried out to tranmitting data register amount of cycles.As shown in figure 4, data are closed It is controlled at countings of the processing circuit DSC_A based on data counter, to select data at each cycle count " M+1 " The selection signal SS_A of circuit DSEL_A is set as level"1".More specifically, Data Synthesis processing circuit DSC_A is controlled System so that selection signal SS_A is arranged in level"1" when the counting of data counter is predetermined value, and works as data counter Counter selection signal SS_A is arranged in level "0" when being the value other than predetermined value.In addition, Data Synthesis processing circuit DSC_A is with the enabled letter of reading with the control of the relationship of selection signal SS_A complementations for fifo buffer FIFO_A1, FIFO_A2 Number REN_A.

When reading enable signal REN_A is in level"1" (that is, selection signal SS_A is in level "0"), FIFO bufferings Device FIFO_A1, FIFO_A2 execute read operation.Due to read operation, fifo buffer FIFO_A1 output data useful signals DV_A2, and fifo buffer FIFO_A2 output normal datas NDT_A2.As a result, as shown in figure 4, reading by being generated The level "0" period of enable signal REN_A makes the effectual time of normal data NDT_A2 and " 1 " of data valid signal DV_A2 Level periods are longer than the effectual time of normal data NDT_Ai and the level"1" period of data valid signal DV_Ai.

When selection signal SS_A is in level "0" (read enable signal REN_A and be in level"1"), data selection electricity Road DSEL_A selects normal data NDT_A2, and when selection signal SS_A (reads enable signal REN_A to be in level"1" Level "0") when data selection circuit DSEL_A selection emergency notice data EDT_Ai.Then, as shown in figure 4, data selection electricity By selected data, alternatively data SDT_A is exported road DSEL_A.

That is, if the counting of data counter is predetermined value, data selection circuit DSEL_A is buffered in FIFO Device FIFO_A1, FIFO_A2 will select data SDT_A to be determined as emergency notice data EDT_Ai in the state of not being read.Phase Instead, if the counting of data counter is the value other than predetermined value, data selection circuit DSEL_A is in fifo buffer Selection data SDT_A is determined as from the normal of fifo buffer FIFO_A2 by FIFO_A1, FIFO_A2 in the state of being read Data NDT_A2.It will be by the data of the frame of final output (DT_Ao) as shown in figure 4, data SDT_A is selected to be used as.

Moreover, as shown in figure 4, Data Synthesis processing circuit DSC_A generates number for the effectual time of selection data SDT_A According to useful signal DV_A3.Error-detecging code counting circuit CRCG is directed to the selection data SDT_A exported from data selection circuit DSEL_A Calculate error-detecging code (or more specifically, CRC (cyclic redundancy check) code).As shown in figure 4, error-detecging code counting circuit CRCG passes through Error-detecging code region FCS is added to the tail end of selection data SDT_A and the value calculated is stored in error-detecging code region FCS Frame data DT_Ao is generated, and frame data DT_Ao is sent from frame data sending node NDt2.In addition, error-detecging code counting circuit CRCG generates data valid signal DV_Ao by the way that data valid signal DV_A3 to be extended to the additive amount of error-detecging code, and from number According to effective sending node NDt1 transmission data useful signals DV_Ao.

Referring now to Fig. 4, interrupt control circuit INTC transmissions shown in FIG. 1 for example indicate to be not present under normal circumstances tight The value A suddenly notified is as emergency notice data EDT_Ai, and the sending value B when emergency notice occurs.Indicating emergency notice Value B is inserted into according to the level"1" period of the selection signal SS_A followed closely in frame.Therefore, it can be sent with short delay urgent Notice.That is, the value based on interval setting M can ensure emergency notice delay time.For example, if with 20 byte intervals It is inserted into 1 byte emergency notice, then the transmission of emergency notice can be that (communication speed is in the delay no more than 20 byte times It is 1.6 microseconds when 100Mbps) start.

Moreover, in the example of fig. 4, when emergency notice data EDT_Ai is inserted into the payload region PLD of frame When, the data in the HD of Header Area are safeguarded as usual.In addition, when calculating error-detecging code for selection data SDT_A, for normal The entire frame that data and emergency notice data coexist determines correct error-detecging code.As these operations as a result, even if for example There is conventional Ethernet switch in network N W1 shown in FIG. 1, the versatility of ethernet communication can also be kept without causing Any specific problem.

<<The details of Data Synthesis processing circuit>>

Fig. 5 is the circuit block diagram for the example arrangement for showing Data Synthesis processing circuit shown in Fig. 3.Fig. 6 is to show Fig. 5 institutes The oscillogram of the exemplary operations of the Data Synthesis processing circuit shown.Data Synthesis processing circuit DSC_A shown in fig. 5 includes header Counter HCT_A, data counter DCT_A, state machine SM_A, data efficiently generate circuit DVG_A and selection signal generates electricity Road SSG_A.

As shown in fig. 6, state machine SM_A is converted between three kinds of different conditions, that is, idle state S_IDLE, header state S_HD and data mode S_DAT.When data valid signal DV_A2 becomes level"1" from level "0", state machine SM_A is from sky Not busy state S_IDLE is converted to header state S_HD.In response to the transformation to header state S_HD, preamble counter HCT_A starts Counting operation, and tranmitting data register amount of cycles " N+1 " is counted based on the known data length of Header Area HD.When header meter When the counting operation of number device HCT_A is completed, state machine SM_A is converted to data mode S_DAT from header state S_HD.

In response to the transformation to data mode S_DAT, data counter DCT_A starts counting up operation, and in terms of by the period Count tranmitting data register amount of cycles to the gap periods that number " M+1 " defines.Selection signal generative circuit SSG_A controlled with Just if being counted as " 0 " in data mode S_DAT and data counter DCT_A, enable signal REN_A will be read and set It is set to level "0", and is controlled and is set as level"1" so that enable signal REN_A will be read in other cases.

In addition, the reverse phase of enable signal REN_A alternatively signal SS_ is read in selection signal generative circuit SSG_A output A.That is, when data counter DCT_A is when being counted as " 0 ", controlled to set selection signal SS_A to " 1 " electricity It is flat, and when it is the value in addition to " 0 " to count, set selection signal SS_A to level "0".When not executing counting operation When, data counter DCT_A outputs set reading enable signal REN_A to level"1" and (set selection signal SS_A to Level "0") value (for example, " M ").

If it is to remove that data valid signal DV_A2, which is in level "0" (condition A) and the counting of data counter DCT_A, Value (condition B) (that is, read enable signal REN_A be in level"1") other than " 0 ", then state machine SM_A is from data mode S_ DAT is converted to idle state S_IDLE.In response to the transformation to idle state S_IDLE, data counter DCT_A, which is terminated, to be counted Operation.

As shown in Figure 4 and Figure 6, above-mentioned condition B is such condition, that is, if the processing in payload region PLD is whole The tranmitting data register period after only is consistent with the insertion period of emergency notice data EDT_Ai, then is inserted on such period tight Anxious notification data EDT_Ai.Therefore, even if the time for example before the termination of the processing of payload region PLD is pointed out Existing emergency notice, emergency notice can also be reflected in currently processed frame.

It is controlled as shown in fig. 6, data efficiently generate circuit DVG_A, so as to during the period of header state S_HD Data valid signal DV_A3 is set to be maintained at level"1" with during period of data mode S_DAT.If above-mentioned condition B does not go out Show, then level"1" period of the level"1" period of data valid signal DV_A3 equal to data valid signal DV_A2.However, such as There is above-mentioned condition B in fruit, then level"1" of the level"1" period than data valid signal DV_A2 of data valid signal DV_A3 When segment length's a cycle.

When transmission circuit TXC by fifo buffer FIFO_A1, FIFO_A2, Fig. 5 in Fig. 3 counter (HCT_A, It DCT_A) and when above-mentioned state machine SM_A formation, can be by using simple configuration and shirtsleeve operation scheme by emergency notice Data are inserted into frame.With reference to figure 6, when the counting of data counter DCT_A is " 0 ", it is inserted into emergency notice data.But The counting of data counter DCT_A is not always restricted to " 0 ".However, being set from sending emergency notice as early as possible and expanding interval From the viewpoint of setting the range of M, the counting of data counter DCT_A is preferably " 0 ".For example, if being counted as " 7 ", initially The time point for sending the emergency notice in frame postpones 7 periods from the case where being counted as " 0 ", and is spaced the minimum value of setting M It is limited to " 7 " or bigger.

<<The details of the major part of receiving circuit>>

Fig. 7 is the circuit block of the example arrangement for the major part for showing the receiving circuit in semiconductor equipment shown in FIG. 1 Figure.Fig. 8 is the oscillogram for the exemplary operations for showing receiving circuit shown in Fig. 7.Receiving circuit RXC as shown in Figure 7 includes number It is exported according to effective receiving node NDr1, frame data receiving node NDr2, normal data output node NDo1 and emergency notice data Node NDo2.Receiving circuit RXC further includes error detection circuit CRCD, interval setting register SREG_B, data allocation circuit DDC_ B, latch cicuit LT_B and fifo buffer FIFO_B.Receiving circuit is synchronously received frame with the clock cycle is received, and executes and connect Various processing needed for receiving.

The effective receiving node NDr1 of data receives data valid signal DV_Bi, and frame data receiving node from network N W1 NDr2 is from network N W1 frames receiveds according to DT_Bi.Frame data DT_Bi has the identical n-bit (example of the case where with transmission circuit TXC Such as 4 bits or 8 bits) bit width.As shown in figure 8, data valid signal DV_Bi and frame data DT_Bi are respectively equal to Fig. 6 In data valid signal DV_Ao and frame data DT_Ao.It says in the sense that accurate, data valid signal DV_Bi and frame data DT_Bi is to be inputted from PHY circuit PHY2 shown in FIG. 1, and data valid signal DV_Bi is generated by PHY circuit PHY2.

Error detection circuit CRCD is calculated for the data in the Header Area HD and payload region PLD of frame data DT_Bi Error-detecging code (CRC code), and the CRC code calculated is compared with the CRC code in the FCS of error-detecging code region to detect mistake. As previously mentioned, transmission circuit TXC stores the CRC code of the state for being inserted into emergency notice data in the FCS of error-detecging code region.Cause This, error detection circuit CRCD can execute normal error detection to frame data DT_Bi.

Interval setting register SREG_B keeps the interval of CPU settings for example as shown in Figure 1 that M is arranged.As referring to Fig.1 and Described in Fig. 2, interval setting M is to determine the value of the periodically data break of extraction emergency notice data.For transmission circuit TXC Identical interval is set with receiving circuit RXC, M is set.Latch cicuit LT_B is the circuit for keeping emergency notice data, and And fifo buffer FIFO_B is for keeping normal data (that is, being stored in the Header Area HD and payload region PLD of frame In data) buffer.

Although will provide details later, data allocation circuit DDC_B includes data counter, the data counter The quantity for receiving the clock cycle is cyclically counted with the interval defined by interval setting M (cycle count " M+1 "), is such as sending electricity Situation in the TXC of road is such.As shown in figure 8, the counting based on data counter, data allocation circuit DDC_B is controlled, with Just " 1 " electricity will be set as the latch enable signal LEN_B of latch cicuit LT_B with the interval defined by cycle count " M+1 " It is flat, and the write-in enable signal WEN_B for fifo buffer FIFO_B is controlled to be complementation with latch enable signal LEN_B Relationship.

More specifically, if the counting of data counter is predetermined value, data allocation circuit DDC_B is controlled, It is set as level"1" so that enable signal LEN_B will be latched.In response to latching enable signal LEN_B, latch cicuit LT_B is latched The frame data DT_Bi that (that is, extraction) receives on the associated reception clock cycle is as emergency notice data, then from urgent The emergency notice data that the NDo2 outputs of notification data output node are latched are as emergency notice data EDT_Bo.

Meanwhile if the counting of data counter is the value other than predetermined value, data allocation circuit DDC_B is carried out Control, sets write enable signal WEN_B to level"1".In response to write enable signal WEN_B, in associated reception The frame data DT_Bi received on the clock period is by as normal data write-in fifo buffer FIFO_B.In order to avoid being filled, Fifo buffer FIFO_B executes read operation on each reception clock cycle, and will come from normal data output node The reading data of NDo1 are exported as normal data NDT_Bo.

<<The details of data allocation circuit>>

Fig. 9 is the circuit block diagram for the example arrangement for showing data allocation circuit shown in Fig. 7.Figure 10 is shown shown in Fig. 9 Data allocation circuit exemplary operations oscillogram.Data allocation circuit DDC_B as shown in Figure 9 includes preamble counter HCT_B, data counter DCT_B, state machine SM_B and enable signal generative circuit ENG_B.Preamble counter HCT_B, data The configuration and operation of counter DCT_B and state machine SM_B with it is described identical referring to figure 5 and figure 6.

In short, when data valid signal DV_Bi is in level"1", state machine SM_B turns from idle state S_IDLE Header state S_HD is changed to, as shown in Figure 10.Preamble counter HCT_B starts counting up operation in response to above-mentioned transformation, and base The number " N+1 " in tranmitting data register period is counted in the known data length of Header Area HD.As preamble counter HCT_B Counting operation complete when, state machine SM_B is converted to data mode S_DAT.In response to such transformation, data counter DCT_B cyclically counts the quantity for receiving the clock cycle with the interval defined by cycle count " M+1 ".

If data mode S_DAT exists and data counter DCT_B is counted as " 0 ", enable signal generates electricity Road ENG_B is controlled is set as level"1" to latch enable signal LEN_B, and if it is other than " 0 " to count Value is then controlled and is in level "0" so that latch enable signal LEN_B is arranged.In addition, enable signal generative circuit ENG_B is defeated Go out to latch the reverse phase of enable signal LEN_B as write enable signal WEN_B.That is, when the counting of data counter DCT_B For " 0 " when, controlled and be arranged in level "0" so that enable signal WEN_B will be written, and be other than " 0 " when counting Value when, then be set as level"1".If idle state S_IDLE occurs, enable signal generative circuit ENG_B is controlled Write enable signal WEN_B is arranged in level "0" system.

If it is to remove that data valid signal DV_Bi, which is in level "0" (condition D) and the counting of data counter DCT_B, Value (condition D) (that is, write-in enable signal WEN_B be in level"1") except " 0 ", state machine SM_B is from data mode S_DAT It is converted to idle state S_IDLE.In response to being converted to idle state S_IDLE, data counter DCT_B terminates counting operation. Condition D meets the condition B of the state machine SM_A described before.

As described above when receiving circuit RXC by Fig. 9 counter (HCT_B, DCT_B) and state machine SM_B formed when, By using simple configuration and shirtsleeve operation scheme, emergency notice data can be extracted.For extracting emergency notice data The counting of data counter DCT_B be not always restricted to " 0 ".However, transmission circuit TXC and receiving circuit RXC need Use identical counting.

<<The main advantageous effect of first embodiment>>

The method according to first embodiment being described above allows to send emergency notice with short delay, and does not have to The currently transmitted completion until frame or retransmission frame are waited for, as shown in figure 30.As a result, the vehicle-carrying communication system high in safety requirements Advantageous effect is obtained in system or other systems.In addition, compared with comparative example 2, the necessity for retransmitting and filling has been substantially eliminated. Therefore, it is possible to reduce due to retransmitting and filling caused bandwidth cost.Further, since the necessity of re-transmission is eliminated, at some In the case of can reduce the delay of normal data transmission and improve the reliability of communication system.

Emergency notice data be not limited to error detection data or other similar to data, and can be need periodically sent with short delay Specific data (for example, by abnormality sensor measure value).In addition, be configured such that can be with for communication system 1 shown in FIG. 1 Two-way communication is established between semiconductor equipment DEV1 and semiconductor equipment DEV2.However, it is possible to only be built using alternative configurations Vertical one-way communication.

Second embodiment

<<Communication system summary (applies example)>>

Figure 11 is the schematic diagram of the example arrangement for the major part for showing communication system according to a second embodiment of the present invention. Communication system shown in Figure 11 and communication system shown in FIG. 1 the difference is that, the semiconductor equipment DEV1 in Fig. 1 is by Figure 11 In semiconductor equipment DEV1a replace, and add network N W2, semiconductor equipment DEV'1, DEV'2 and PHY circuit PHY3, PHY4.Each semiconductor equipment DEV'1, DEV'2 are existing semiconductor equipments and include for example send and receive frame normal Advise telecommunication circuit CC'.Semiconductor equipment DEV'1, DEV'2 will be produced by general communication circuit CC' by interrupt control circuit INTC Raw emergency notice data EDT is sent to network N W2.

Semiconductor equipment DEV1 in semiconductor equipment 1a and Fig. 1 the difference is that, interrupt control circuit INTC quilts General communication circuit CC' is replaced.Telecommunication circuit CC' receives emergency notice by network N W2 from semiconductor equipment DEV'1, DEV'2 Data EDT, and the emergency notice data EDT received is output to the telecommunication circuit CC described in conjunction with first embodiment.Such as knot It closes described in first embodiment, the emergency notice data of input are periodically inserted into frame by telecommunication circuit CC, and by frame (frame data DT) is sent to network N W1.

<<The main advantageous effect of second embodiment>>

As described above, the emergency notice number that semiconductor equipment DEV1a relayings are sent from semiconductor equipment DEV'1, DEV'2 According to.This is eliminated is applied to all semiconductor equipments that communication system includes by telecommunication circuit CC according to first embodiment Necessity.For example, existing network can be used as former state low level network (in present exemplary, network N W2 and semiconductor equipment DEV' 1, DEV'2), and the high-level network that method according to first embodiment can be applied to normal frame and emergency notice frame coexists The part of (the network N W1 in present exemplary and semiconductor equipment DEV1a, DEV2).Therefore, second embodiment not only provides knot The various advantageous effects of first embodiment description are closed, but also the cost of communication system can be inhibited to increase.

3rd embodiment

<<The details (modified example) of Data Synthesis processing circuit>>

Figure 12 is the circuit block diagram for the example arrangement for showing the Data Synthesis processing circuit in Fig. 3, Data Synthesis processing Circuit is included in semiconductor equipment according to a third embodiment of the present invention.Figure 13 is to show Data Synthesis shown in Figure 12 The oscillogram of the exemplary operations of processing circuit.The Data Synthesis processing circuit of Figure 12 and the Data Synthesis processing circuit DSC_A of Fig. 5 The difference is that state machine SM_C and data efficiently generate circuit DVG_C due to the elimination of preamble counter HCT_A and with Different modes operate.

As shown in figure 13, it is compared at notable with Fig. 5 and situation shown in fig. 6, Data Synthesis processing circuit shown in Figure 12 Emergency notice data are usually not only inserted into the payload region PLD of frame by DSC_C, but also are inserted in Header Area HD In.When it is such operation be performed, when data valid signal DV_A2 changes to level"1" from level "0", state machine SM_C It is converted to data mode S_DAT from idle state S_IDLE rather than header state S_HD.In response to this to data mode S_ The transformation of DAT, data counter DCT_A start counting up operation.

Selection signal generative circuit SSG_A is controlled, if so as to data mode S_DAT presence and data counter DCT_A's is counted as " 0 ", then will read enable signal REN_C and be set as level "0", and controlled in other situations The lower enable signal REN_C that will read is set as level"1".In addition, enable signal is read in the SSG_A outputs of selection signal generative circuit The reverse phase of REN_C alternatively signal SS_C.Sharp contrast is formed with situation shown in Fig. 5, data efficiently generate circuit DVG_C is controlled, data valid signal DV_C3 is maintained at level"1" during the period of data mode S_DAT.

<<The main advantageous effect of 3rd embodiment>>

As described above, emergency notice data start to be inserted into the HD of Header Area.Therefore, 3rd embodiment provides not only In conjunction with the various advantageous effects that first embodiment describes, but also emergency notice can be sent with short delay.For example, if header Length is 14 bytes, then delay time can reduce by 14 byte times.But if emergency notice data are inserted into header region Domain HD, then for example commodity ethernet interchanger cannot correctly identify Header Area HD.Therefore, in this sense, as combined Described in first embodiment like that, emergency notice data are preferably inserted into the PLD of payload region.

Fourth embodiment

<<The details (applying example) of the major part of transmission circuit>>

Figure 14 is the circuit block diagram of the example arrangement for the major part for showing the transmission circuit in Fig. 1, the transmission circuit quilt It is included in semiconductor equipment according to a fourth embodiment of the present invention.Figure 15 is to show Data Synthesis processing circuit shown in Figure 14 Example arrangement circuit block diagram.Figure 16 is to show that data shown in Figure 14 divide the circuit diagram of the example arrangement of circuit.Figure 17 It is the oscillogram for the exemplary operations for showing transmission circuit shown in Figure 14.Figure 18 is to show Data Synthesis processing electricity shown in figure 15 The oscillogram of the exemplary operations on road.

The example arrangements as shown in figure 3 of transmission circuit TXC shown in Figure 14 the difference is that, frame generative circuit FRG_ The configuration and operation of D are different from the configuration and operation of frame generative circuit FRG_A, because being input to emergency notice data input node The bit width of the emergency notice data EDT_Di of NDi3 is changed to " 2 × n " bit.As shown in figure 17, with cycle count " M+ 1 " the interval defined, transmission circuit TXC shown in Figure 14 are inserted into " 2 × n " bit usually on two periods with n-bit increment Emergency notice data EDT_Di.

Frame generative circuit FRG_D example arrangements as shown in figure 3 the difference is that, increase data and divide circuit DDIV and different from the configuration and operation of Data Synthesis processing circuit DSC_D.As shown in figure 16, data divide circuit DDIV packets Include selection circuit SEL_D.When the counting CN_D of data counter is " 0 ", selection circuit SEL_D selects emergency notice data Emergency notice data (high position) EDT_Du of the high-order n-bit of EDT_Di, and when it is " 1 " to count CN_D, select urgent logical Emergency notice data (low level) EDT_D1 of the low level n-bit of primary data EDT_Di.Selection circuit SEL_D exports the data of selection As emergency notice data EDT_Dx.If it is the value other than " 0 " or " 1 " to count CN_D, emergency notice data EDT_Dx can To be unrelated value.

As shown in figure 15, Data Synthesis processing circuit DSC_D and Data Synthesis processing circuit DSC_A in following three points not Together.First, data counter DCT_A is the point that CN_D to data division circuit DDIV is counted from its output.Secondly, selection signal The configuration and operation of generative circuit SSG_D are different.The configuration and operation of third, state machine SM_D are different.

As shown in figure 18, if data mode S_DAT exists and data counter DCT_A is counted as " 0 " or " 1 ", Then selection signal generative circuit SSG_D is controlled is set as level "0" to read enable signal REN_D, and carries out Control is set as level"1" to read enable signal REN_D in other cases.In addition, selection signal generative circuit The reverse phase of enable signal REN_D alternatively signal SS_D is read in SSG_D outputs.That is, when data counter DCT_A's It when being counted as " 0 " or " 1 ", is controlled to set selection signal SS_D to level"1", and works as data counter DCT_A Value of the counting in addition to " 0 " or " 1 " when be set as level "0".

State machine SM_D and state machine SM_A shown in fig. 5 the difference is that, from data mode S_DAT to idle shape The condition B that the above-mentioned state transformation of state S_IDLE occurs is different.More specifically, if meeting condition E rather than condition The counting of B, i.e. data counter DCT_A are that (that is, reading enable signal REN_D, be in " 1 " electric for value in addition to " 0 " or " 1 " It is flat), then state machine SM_D is converted to idle state S_IDLE.As a result, as shown in figure 18, circuit DVG_ is efficiently generated from data The data valid signal DV_D3 of A can be extended for two periods longer than data valid signal DV_A2 sometimes.

When selection signal SS_D is in level "0" (read enable signal REN_D and be in level"1"), shown in Figure 14 Data selection circuit DSEL_A selects normal data NDT_A2, and (reads enabled letter when selection signal SS_D is in level"1" Number REN_D is in level "0") when selection divide the emergency notice data EDT_Dx that circuit DDIV is received from data.Such as Figure 17 institutes Show, then by the data of selection, alternatively data SDT_D is exported data selection circuit DSEL_A.In this case, it is selecting During the level"1" period for selecting signal SS_D, data selection circuit DSEL_A is (high in a cycle output emergency notice data Position) EDT_Du, and export emergency notice data (low level) EDT_D1 in second period.

Then, as the case where first embodiment, by error-detecging code counting circuit CRCG from frame data sending node NDt2 sends n-bit frame data DT_Do, and has valid data signal DV_Do from data by error-detecging code counting circuit CRCG Sending node NDt1 is imitated to send.Although being not described in, when receiving circuit RXC is with side identical with transmission circuit TXC When formula changes, the emergency notice data being divided into two periods can be received.In addition, although present exemplary assumes urgent lead to Primary data was divided into two periods, but emergency notice data can be divided into three or more periods.

<<The main advantageous effect of fourth embodiment>>

As described above, providing not only the various advantageous effects described in conjunction with first embodiment according to the method for fourth embodiment Fruit, and allow to suitably handle the case where bit width of emergency notice data is more than normal data.That is, can To send the emergency notice data with relatively large size of data, limited without the bit width by normal data.This example Such as provide improved convenience for users.

5th embodiment

<<Assuming that the problem of>>

When using preceding method according to first embodiment, the combination of frame length and interval setting M is depended on, it is urgent logical The reception period of primary data can be consistent with the reception period of the CRC code in receiving circuit RXC.In such example, CRC code It may be mistakenly identified as emergency notice data.More specifically, it such as with reference to figure 8, is in latching enable signal LEN_B The frame data DT_Bi received on the period of level"1" is received circuit RXC and is simply identified as emergency notice data EDT_Bo. Thus, for example, being in " 1 " electricity if there is enable signal LEN_B is latched during the period (4 byte) of detection code region FCS Flat situation, then receiving circuit RXC can not know that the data received on such period are CRC codes.

Meanwhile such as by limiting frame length and being spaced the combination of setting M, the reception week of emergency notice data can be prevented Phase and the reception period of CRC code are consistent with each other.However, such limitation causes convenience for users to reduce.In the above case, with Lower method will be beneficial.

<<The details (applying example) of the major part of receiving circuit>>

Figure 19 is the circuit block diagram of the example arrangement for the major part for showing the receiving circuit in Fig. 1, the receiving circuit quilt It is included in semiconductor equipment according to a fifth embodiment of the present invention.Figure 20 is to show showing for data allocation circuit shown in Figure 19 The circuit block diagram of example configuration.Figure 21 is the oscillogram for the exemplary operations for showing receiving circuit shown in Figure 19.Shown in Figure 19 Receiving circuit RXC and example arrangement shown in Fig. 7 the difference is that, be added to delay circuit DLY1, DLY2 and shielding letter Number generative circuit MSKG, and the configuration and operation of data allocation circuit DDC_E are different.

As shown in figure 21, when the data valid signal DV_Bi received by the effective receiving node NDr1 of data turns from level"1" When changing to level "0", the K period of shielded signal generative circuit MSKG output shielded signals MSK.Term " K period " indicates The quantity of the clock cycle of the data length of CRC code based on frame.For example, if the bit width n of frame data DT_Bi is 1 word It saves, then term " K period " indicates 4 periods.

As shown in figure 21, the data valid signal DV_ that delay circuit DLY1 will be received by the effective receiving node NDr1 of data Bi postpones K period (for example, 4 periods), then exports the data valid signal DV_E of delay.Similarly, delay circuit The frame (frame data DT_Bi) received by frame data receiving node NDr2 is postponed K period (such as 4 periods) by DLY2, then Export the frame (frame data DT_E) of delay.

Therefore, as shown in figure 21, during the period of data in frame data DT_E being error-detecging code region FCS, can export Corresponding to the shielded signal MSK of the level"1" of the period.Therefore, when the counting of data counter DCT_B is predetermined value (example Such as, " 0 ") and shielded signal MSK when not exported, data allocation circuit DDC_E will latch enabled letter by being controlled Number LEN_E is arranged in level"1", to extract frame data DT_E as emergency notice data EDT_Eo.

Meanwhile when the counting of data counter DCT_B is predetermined value (for example, " 0 ") and exports shielded signal MSK, Data allocation circuit DDC_E latches the level"1" of enable signal LEN_E to forbid extracting tightly from frame data DT_E by shielding Anxious notification data.On the contrary, the level "0" of enable signal WEN_E is written by frame data by shielding in data allocation circuit DDC_E Fifo buffer FIFO_B is written in DT_E.

In order to execute aforesaid operations, data allocation circuit DDC_E have for example in fig. 20 shown in configure.Shown in Figure 20 Data allocation circuit DDC_E and data allocation circuit DDC_B shown in Fig. 9 the difference is that, state machine SM_B inputs The data valid signal DV_E of delay and increase OR computing circuits OR1 and AND operation circuit AD1.AND operation circuit AD1 It carries out and transports by the reverse phase to latch enable signal LEN_B and shielded signal MSK from enable signal generative circuit ENG_B It calculates, enable signal LEN_E is latched in output.OR computing circuits OR1 is by making the write-in from enable signal generative circuit ENG_B Energy signal WEN_B and shielded signal MSK progress or operation, output write-in enable signal WEN_E.

<<The main advantageous effect of 5th embodiment>>

As described above, providing not only the various beneficial effects described in conjunction with first embodiment according to the method for the 5th embodiment Fruit, and be also prevented from receiving circuit RXC and CRC code is mistakenly identified as emergency notice data.In addition, in such case Under, the combination of frame length and interval setting M need not be limited.This for example provides improved convenience for users.

Sixth embodiment

<<The details (applying example) of the major part of transmission circuit>>

Figure 22 is the circuit block diagram of the example arrangement for the major part for showing the transmission circuit in Fig. 1, the transmission circuit quilt It is included in semiconductor equipment according to a sixth embodiment of the present invention.Figure 23 A show bit termination power shown in Figure 22 The circuit diagram of example arrangement.Figure 23 B are the specific examples output and input for showing bit termination power shown in Figure 23 A Figure.Figure 24 is the oscillogram for the exemplary operations for showing transmission circuit shown in Figure 22.According to the method for sixth embodiment with knot The different mode of mode for closing the description of the 5th embodiment solves the problems, such as the wrong identification described in conjunction with the 5th embodiment.

As shown in figure 24, the week that transmission circuit TXC is inserted into generally directed to each frame in termination emergency notice data EDT_Fx At interim one in the n bit of emergency notice data EDT_Fx, storage predetermined logic level (be in this example " 1 " Level) final data mark FLG.In response to this storage, as described later, receiving circuit RXC is detecting predetermined logic electricity Emergency notice data are extracted after flat final data mark FLG not from every frame.

The example arrangements as shown in figure 3 of transmission circuit TXC shown in Figure 22 the difference is that, because being input to urgent The bit width of the emergency notice data EDT_Fi of notification data input node NDi3 is changed to " n-1 " bit, and frame generates electricity The configuration and operation of road FRG_F are different.In addition, example arrangement as shown in figure 3 forms sharp contrast, transmission circuit TXC It is configured as from bus interface BSIF input frame lengths FLNG.

Frame generative circuit FRG_A in frame generative circuit FRG_F and Fig. 3 the difference is that, be added to bit coupling The configuration and operation of circuit BLN and Data Synthesis processing circuit DSC_F are different.As shown in fig. 23 a, bit coupling electricity Road BLN is final by the emergency notice data EDT_Fi of " n-1 " bit from Data Synthesis processing circuit DSC_F and 1 bit Data Labels FLG couplings, and export the emergency notice data EDT_Fx of n-bit.

Although being not shown, Data Synthesis processing circuit DSC_F has and the Data Synthesis processing circuit DSC_A phases in Fig. 5 Same configuration, but includes additionally the electricity of frame length FLNG and interval setting M output final data marks FLG based on input Road.That is, as frame length FLG and interval setting M (cycle count " M+1 ") known in advance, Data Synthesis processing circuit DSC_F can calculate the time point for terminating the final period that emergency notice data are inserted into, and be exported at calculated time point The final data mark FLG of level"1".

Data selection circuit DSEL_A shown in Figure 22 is in level "0" in selection signal SS_A and (reads enable signal REN_A is in level"1") when select normal data NDT_A2, and be in level"1" in selection signal SS_A and (read and enabled believe Number REN_A is in level "0") when select the emergency notice data EDT_Fx received from bit termination power BLN.Such as Figure 24 institutes Show, then by the data of selection, alternatively data SDT_F is exported data selection circuit DSEL_A.

Referring now to Figure 24, as n=8, selection signal SS_A the level"1" period (that is, emergency notice data EDT_ Fx value C2, D2 and D3 of the selection data SDT_F exported during) is as shown in fig. 23b.For example, the 0th to the 6th bit table of value D2 It is shown as the value D1 of emergency notice data EDT_Fi, and the 7th bit of value D2 indicates the final data mark FLG of level "0". Meanwhile the 0th to the 6th bit of value D3 indicates identical value D1, but the 7th bit of value D3 indicates the final data mark of level"1" Will FLG.

<<The details (applying example) of the major part of receiving circuit>>

Figure 25 is the circuit block diagram of the example arrangement for the major part for showing the receiving circuit in Fig. 1, the receiving circuit quilt It is included in semiconductor equipment according to a sixth embodiment of the present invention.Figure 26 shows that bit shown in Figure 25 divides circuit The circuit diagram of example arrangement.Figure 27 is the circuit block diagram for the example arrangement for showing data allocation circuit shown in Figure 25.Figure 28 is The oscillogram of the exemplary operations of receiving circuit shown in Figure 25 is shown.Receiving circuit RXC shown in Figure 25 and example shown in Fig. 7 Configuration the difference is that, be added to bit and divide circuit BDIV, and the configuration and operation of data allocation circuit DDC_G are not With.

Data valid signal DV_Gi is input into the effective receiving node NDr1 of data of receiving circuit shown in Figure 25, and And frame data DT_Gi is input into frame data receiving node NDr2.As shown in figure 28, data valid signal DV_Gi and frame data DT_Gi be respectively equal to the data valid signal DV_Fo that transmission circuit TXC is sent shown in Figure 22 and frame data DT_Fo (referring to Figure 24).

As illustrated in figs. 25 and 26, the n-bit emergency notice data EDT_Gx from latch cicuit LT_B is input into ratio Spy divides circuit BDIV.Bit divides circuit BDIV by the emergency notice data from urgent notification data output node NDo2 The 0th to the (n-1)th bit of EDT_Gx is exported as emergency notice data EDT_Go, and the n-th bit is exported to data and distributes electricity Road DDC_G is as final data mark FLG.

As shown in figure 27, the difference of the data allocation circuit DDC_E in data allocation circuit DDC_G and Figure 20 exists In shielded signal MSK is replaced by final data mark FLG.Latch cicuit LT_B shown in Figure 25 is in response to coming from data point Latch enable signal LEN_G with circuit DDC_G, periodically from frame data DT_Gi extraction emergency notice data EDT_Gx.Such as Shown in Figure 28, if the emergency notice data EDT_Gx extracted is the value D3 of the final data mark FLG comprising level"1", Then bit divides circuit BDIV and the final data mark FLG of level"1" is output to data allocation circuit DDC_G.

By using shielded signal MSK, data allocation circuit DDC_G shown in final data mark FLG rather than Figure 21 To write-in enable signal WEN_B and latch enable signal LEN_B progress OR and AND from enable signal generative circuit ENG_B Operation, such as the case where Figure 21.As a result, after detecting the final data mark FLG of level"1", data allocation circuit Lock of the DDC_G shieldings for the level "0" of the write enable signal WEN_G of fifo buffer FIFO_B and for latch cicuit LT_B The level"1" of enable signal LEN_G is deposited, as shown in figure 28.Therefore, the final data mark FLG for detecting level"1" it Afterwards, emergency notice data will not be extracted.

<<The main advantageous effect of sixth embodiment>>

As described above, the side according to the 5th embodiment for being provided according to the method for sixth embodiment and being had been described before The identical advantageous effect of method.In addition, with according to the method for the 5th embodiment at sharp contrast, not according to the method for sixth embodiment Need delay circuit DLY1, DLY2 in receiving circuit RXC.This for example can be sent emergency notice data with shorter delay To the interrupt control circuit INTC of receiving circuit RXC.

7th embodiment

<<Communication system operation method>>

The side for determining interval setting M described in conjunction with first, second, the four, the 5th and sixth embodiment will now be described Method.Interval setting M can be determined as needed.In principle, interval setting is smaller, can transmit the delay of emergency notice data It is shorter.But in fact, interval setting is too small may not always to shorten delay.Figure 29 is to show to implement according to the present invention the 7th The figure of the spaced exemplary method of determination in the communication system of example.

Figure 29 shows the state that frame FR is continuously transmitted." X " in frame FR indicates the value of emergency notice data.But it is real On border, interframe emergency notice interval T1 is present in except frame as shown in figure 29.The worst-case value of emergency notice delay time by The limitation of interframe emergency notice interval T1.Interframe emergency notice interval T1 is the CRC length of error-detecging code region FCS (for example, 4 words Section), the sum of the header length (including preamble area) at the interval of frame FR and Header Area HD that is for example defined by standard (example Such as 22 bytes).

As described above, the worst value is limited by interframe emergency notice interval T1.Therefore, setting M in interval preferably makes The data break obtained corresponding to cycle count " M+1 " is not shorter than interframe emergency notice interval T1.Interval setting M more preferably makes Data break is equal to interframe emergency notice interval T1.This allows to that M is arranged by interval to determine emergency notice delay time Worst-case value, and inhibit for example due to interval setting M it is too small caused by bandwidth cost increase.In addition, based on interval When the data break of M being set being arranged to value identical with interframe emergency notice interval T1, emergency notice delay time it is worst Value can be set to the minimum value of actual use.

Although the present invention completed by inventor is described in detail by embodiment, the present invention is not limited to aforementioned Embodiment.It should be appreciated by those skilled in the art that can carry out without departing from the spirit and scope of the present invention various Modification.For example, previous embodiment is described in detail in order to understand the present invention.The present invention is not always limited to have all The embodiment of said elements.Some elements of some embodiment can be substituted by the element of another embodiment.In addition, some reality The element of another embodiment can be added to by applying the element of example.Moreover, some elements of each embodiment can be deleted, Addition other elements are replaced by other elements.

Claims

1. a kind of communication system, including：

Sending device generates the outside for meeting the frame of ethernet standard and the frame of generation being sent to the equipment；With

Receiving device receives the frame sent from the sending device,

First data are inserted into the frame by the wherein described sending device with scheduled data break, and

The wherein described receiving device obtains described with data break identical with the sending device from the frame of reception One data, and remaining data is obtained as the data in the Header Area and payload region of the frame.

2. communication system according to claim 1,

First data are inserted into the described effective of the frame by the wherein described sending device with the scheduled data break In load region, and

The wherein described receiving device is with data break identical with the sending device from effective load of the frame of reception Lotus region obtains first data.

3. communication system according to claim 1,

The wherein described sending device is directed to the data in the frame for inserting first data and calculates error-detecging code, and will calculate Value be stored in the error-detecging code region of the frame.

4. communication system according to claim 1,

Wherein, the scheduled data break is arranged to the data length not less than the error-detecging code for the frame, institute State the value at the sum of interval between the data length and the frame and consecutive frame of Header Area.

5. communication system according to claim 1,

The wherein described sending device sends the frame with tranmitting data register cycle synchronisation,

The wherein described receiving device is synchronously received the frame with the clock cycle is received,

The wherein described sending device includes：

The first buffer of the second data, second data is kept to be stored in Header Area and the payload area of the frame In domain；With

Frame generative circuit generates the frame, while sequentially determining the institute on each tranmitting data register period sequentially in time The data in frame are stated,

Wherein, the frame generative circuit includes：

First data counter cyclically counts the tranmitting data register period to count the interval defined by predetermined period；With

Data selection circuit will be in the frame when the counting of first data counter is the value different from the first value Data are determined as second data read from first buffer, and when the counting of first data counter is When first value, the data in the frame are determined as first data, and

The wherein described receiving device includes：

Keep the second buffer of second data；

Second data counter, with the interval that is defined by cycle count identical with first data counter come periodically The reception clock cycle is counted；With

Data allocation circuit will be in correlation when the counting of second data counter is the value different from first value Data in the frame received on the reception clock cycle of connection are written to second buffer as second data, and And when the counting of second data counter is first value, connect on the associated reception clock cycle described in extraction Data in the frame received are as first data.

6. communication system according to claim 5,

Wherein described first data are more urgent than second data.

7. communication system according to claim 5,

The frame generative circuit in the wherein described sending device is calculated also directed to the data exported from the data selection circuit Error-detecging code, and the value of calculating is stored in the error-detecging code region of the frame.

8. communication system according to claim 5,

Wherein all by first data of the data selection circuit selection in the sending device and second data It is formed by the equal multiple bits of bit width,

The week of the frame generative circuit in the wherein described sending device in the insertion for terminating first data for each frame The final data mark that predetermined logic level is stored at the position of one of the bit on phase, in first data, with And

The wherein described receiving device is forbidden after detecting the final data mark of the predetermined logic level from each Frame extracts first data.

9. a kind of semiconductor equipment, including：

Transmission circuit generates the outside for meeting the frame of ethernet standard and the frame of generation being sent to the equipment；

The wherein described transmission circuit includes：

Keep the buffer of the second data, second data that will be stored in Header Area and the payload region of the frame In；With

Frame generative circuit generates the frame in chronological order, while sequentially determining in the frame on each clock cycle Data, and

Wherein, the frame generative circuit includes：

Data counter cyclically counts the clock cycle to count the interval defined by predetermined period；With

Data selection circuit, when the counting of the data counter is the value different from the first value, by the data in the frame It is determined as second data read from the buffer, and when the counting of the data counter is first value When, the data in the frame are determined as the first data, first data are different from second data.

10. semiconductor equipment according to claim 9,

Wherein described first data are more urgent than second data.

11. semiconductor equipment according to claim 9,

The wherein described frame generative circuit further includes error-detecging code counting circuit, and the error-detecging code counting circuit is directed to from the data and selects The data for selecting circuit output calculate error-detecging code, and the value of calculating is stored in the error-detecging code region of the frame.

12. semiconductor equipment according to claim 9,

Wherein, when will from the buffer read second data from the data in the Header Area become it is described effectively When data in load region, the data counter starts counting up operation.

13. semiconductor equipment according to claim 12,

The wherein described transmission circuit further includes data input node and the effective input node of data,

The wherein described data input node inputs second data during predetermined period, and in addition to the predetermined period Data related with idle state are inputted during period in addition,

The wherein described effective input node input data useful signal of data, the data valid signal is in the predetermined period phase Between in the first logic level and during the period in addition to the predetermined period be in the second logic level,

The wherein described buffer includes：

First FIFO (first in, first out) buffer has the capacity of the clock cycle for predetermined quantity, and in each clock The data valid signal at the effective input node of the data is obtained on period；With

Second fifo buffer has the capacity of the clock cycle for quantity identical as first fifo buffer, and The data at the data input node are obtained on each clock cycle,

The wherein described frame generative circuit further includes preamble counter, and the preamble counter is read from first fifo buffer The data valid signal taken starts counting up operation when becoming first logic level from second logic level, and The quantity of the clock cycle is counted based on the data length of the Header Area, and

Wherein when the preamble counter completes the counting operation, the data counter starts counting up operation.

14. semiconductor equipment according to claim 9,

Wherein described first value is multiple continuous counters.

15. semiconductor equipment according to claim 9,

First data and second data wherein selected by the data selection circuit are all equal by bit width Multiple bits are formed, and

The wherein described frame generative circuit counts on the period for the insertion for terminating first data for each frame, described first The final data mark of predetermined logic level is stored at the position of one of the bit in.

16. a kind of semiconductor equipment, including：

Receiving circuit receives the frame for meeting ethernet standard in chronological order on each clock cycle,

The wherein described receiving circuit includes：

The buffer of the second data, second data is kept to be stored in Header Area and the payload region of the frame In；With

Data counter periodically counts the clock cycle to count the interval defined by predetermined period, and

Data allocation circuit will be in associated clock when the counting of the data counter is the value different from the first value The buffer is written as second data in data in the frame received on period, and works as the data counter Counting when being first value, extract the data in the frame received on the associated clock cycle as first Data, first data are different from second data.

17. semiconductor equipment according to claim 16,

Wherein described first data are more urgent than second data.

18. semiconductor equipment according to claim 16,

Wherein, when second data that will be distributed from the data allocation circuit become from the data in the Header Area When data in the payload region, the data counter starts counting up operation.

19. semiconductor equipment according to claim 18,

The wherein described receiving circuit further includes frame data receiving node, the effective receiving node of data and preamble counter,

The wherein described frame data receiving node receives the frame during predetermined period, and in addition to the predetermined period Data related with idle state are received during period,

The wherein described effective receiving node of data receives data valid signal, and the data valid signal is in the predetermined period phase Between in the first logic level and during the period in addition to the predetermined period be in the second logic level,

The wherein described preamble counter becomes the first logic electricity in the data valid signal from second logic level Usually start counting up operation, and counted to the number of the clock cycle based on the data length of the Header Area Number, and

20. semiconductor equipment according to claim 19,

The wherein described receiving circuit further includes：

The data valid signal received by the effective receiving node of the data is postponed K period by the first delay circuit, and The data valid signal of delay is exported, the K period is made equal based on the data of the error-detecging code for the frame The clock cycle of length；

Second delay circuit by the K period described in the frame delay received by the frame data receiving node, and exports delay The frame；With

Shielded signal generative circuit, when the data valid signal received by the effective receiving node of the data is from the first logic When level conversion is to second logic level, start shielded signal of the output for the K period, and

Wherein when the count value of the data counter is first value and the shielded signal is not exported, the number According to the data in the frame of distributor circuit extraction delay as first data, and when exporting the shielded signal, Forbid extracting first data.