CN114995780A

CN114995780A - FIFO buffer and control method of FIFO buffer

Info

Publication number: CN114995780A
Application number: CN202210652557.8A
Authority: CN
Inventors: 赵昌兵; 童力
Original assignee: Espressif Systems Shanghai Co Ltd
Current assignee: Espressif Systems Shanghai Co Ltd
Priority date: 2022-06-07
Filing date: 2022-06-07
Publication date: 2022-09-02

Abstract

The application discloses a first-in first-out buffer and a control method thereof, wherein the first-in first-out buffer comprises: the device comprises an input processing module, a register file, an output processing module and a state generating module. The state generation module determines state information; the input processing module receives a request for inputting the multi-channel data and determines valid data to be written in the multi-channel data; determining the effective quantity of the writable data according to the quantity of the effective data to be written and the quantity of the remaining receivable data, generating an increment of a write pointer based on the effective quantity of the writable data, and sending the effective data to be written to a register file; the output processing module receives a request for outputting data, generates an increment of a read pointer and sends the increment to the register file; and the register file writes the effective data to be written into the register according to the write pointer and updates the write pointer according to the increment of the write pointer, and/or reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer. According to the scheme, the register file is used as the storage unit, and the problem of resource waste when the depth is small can be solved.

Description

FIFO buffer and control method of FIFO buffer

Technical Field

The present invention relates to the field of data buffering technologies, and in particular, to a first-in first-out buffer and a control method of the first-in first-out buffer.

Background

A First-in First-out buffer (FIFO) is a data buffer device commonly used in modern digital integrated circuit design, and mainly implements data queue buffering, and buffers and outputs data according to the Input order of the data. Conventional FIFOs can only implement single input and single output, i.e. only one data can be output or input at a time. For the condition that a plurality of input data are required to be buffered and output in sequence, only a plurality of FIFOs can be adopted for buffering, and an arbiter is adopted at the FIFO outlet to select one of the data for output. This method requires the use of a plurality of FIFOs and the use of an arbiter, which is wasteful of resources.

The existing multi-input FIFO mainly aims at a scene with a large storage depth, and is generally implemented in the form of a multi-level cache by using a Random Access Memory (RAM). For example, in a scheme disclosed in patent No. CN104778025A entitled "circuit configuration of FIFO based on random access memory", a RAM is used to implement a multiple-input single-output FIFO, but in this scheme, N +1 blocks of RAMs are required for N inputs, and if the depth of each block of RAM is M, the number of valid data stored in the FIFO is only N × M, but not (N +1) × M, and this may cause a waste of resources when the storage depth is relatively small.

In view of the above, the present application aims to provide a multi-way FIFO buffer scheme capable of avoiding resource waste in the case of a smaller FIFO depth.

It should be understood that the above-listed technical problems are only exemplary and not limiting to the present invention, and the present invention is not limited to the technical solutions for simultaneously solving all the above technical problems. Technical solutions of the present invention may be implemented to solve one or more of the above or other technical problems.

Disclosure of Invention

To solve the above and other problems, the present application provides a first-in first-out buffer including: the device comprises an input processing module, a register file, an output processing module and a state generating module; the register file comprises a plurality of registers as storage units;

wherein the state generation module is in communication with the register file and is configured to determine state information including at least a quantity of data remaining receivable by the register file;

the input processing module is communicated with the state generating module and is configured to receive a request for inputting multi-path data and determine valid data to be written in the multi-path data; determining the effective quantity of writable data according to the quantity of the effective data to be written and the quantity of the residual receivable data, generating an increment of a write pointer based on the effective quantity of the writable data, and sending the effective data to be written to the register file;

the output processing module is in communication with the state generation module and is configured to receive a request to output data, generate an increment of a read pointer, and send the increment to the register file;

the register file is respectively communicated with the input processing module and the output processing module, and is configured to write the valid data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and/or read the data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

Optionally, the register file is configured to determine a start position of writing to a register according to the write pointer, and the valid data to be written is input from the start position, and the input data is the same as the valid amount of the writable data.

Optionally, the input processing module is further configured to: and inputting the valid data to be written from the starting position according to a preset sequence.

Optionally, the preset order is arranged in a positive order or a negative order according to the size of the channel number, starting from the lowest bit or the highest bit of the valid data to be written.

Optionally, the fifo buffer supports synchronization or asynchronization of the read/write clocks, where the read/write clocks need to be processed across clock domains during asynchronization and the read/write clocks do not need to be processed across clock domains during synchronization.

Optionally, the register file is a two-dimensional register matrix.

Optionally, the write pointer is represented by binary, the width of the write pointer is represented by log2(K) +1 bit, where K is the depth of the register file, log2(K) bit represents the position of write data with depth of K, 1 bit highest bit is additionally added for determining whether the write pointer loops around boundary K, and the highest bit of the write pointer is flipped each time the write pointer crosses the boundary of K.

Optionally, the write pointer is updated when the effective amount of the writable data is greater than zero, and the value increased each time is the effective amount of the writable data.

Optionally, the read pointer is represented by binary, the width of the read pointer is represented by log2(K) +1 bit, where K is the depth of the register file, log2(K) bit represents the position of read data with the depth of K, and the most significant bit added by 1 bit is used to determine whether the read pointer loops around the boundary K, and the most significant bit of the read pointer is flipped each time the read pointer crosses the boundary of K.

Optionally, the read pointer is updated when the number of remaining receivable data is greater than zero and a data output request is received, each time the incremented value is 1.

Optionally, the state generation module is configured to determine the amount of remaining receivable data based on the write pointer, the read pointer, and the depth K of the register file:

when the highest bit of the write pointer and the read pointer is the same, the number of the residual receivable data is K- (WPTR-RPTR); wherein WPTR represents a value of the read pointer and RPTR represents a value of the write pointer;

when the highest bits of the write pointer and the read pointer are different, the number of the residual receivable data is RPTR _ LSB-WPTR _ LSB; and WPTR _ LSB represents a value after the WPTR removes the highest bit, and RPTR _ LSB represents a value after the RPTR removes the highest bit.

Optionally, the state generating module is further configured to convert binary read and write pointers into gray codes for representation when the fifo buffer implements asynchronous input, and perform two-stage register synchronization using the gray codes to convert the synchronized gray codes into binary.

Optionally, the state generating module is further configured to generate empty state information, to-full state information, and full state information;

wherein the null state information is generated when the number of received data is 0;

when the number of the received data is less than or equal to a preset to-be-empty threshold value, generating to-be-empty state information;

when the quantity of the received data is larger than or equal to a preset to-be-full threshold value, generating the to-be-full state information;

the full state information is generated when the amount of received data is equal to the depth of the register file.

The present application further provides a method for controlling a fifo buffer, which is applied to any one of the above fifo buffers, the method including:

the input processing module receives a request for inputting multi-channel data;

the input processing module compares the quantity of the valid data to be written with the quantity of the residual receivable data determined by the state generating module; if the quantity of the valid data to be written is larger than the quantity of the remaining receivable data, the effective quantity of the writable data is the quantity of the remaining receivable data; if the quantity of the valid data to be written is not larger than the quantity of the remaining receivable data, the effective quantity of the writable data is the quantity of the valid data to be written;

the input processing module generates increment of a write pointer based on the effective quantity of the writable data and sends the effective data to be written to the register file;

and the register file writes the effective data to be written into the register according to the write pointer and updates the write pointer according to the increment of the write pointer.

Optionally, the method further comprises:

the output processing module receives a request for outputting data, generates an increment of a read pointer and sends the increment to the register file;

and the register file reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer.

The present application provides a fifo buffer and a control method thereof, the fifo buffer including: the device comprises an input processing module, a register file, an output processing module and a state generating module; the register file includes a plurality of registers as storage units; wherein the state generation module is in communication with the register file and is configured to determine state information including at least an amount of data remaining receivable by the register file; the input processing module is communicated with the state generating module and is configured to receive a request for inputting the multi-channel data and determine valid data to be written in the multi-channel data; determining the effective quantity of the writable data according to the quantity of the effective data to be written and the quantity of the residual receivable data, generating an increment of a write pointer based on the effective quantity of the writable data, and sending the effective data to be written to a register file; the output processing module is communicated with the state generating module and is configured to receive a request for outputting data, generate an increment of a read pointer and send the increment to the register file; the register file is respectively communicated with the input processing module and the output processing module and is configured to write the effective data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and/or read the data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

Therefore, the scheme provided by the application adopts the register file as the storage unit, effective data in input data can be stored in the register file in sequence through the control of the write pointer, and as the area of the register is smaller than that of a multi-stage storage unit adopting an RAM, the first-in first-out cache of multi-path input data can be completed under the condition of small hardware overhead under the condition of small depth, so that the problem of resource waste caused by the existing scheme adopting the multi-stage storage unit under the condition of small depth can be solved.

Drawings

Hereinafter, the present application will be further explained with reference to the drawings based on embodiments.

FIG. 1 is a block diagram schematically illustrating an embodiment of a FIFO buffer provided in the present application;

FIG. 2 is a schematic diagram illustrating another embodiment of a FIFO buffer provided in the present application;

FIG. 3 is a flow chart schematically illustrating a method of controlling a FIFO buffer provided herein;

fig. 4 schematically shows a data path diagram of a 4-way input data, first-in-first-out buffer with a depth of 10.

Detailed Description

The method and apparatus of the present application will be described in detail below with reference to the following figures and detailed description of the preferred embodiments. It is to be understood that the embodiments shown in the drawings and described below are merely illustrative and not restrictive of the application.

A structural block diagram of an embodiment of the fifo buffer provided in the present application is shown in fig. 1, where the fifo buffer specifically includes: an input processing module 11, a register file 12, an output processing module 13 and a state generating module 14; the register file 12 includes a plurality of registers as memory units.

Wherein the status generation module 14 is in communication with the register file 12 and is configured to determine status information including at least an amount of data remaining receivable by the register file.

The input processing module 11 is in communication with the status generating module 14, and is configured to receive a request for inputting multiple paths of data, and determine valid data to be written in the multiple paths of data; determining the effective amount of the writable data according to the amount of the effective data to be written and the amount of the remaining receivable data, generating an increment of a write pointer based on the effective amount of the writable data, and sending the effective data to be written to the register file 12.

The output processing module 13 is in communication with the state generation module 14 and is configured to receive a request to output data, generate an increment of a read pointer and send it to the register file 12.

The register file 12 is in communication with the input processing module 11 and the output processing module 13, respectively, and is configured to write the valid data to be written into the register according to the write pointer and update the write pointer according to an increment of the write pointer, and/or read the data to be output from the register according to the read pointer and update the read pointer according to an increment of the read pointer.

The first-in first-out buffer and the control method thereof provided by the application comprise: the device comprises an input processing module, a register file, an output processing module and a state generating module; the register file includes a plurality of registers as storage units; wherein the state generation module is in communication with the register file and is configured to determine state information including at least an amount of data remaining receivable by the register file; the input processing module is communicated with the state generating module and is configured to receive a request for inputting the multi-channel data and determine valid data to be written in the multi-channel data; determining the effective quantity of the writable data according to the quantity of the effective data to be written and the quantity of the remaining receivable data, generating an increment of a write pointer based on the effective quantity of the writable data, and sending the effective data to be written to a register file; the output processing module is communicated with the state generating module and is configured to receive a request for outputting data, generate an increment of a read pointer and send the increment to the register file; the register file is respectively communicated with the input processing module and the output processing module and is configured to write the effective data to be written into the register according to the write pointer and update the write pointer according to the increment of the write pointer, and/or read the data to be output from the register according to the read pointer and update the read pointer according to the increment of the read pointer.

Therefore, the scheme provided by the application adopts the register file as the storage unit, effective data in input data can be stored in the register file in sequence through the control of the write pointer, and as the area of the register is smaller than that of a multi-stage storage unit adopting an RAM, the first-in first-out of multi-path input data can be completed under the condition of small hardware overhead under the condition of smaller depth, so that the problem of waste of hardware storage resources when the depth is smaller in the existing scheme adopting the multi-stage storage unit can be avoided.

Fig. 2 is a schematic structural diagram of another embodiment of the fifo buffer according to the present application.

The input processing module 11 is configured to receive a request for inputting multiple paths of data, and the present embodiment takes N paths of input data as an example. The input processing module 11 receives a request for inputting N-way data, receives the N-way data, and determines the number VALID _ REQ _ NUM of VALID data to be written in the N-way data. Specifically, when the input request signal identifier is 1, it indicates that the input request is valid; when the input request signal flag is 0, it indicates that the input signal is invalid. In the N-way data requests, the number VALID _ REQ _ NUM to be written with VALID data may be determined according to the number statistics of the input requests with VALID identifiers.

The input processing module 11 obtains the amount ENTRY _ LEFT of the remaining receivable data of the register file 12 from the state generation module 14. Further, according to the amount VALID _ REQ _ NUM of VALID data to be written and the amount ENTRY _ LEFT of the remaining receivable data, a VALID amount VALID _ WNUM of writable data can be determined. The specific determination process is as follows: if the number VALID _ REQ _ NUM of VALID data to be written is greater than the number ENTRY _ LEFT of remaining receivable data of the register file, the VALID number VALID _ WNUM of writable data may be determined as the number ENTRY _ LEFT of remaining receivable data. Otherwise, in the case that the number VALID _ REQ _ NUM of VALID data to be written is not greater than the number ENTRY _ LEFT of data that can be received by the register file, the VALID number VALID _ WNUM of writable data is the number VALID _ REQ _ NUM of VALID data to be written.

And the input processing module inputs the valid data to be written from the lowest bit or the highest bit of the written data according to a preset sequence and from the starting position. And the register file determines the starting position of writing to the register according to the writing pointer, and inputs effective data to be written from the starting position, wherein the quantity of the input data is the same as the effective quantity of the writable data.

It is understood that the preset sequence is the position in the write data to the register file when multiple paths of input data come simultaneously, and the arrangement mode can be specified in advance, for example, the preset sequence can be arranged in a positive sequence or a negative sequence according to the size of the channel number. As a preferred embodiment, the write data converted to the register file may be tightly packed in a predetermined order, it being understood that tight packing means that there is no invalid data between every two valid data.

The input processing module is further configured to generate an increment delta of the write pointer based on the effective amount of the writeable data _WPTR The effective amount of write pointer WPTR VALID _ WNUM in the writable data>Increment delta from write pointer at 0 _WPTR Update, write pointer WPTR and delta _WPTR And adding after removing the highest bit, and if the addition result exceeds the boundary, turning over the highest bit of the write pointer WPTR. It will be appreciated by those skilled in the art that the write pointer WPTR may be incremented each time by a value of 1. In some embodiments, the value of the write pointer WPTR may also be increased each time (i.e., the increment of the write pointer) by more than 1, as desired. Specifically, the write pointer WPTR is represented by binary, the width of the write pointer is represented by log2(K) +1 bit, where K is the depth of the register file, log2(K) bit represents the position of write data with depth of K, 1 bit highest bit is additionally added for determining whether the write pointer loops around the boundary K, and the highest bit of the write pointer is inverted each time the write pointer crosses the boundary of K. Taking 8 as an example of the depth of the register file, the width of the write pointer is represented by a binary number of 4 bits, log2(K) +1 bit, where the extra highest bit is used to determine whether the write pointer loops around the boundary K. The write pointer at the start position is 0000, and when 8 data have been written, the highest bit of the write pointer is inverted from 0 to 1, that is, at this time, the write pointer WPTR is represented as: 1000.

the register file 12 is in communication with the input processing module 11 and the output processing module 13, respectively, and is configured to write valid data to be written into the register according to the write pointer and update the write pointer according to an increment of the write pointer, and/or read data to be output from the register according to the read pointer and update the read pointer according to an increment of the read pointer.

As a specific embodiment, the register file 12 is configured to determine a start position of writing to a register according to the write pointer, and the valid data to be written is input from the start position, and the input data is the same as the valid amount of the writable data.

In this embodiment, the register file 12 is a two-dimensional register matrix. If each path of the N paths of input data is M bits, the width of the register file is M, and when the depth of the register file is K, the depth K of the register file and the number N of the input paths should satisfy: k > -N, otherwise data is easily lost because the FIFO is full.

The output processing module 13 is configured to receive a request to output data, generate an increment of the read pointer and send it to the register file 12. The register file 12 reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer.

The output processing module 13 generates an increment delta of the read pointer _RPTR The read pointer RPTR is incremented by Δ according to the read pointer when the number of remaining receivable data ENTRY _ LEFT is greater than zero and a data output request is received _RPTR Updating, in particular, the read pointer RPTR and the increment Δ _RPTR And adding after removing the highest bit, and if the addition result exceeds the boundary, turning over the highest bit of the read pointer RPTR. In this embodiment, the value of the read pointer RPTR is 1 at each increment. Specifically, the read pointer may be represented by binary, and the width of the read pointer is represented by log2(K) +1 bit, where K is the depth of the register file, log2(K) bit represents the position of read data with depth of K, and the most significant bit of 1 bit is additionally added to determine whether the read pointer loops around the boundary K, and the most significant bit of the read pointer is inverted each time the read pointer crosses the boundary of K. Similarly, taking the depth of the register file as 8 as an example, the width of the read pointer is represented by using a log2(K) + 1-bit to 4-bit binary number, wherein the extra highest bit is used to determine whether the read pointer loops at the boundary K. The read pointer at the start position is 0000, and when 8 data have been read, the highest bit of the read pointer is inverted from 0 to 1, that is, the read pointer RPTR at this time is represented as: 1000; if 2 data have been read, the highest bit of the read pointer does not flip, and at this time, the read pointer RPTR is expressed as: 0010.

the state generation module 14 is configured to determine the amount of remaining receivable data ENTRY, and the amount of received data ENTRY, based on the write pointer, the read pointer, and the depth K of the register file.

When the highest bits of the write pointer and the read pointer are the same, the number of the residual receivable data ENTRY _ LEFT is K- (WPTR-RPTR); the amount of received data ENTRY _ USED is WPTR-RPTR. Wherein WPTR represents the value of the read pointer and RPTR represents the value of the write pointer.

When the highest bits of the write pointer and the read pointer are different, the number of the residual receivable data ENTRY _ LEFT is RPTR _ LSB-WPTR _ LSB; the amount of received data ENTRY USED is K- (RPTR _ LSB-WPTR _ LSB). And WPTR _ LSB represents a value of WPTR after the highest bit is removed, and RPTR _ LSB represents a value of RPTR after the highest bit is removed.

For example, the depth K of the register file is 8, the read and write pointers are each 4 bits, and the start data is 0000. If 8 data are written, the highest bit is flipped and the write pointer is 1000. If 2 data are read, the read pointer is 0010. Then the remaining number of receivable data, ENTRY _ LEFT ═ RPTR _ LSB-WPTR _ LSB — (010 —) 000 (in binary representation) is 2 (in decimal representation).

The first-in first-out buffer provided by the application supports multi-channel simultaneous input and single-channel output, and can support synchronization or asynchronization of the read-write clock, the read-write clock needs to be processed across clock domains during asynchronization, and the read-write clock does not need to be processed across clock domains during synchronization.

The state generating module 14 is further configured to, when the fifo buffer implements asynchronous input, convert binary read and write pointers into gray codes for representation, perform two-level register synchronization using the gray codes, convert the synchronized gray codes into binary, and implement cross-clock-domain processing of the read and write pointers. The synchronous FIFO is realized without the need of the cross-clock domain processing of the read-write pointer.

The status generation module 14 is further configured to generate empty status information, to-full status information, full status information.

Wherein the empty state information is generated when the number of received data ENTRY _ USED is 0.

And generating the to-be-empty state information when the number of received data ENTRY _ USED is less than or equal to a preset to-be-empty threshold value AEMPTY _ THRES.

The to-full state information is generated when the number of received data ENTRY _ USED is greater than or equal to a preset to-full threshold AFULL _ THRES.

The full state information is generated when the amount of received data ENTRY USED equals the depth of the register file.

In addition, the present application further provides a method for controlling a fifo buffer, which can be applied to the fifo buffer described above, and with reference to fig. 3, the method specifically includes:

s101: the input processing module receives a request for inputting multiple paths of data.

S102: the input processing module compares the quantity VALID _ REQ _ NUM of VALID data to be written with the quantity ENTRY _ LEFT of the remaining receivable data determined by the state generation module; if the quantity VALID _ REQ _ NUM of the VALID data to be written is greater than the quantity ENTRY _ LEFT of the remaining receivable data, the VALID quantity VALID _ WNUM of the writable data is the quantity ENTRY _ LEFT of the remaining receivable data; and if the quantity VALID _ REQ _ NUM of the VALID data to be written is not larger than the quantity ENTRY _ LEFT of the remaining receivable data, the VALID quantity VALID _ WNUM of the writable data is the quantity VALID _ REQ _ NUM of the VALID data to be written.

S103: and the input processing module generates an increment of a write pointer based on the effective quantity of the writable data and sends the effective data to be written to the register file.

S104: and the register file writes the effective data to be written into the register according to the write pointer and updates the write pointer according to the increment of the write pointer.

The register file acquires the position of the updated register according to the write pointer, and judges how many registers are updated backwards from the position starting from the write pointer according to the VALID amount VALID _ WNUM of the writable data.

On the basis of the foregoing embodiment, the method provided by the present application may further include: the output processing module receives a request for outputting data, generates an increment of a read pointer and sends the increment to the register file; and the register file reads the data to be output from the register according to the read pointer and updates the read pointer according to the increment of the read pointer.

And the output processing module generates the increment of the read pointer according to the request of the output data. And the register file feeds back the value of the corresponding position register to the output processing module according to the read pointer to be used as data to be output.

In the process, the status generating module 14 is used for generating status information to provide information for the fifo buffer for control.

FIG. 4 shows a data path diagram for a 4-way input data, first-in-first-out buffer of depth 10. Referring to fig. 4, the detailed operation of the fifo is described below with reference to the drawings.

In this embodiment, the input channel numbers are sorted from low to high, the row with the smaller input channel number is at the lowest position, and accordingly, the position in the register file is closest to the exit, so that the input channel numbers are output first.

For simplicity of description, only the case where data can only go in and out is considered:

in the first clock cycle, VALID data exists in the second, third and fourth ways, VALID _ REQ _ NUM is 3, and at this time, there is no data in the register file, so ENTRY _ LEFT is 10, ENTRY _ LEFT > VALID _ REQ _ NUM, so VALID _ WNUM is VALID _ REQ _ NUM is 3, all VALID data to be written are written into the register file, and the write pointer is incremented by 3.

In the second clock cycle, VALID data exists in the first and third paths, VALID _ REQ _ NUM is 2, and at this time, there are already 3 data in the register file, so ENTRY _ LEFT is 10-3-7, ENTRY _ LEFT > VALID _ REQ _ NUM, so VALID _ WNUM is VALID _ REQ _ NUM is 2, all VALID data to be written are written into the register file, and the write pointer is incremented by 2.

In the third clock cycle, VALID data exists in the first, second and fourth ways, VALID _ REQ _ NUM is 3, and at this time, there are 5 data already in the register file, so ENTRY _ LEFT is 10-5 to 5, ENTRY Y _ LEFT > VALID _ REQ _ NUM, so VALID _ WNUM is VALID _ REQ _ NUM 3, all VALID data to be written are written into the register file, and the write pointer is incremented by 3.

In the fourth clock cycle, the first, second and fourth paths have VALID data, VALID _ REQ _ NUM is 3, and at this time, there are already 8 data in the register file, so ENTRY _ LEFT is 10 "8 ═ 2, ENTRY _ LEFT < VALID _ REQ _ NUM, so VALID _ WNUM ═ ENTRY _ LEFT ═ 2, only the first and second paths of input data are written into the register file, the fourth path of data is lost, and the write pointer is incremented by 2.

The fifth clock cycle, since there is only input and no output, when the FIFO is full, ENT RY _ LEFT is 0, and all incoming data to be written is lost.

Considering the case of output:

if there is exactly one output request in the fourth cycle, the write pointer is incremented by 1, and ENTRY _ LEFT is also incremented by 1, where ENTRY _ LEFT is VALID _ REQ _ NUM is 3, and all three VALID input data are written into the register file, and the write pointer is incremented by 3.

The fifth cycle ENTRY LEFT is also 0 and the FIFO is full, all inputs are discarded if there is no output request.

The control method of the fifo buffer provided in the present application corresponds to the fifo buffer described above, and specific implementation contents can be referred to each other, and are not described herein again.

While various embodiments of aspects of the present application have been described for purposes of this disclosure, they are not to be construed as limiting the teachings of the present disclosure to these embodiments. Features disclosed in one particular embodiment are not limited to that embodiment, but may be combined with features disclosed in different embodiments. For example, one or more features and/or operations of a method according to the present application described in one embodiment may also be applied, individually, in combination, or in whole, in another embodiment. It will be understood by those skilled in the art that there are many more alternative embodiments and variations possible and that various changes and modifications may be made to the system described above without departing from the scope defined by the claims of the present application.

Claims

1. A fifo buffer, comprising: the device comprises an input processing module, a register file, an output processing module and a state generating module; the register file comprises a plurality of registers as storage units;

the input processing module is communicated with the state generating module and is configured to receive a request for inputting multi-channel data and determine valid data to be written in the multi-channel data; determining the effective quantity of writable data according to the quantity of the effective data to be written and the quantity of the residual receivable data, generating an increment of a write pointer based on the effective quantity of the writable data, and sending the effective data to be written to the register file;

2. A fifo buffer according to claim 1, wherein the register file is configured to determine a start position of writing to a register from which the valid data to be written is input according to the write pointer, the amount of data input being the same as the valid amount of the writable data.

3. The fifo buffer of claim 2, wherein the input processing module is further configured to: and inputting the valid data to be written from the starting position according to a preset sequence.

4. The fifo buffer of claim 3, wherein the predetermined order is a positive order or a negative order in accordance with a size of a channel number, starting from a lowest order or a highest order of the valid data to be written.

5. The fifo of claim 1, wherein the fifo supports synchronization or asynchrony of read and write clocks, wherein the read and write clocks need to be processed across clock domains when asynchronous, and wherein the read and write clocks do not need to be processed across clock domains when synchronous.

6. The fifo buffer of claim 1, wherein the register file is a two-dimensional register matrix.

7. The FIFO buffer of claim 6, wherein the write pointer is represented in binary, and the width of the write pointer is represented by log2(K) +1 bit, where K is the depth of the register file, log2(K) bit represents the position of write data with depth K, and 1 bit most significant bit is added to determine whether the write pointer loops around the boundary K, and the most significant bit of the write pointer is flipped each time the write pointer crosses the boundary of K.

8. The fifo of claim 7, wherein the write pointer is updated when the effective amount of writable data is greater than zero, each increment being by the effective amount of writable data.

9. The fifo buffer of claim 8, wherein the read pointer is represented in binary, the width of the read pointer is represented by log2(K) +1 bit, where K is the depth of the register file, log2(K) bit represents the location of read data with depth K, and 1 bit most significant bit is added to determine whether the read pointer loops around the boundary K, and the most significant bit of the read pointer is flipped each time the read pointer crosses the boundary of K.

10. The fifo buffer of claim 9, wherein the read pointer is updated each time a data output request is received with an increment of 1 when the amount of receivable data remaining is greater than zero.

11. The fifo buffer of claim 10, wherein the state generation module is configured to determine the amount of remaining receivable data based on the write pointer, the read pointer, and the depth K of the register file:

12. A fifo buffer as recited in any one of claims 7-11, wherein the state generation module is further configured to convert binary read and write pointers into gray codes for representation and two-stage register synchronization using the gray codes to convert synchronized gray codes into binary when the fifo buffer implements asynchronous input.

13. The fifo buffer of any of claims 1-11, wherein the state generation module is further configured to generate empty state information, to-full state information;

generating the to-be-empty state information when the number of the received data is less than or equal to a preset to-be-empty threshold value;

14. A method for controlling a fifo buffer, applied to the fifo buffer according to any one of claims 1 to 13, the method comprising:

and the register file writes the valid data to be written into the register according to the write pointer.

15. The method of controlling a fifo buffer of claim 14, further comprising: