CN118132474A - DMA-based data transmission system - Google Patents
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- CN118132474A CN118132474A CN202410387697.6A CN202410387697A CN118132474A CN 118132474 A CN118132474 A CN 118132474A CN 202410387697 A CN202410387697 A CN 202410387697A CN 118132474 A CN118132474 A CN 118132474A
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Abstract
The invention relates to the technical field of data transmission, in particular to a data transmission system based on DMA, which comprises a software module and a hardware module, wherein the software module comprises N first storage areas and R second storage areas; the hardware module comprises a DMA engine, N first transmission channels and R second transmission channels; the DMA engine is respectively connected with the software module, the N first transmission channels and the R second transmission channels; the software module is used for storing data D n into the HM n; the DMA engine is used for acquiring data D n and caching D n into PF n of P n; p n is used to transmit D n in the PF n to the first target device; q r is configured to receive data E r in the second target device, and buffer E r in QF r of Q r; the DMA engine is used for transmitting E r to the software module; the software module is used to store E r into CM r. The invention reduces the DMA transmission delay and improves the effective transmission rate of the data.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a data transmission system based on DMA.
Background
In the existing data transmission system, in the process of executing data handling (DMA), the DMA operation is usually required to be initiated by software, and frequent interaction is required between software and hardware, so that the DMA transmission delay is increased. In the existing data transmission system, data is transmitted through a data channel from software to the tail end of a system bus, and once a data channel is blocked, the normal operation of the software is affected, so that the effective transmission rate of data is reduced. Therefore, how to reduce the DMA transfer delay and improve the effective data transfer rate is a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a data transmission system based on DMA, which reduces DMA transmission delay and improves the effective transmission rate of data.
According to a first aspect of the present invention, there is provided a DMA-based data transmission system, comprising a software module and a hardware module, the software module comprising N first storage areas { HM 1,HM2,…,HMn,…,HMN } and R second storage areas { CM 1,CM2,…,CMr,…,CMR }, wherein HM n is the nth first storage area, N has a value ranging from 1 to N, CM r is the R second storage area, and R has a value ranging from 1 to R;
The hardware module comprises a DMA engine, N first transmission channels { P 1,P2,…,Pn,…,PN }, R second transmission channels { Q 1,Q2,…,Qr,…,QR},Pn are nth first transmission channels, Q r are nth second transmission channels, corresponding buffers PF n,Qr are arranged in P n, and corresponding buffers QF r are arranged in P n;
the DMA engine is respectively connected with the software module, the N first transmission channels and the R second transmission channels;
the software module is used for storing data D n into the HM n;
The DMA engine is used for acquiring data D n and caching D n into PF n of P n;
P n is used to transmit D n in the PF n to the first target device;
Q r is configured to receive data E r in the second target device, and buffer E r in QF r of Q r;
the DMA engine is used for carrying Er into the CM r;
The software module is used to read E r from CM r.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the DMA-based data transmission system provided by the invention can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects:
The system divides DMA transmission into a stage of transmission in a software module, a stage of transmission in a hardware module and a stage of transmission from the hardware stage to the target equipment, the blockage of any one stage does not directly influence the data transmission process of other transmission stages, and the effective transmission rate of data is improved under the condition of a certain bandwidth. In addition, the system reduces the interaction process of the hardware module and the software module and reduces the DMA transmission delay.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a DMA-based data transmission system according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a DMA-based data transmission system, as shown in fig. 1, comprising a software module and a hardware module, wherein the software module comprises N first storage areas { HM 1,HM2,…,HMn,…,HMN } and R second storage areas { CM 1,CM2,…,CMr,…,CMR }, HM n is the nth first storage area, the value range of N is 1 to N, and N is the total number of the first storage areas. CM r is the R second storage area, the value range of R is 1 to R, and R is the total number of the second storage areas.
The hardware module includes DMA (Data Memory Access) engines, N first transmission channels { P 1,P2,…,Pn,…,PN }, R second transmission channels { Q 1,Q2,…,Qr,…,QR},Pn is an nth first transmission channel, Q r is an nth second transmission channel, and a corresponding buffer QF r,PFn、QFr may be specifically set as a FIFO in P n in which a corresponding buffer PF n,Qr is set. The corresponding buffer is arranged in each transmission channel, so that the data transmission of the hardware module is not affected no matter the software module is temporarily blocked or the path from the hardware module to the target equipment is temporarily blocked, and in addition, the normal operation of the software module is not affected even if the path from the hardware module to the target equipment is temporarily blocked. N is less than or equal to K-1, R is less than K-1, K is the number of communication channels corresponding to DMA, and one communication channel can be provided with a first transmission channel and a second transmission channel at the same time. It should be noted that one of the channels of the DMA, which is required for use in configuring registers of the hardware module at the initial time, cannot be provided with the first transfer channel and the second transfer channel. Some state information of the hardware module needs to be transmitted to the software module, so that a channel which has the same direction as the second transmission channel in one communication channel needs to be occupied, and a first transmission channel can be arranged in the channel, so that N is less than or equal to K-1 and R is less than or equal to K-1.
The DMA engine is respectively connected with the software module, the N first transmission channels and the R second transmission channels. The system mainly executes the operation of DMA data writing and the operation of DMA data reading. The software module is used to store data D n into HM n, and it should be noted that D n generally refers to all data that needs to be stored in HM n. The DMA engine is used for acquiring data D n and caching D n into PF n of P n; p n is used to transmit D n in the PF n to the first target device; thereby realizing the operation of writing data by DMA. Q r is used to receive data E r,Er in the second target device, which generally refers to all data that needs to be stored to the CM r. Buffer E r into QF r of Q r; the DMA engine is used for carrying Er into the CM r; the software module is used for reading E r from the CM r; thereby realizing the operation of DMA data reading. The first target device and the second target device may be the same device or different devices. In the example of fig. 1, the simplification process is performed to simplify the first target device and the second target device by one target device, but it is understood that the target device is not limited to only one, and the first target device and the second target device may be different target devices.
It should be noted that, the system divides the DMA transfer into a stage of transferring in the software module, a stage of transferring in the hardware module, and a stage of transferring the hardware stage to the target device, and the blocking of any one stage does not directly affect the data transfer process of other transfer stages, thereby improving the effective transfer rate of the data.
The system of the embodiment of the invention reduces the interaction between the hardware module and the software module and reduces the DMA delay. To further reduce interdependence between hardware and software modules, data transfer may be accomplished by maintaining pointers without requiring frequent interaction of the hardware and software modules, as one embodiment, HM n includes corresponding Producer (Producer) and Consumer (Consumer) pointers HC n and HC n,HPn to the address of the HM n where the currently stored data arrives, and HC n to the address of the HM n where the currently read data arrives; the software modules are used for maintaining HP n and CC r; the hardware module is used to maintain HC n and CP r. Wherein the producer is the party generating the data and the consumer is the party using the data. CM r includes a corresponding producer pointer CP r and consumer pointer CC r,CPr for pointing to the address in CM r where the currently stored data arrives, and CC r for pointing to the address in CM r where the currently read data arrives. According to the producer and consumer pointers corresponding to each storage area, whether data can be read currently or not and whether the storage space can continue writing data currently or not can be judged.
As one embodiment, the system is in the process of performing DMA write operations:
The software module is configured to write D n to HM n based on HP n and HC n, update HP n, and synchronize the updated HP n to the hardware module. Based on HP n and HC n, it may be determined whether there is currently enough space to write to D n.
The hardware module is used for comparing HC n with HP n, judging whether D n to be carried exists in HM n currently, if so, judging whether a storage space corresponding to D n to be carried exists in PF n currently, and if so, initiating an operation instruction of carrying D n in a software direction towards a hardware direction by the DMA engine; the carrying data of the software direction towards the hardware direction is initiated by the hardware module, and the carrying data does not need to be initiated by the software module, so that the interaction between the software and the hardware is reduced.
The DMA engine is configured to obtain a D n to be carried based on an operation instruction of a carrying D n in a software direction toward a hardware direction, cache the D n to be carried into a PF n of P n, update HC n by the hardware module, and synchronize the updated HC n to the software module.
As one embodiment, the system is in the process of performing DMA read operations:
The software module is configured to read data from CM r based on CC r and CP r, update CC r, and synchronize updated CC r to the hardware module. Based on CC r and CP r, it may be determined whether readable E r is currently present, and if so, data is read from CM r and CC r is updated.
The hardware module is used for comparing the current CC r with the CP r, judging whether a storage space corresponding to E r to be carried exists in the CM r currently, if so, judging whether a storage space corresponding to E r to be carried exists in the QF r, and if so, the DMA engine initiates an operation instruction of carrying E r in the hardware direction towards the software direction; the operation instruction of the handling E r with the hardware direction facing the software direction is initiated by the hardware module, and the operation instruction is not initiated by the software module, so that the interaction between the software and the hardware is reduced.
The DMA engine is configured to obtain E r to be handled from the second target device based on an operation instruction of handling E r in a hardware direction toward a software direction, cache E r to be handled in QF r of Q r, and further handle E r from QF r to CM r.
The software module is configured to read E r from CM r to complete the DMA read operation.
After the hardware module completes the DMA read operation, the CP r is updated, and the updated CP r is synchronized to the software module.
As an embodiment, the software module further comprises a third storage area SM, and the hardware module further comprises a state register, a state information transmission channel, and a control state machine QL r corresponding to a control state machine PL n、Qr corresponding to P n, where each PL n and QL r is connected to the state information transmission channel.
The status register is used to store updated HP n and current CC r sent by the latest software module, so that the hardware module can obtain the latest HP n and CC r.
The PL n is configured to obtain the updated HC n, and transmit the updated HC n to the SM of the software module through the status information transmission channel; note that, the HC n may also carry the identifier of the corresponding transmission channel.
The QL r is configured to obtain an updated CP r, and transmit the updated CP r to the SM of the software module through the state information transmission channel; it should be noted that the CP r may also carry the identifier of the corresponding transmission channel.
As one embodiment, the software module includes a state acquisition thread that is used to poll the SM to acquire HC n and CP r in the SM. It should be noted that, the state acquisition thread is adopted to poll the SM, so that the host CPU is not frequently intended, and the utilization rate of the CPU can be improved.
As an embodiment, the DMA engine is XDMA engine, XDMA includes a first communication channel of 4 communication channels { CH 1,CH2,CH3,CH4},CH1 being XDMA, for configuring a hardware module, specifically, a configuration register, at an initial time. CH 2 is the second communication channel of XDMA, CH 2 includes the third communication channel of HM 1 and CM 1,CH3 is XDMA, CH 3 includes the third communication channel of HM 2 and CM 2,CH4 is XDMA, and the status information transmission channel is provided in CH 4.
As an embodiment, the DMA engine is based on PCIE bus communication. The PCIE bus can further increase the data transmission rate.
For different transmission channels, the different transmission channels can be selected and used according to the use conditions of the different transmission channels, and the different channels can be divided according to the data priority, so that the data transmission efficiency is further improved. As an embodiment, CH 2 is used to transmit data with highest priority, and CH 3 is used to transmit data other than the highest priority data.
As an embodiment, the system includes a routing module, where the routing module is connected to the hardware module and the target device, and the routing module is configured to transmit D n in the PF n transmitted by the hardware module to the first target device, or receive data E r in the second target device, and transmit E r to the hardware module, where it needs to be noted that, through the routing module, any one target device may perform data handling with any one storage area of the software module.
The system of the embodiment of the invention divides DMA transmission into a stage of transmission in a software module, a stage of transmission in a hardware module and a stage of transmission from the hardware stage to the target equipment, the blockage of any one stage does not directly influence the data transmission process of other transmission stages, and the effective transmission rate of data is improved under the condition of a certain bandwidth. In addition, the system reduces the interaction process of the hardware module and the software module and reduces the DMA transmission delay.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (10)
1. A DMA-based data transfer system, characterized in that,
The device comprises a software module and a hardware module, wherein the software module comprises N first storage areas { HM 1,HM2,…,HMn,…,HMN } and R second storage areas { CM 1,CM2,…,CMr,…,CMR }, wherein HM n is an nth first storage area, the value range of N is 1 to N, CM r is an nth second storage area, and the value range of R is 1 to R;
The hardware module comprises a DMA engine, N first transmission channels { P 1,P2,…,Pn,…,PN }, R second transmission channels { Q 1,Q2,…,Qr,…,QR},Pn are nth first transmission channels, Q r are nth second transmission channels, corresponding buffers PF n,Qr are arranged in P n, and corresponding buffers QF r are arranged in P n;
the DMA engine is respectively connected with the software module, the N first transmission channels and the R second transmission channels;
the software module is used for storing data D n into the HM n;
The DMA engine is used for acquiring data D n and caching D n into PF n of P n;
P n is used to transmit D n in the PF n to the first target device;
Q r is configured to receive data E r in the second target device, and buffer E r in QF r of Q r;
The DMA engine is to handle E r into CM r;
The software module is used to read E r from CM r.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
HM n includes corresponding producer pointer HP n and consumer pointer HC n,HPn, which is the address in HM n where the currently stored data arrives, and HC n, which is the address in HM n where the currently read data arrives;
CM r includes corresponding producer pointer CP r and consumer pointer CC r,CPr for pointing to the address in CM r where the currently stored data arrives, and CC r for pointing to the address in CM r where the currently read data arrives;
The software modules are used for maintaining HP n and CC r;
the hardware module is used to maintain HC n and CP r.
3. The system of claim 2, wherein the system further comprises a controller configured to control the controller,
The system performs a DMA write operation during the course of performing the DMA write operation:
The software module is configured to write D n to HM n based on HP n and HC n, update HP n, and synchronize the updated HP n to the hardware module;
The hardware module is used for comparing HC n with HP n, judging whether D n to be carried exists in HM n currently, if so, judging whether a storage space corresponding to D n to be carried exists in PF n currently, and if so, initiating an operation instruction of carrying D n in a software direction towards a hardware direction by the DMA engine;
The DMA engine is configured to obtain a D n to be carried based on an operation instruction of a carrying D n in a software direction toward a hardware direction, cache the D n to be carried into a PF n of P n, update HC n by the hardware module, and synchronize the updated HC n to the software module.
4. The system of claim 2, wherein the system further comprises a controller configured to control the controller,
The system performs a DMA read operation during the process:
The software module is used for reading data from the CM r based on the CC r and the CP r, updating the CC r and synchronizing the updated CC r to the hardware module;
The hardware module is used for comparing the current CC r with the CP r, judging whether a storage space corresponding to E r to be carried exists in the CM r currently, if so, judging whether a storage space corresponding to E r to be carried exists in the QF r, and if so, the DMA engine initiates an operation instruction of carrying E r in the hardware direction towards the software direction;
The DMA engine is configured to acquire an E r to be handled from a second target device based on an operation instruction of handling the E r in a hardware direction toward a software direction, cache the E r to be handled in QF r of Q r, and further handle the E r from QF r to CM r;
The software module is used for reading E r from the CM r and finishing DMA reading operation;
after the hardware module completes the DMA read operation, the CP r is updated, and the updated CP r is synchronized to the software module.
5. The system of claim 2, wherein the system further comprises a controller configured to control the controller,
The software module further comprises a third storage area SM, and the hardware module further comprises a status register, a status information transmission channel and a control state machine QL r corresponding to a control state machine PL n、Qr corresponding to P n, wherein each PL n and QL r is connected with the status information transmission channel;
The status register is configured to store the updated HP n and the current CC r sent by the latest software module;
The PL n is configured to obtain the updated HC n, and transmit the updated HC n to the SM of the software module through the status information transmission channel;
QL r is configured to obtain an updated CP r, and transmit the updated CP r to the SM of the software module through the state information transmission channel.
6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
The software module includes a state acquisition thread for polling the SM to acquire HC n and CP r in the SM.
7. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
The DMA engine is XDMA engine, XDMA includes a first communication channel of 4 communication channels { CH 1,CH2,CH3,CH4},CH1 is XDMA, for configuring the hardware module at the initial time, a second communication channel of CH 2 is XDMA, CH 2 includes a third communication channel of HM 1 and CM 1,CH3 is XDMA, CH 3 includes a third communication channel of HM 2 and CM 2,CH4 is XDMA, and the status information transmission channel is set in CH 4.
8. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
CH 2 is used to transmit data with highest priority, and CH 3 is used to transmit data other than the highest priority data.
9. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The DMA engine communicates based on a PCIE bus.
10. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
The system comprises a routing module, wherein the routing module is connected with the hardware module and the target equipment, and is used for transmitting D n in PF n transmitted by the hardware module to the first target equipment or receiving data E r in the second target equipment and transmitting E r to the hardware module.
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