CN117080257A - Double-junction field effect transistor and preparation method thereof - Google Patents
Double-junction field effect transistor and preparation method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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Abstract
The invention relates to a double-junction field effect transistor and a preparation method thereof, wherein the double-junction field effect transistor comprises the following components: substrate, p-type Te nano-sheet and n-type MoS 2 The device comprises a nanosheet, a source electrode, a drain electrode, a top gate electrode and a substrate gate electrode; the p-type Te nano-sheet is arranged on the surface of the substrate, and the n-type Te nano-sheet is arranged on the surface of the substrateMoS 2 The nano-sheets are arranged in the Te nano-sheets in an interpenetration way and are intersected with the Te nano-sheets, and the Te nano-sheets are intersected with the MoS 2 The vertical double van der Waals heterojunction is formed between the nano sheets; te and MoS are combined in the invention 2 Applied to a junction transistor (JFET), the p-type Te nano-sheet and MoS are realized by regulating and controlling the grid voltage of the p-type Te nano-sheet 2 The depth of the depletion regions of the two formed p-n junction van der Waals heterojunction regions can realize the adjustment of the electrical properties of the depletion regions, and the device has the electrical properties of lower subthreshold swing, high switching ratio and the like.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a double-junction field effect transistor and a preparation method thereof.
Background
With tungsten disulfide and MoS 2 Two-dimensional Transition Metal Sulfides (TMDCs), which are representative, are considered to be extremely potential semiconductor materials due to their superior mechanical properties with atomic-scale thickness, adjustable band gap, and no surface dangling bonds. Te is used as an emerging element semiconductor material, has a direct band gap of about 0.35eV, has very high hole carrier mobility, and has a narrow band gap, so that Te can show effective light response in a near infrared band and has wide prospects in the application fields of photodetectors, field effect transistors and the like.
In recent years, as silicon-based semiconductor processes continue to advance, transistor sizes have approached physical limits, and semiconductor devices have faced challenges of short channel effects, increased drain-gate leakage currents, and increased power consumption. Metal-oxide semiconductor field effect transistors (MOSFETs) are widely used in the electronics field due to their high resistance, high operating efficiency, good thermal stability, etc. In practice, however, the quality of the MOSFET oxide dielectric severely limits its electrical performance and stability. The JFET has the advantages of small device size, low frequency noise, high input impedance and the like, and has wide application prospects in the fields of integrated circuits, photodetectors and the like. In the JFET, the Subthreshold Swing (SS) of the JFET can be close to an ideal value of 60mV/dec without complex dielectric engineering because the capacitance from the grid electrode to the channel is far greater than the capacitance from the source electrode to the channel, and the JFET can be better used in low-power consumption devices.
At present, a two-dimensional material heterojunction is reported to be made into a JFET (junction field effect transistor) and applied to the fields of photoelectricity and low-power consumption devices. However, in the existing work, researchers all use some Transition Metal Sulfide (TMDCs) two-dimensional materials to make heterojunctions and build single heterojunction JFET devices, which have obvious disadvantages in performance, such as large Subthreshold Swing (SS), lower switching ratio, etc.
Disclosure of Invention
The primary object of the present invention is to provide a Dual junction field effect transistor (Dual-JFET) and a method for manufacturing the same. The double-junction field effect transistor combines a two-dimensional p-type Te nano-sheet without surface dangling bond with a two-dimensional n-type MoS 2 The nano-sheets are combined to construct a p-n junction, and n-type MoS is adopted 2 The nano sheet is used as a channel to be arranged in an upper Te nano sheet and a lower Te nano sheet to form a double heterojunction with an upper vertical structure, and a Dual-JFET with novel structure and high performance and n-type MoS are constructed based on the double heterojunction 2 The nano-sheet channel is contacted with the p-type Te nano-sheet to form a van der Waals heterojunction, so that the interface defect is effectively avoided, the purity of the interface is ensured, the influence of an interface state on carrier transportation is reduced, and by means of the advantage that JFET has no complex dielectric engineering, stable and lower subthreshold swing (high switching speed), lower pinch-off voltage and turn-off current can be obtained at room temperature, the current switching ratio of the device is improved, and the performance of the device is improved.
In order to achieve the above purpose, the present invention adopts at least the following technical scheme:
an aspect of the present invention provides a double junction field effect transistor, including a substrate, an insulating layer disposed on the substrate, a p-type Te nano-plate disposed on the insulating layer, and an n-type MoS interposed in the Te nano-plate and intersecting the Te nano-plate 2 A nano-sheet channel, the Te nano-sheet and the MoS 2 The vertical double van der Waals heterojunction is formed between the nano sheets;
source and drain electrodes respectively arranged on the MoS 2 The first top gate electrode and the second top gate electrode are respectively arranged on the two ends of the Te nano-plate;
the double-junction field effect transistorThe subthreshold swing of the body tube is less than or equal to 86mV/dec, and the current switching ratio is greater than or equal to 10 4 。
Further, the Te nano-sheet is formed by stacking a first Te nano-sheet and a second Te nano-sheet, and the MoS 2 The nanoplatelets are disposed between the first Te nanoplatelets and the second Te nanoplatelets.
Further, the second Te nano-plate is arranged on the MoS 2 And the first top gate electrode and the second top gate electrode are respectively arranged on two ends of the second Te nano-plate on the nano-plate.
Further, the thickness of the Te nano-sheet is 10 nm-100 nm; preferably, the thickness of the Te nano-plate is 60nm-100nm.
Further, the MoS 2 The thickness of the nano sheet is 10 nm-100 nm; preferably, the MoS 2 The thickness of the nano-sheet is 10 nm-60 nm.
Further, the substrate is a Si substrate, and the Si substrate is a bottom gate electrode.
Further, the insulating layer is made of SiO 2 、Al 2 O 3 BN or SiN x 。
Further, at least one of the source electrode, the drain electrode and the top gate electrode is selected from Cr, ti, ni, au, pd, pt, and the thickness of the electrode is 40 nm-100nm.
Another aspect of the present invention provides a method for manufacturing a dual junction field effect transistor, comprising the steps of:
preparing a first p-type Te nano-plate and a second p-type Te nano-plate on a substrate with an insulating layer;
transfer of n-type MoS on Polydimethylsiloxane (PDMS) by mechanical lift-off process 2 A nanosheet;
subjecting the n-type MoS to 2 Transferring the nano sheet to the first p-type Te nano sheet to form Te/MoS in a cross shape with the first p-type Te nano sheet 2 A p-n junction;
transferring the second p-type Te nano-plate to the p-n junction by adopting PDMS/PVA transfer technology to form a nano-plate with the n-type MoS 2 The nano-sheets are cross-shapedForm Te/MoS 2 Vertical double heterojunction of Te;
at the n-type MoS 2 And preparing a source electrode and a drain electrode on the nano-sheet, preparing a first top gate electrode and a second top gate electrode on the second p-type Te nano-sheet, and taking the substrate as a bottom gate electrode.
Further, a first p-type Te nano-plate and a second p-type Te nano-plate are prepared on the substrate with the insulating layer by adopting a solution spin coating method.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention adopts a transfer method to select the p-type Te nano-sheet and the n-type MoS without surface dangling bonds by selecting materials 2 Two-dimensional semiconductor combination of nano-sheet, preparation of Dual-JFET, n-type MoS 2 The nanosheets are used as channels, so that interface defects are effectively avoided, the purity of an interface is ensured, the influence of interface states on carrier transport is reduced, and n-type MoS is adopted by virtue of the advantages of the JFET without complex dielectric engineering 2 The nano-sheet is used as a double-junction device constructed by a channel, and stable and lower subthreshold swing SS (less than or equal to 86 mV/dec) and lower turn-off current (10 -10 A) Higher current On/Off ratio (greater than 10 4 ) And a pinch-off voltage of-1V. The method has great advantages in the application of low-power-consumption high-performance devices, and simultaneously provides a new structure for the development and application of the transistors. The preparation method is simple and easy to operate, and has good controllability.
Drawings
Fig. 1 is a schematic structural diagram of a dual junction field effect transistor according to an embodiment of the present invention.
Fig. 2 is an optical microscopic image of a double junction field effect transistor prepared according to an embodiment of the present invention.
Fig. 3 is a graph of top gate electrical transfer characteristics of a dual junction field effect transistor according to an embodiment of the present invention.
Fig. 4 is a graph showing electrical output characteristics of a dual junction field effect transistor according to an embodiment of the present invention.
Fig. 5 is a graph of top gate subthreshold swing characteristics of a dual junction field effect transistor according to an embodiment of the present invention.
Fig. 6 is a graph of sub-threshold swing characteristics of a dual junction field effect transistor incorporating both a top gate electrode and a substrate gate electrode in accordance with an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. Based on the embodiments of the present invention, other embodiments that may be obtained by those of ordinary skill in the art without making any inventive effort are within the scope of the present invention. The preparation methods described in the following examples are all conventional methods unless otherwise specified; the reagents and materials, unless otherwise specified, are commercially available from the public sources.
Spatially relative terms, such as "under", "below", "lower", "above", "upper" and the like, may be used herein to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures.
In addition, the use of terms such as "first," "second," etc. to describe various elements, layers, regions, sections, etc. are not intended to be limiting. The use of "having," "containing," "including," etc. are open ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly dictates otherwise.
Fig. 1 is a schematic structural diagram of a dual junction field effect transistor according to an embodiment of the present invention, which includes a substrate 1, and an insulating layer 2 disposed on the substrate 1. In this embodiment, the substrate 1 is Si substrate, and the insulating layer 2 is SiO 2 Insulating layer, in other embodiments, the insulating layer 2 is Al 2 O 3 BN or SiN x 。
A first p-type Te nano-sheet 3 is disposed on the insulating layer 2, and a second p-type Te nano-sheet 4 is disposed on the first p-type Te nano-sheet 3, in this embodiment, the second p-type Te nano-sheet 4 is disposed overlapping the first p-type Te nano-sheet 3; alternatively, in other embodiments, the first p-type Te nanoplatelets 3 partially overlap with the second p-type Te nanoplatelets 4. The thickness of the p-type Te nano-plate is 10nm to 100nm, more preferably, the thickness thereof is 60nm to 100nm.
n-type MoS 2 The nano-sheet 5 is arranged between the first Te nano-sheet 3 and the second Te nano-sheet 4, and the n-type MoS 2 The thickness of the nanoplatelets is 10nm to 100nm, more preferably, the thickness thereof is 10nm to 60nm.
First Te nano-sheet 3 and MoS 2 Nanoplatelets 5 and MoS 2 The nano sheet 5 and the second Te nano sheet 4 form two van der Waals p-n junctions with vertical structures to form an upper heterojunction and a lower heterojunction, and the upper heterojunction and the lower heterojunction are overlapped on a projection surface to form Te/MoS with novel structure and high performance 2 A Te double junction field effect transistor.
A source electrode 6 and a drain electrode 7 arranged on MoS 2 The first top gate electrode 8 and the second top gate electrode 9 are arranged at the two ends of the second Te nano-plate 4, and one or a combination of a plurality of Cr, ti, ni, au, pd, pt is selected as the source electrode, the drain electrode and the first top gate electrode, and the thickness of the first top gate electrode and the second top gate electrode is 40 nm-100nm.
Examples
In the present embodiment, moS 2 The thickness of the nano-sheets was 50nm, and the thicknesses of the first Te nano-sheets and the second Te nano-sheets were each 70nm.
Firstly, silicon dioxide/silicon chips are selected as substrates, ethanol, acetone and deionized water are respectively used for ultrasonic treatment for 5 minutes, then the substrates are subjected to heat treatment for 1 hour on a heating table at 300 ℃, and then the substrates are kept in a dry environment.
Then, the Te liquid synthesized by the hydrothermal method is spin-coated on the SiO by a spin coater 2 On the Si substrate, the spin-coating was performed at 5000rpm for 1 minute. And then cleaning the substrate with the Te spin coating liquid in deionized water to remove superfluous spin coating liquid on the surface, and drying by a nitrogen gun to obtain the required p-type Te nano-sheet on the surface of the substrate.
Next, a smooth-surfaced PDMS (polydimethylsiloxane) film was attached to the upper surface of the slide glass, and the slide glass was prepared with n-type MoS obtained by mechanical peeling 2 Adhesive tape of sample, adhesive tape is tightly adheredAdhesion to PDMS to n-type MoS 2 The sample is contacted with PDMS, the adhesive tape is taken down, and n-type MoS is formed 2 The nanoplates were attached to PDMS.
Slide glass is rotated to load n-type MoS on PDMS 2 The nano-sheet faces downwards, and the glass slide is arranged on a three-dimensional displacement platform; observed by microscope, n-type MoS 2 The nano-sheets are aligned to the target area to be transferred (namely the selected first p-type Te nano-sheet area), and the PDMS is gradually close to the n-type MoS through a three-dimensional displacement platform 2 The nanosheets contact the target region while heating the substrate and gradually raising the slide to n-type MoS 2 Separation of nanosheets from PDMS, n-MoS 2 The nano sheet is pressed on the first p-type Te nano sheet to obtain Te/MoS 2 A p-n junction.
After that, PDMS coated with PVA was attached to a slide glass, placed on a heating table, and heated at 70 ℃ for 5 minutes to wait for PVA to solidify. Rotating the glass slide to enable the PDMS attached with the PVA to face downwards, and mounting the glass slide on a three-dimensional displacement platform; observing through a microscope, aligning PVA with a target area to be transferred, gradually approaching PDMS through a three-dimensional displacement platform, enabling the PVA to contact a second p-type Te nano-plate, and simultaneously heating a substrate; gradually lifting the glass slide after waiting for a few minutes to separate the PVA from the PDMS; the PVA was removed from the wafer and reattached to PDMS and the second p-type Te nanoplatelets had been transferred to PVA.
Next, the PVA with the second p-type Te nano-plate adhered thereto is transferred to the Te/MoS 2 On the p-n junction. Rotating the slide glass to enable the surface of the PDMS carrying the second p-type Te nano-sheet to face downwards, and mounting the slide glass on a three-dimensional displacement platform; by microscopic observation, the Te nano-plate is aligned to the target to be transferred, PDMS is gradually close to the target by a three-dimensional displacement platform, and a second p-type Te nano-plate is contacted with Te/MoS 2 On the p-n junction, form MoS 2 a/Te p-n junction while heating the substrate; after waiting for a few minutes, the slide is gradually lifted to separate the substrate from the PDMS and complete the transfer. And then placing the substrate carrying the target material into deionized water, standing for 30 minutes, and removing superfluous PVA on the surface. Te/MoS as described above 2 p-n junction and MoS 2 the/Te p-n junction is overlapped on the projection plane to form vertical Te/MoS 2 Te double Van der Waals heterojunction.
Subsequently, photoresist is spin coated on the substrate, and a source electrode pattern, a drain electrode pattern, and a top gate electrode pattern are prepared using an electron beam exposure technique. Sequentially depositing a 10nm Cr layer and a 40nm Au layer on the source electrode pattern, the drain electrode pattern and the top gate electrode pattern by adopting an electron beam evaporation technology; then, placing the substrate on which the Cr and Au layers are evaporated in acetone for cleaning, removing redundant metal films, cleaning residual acetone by isopropanol, and blow-drying by a nitrogen gun; obtaining Te-based nano-sheets and MoS 2 A nano-sheet double junction field effect transistor is shown in fig. 2.
And finally, scribing the selected area on the surface of the substrate by using a diamond pen, wherein the exposed silicon substrate is used as a bottom gate.
The dual junction field effect transistor prepared in this example utilizes n-type MoS 2 The electrical properties of the transistor were tested with the nanoflakes as channels and the Te nanoflakes as top gates, and the test results are shown in fig. 3-6.
FIG. 3 shows a Te/MoS based 2 Junction gate transfer characteristic of a/Te double junction field effect transistor (Dual-JFET). As can be seen from fig. 3: the threshold voltage was-1V and the sub-threshold swing was calculated to be 68.3mV/dec.
Fig. 4 shows the output characteristic of a double junction field effect transistor. As can be seen from fig. 4, the device is at a top gate voltage V tg In the case of =0v and-1V, both show good current saturation and significant pinch-off characteristics. This shows that the n-type MoS is well regulated by using the heavily doped Te nano-plate as the top as the grid 2 The depletion region of the nanoflake channel allows the double junction field effect transistor (Dual-JFET) to exhibit excellent electrical characteristics.
Fig. 5 shows the subthreshold swing characteristic of Dual-JFET with junction gate regulation alone. As can be seen from fig. 5: the Dual-JFET can achieve a low subthreshold swing of about 68mV/dec, indicating good switching speed of the device.
Fig. 6 shows the subthreshold swing curve of a Dual-JFET with the addition of-20V substrate voltage on top gate basis. As can be seen from fig. 6: the switching speed of the Dual-JFET can be regulated to a certain extent after the bottom gate voltage is added, the depth of a depletion region is deepened, the subthreshold swing (66.3 mV/dec) of the device is further reduced, and the device is close to a theoretical limit.
The invention uses the two-dimensional Te nano-sheet without surface hanging bond and the two-dimensional MoS 2 The nano-sheets are combined to construct a p-n junction, moS is carried out 2 The Dual-Junction Field Effect Transistor (JFET) is arranged in an upper layer Te and a lower layer Te to form an upper double-heterojunction and a lower double-heterojunction, so that the Dual-Junction Field Effect Transistor (JFET) with novel structure and high performance is constructed based on the upper double-heterojunction and the lower double-heterojunction, interface defects are effectively avoided, the purity of an interface is guaranteed, the influence of an interface state on carrier transportation is reduced, the advantages of no complex dielectric engineering are achieved by the JFET, the subthreshold swing and pinch-off voltage of the JFET are further reduced, the current switching ratio of the device is improved, and the performance of the device is improved.
The above examples are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above examples, and any other changes, modifications, substitutions, combinations, and simplifications that do not depart from the spirit and principle of the present invention should be made in the equivalent manner, and the embodiments are included in the protection scope of the present invention.
Claims (10)
1. A double-junction field effect transistor is characterized by comprising a substrate, an insulating layer arranged on the substrate, a p-type Te nano-sheet arranged on the insulating layer, and an n-type MoS which is alternately arranged in the Te nano-sheet and is intersected with the Te nano-sheet 2 A nano-sheet channel, the Te nano-sheet and the MoS 2 The vertical double van der Waals heterojunction is formed between the nano sheets;
source and drain electrodes respectively arranged on the MoS 2 The first top gate electrode and the second top gate electrode are respectively arranged on the two ends of the Te nano-plate;
the subthreshold swing of the double-junction field effect transistor is less than or equal to 86mV/dec, and the current switching ratio is greater than or equal to 10 4 。
2. The double junction field effect transistor of claim 1, wherein the Te nano-meterThe sheet is formed by stacking a first Te nano sheet and a second Te nano sheet, the MoS 2 The nanoplatelets are disposed between the first Te nanoplatelets and the second Te nanoplatelets.
3. The double junction field effect transistor of claim 2, wherein the second Te nanoplatelets are disposed on the MoS 2 And the first top gate electrode and the second top gate electrode are respectively arranged on two ends of the second Te nano-plate on the nano-plate.
4. A double junction field effect transistor according to any of claims 1 to 3, characterized in that the thickness of the Te nanoplatelets is between 10nm and 100nm; preferably, the thickness of the Te nano-plate is 60nm-100nm.
5. A double junction field effect transistor according to any one of claims 1 to 3, wherein the MoS 2 The thickness of the nano sheet is 10 nm-100 nm; preferably, the MoS 2 The thickness of the nano-sheet is 10 nm-60 nm.
6. A double-junction field effect transistor according to any of claims 1 to 3, characterized in that the substrate is selected from Si-substrate, which is a bottom gate electrode.
7. A double junction field effect transistor according to any one of claims 1 to 3, wherein the insulating layer is selected from SiO 2 、Al 2 O 3 BN or SiN x 。
8. A double junction field effect transistor according to any one of claims 1 to 3, wherein at least one of the source electrode, the drain electrode and the top gate electrode is selected from Cr, ti, ni, au, pd, pt, and the thickness of the electrode is 40nm to 100nm.
9. The preparation method of the double-junction field effect transistor is characterized by comprising the following steps of:
preparing a first p-type Te nano-plate and a second p-type Te nano-plate on a substrate with an insulating layer;
transfer of n-type MoS on Polydimethylsiloxane (PDMS) by mechanical lift-off process 2 A nanosheet;
subjecting the n-type MoS to 2 Transferring the nano sheet to the first p-type Te nano sheet to form Te/MoS in a cross shape with the first p-type Te nano sheet 2 A p-n junction;
transferring the second p-type Te nano-plate to the p-n junction by adopting PDMS/PVA transfer technology to form a nano-plate with the n-type MoS 2 The nano-sheets are cross-shaped to form Te/MoS 2 Vertical double heterojunction of Te;
at the n-type MoS 2 And preparing a source electrode and a drain electrode on the nano-sheet, preparing a first top gate electrode and a second top gate electrode on the second p-type Te nano-sheet, and taking the substrate as a bottom gate electrode.
10. The method of manufacturing according to claim 9, wherein the first p-type Te nanoplatelets and the second p-type Te nanoplatelets are manufactured on the substrate with the insulating layer using a solution spin coating method.
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