CN117063625A

CN117063625A - Ferroelectric memory, forming method thereof and electronic equipment

Info

Publication number: CN117063625A
Application number: CN202180095760.3A
Authority: CN
Inventors: 景蔚亮; 黄凯亮; 冯君校; 王正波; 吴颖; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2023-11-14
Also published as: WO2023272536A1

Abstract

The embodiment of the application provides a ferroelectric memory, a forming method thereof and electronic equipment comprising the ferroelectric memory. The method is mainly used for improving the storage density of the ferroelectric memory. The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric field effect transistor; wherein the ferroelectric field effect transistor comprises a gate electrode, a semiconductor layer, a first pole and a second pole, and a ferroelectric layer; the first and second poles are arranged in a first direction perpendicular to the substrate, in particular, one of opposite sides of the gate electrode in a second direction parallel to the substrate has a semiconductor layer, that is, the semiconductor layer is not circumferentially arranged along the periphery of the gate electrode, the gate electrode and the semiconductor layer being separated by the ferroelectric layer. In this way, by providing the semiconductor layer only on one side of the gate electrode, the area occupied by each memory cell on the substrate can be reduced, thereby improving the memory density.

Description

Ferroelectric memory, forming method thereof and electronic equipment

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a ferroelectric memory, a method for forming the ferroelectric memory, and an electronic device including the ferroelectric memory.

Background

Ferroelectric memory is a new type of memory, and is being used more and more widely than traditional dynamic random access memory (dynamic random access memory, DRAM) because of the advantages of non-volatility, high speed, low power consumption, etc. Existing ferroelectric memories include ferroelectric field effect transistor (FeFET) memories.

Fig. 1a, 1b and 1c show process block diagrams of memory cells in FeFET memories of three different structures.

As shown in fig. 1a, the source 02 and the drain 03 of the memory cell are formed by doping in a substrate 01, and a channel layer 04 is formed between the source 02 and the drain 03 of the substrate 01, an insulating layer 05 and a gate 07 are formed stacked over the channel layer 04, and a ferroelectric layer 06 for storing data information is formed between the insulating layer 05 and the gate 07. In an implementation manner, the gate electrode 07 may be made of a metal material, and thus, such a structure may be referred to as a metal-ferroelectric-insulator-semiconductor (MFIS) memory cell structure.

The memory cell shown in fig. 1b differs from the memory cell shown in fig. 1a in that a floating gate 08 is further included in addition to the structure of fig. 1a, the floating gate 08 being located between the insulating layer 05 and the ferroelectric layer 06, such a structure may be referred to as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) memory cell structure.

As can be seen from fig. 1a and fig. 1b, since the source 02 and the drain 03 of the transistor need to be doped in the substrate 01, and the memory cell can only be manufactured by the front process (front end of line, FEOL), three-dimensional stacking of the memory cells cannot be realized, and the storage density of the memory is limited, so that the read-write speed of the memory cannot keep up with the operation speed of the processor, which ultimately results in limited improvement of the performance of electronic products such as computers, mobile phones and the like.

Fig. 1c is a schematic diagram of another process structure of a memory cell, in which a channel layer 04 has a columnar structure, a ferroelectric layer 06 surrounds the periphery of the channel layer 04, an insulating layer 05 is used to isolate the channel layer 04 from the ferroelectric layer 06, and a gate 07, a source 02 and a drain 03 surround the periphery of the ferroelectric layer 06. Although the channel layer 04 in this structure is a vertical channel perpendicular to the substrate, more memory cells can be integrated per unit area of the substrate than in the structure of a horizontal channel, since the channel layer 04, the ferroelectric layer 06, and the insulating layer 05 are each of a columnar structure, the radial dimension (e.g., the dimension in the D direction of fig. 1 c) is large, and there is a large bottleneck in the reduction capability, so that the increase in memory density is also limited.

Disclosure of Invention

The application provides a ferroelectric memory, a forming method thereof and electronic equipment comprising the ferroelectric memory, and mainly aims to provide the ferroelectric memory which can improve the storage density and the storage capacity.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, the present application provides a ferroelectric memory comprising: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric field effect transistor; wherein the ferroelectric field effect transistor comprises a gate electrode, a semiconductor layer (which may also be referred to as channel layer), a first and a second pole, and a ferroelectric layer; the first pole and the second pole are arranged along a first direction perpendicular to the substrate, the grid electrode is arranged between the first pole and the second pole, one of two opposite sides of the grid electrode along the second direction is provided with a semiconductor layer, namely, the semiconductor layer is not arranged along the periphery of the grid electrode in a surrounding manner, or the grid electrode is not arranged along the periphery of the semiconductor layer in a surrounding manner, the semiconductor layer is respectively electrically connected with the first pole and the second pole, the grid electrode and the semiconductor layer are isolated by the ferroelectric layer, and the second direction is defined as a direction parallel to the substrate.

In the ferroelectric memory provided by the application, as the first pole and the second pole of the ferroelectric field effect transistor in the memory cell are arranged along the direction vertical to the substrate, the formed ferroelectric field effect transistor is a transistor structure with a vertical channel, namely a transistor with a vertical plane channel structure, compared with a transistor with a horizontal channel, the projection area of the memory on the substrate can be reduced, so that the memory density is improved, and the memory capacity of the ferroelectric memory is improved.

In addition, in particular, in the ferroelectric field effect transistor, the semiconductor layer is provided on one of the opposite sides of the gate electrode in the second direction, instead of surrounding the semiconductor layer along the periphery of the gate electrode, and thus the size of the entire ferroelectric field effect transistor in the second direction can be reduced, the memory cell can be further miniaturized, and the ferroelectric field effect transistor can reach 4F based on these characteristics ² Left and right occupied areas, compared with the existing 6F ² Even larger occupation area, the memory cell is effectively miniaturized, so that more memory cells can be integrated on the unit area of the substrate, and the memory capacity is improved.

In a possible implementation manner of the first aspect, the semiconductor layer is a vertical structure extending along the first direction, and one of opposite ends of the semiconductor layer along the first direction is in contact with the first pole, and the other end is in contact with the second pole.

The semiconductor layer is arranged in a vertical structure and is in ohmic contact with the first pole and the second pole, so that the semiconductor layer forms a vertical channel structure perpendicular to the substrate, and the memory cell is further miniaturized.

In a possible implementation manner of the first aspect, the semiconductor layer is a vertical structure extending along a first direction, a surface opposite to the second pole in the first pole is a first wall surface, and a surface opposite to the first pole in the second pole is a second wall surface; one of opposite ends of the semiconductor layer in the first direction is in contact with the first wall surface, and the other end is in contact with the second wall surface.

That is, the vertical semiconductor layer is disposed in the region between the first pole and the second pole.

In a possible implementation manner of the first aspect, the semiconductor layer is a vertical structure extending along a first direction, a surface opposite to the second pole in the first pole is a first wall surface, and a surface adjacent to the first wall surface in the first pole is a first side surface; the surface opposite to the first pole in the second pole is a second wall surface, the surface adjacent to the second wall surface in the second pole is a second side surface, and the first side surface and the second side surface are positioned on the same side; one of opposite ends of the semiconductor layer in the first direction is in contact with the first side surface, and the other end is in contact with the second side surface.

It can be said that the semiconductor layer stands on one side of the first pole and the second pole.

In a possible implementation manner of the first aspect, the semiconductor layer includes a first portion and a second portion that each extend along the second direction, and a third portion that extends along the first direction and is connected to the first portion and the second portion; the surface of the first pole opposite to the second pole is a first wall surface, and the surface of the second pole opposite to the first pole is a second wall surface; the first portion is disposed on the first wall surface and the second portion is disposed on the second wall surface.

In this way, from the performance aspect of the formed memory cell, the contact area between the semiconductor layer and the first pole and the second pole can be increased, so as to reduce the resistance between the first pole and the semiconductor layer and between the second pole and the semiconductor layer, increase the current flow rate, and finally increase the read-write speed of the memory cell; from the process perspective of forming the memory cell, the manufacturing process flow can be simplified, and the process difficulty can be reduced.

In a possible implementation manner of the first aspect, the first portion, the second portion and the third portion are connected in an integrally formed structure.

In a possible implementation manner of the first aspect, the semiconductor layer includes a first portion extending along the second direction, and a third portion extending along the first direction and connected to the first portion; the surface of the first pole opposite to the second pole is a first wall surface, and the surface of the second pole opposite to the first pole is a second wall surface; the memory also comprises a connecting electrode, and the connecting electrode is arranged on the second wall surface; the third portion is in contact with the first wall surface, and the first portion is in contact with the connection electrode.

That is, the semiconductor layer and the ferroelectric layer are designed to be close to L-shaped structures, so that from the process perspective of forming the memory cell, etching process steps in the preparation process can be reduced, and further, the preparation efficiency can be improved.

In a possible implementation manner of the first aspect, a surface opposite to the second pole in the first pole is a first wall surface, and a surface opposite to the first pole in the second pole is a second wall surface; the grid is positioned in the area between the first wall surface and the second wall surface.

The gate electrode is arranged in the region between the first pole and the second pole, so that the projection area of the memory cell on the substrate can be further reduced, and the integration density can be further improved.

In a possible implementation manner of the first aspect, a surface opposite to the second pole in the first pole is a first wall surface, and a surface adjacent to the first wall surface in the first pole is a first side surface; the surface opposite to the first pole in the second pole is a second wall surface, the surface adjacent to the second wall surface in the second pole is a second side surface, and the first side surface and the second side surface are positioned on the same side; the grid is positioned on one side of the first side surface and the second side surface.

In a possible implementation manner of the first aspect, the ferroelectric field effect transistor is fabricated by a post-process.

When the ferroelectric field effect transistor is manufactured by adopting a back-pass process, the control circuit is manufactured by adopting a front-pass process. The control circuitry may include one or more of decoders, drivers, timing controllers, buffers, or input-output drivers, as well as other functional circuitry. Thus, the ferroelectric field effect transistor of the memory unit is manufactured through a subsequent process, and the memory unit can be stacked along the direction vertical to the substrate by adopting a three-dimensional integration method, so that the high-density integration of the memory is realized.

In a possible implementation manner of the first aspect, the plurality of memory cells includes a first memory cell and a second memory cell that are arranged in a direction parallel to the substrate and are adjacent to each other; the semiconductor layer in the first memory cell is disposed opposite to the semiconductor layer in the second memory cell.

In a possible implementation manner of the first aspect, the ferroelectric memory further includes: bit lines, source lines, and word lines; wherein the gate is electrically connected to the word line, the first pole is electrically connected to the source line, and the second pole is electrically connected to the bit line.

That is, the read/write operation is realized by applying voltages to the word line, the bit line, and the source line to control the voltage difference across the ferroelectric layer.

The bit lines, source lines and word lines may be fabricated by a back-pass process, or may be fabricated by a front-pass process, or may be fabricated in part by a back-pass process.

In a possible implementation manner of the first aspect, the source line and the bit line each extend along a second direction parallel to the substrate; the word line extends along a third direction parallel to the substrate, the second direction being perpendicular to the third direction; a first electrode of the plurality of memory cells arranged along the second direction is electrically connected with the same source line; a second pole of the plurality of memory cells arranged along a second direction is electrically connected with the same bit line; the gates of the plurality of memory cells arranged in the third direction are electrically connected to the same word line.

By sharing the same source line for the plurality of first poles in the second direction, sharing the same bit line for the plurality of second poles in the second direction, and sharing the same word line for the plurality of gates in the third direction, voltages can be applied to the plurality of bit lines, the plurality of source lines, and the plurality of word lines at the time of reading and writing to select a memory cell to be read and written.

In a possible implementation manner of the first aspect, the source line extending along the second direction in the first layer of storage arrays is close to the bit line extending along the second direction in the second layer of storage arrays; the source lines in the first layer memory array and the bit lines in the second layer memory array are mutually independent signal lines.

In an achievable structure, an insulating layer may be formed between the source line of the first-layer memory array and the bit line of the second-layer memory array so that the bit line and the source line are signal lines independent of each other.

In a possible implementation manner of the first aspect, the plurality of memory cells form a first layer memory array and a second layer memory array arranged along a first direction; source lines extending in the second direction in the first-layer memory array are close to the source lines extending in the second direction in the second-layer memory array; the source lines in the first layer of memory arrays share the same signal line with the source lines in the second layer of memory arrays.

Because the source lines in the first-layer memory array share the same signal line with the source lines in the second-layer memory array, the height of each layer of memory array can be reduced, and higher integration density in the first direction can be realized.

In a possible implementation manner of the first aspect, during the writing phase, the word line is used to receive a word line control signal, the source line and the bit line are used to receive the same control signal, and a voltage difference between the word line control signal and the control signal on the source line polarizes the ferroelectric film layer. For example, when the word line control signal is greater than zero and greater than the operating voltage, the ferroelectric film layer is positively polarized, and when the word line control signal is less than zero and greater than the operating voltage, the ferroelectric film layer is negatively polarized.

In a possible implementation manner of the first aspect, during a reading phase, the word line is used for receiving a ground, the source line is used for receiving a source line control signal, the source line control signal and the bit line control signal have a positive voltage difference, and the ferroelectric field effect transistor is turned on. For example, when the ferroelectric field effect transistor is turned on, a "1" is read.

In a possible implementation manner of the first aspect, during a reading phase, the word line is used for receiving a ground, the source line is used for receiving a source line control signal, the source line control signal and the bit line control signal have a negative voltage difference, and the ferroelectric field effect transistor is turned off. For example, when the ferroelectric field effect transistor is turned off, a "0" is read.

In a possible implementation manner of the first aspect, the ferroelectric memory further includes a controller, where the controller is configured to: outputting a word line control signal to control a voltage on the word line; outputting a source line control signal to control a voltage on the source line; and outputting a bit line control signal to control a voltage on the bit line.

In a second aspect, the present application further provides an electronic device, including a processor and a ferroelectric memory in any one of the above implementations of the first aspect, where the processor is electrically connected to the ferroelectric memory.

The electronic device provided by the embodiment of the application comprises the ferroelectric memory of the embodiment of the first aspect, so that the electronic device provided by the embodiment of the application and the ferroelectric memory of the technical scheme can solve the same technical problems and achieve the same expected effects.

In a possible implementation manner of the second aspect, the processor and the ferroelectric memory are integrated in the same chip.

The memory so formed may be referred to as an embedded memory structure.

In a third aspect, the present application also provides a method of forming a ferroelectric memory, the method comprising: the first and second poles are formed along a first direction perpendicular to the substrate, and a semiconductor layer, a gate electrode and a ferroelectric layer are formed, and one of opposite sides of the gate electrode along the second direction is formed with the semiconductor layer electrically connected to the first and second poles, respectively, and the ferroelectric layer is formed between the gate electrode and the semiconductor layer to form a ferroelectric field effect transistor.

In this way, in the memory cell manufactured by the method, the first pole and the second pole are arranged along the direction vertical to the substrate, and the semiconductor layer is a vertical channel vertical to the substrate, so that the projection area of the memory cell on the substrate is smaller, and high-density integration of the memory cell can be realized.

Furthermore, since the semiconductor layer is arranged on one of two opposite sides of the gate along the second direction, the size of the whole transistor along the second direction can be reduced, the memory unit can be further miniaturized, and based on the characteristics, the memory density of the memory can be obviously improved, the memory capacity can be improved, and the read-write speed of the memory can be improved.

In a possible implementation manner of the third aspect, before forming the memory cell, the forming method further includes: forming a control circuit on a substrate; an interconnection line electrically connecting the control circuit and the memory cell is formed on the control circuit.

That is, the memory cells in the memory are fabricated by a subsequent process, and the memory cells can be stacked in a direction perpendicular to the substrate by a three-dimensional integration method, so as to realize high-density integration of the memory.

In a possible implementation manner of the third aspect, when forming the ferroelectric field effect transistor, the method includes: stacking a first conductive layer, a sacrificial layer, and a second conductive layer sequentially along a first direction; a first groove penetrating through the second conductive layer and the sacrificial layer is formed; sequentially forming a ferroelectric layer and a gate electrode on the sidewall surface of the first trench along a second direction parallel to the substrate; removing the sacrificial layer in contact with the ferroelectric layer to form a concave cavity, wherein a first pole and a second pole are formed on two sides of the concave cavity; a semiconductor layer is formed on at least a wall surface of the cavity near the ferroelectric layer to produce a ferroelectric field effect transistor.

In a possible implementation manner of the third aspect, when forming the ferroelectric field effect transistor, the method includes: stacking a first conductive layer, a sacrificial layer, and a second conductive layer sequentially along a first direction; a first groove penetrating through the second conductive layer and the sacrificial layer is formed; forming a semiconductor layer on the sidewall surface of the first groove along a second direction parallel to the substrate; removing the sacrificial layer in contact with the semiconductor layer to form a concave cavity, wherein a first pole and a second pole are formed on two sides of the concave cavity; a gate and a ferroelectric layer for isolating the gate and the semiconductor layer are formed in the cavity to produce a ferroelectric field effect transistor.

In a possible implementation manner of the third aspect, when forming the ferroelectric field effect transistor, the method includes: stacking a first conductive layer, a sacrificial layer, and a second conductive layer sequentially along a first direction; a first groove penetrating through the second conductive layer and the sacrificial layer is formed; removing the sacrificial layer to form a concave cavity, wherein a first pole and a second pole are formed on two sides of the concave cavity; a semiconductor layer, a gate electrode and a ferroelectric layer for isolating the gate electrode and the semiconductor layer are formed in the cavity to manufacture the ferroelectric field effect transistor.

In a possible implementation manner of the third aspect, when forming the ferroelectric field effect transistor, the method includes: stacking a first conductive layer, a sacrificial layer, and a second conductive layer sequentially along a first direction; a first groove penetrating through the first conductive layer is formed; forming a ferroelectric layer and a semiconductor layer on the side surface of the first groove in sequence so that the second conductive layer forms a grid electrode, and the first conductive layer forms a first pole; forming a second electrode on the semiconductor layer to produce the ferroelectric field effect transistor.

Drawings

FIG. 1a is a process block diagram of a memory cell of a FeFET memory according to the prior art;

FIG. 1b is a process block diagram of a memory cell of a FeFET memory according to the prior art;

FIG. 1c is a process block diagram of a memory cell of a FeFET memory according to the prior art;

fig. 2 is a circuit diagram of an electronic device according to an embodiment of the present application;

fig. 3 is a circuit diagram of a ferroelectric memory according to an embodiment of the present application;

fig. 4 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

FIG. 5a is a schematic diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 5b is a cross-sectional view A-A of FIG. 5 a;

FIG. 6 is a simplified top-down schematic diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 7a is a process structure diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 7B is a cross-sectional view B-B of FIG. 7 a;

fig. 8a is a process structure diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 8b is a cross-sectional view C-C of FIG. 8 a;

fig. 9a is a process structure diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 9b is a section D-D of FIG. 9 a;

fig. 10a is a process structure diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 10b is a section E-E of FIG. 10 a;

FIG. 11a is a schematic diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 11b is a cross-sectional F-F view of FIG. 11 a;

fig. 12 is a three-dimensional process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

FIG. 13 is an M1 view of FIG. 12;

fig. 14 is a three-dimensional process structure diagram of a multi-layer memory array of a ferroelectric memory according to an embodiment of the present application;

FIG. 15 is an M2 view of FIG. 14;

fig. 16 is a three-dimensional process structure diagram of a multi-layer memory array of a ferroelectric memory according to an embodiment of the present application;

FIG. 17 is an M3 view of FIG. 16;

FIG. 18 is a schematic process diagram of a memory chip according to an embodiment of the present application;

fig. 19 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

FIGS. 20a to 20j are process block diagrams after completion of steps for forming a memory cell according to an embodiment of the present application;

fig. 21a to 21j are process structure diagrams after completing each step of forming a memory cell according to an embodiment of the present application;

FIGS. 22 a-22 j are process block diagrams after completion of steps for forming a memory cell according to an embodiment of the present application;

FIGS. 23 a-23 i are process block diagrams after completion of steps for forming a memory cell according to embodiments of the present application;

fig. 24a to 24g are process structure diagrams after the steps of forming a memory cell according to an embodiment of the present application are completed.

Reference numerals:

01. 100-a substrate; 02-source; 03-drain electrode; 04-a channel layer; 05-an insulating layer; 06-a ferroelectric layer; 07-gate; 08-floating gate;

51-a first pole; 52-second pole; 53-a semiconductor layer; 531-first portion; 532-a second portion; 533-third part; 54-ferroelectric layer; 541-a first portion; 542-a second portion; 543-third portion; 55-gate; 561. 562, 563, 564-insulating layer; 57-sacrificial layer, 581, 582-conductive layer; 59-connecting the electrodes; 3101-a first tier storage array; 3102-a second tier storage array; 3103-a third tier storage array; 400. 401, 402, 403, 404-memory cells; 101-a first tank; 102-a second tank; 103-cavity; 104-third groove.

Detailed Description

Ferroelectric memories store data based on the ferroelectric effect of ferroelectric materials. Ferroelectric memories are expected to be a major competitor to DRAM due to their ultra-high memory density, low power consumption, and high speed. The memory cells in ferroelectric memories comprise a ferroelectric capacitor comprising a ferroelectric layer made of ferroelectric material. Due to the non-linear nature of the ferroelectric material, the dielectric constant of the ferroelectric material can be adjusted, and the difference between before and after the polarization state of the ferroelectric layer is reversed is very large, which makes the ferroelectric capacitor smaller than other capacitors, for example, much smaller than the capacitor for storing charges in DRAM.

In ferroelectric memories, the ferroelectric layer may be formed of a common ferroelectric material, such as ZrO ₂ ，HfO ₂ Etc. When an electric field is applied to the ferroelectric layer, the central atoms stop in a low energy state along the electric field, whereas when an electric field reversal is applied to the ferroelectric layer, the central atoms move in the crystal along the direction of the electric field and stop in another low energy state. A large number of central atoms are mobile-coupled in the crystal unit cell to form ferroelectric domains (ferroelectric domains), which form polarized charges under the action of an electric field. The ferroelectric domain has higher polarized charge formed by inversion under the electric field, the ferroelectric domain has lower polarized charge formed by non-inversion under the electric field, and the binary stable state of the ferroelectric material enables the ferroelectric to be used as a memory.

The embodiment of the application provides an electronic device comprising a ferroelectric memory. Fig. 2 is a circuit diagram of an electronic device 200 according to an embodiment of the present application, where the electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, a personal computer (personal computer, PC), a server, a workstation, etc. The electronic device 200 includes a bus 205, a System On Chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC210 may be used to process data, such as data of processing applications, process image data, and buffer temporary data. The ROM220 may be used to hold non-volatile data such as audio files, video files, and the like. ROM220 may be a PROM (programmable read-only memory), EPROM (erasable programmable read-only memory ), flash memory (flash memory), or the like.

In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240. The communication chip 230 may be used for processing the protocol stack, amplifying, filtering, etc. the analog radio frequency signal, or simultaneously implementing the above functions. The power management chip 240 may be used to power other chips.

In one embodiment, the SOC210 may include an application processor (application processor, AP) 211 for processing applications, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a random access memory (random access memory, RAM) 213 for caching data.

The AP211, the GPU212, and the RAM213 may be integrated into one die (die), or integrated into a plurality of dies (die), respectively, and packaged in a package structure, for example, using a 2.5D (dimension) package, a 3D (dimension) package, or other advanced packaging technologies. In one embodiment, the AP211 and the GPU212 are integrated in one die, the RAM213 is integrated in another die, and the two die are packaged in a package structure, so as to obtain a faster inter-die data transmission rate and a higher data transmission bandwidth.

Fig. 3 is a circuit diagram of a ferroelectric memory 300 in an electronic device according to an embodiment of the present application. The ferroelectric memory 300 may be a RAM213 as shown in fig. 2, belonging to FeRAM. In one embodiment, ferroelectric memory 300 may also be a RAM disposed external to SOC 210. The present application does not limit the position of the ferroelectric memory 300 in the electronic device and the positional relationship with the SOC 210.

Continuing with fig. 3, ferroelectric memory 300 includes memory array 310, decoder 320, driver 330, timing controller 340, buffer 350, and input-output driver 360. The memory array 310 includes a plurality of memory cells 400 arranged in an array, wherein each memory cell 400 may be used to store 1bit or more of data. The memory array 310 further includes signal lines such as Word Lines (WL), bit Lines (BL), source Lines (SL), and the like. Each memory cell 400 is electrically connected to a corresponding word line WL, bit line BL, and source line SL. One or more of the word line WL, the bit line BL, or the source line SL is used for selecting the memory cell 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the polarization direction of the ferroelectric capacitor in the memory cell 400, thereby implementing the data read and write operation. For convenience, the word line WL, the bit line BL, and the source line SL described above are collectively referred to as signal lines in the embodiments of the present application.

In the ferroelectric memory 300 structure shown in fig. 3, the decoder 320 is configured to decode according to the received address to determine the memory cell 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby realizing access to the designated memory cell 400. The buffer 350 is used for buffering the read data, and may be, for example, a first-in first-out (FIFO) buffer. The timing controller 330 is used for controlling the timing of the buffer 350 and controlling the driver 330 to drive the signal lines in the memory array 310. The input-output driver 360 is used to drive transmission signals, such as to drive received data signals and to drive data signals to be transmitted, so that the data signals can be transmitted over a long distance.

The memory array 310, the decoder 320, the driver 330, the timing controller 340, the buffer 350, and the input/output driver 360 may be integrated into one chip, or may be integrated into a plurality of chips, respectively.

Fig. 4 shows a partial circuit diagram of a memory array 310 in a ferroelectric memory, which memory array 310 exemplarily shows 4 memory cells 400, each comprising a ferroelectric field effect transistor (FeFET), wherein the gate (gate) of the ferroelectric field effect transistor is electrically connected to a Word Line (WL), the first pole of the ferroelectric field effect transistor is electrically connected to a Source Line (SL), and the second pole of the ferroelectric field effect transistor is electrically connected to a Bit Line (BL).

In the present application, one of the drain (drain) or source (source) of the ferroelectric field effect transistor is referred to as a first pole, and the other pole is referred to as a second pole. The drain and source may be determined according to the flow direction of the current, for example, in fig. 4, when the current is from left to right, the left end is the drain, the right end is the source, and conversely, when the current is from right to left, the right end is the drain, and the left end is the source.

In each of the memory cells 400 shown in fig. 4, the ferroelectric field effect transistor includes a ferroelectric layer for storing data information, the existence of self-polarized field of the ferroelectric layer shifts the threshold voltage of the ferroelectric field effect transistor, and the positive and negative polarized fields shift the threshold voltage in different directions, so that the difference between the positive and negative polarized fields forms a memory window of the ferroelectric field effect transistor. When the gate of the ferroelectric transistor, i.e., the word line in fig. 4, applies a level between two threshold voltages, one of the high-resistance and low-resistance states exists between the source and drain of the ferroelectric field effect transistor, and the two states can be respectively read by applying a voltage between the source and drain, thereby realizing the memory function.

With the continuous evolution of integrated circuit technology in electronic devices, the number of transistors per unit area on a chip of the electronic device is continuously increased, so that the performance of the electronic device is continuously optimized. On the one hand, the amount of data that can be operated by the processor in a unit time is continuously increased, for example, the amount of data operated by the GPU212 in fig. 2 is rapidly increased; on the other hand, the storage density of the memory is also increasing, so that the demand for data processing in the information age is satisfied. However, there is a gap in the degree to which the performance of both the processor and the memory is improved due to the difference in the structure and the process of the logic unit and the memory storage unit in the processor. That is, the memory has low storage density, and the read-write speed cannot keep pace with the operation speed of the processor, which restricts the rapid improvement of the performance of the electronic device.

The embodiment of the application provides a ferroelectric memory which has larger memory density, higher memory capacity and higher read-write speed, thereby reducing the gap with the improvement of the performance of a processor.

Fig. 5a shows a three-dimensional process structure of a memory cell 400 in a ferroelectric memory, and a substrate 100, and fig. 5b is a cross-sectional view A-A of fig. 5 a.

Referring to fig. 5a and 5b, the memory cell 400 includes ferroelectric field effect transistors, so that one ferroelectric field effect transistor is one memory cell 400, and then 400 shown in fig. 5a and 5b is also a process structure diagram of one ferroelectric field effect transistor, which includes a first pole 51 and a second pole 52, and a semiconductor layer 53 and a gate 55, and the semiconductor layer 53 may be also referred to as a channel layer.

It will be appreciated that the ferroelectric field effect transistor herein is a transistor device having three terminals, and that the ferroelectric field effect transistor may be selected from NMOS (N-channel metal oxide semiconductor ) transistors or from PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistors.

With continued reference to fig. 5a and 5b, the first pole 51 and the second pole 52 are arranged along a first direction Z perpendicular to the substrate 100, the gate 55 is located between the first pole 51 and the second pole 52, and the gate 55 is insulated from the first pole 51, and the gate 55 is insulated from the second pole 52.

In particular, the present application provides that one of opposite sides of the gate electrode 55 in a direction parallel to the substrate 100 (e.g., Y direction of fig. 5a and 5 b) has a semiconductor layer 53, and the semiconductor layer 53 is electrically connected to the first and second poles 51 and 52, respectively.

It can be understood that the feature of "one of opposite sides of the gate electrode 55 in the Y direction parallel to the substrate 100 has the semiconductor layer 53" is that, as shown in fig. 5b, opposite sides of the gate electrode 55 in the Y direction are the P1 side and the P2 side, respectively, the semiconductor layer 53 is located on the P2 side, or the semiconductor layer 53 is located on the P1 side, that is, one of the P1 side and the P2 side of the gate electrode 55 is provided with the semiconductor layer 53, and the other side is not provided with the semiconductor layer 53, or the semiconductor layer 53 is not circumferentially located along the periphery of the gate electrode 55.

The positional relationship between the gate electrode 55 and the semiconductor layer 53 in the process structure is designed in this way, the size of the ferroelectric field effect transistor in the Y direction can be reduced, and further, the size of the ferroelectric field effect transistor can be reduced, high density integration of the memory cell is realized, the memory capacity is improved, correspondingly, the read-write speed of the memory can be improved, the degree of mismatch with the development of the processor is reduced, and when the memory density is increased, the higher data transmission bandwidth can be realized under the condition that the memory capacity is improved.

Based on the description of the memory cell 400 of fig. 5a and 5b, the semiconductor layer 53 between the first pole 51 and the second pole 52 is a vertical channel arranged perpendicular to the substrate 100, and the projected area on the substrate 100 can be reduced compared to a transistor structure of a horizontal channelThe memory unit 400 is miniaturized to increase the memory density, increase the memory capacity, and increase the read/write speed. For example, as shown in fig. 6, one memory cell 400 in the ferroelectric memory has an active area of 1F and a field area of 1F in the X-direction and the Y-direction, respectively, and finally one memory cell 400 occupies 2 fx2f=4f ² With the continuous miniaturization of semiconductor devices, the ferroelectric field effect transistor with the vertical channel provided by the application can obviously improve the storage density compared with other transistor structures with parallel channels. The ferroelectric field effect transistor of this structure may be referred to as an oxide semiconductor ferroelectric field effect transistor (vertical oxide semiconductor FeFET, VOS-FeFET) having a vertical structure.

In addition, the first pole 51 and the second pole 52 are each a film structure, for example, may be formed by deposition, sputtering, and not doping in the substrate 100, so that the memory cell 400 may be stacked in three dimensions (3D) on the substrate 100 to achieve high density integration.

Also, referring again to fig. 5a and 5b, the memory cell 400 further includes a ferroelectric layer 54 for storing charges, and the gate electrode 55 and the semiconductor layer 53 are isolated by the ferroelectric layer 54, i.e., the ferroelectric layer 54 is disposed between the gate electrode 55 and the semiconductor layer 53.

The materials of the first pole 51 and the second pole 52 are conductive materials, such as metal materials. In an alternative embodiment, the material of the first and second electrodes 51 and 52 may be one or more of TiN (titanium nitride), ti (titanium), au (gold), W (tungsten), mo (molybdenum), in—ti—o (ITO, indium TiN oxide), al (aluminum), cu (copper), ru (ruthenium), ag (silver), and the like.

The material of the gate 55 is a conductive material, such as a metal material. In alternative embodiments, one or more of TiN (titanium nitride), ti (titanium), au (gold), W (tungsten), mo (molybdenum), in—ti—o (ITO, indium TiN oxide), al (aluminum), cu (copper), ru (ruthenium), ag (silver), and the like may be used.

The material of the semiconductor layer 53 may be Si (silicon), poly-Si (p-Si, polysilicon), amorphorus-Si (a-Si, amorphous)Silicon), in-Ga-Zn-O (IGZO, inGaZn oxide) polynary compound, znO (zinc oxide), ITO (indium tin oxide), tiO ₂ (titanium dioxide), moS ₂ (molybdenum disulfide), WS ₂ One or more of semiconductor materials such as (tungsten disulfide).

The material described above for insulating the gate electrode 55 and the first pole 51, and the insulating layer between the gate electrode 55 and the second pole 52 may be SiO ₂ (silica), al ₂ O ₃ (aluminum oxide), hfO ₂ (hafnium dioxide), zrO ₂ (zirconia) TiO ₂ (titanium dioxide), Y ₂ O ₃ (yttrium oxide) and Si ₃ N ₄ (silicon nitride) and the like.

The ferroelectric layer 54 may be made of ZrO ₂ ，HfO ₂ Al doped HfO ₂ Si doped HfO ₂ Zr-doped HfO ₂ La doped HfO ₂ Y-doped HfO ₂ One or more of an isoparaffinic material or a material doped with other elements based on the material.

The semiconductor layer 53 and ferroelectric layer 54 of the present application have a variety of structures that can be realized. The following is explained with reference to the drawings.

Referring to fig. 5b, the semiconductor layer 53 is of a vertical structure extending in a Z direction perpendicular to the substrate, and the first pole 51 has a first wall surface M1 opposite to the second pole 52, the second pole 52 has a second wall surface M2 opposite to the first pole 51, one of opposite ends of the semiconductor layer 53 in the Z direction is in contact with the first wall surface M1 to be coupled electrically, and the other of the opposite ends of the semiconductor layer 53 in the Z direction is in contact with the second wall surface M2 to be coupled electrically.

Also, the ferroelectric layer 54 is also of a vertical structure, and the ferroelectric layer 54 and the semiconductor layer 53 are juxtaposed in the Y direction parallel to the substrate 100.

In addition, the gate 55 is located in a region between the first wall surface M1 of the first pole 51 and the second wall surface M2 of the second pole 52.

In a practical process, the second pole 52, the first insulating layer, the gate electrode 55 and the second insulating layer may be sequentially stacked in the Z direction shown in fig. 5b, then a slot penetrating to the second pole 52 is opened in the Z direction in these stacked structures, and the ferroelectric layer 54 and the semiconductor layer 53 are sequentially stacked on the sides of the slot; finally, the first pole 51 is formed on a second insulating layer, where the first insulating layer serves as an insulating structure for insulating the gate 52 and the second pole 52, and the second insulating layer serves as an insulating structure for insulating the gate 52 and the first pole 51.

Based on the above description of the memory cell process flow and the memory cell structure, it can be seen that the semiconductor layer 53 is a vertical channel perpendicular to the substrate 100 and has only one layer structure along the Y direction, so that the memory cell 400 can be miniaturized in the Y direction to improve the memory density.

Fig. 7a and 7B show another process structure of the memory cell 400, fig. 7B is a cross-sectional B-B view of fig. 7a, and fig. 7a and 7B are combined, which is the same as the memory cell 400 shown in fig. 5a and 5B described above in that the semiconductor layer 53 is also a vertical structure extending in the Z direction perpendicular to the substrate, and is different in that the semiconductor layer 53 in this embodiment is disposed at a position different from the semiconductor layer 53 in the above-mentioned 5a and 5B, in fig. 7B, the first pole 51 has a first wall surface M1 opposite to the second pole 52, the second pole 52 has a second wall surface M2 opposite to the first pole 51, in addition, the first pole 51 has a first side surface C1 adjacent to the first wall surface M2, and the first side surface C1 and the second side surface C2 are located at the same side, the semiconductor layer 53 is located at the opposite side of the first side surface C1 and the second side surface C2 in the opposite to the Z direction, and the opposite ends of the semiconductor layer 53 are electrically coupled to the opposite ends of the first side surface C1 in the Z direction.

In a practically feasible process, the end of the semiconductor layer 53 that is in contact with the first pole 51 is flush with the end face of the first pole 51 that faces away from the second pole 52, and also the end of the semiconductor layer 53 that is in contact with the second pole 52 is flush with the end face of the second pole 52 that faces away from the first pole 51.

With continued reference to fig. 7b, since the gate 55 is located in the region between the first wall M1 and the second wall M2, the projected area of the memory cell 400 on the substrate can be further reduced to further miniaturize the memory cell size.

In this embodiment, in combination with fig. 7b, the ferroelectric layer 54 includes a first portion 541 and a second portion 542 extending in a Y direction parallel to the substrate, and a third portion 543 connecting the first portion 541 and the second portion 542, the first portion 541 being formed on the first wall M1, and the second portion 542 being formed on the second wall M2, so that the ferroelectric layer 54 has an open cavity structure around, and the gate 55 is disposed in the cavity.

As such, the first portion 541 serves as an insulating structure for insulating the gate electrode 55 and the first pole 51, and the second portion 542 serves as an insulating structure for insulating the gate electrode 55 and the second pole 52.

In an achievable process, the second pole 52, the sacrificial layer (defined as a sacrificial layer structure because it eventually needs to be removed) and the first pole 51 may be stacked in order first; then forming grooves penetrating them in the stacked three-layer structure, and forming a semiconductor layer 53 on the sides of the grooves near the first pole 51, the sacrificial layer and the second pole 52; removing the sacrificial layer to form a cavity between the first pole 51 and the second pole 52; a ferroelectric layer 54 and a gate 55 are then formed in the recess to produce the memory cell shown in fig. 7 b. From the standpoint of the process of forming the structure shown in fig. 7a and 7b, the manufacturing process is simple and easy to implement. In particular, the semiconductor layer 53 of each memory cell 400 includes only a channel structure extending in the Z direction to reduce the size of a plurality of memory cells in the Y direction parallel to the substrate, thereby enabling more memory cells to be formed on a single bit plane of the substrate.

Fig. 8a and 8b show another process structure of a memory cell 400, fig. 8b is a C-C cross-sectional view of fig. 8a, and in combination with fig. 8a and 8b, the same as the memory cell 400 shown in fig. 7a and 7b described above is that the semiconductor layer 53 is also a vertical structure extending in a Z direction perpendicular to the substrate, and the same includes: the ferroelectric layer 54 also includes a first portion 541 and a second portion 542 extending in a Y direction parallel to the substrate, and a third portion 543 connecting the first portion 541 and the second portion 542, the first portion 541 being formed on the first wall M1, and the second portion 542 being formed on the second wall M2 so that the ferroelectric layer 54 has an open cavity structure around the cavity in which the gate 55 is located. Unlike the memory cell 400 shown in fig. 7a and 7b described above, the arrangement position of the semiconductor layer 53 in this embodiment is different from the arrangement position of the semiconductor layer 53 in fig. 7a and 7b described above, in this embodiment, one of the opposite ends of the semiconductor layer 53 in the Z direction is in contact with the first wall surface M1 of the first pole 51 to be electrically connected thereto for coupling, and the other of the opposite ends of the semiconductor layer 53 in the Z direction is in contact with the second wall surface M2 of the second pole 52 to be electrically connected thereto for coupling.

Based on the description of the memory cell shown in fig. 8a and 8b, since the gate electrode 55, the semiconductor layer 53 and the ferroelectric layer 54 are all located in the region between the first pole 51 and the second pole 52, the memory cell 400 is further miniaturized in the Y direction, and in addition, since the ferroelectric layer 54 includes the first portion 541 and the second portion 542, and the third portion 543, the ferroelectric layer 54 has a larger area, and thus the read/write efficiency of the memory can be improved.

In the above-described structure of the ferroelectric layer 54 including the first and second portions 541 and 542, and the third portion 543, the first and second portions 541 and 542, and the third portion 543 may be an integrally formed structure, i.e., the first, second, and third portions 541, 542, and 543 are formed at one time by one process in a realizable process step.

Fig. 9a and 9b show another process structure of the memory cell 400, fig. 9b is a D-D cross-sectional view of fig. 9a, and in combination with fig. 9a and 9b, the same as the memory cell 400 shown in fig. 8a and 8b described above is that the ferroelectric layer 54 in this embodiment also includes a first portion 541 and a second portion 542 extending in a Y direction parallel to the substrate, and a third portion 543 connecting the first portion 541 and the second portion 542 so that the ferroelectric layer 54 encloses a cavity structure having an opening, and the gate 55 is located in the cavity, except that the semiconductor layer 53 includes a first portion 531 and a second portion 532 each extending in the Y direction parallel to the substrate 100, and includes a third portion 533 extending in a Z direction perpendicular to the substrate 100, and the third portion 533 is connected to the first portion 531 and the second portion 532. That is, the semiconductor layer 53 in this embodiment is formed in a cavity structure having an opening, the first portion 531 is disposed on the first wall M1, the second portion 532 is disposed on the second wall M1, and the ferroelectric layer 54 and the gate electrode 55 are located in the cavity around the semiconductor layer 53.

In terms of the performance of the transistor having such a structure, the first wall surface M1 of the first electrode 51 and the second wall surface M2 of the second electrode 52 each have a semiconductor layer. In this way, the ohmic contact area between the semiconductor layer and the first electrode 51 and the ohmic contact area between the semiconductor layer and the second electrode 52 can be increased, and further, the resistance between the semiconductor layer and the first electrode 51 and the resistance between the semiconductor layer and the second electrode 52 can be reduced, so that the current flow rate and finally the read/write speed of the memory cell can be improved.

In terms of the process of forming a transistor of this structure, when the transistor is formed, as shown in fig. 9b, in the region between the first pole 51 and the second pole 52, a physical vapor deposition method (physical vapor deposition,

PVD), or chemical vapor deposition (chemical vapor deposition, CVD) to form a semiconductor layer structure between the first wall M1 and the second wall M2, and between the first wall M1 and the second wall M2, without removing the semiconductor layer on the first wall M1 and the second wall M2, so that the manufacturing process flow can be simplified and the process difficulty can be reduced.

Based on the above description of the structure of the memory cell 400, only one semiconductor layer structure is provided along the Y direction parallel to the substrate 100, so that the memory cell can be miniaturized and the memory density of the whole memory can be improved compared with the existing two semiconductor layer structure.

Fig. 10a and 10b show another process structure of the memory cell 400, fig. 10b is a cross-sectional E-E view of fig. 10a, and fig. 10a and 10b are combined, which is the same as the memory cell 400 shown in fig. 9a and 9b described above, in that the semiconductor layer 53 in this embodiment also includes a first portion 531 and a second portion 532 each extending in a Y direction parallel to the substrate 100, and a third portion 533 extending in a Z direction perpendicular to the substrate 100, and the third portion 533 is connected to the first portion 531 and the second portion 532. That is, the semiconductor layer 53 in this embodiment forms a concave structure having an opening, the first portion 531 is provided on the first wall surface M1, and the second portion 532 is provided on the second wall surface M1. The difference from the memory cell shown in fig. 9a and 9b described above is that the gate 55 is disposed at a different position, and in this embodiment, as shown in fig. 10b, the gate 55 is located on the first side C1 and the second side C2, and the gate 55 is isolated from the first electrode 51, the second electrode 52 and the semiconductor layer 53 by the ferroelectric layer 54.

In a practical implementation, the end of the gate 55 close to the first pole 51 is flush with the end of the first pole 51 facing away from the second pole 52, and also the end of the gate 55 close to the second pole 52 is flush with the end of the second pole 52 facing away from the first pole 51. Such a structure may also be defined as having the gate 55 between the first pole 51 and the second pole 52.

Since the first wall surface M1 of the first pole 51 and the second wall surface M2 of the second pole 52 each have a semiconductor layer. In this way, the ohmic contact area between the semiconductor layer and the first electrode 51 and the ohmic contact area between the semiconductor layer and the second electrode 52 can be increased, and further, the resistance between the semiconductor layer and the first electrode 51 and the resistance between the semiconductor layer and the second electrode 52 can be reduced, so that the current flow rate can be increased, and the read/write speed of the memory cell can be increased.

In addition, as shown in fig. 10b, the first portion 531, the second portion 532 and the third portion 533 enclose an open cavity, and another insulating layer 56 is filled in the cavity.

In an achievable process, the second pole, the sacrificial layer and the first pole may be stacked in sequence along the Z direction shown in fig. 10b, then slots penetrating the second pole, the sacrificial layer and the first pole are opened in the stacked structures along the Z direction, and the ferroelectric layer 54 and the gate 55 are stacked in sequence on the sides of the slots; the sacrificial layer is removed again to form a cavity between the first pole 51 and the second pole 52, and the semiconductor layer 33 is filled in the cavity, and then the insulation material is filled in the remaining space of the cavity to form the insulation layer 56.

Fig. 11a and 11b show another process structure of the memory cell 400, fig. 11b is a cross-sectional view F-F of fig. 11a, and, in combination with fig. 11a and 11b, the semiconductor layer 53 in this embodiment includes a first portion 531 extending in a Y direction parallel to the substrate 100, and a third portion 533 extending in a Z direction perpendicular to the substrate 100, and the third portion 533 is connected to the first portion 531, wherein one end of the third portion 533 is in contact with the first wall surface M1 of the first electrode 51, a connection electrode 59 is further disposed on the second electrode 52, and the first portion 531 is in contact-coupled electrical connection with the connection electrode 59. That is, the semiconductor layer 53 in this embodiment has a structure close to an L-shape, and the ferroelectric layer 54 has a structure close to an L-shape.

The material of the connection electrode 59 may be the same as that of the second pole 52 or may be different.

When the memory cell of the structure shown in fig. 11a and 11b is fabricated, the ferroelectric layer 54 is prevented from being damaged by the etching process for a relatively large number of times, and the read/write performance of the memory cell is affected.

Based on the above description of the memory cell 400 having various structures, only one semiconductor layer structure is provided along the Y direction parallel to the substrate 100, so that the memory cell can be miniaturized and the memory density of the entire memory can be improved compared with the conventional two semiconductor layer structure.

In addition, since the semiconductor layer 53 of the memory cell provided by the application can be made of the oxide semiconductor material, the uniformity of the oxide semiconductor material of the semiconductor layer 53 is easy to control from the process point of view, and the oxide semiconductor material of the semiconductor layer 53 has higher mobility from the performance point of view, so that the memory cell has the characteristics of high forbidden bandwidth, high ground hole mobility, low refresh frequency, better memory performance and the like.

Except for the memory cells of several different structures given above, ferroelectric field effect transistors as long as the channels in the memory cells are vertical channels are within the scope of the present application, and the remaining structures are not explained here.

In the memory cell 400 having the above-described different structure, the gate electrode 53 is electrically connected to the word line WL, the first electrode 51 is electrically connected to the source line SL, and the second electrode is electrically connected to the bit line BL.

When a plurality of memory cells 400 as described above are arranged in an array along the second direction Y and the third direction X, which are parallel to the substrate 100, a single layer of memory array 310 is formed as shown in fig. 12. Thus, the first poles 51 of the plurality of memory cells arranged in the second direction Y share one source line SL extending in the second direction Y, the second poles 52 of the plurality of memory cells arranged in the second direction Y share one bit line BL extending in the second direction Y, the gates 55 of the plurality of memory cells arranged in the third direction X share one word line WL extending in the third direction X, and the plurality of word lines WL are arranged in parallel in the second direction Y.

In some alternative embodiments, as shown in fig. 13, fig. 13 is an M1 view of the structure shown in fig. 12, where the semiconductor layer 53 of two adjacent memory cells is disposed opposite to each other in the plurality of memory cells arranged along the second direction Y, for example, in fig. 13, there is shown a memory cell 401, a memory cell 402, a memory cell 403, and a memory cell 404 sequentially arranged along the second direction Y, where the semiconductor layer 53 of the memory cell 401 is disposed opposite to the semiconductor layer 53 of the memory cell 402, the gate 55 of the memory cell 402 is disposed opposite to the gate 55 of the memory cell 403, and further, the semiconductor layer 53 of the memory cell 403 is disposed opposite to the semiconductor layer 53 of the memory cell 404.

In addition to the memory array shown in fig. 12 and 13, when more memory cells 400 are further included, multiple layers of memory arrays may be stacked sequentially along the first direction Z perpendicular to the substrate 100 to form a three-dimensional memory structure, for example, two three-dimensional stacked memory arrays with different structures are shown in fig. 14 and 16.

Fig. 14 illustrates a three-dimensional process architecture diagram of a memory 300, the memory 300 comprising a first tier memory array 3101, a second tier memory array 3102 and a third tier memory array 3103 arranged along a first direction Z perpendicular to the substrate. Wherein the source line SL of the first layer memory array 3101 is close to the bit line BL of the second layer memory array 3102, the source line SL of the second layer memory array 3102 is close to the bit line BL of the third layer memory array 3103, and the source line SL of the first layer memory array 3101 and the bit line BL of the second layer memory array 3102 are signal lines independent of each other, the source line SL of the second layer memory array 3102 and the bit line BL of the third layer memory array 3103 are signal lines independent of each other. That is, the source lines and bit lines in each adjacent two-layer memory array are independent of each other.

In another alternative embodiment, as shown in fig. 15, the source line SL of the first layer storage array 3101 is close to the source line SL of the second layer storage array 3102, the bit line BL of the second layer storage array 3102 is close to the bit line BL of the third layer storage array 3103, the source line SL of the first layer storage array 3101 and the source line SL of the second layer storage array 3102 are signal lines independent from each other, the bit line BL of the second layer storage array 3102 and the bit line BL of the third layer storage array 3102 are signal lines independent from each other.

Fig. 16 illustrates a three-dimensional process architecture diagram of another memory 300, and like fig. 14 and 15 described above, the memory 300 of fig. 16 also illustrates a first tier memory array 3101, a second tier memory array 3102, and a third tier memory array 3103 arranged along a first direction Z perpendicular to the substrate. The source line SL of the first layer memory array 3101 is close to the source line SL of the second layer memory array 3102, and the bit line BL of the second layer memory array 3102 is close to the bit line BL of the third layer memory array 3103, unlike the source line SL of the first layer memory array 3101 and the source line SL of the second layer memory array 3102 described above with reference to fig. 14 and 15, the bit line BL of the second layer memory array 3102 and the bit line BL of the third layer memory array 3103 share the same signal line.

When the multi-layer memory array adopts the layout manner shown in fig. 16, since the signal lines close to each other of the memory arrays of two adjacent layers are shared, as shown in fig. 17, more multi-layer memory arrays can be integrated in the Z direction of the first direction, so as to further increase the density of the memory arrays and form a high-density memory array structure.

The ferroelectric memory according to the present application can be fabricated by back end of line (BEOL), and fig. 18 shows a BEOL schematic diagram of the back end of line. In fig. 18, the control circuit is fabricated on the substrate by a front-end-of-line process (front end of line, FEOL). The control circuitry may include one or more of the decoder 320, the driver 330, the timing controller 340, the buffer 350, or the input-output driver 360 as shown in fig. 3, and may also include other functional circuitry. The control circuit can control the signal lines (word line WL, source line SL, bit line BL) in the embodiment of the present application. After the front end of line FEOL is completed, both interconnect lines and memory arrays are fabricated by the back end of line BEOL. The memory array here includes a plurality of ferroelectric field effect transistors and portions of signal lines (word line WL, source line SL, bit line BL) corresponding to the plurality of memory cells, as described above. The interconnect lines include both interconnect lines connecting devices in the control circuit and other portions of the signal lines. The ferroelectric field effect transistor in the memory array is manufactured through a subsequent process, so that the circuit density in the unit area is higher, and the performance of the unit area is improved.

The following describes the read-write operation process of the above-mentioned memory cell in detail, and takes the ferroelectric field effect transistor as an NMOS transistor for explanation.

The voltage value list shown in table 1 is a voltage value on each signal line corresponding to the memory cell 401 and each signal line corresponding to the remaining memory cells 402, 403, and 404 when the memory cell 401 in the memory array 310 in fig. 19 is read and written. Wherein V is the first working voltage, V1 is the second working voltage, V2 is the third working voltage, and V3 is the fourth working voltage. The present application does not limit specific values of the first operating voltage V, the second operating voltage V1, the third operating voltage V2, and the fourth operating voltage V3.

Operation of	WL	Unsel WL	BL	Unsel BL	SL	Unsel SL
Write 1	V	V/3	0	2V/3	0	2V/3
Write 0	0	2V/3	V	V/3	V	V/3
Read 0/1	0	V1	V2	0	0	0

TABLE 1

In fig. 19, since the read/write operation is required for the selected memory cell 401, the word line electrically connected to the memory cell 401 is referred to as a selected word line WL, the bit line is referred to as a selected bit line BL, the source line is referred to as a selected source line SL, the word lines electrically connected to the remaining unselected memory cells 402, 403, 404 are referred to as unselected word lines un WL, the bit line is referred to as unselected bit lines un BL, and the source line is referred to as unselected source line un SL.

Writing to memory cell 401 actually changes the polarization state of the ferroelectric film layer in memory cell 401. When the absolute value of the voltage difference between the two ends of the ferroelectric film layer is larger than the coercive electric field of the ferroelectric film layer, the polarization state of the ferroelectric film layer is changed; when the absolute value of the voltage difference across the ferroelectric film layer is less than or equal to the coercive electric field of the ferroelectric film layer, the polarization state of the ferroelectric film layer is not changed. The strength of the coercive electric field can be measured from the material of the ferroelectric film layer and then an operating voltage V0 is set. When the absolute value of the voltage difference between the two ends of the ferroelectric film layer is larger than V0, the polarization state of the ferroelectric film layer is changed; when the absolute value of the voltage difference between the two ends of the ferroelectric film layer is less than or equal to V0, the polarization state of the ferroelectric film layer is not changed. In the voltage values shown in table one, for example, when the absolute value of the voltage difference across the ferroelectric film layer is greater than V/3, the polarization state of the ferroelectric film layer is changed, and when the absolute value of the voltage difference across the ferroelectric film layer is less than or equal to V/3, the polarization state of the ferroelectric film layer is not changed.

As shown in table 1, when the write "1" operation is performed on the memory cell 401, the selected word line WL receives the first operating voltage V, the selected bit line BL is grounded, and the selected source line SL is grounded, the voltage difference across the ferroelectric layer of the memory cell 401 is V, and V is greater than the operating voltage v0=v/3, so that the polarization state of the ferroelectric film layer in the memory cell 401 becomes positive polarization, thereby implementing the write "1" operation on the memory cell 401.

In addition, since the write "1" operation is not performed on the memory cell 402, the unselected bit line insel BL and the unselected source line insel SL electrically connected to the memory cell 402 each receive 2V/3, and the voltage difference across the ferroelectric layer of the memory cell 402 is V/3, and V/3 is less than or equal to the operation voltage v0=v/3, so that the change of polarization state of the ferroelectric film layer in the memory cell 402 is not caused, and the write "1" operation is not performed on the memory cell 402.

Since the write "1" operation is not required for the memory cell 403 and the memory cell 404, the unselected word line insel WL receives V/3, the unselected bit line insel BL and the unselected source line insel receive 2V/3, the voltage difference across the ferroelectric layer of the memory cell 402 is V/3, and V/3 is less than or equal to the operating voltage v0=v/3, so that the change of the polarization state of the ferroelectric film in the memory cell 403 is not caused, the write "1" operation is not performed for the memory cell 403, and the voltage difference across the ferroelectric layer of the memory cell 404 is-V/3, that is, the absolute value of the voltage difference is less than or equal to the operating voltage v0=v/3, so that the change of the polarization state of the ferroelectric film in the memory cell 404 is not caused, and the write "1" operation is not performed for the memory cell 404.

As shown in table 1, when the write "0" operation is performed on the memory cell 401, the selected word line WL is grounded, and the selected bit line BL and the selected source line SL both receive V, the voltage difference across the ferroelectric layer of the memory cell 401 is-V, and the absolute value of-V is greater than the operation voltage v0=v/3, so that the polarization state of the ferroelectric film layer in the memory cell 401 becomes negative polarization, thereby implementing the write "0" operation on the memory cell 401.

Since the operation of writing "0" to the memory cell 402 is not performed, the unselected bit line insel BL and the unselected source line insel electrically connected to the memory cell 402 each receive V/3, and the voltage difference across the ferroelectric layer of the memory cell 402 is-V/3, that is, the absolute value of the voltage difference is less than or equal to the operation voltage v0=v/3, so that the change of polarization state of the ferroelectric film layer in the memory cell 402 is not caused, and the operation of writing "0" to the memory cell 404 is not performed.

Since the operation of writing "0" to the memory cell 403 and the memory cell 404 is not required, the unselected word line insel WL receives 2V/3, the unselected bit line insel BL and the unselected source line insel SL both receive V/3, and the voltage difference between the two ends of the ferroelectric layer of the memory cell 403 is-V/3, that is, the absolute value of the voltage difference is less than or equal to the operation voltage v0=v/3, so that the change of polarization state of the ferroelectric film layer in the memory cell 402 is not caused, and the operation of writing "0" to the memory cell 404 is not performed; also, the voltage difference across the ferroelectric layer of the memory cell 404 is V/3, that is, the voltage difference is less than or equal to the operating voltage v0=v/3, so that the change of the polarization state of the ferroelectric film layer in the memory cell 404 is not caused, and the writing of "0" to the memory cell 404 is not performed.

As shown in Table 1, when a read operation is performed on memory cell 401, selected word line WL receives V3 (e.g., V3 is 0 or V3 is a voltage between two threshold voltages), selected bit line BL receives V2 (V2 is greater than 0 due to the NPOS transistor selected), and selected source line SL is grounded. Whether the ferroelectric field effect transistor of memory cell 401 is in an on or off state depends on the polarization state of the ferroelectric layer in memory cell 401.

If the ferroelectric film layer of the memory cell 401 is in the positive polarization state, that is, if the data stored in the memory cell 401 is "1", the ferroelectric field effect transistor of the memory cell 401 is in the on state, and the "1" state of the memory cell is read by detecting the current of the selected bit line BL.

If the ferroelectric film layer of the memory cell 401 is in the negative polarization state, that is, if the data stored in the memory cell 401 is "0", the ferroelectric field effect transistor of the memory cell 401 is in the off state, and the "0" state of the memory cell is read by detecting the current of the selected bit line BL.

In addition, since the read operation is not performed on the memory cell 402, both the unselected bit line un sel BL and the unselected source line un SL electrically connected to the memory cell 402 are grounded, and thus the read operation is not performed on the memory cell 402.

Also, since the read operation is not performed on the memory cell 403 and the memory cell 404, the unselected word line ensel WL receives V1 to put the ferroelectric field effect transistor of the memory cell 403 in the off state and the ferroelectric field effect transistor of the memory cell 404 in the off state, the read operation is not performed on the memory cell 403 and the memory cell 404.

The method for manufacturing the ferroelectric memory according to the present application is exemplified by forming a control circuit on a substrate; forming an interconnection line on the control circuit; then, a plurality of memory cells arranged in an array are formed on the interconnect line, and the control circuit and the plurality of memory cells are electrically connected through the interconnect line, so that reading and writing of the memory cells are controlled by the control circuit.

In forming a memory cell, a first pole and a second pole are formed along a first direction perpendicular to a substrate, and a semiconductor layer, a gate electrode and a ferroelectric layer are formed, wherein one of two opposite sides of the gate electrode along the second direction is provided with the semiconductor layer, the semiconductor layer is respectively electrically connected with the first pole and the second pole, and the ferroelectric layer is formed between the gate electrode and the semiconductor layer to form a ferroelectric field effect transistor of the memory cell.

The present application provides specific preparation methods for preparing a plurality of different memory cell structures, and the detailed explanation is given below.

Fig. 20a to 20j are cross-sectional views showing a process structure after each step in a process for manufacturing a memory cell according to the present application.

As shown in fig. 20a, the first electrode 51, the insulating layer 561, the gate electrode 55, and the insulating layer 562 are sequentially stacked in a first direction Z perpendicular to the substrate.

The materials of the first electrode 51, the insulating layer 561, the gate electrode 55, and the insulating layer 562 are described above and will not be described here.

As shown in fig. 20b, a plurality of first grooves 101 are formed along a second direction Y parallel to the substrate, the first grooves 101 penetrating through the insulating layer 562, the gate electrode 55, and the insulating layer 561. That is, the first trench 101 cannot pass through the first pole 51 because the first pole 51 may serve as a bit line BL or a source line SL of the memory array.

As shown in fig. 20c, an insulating material is filled in the first trench 101 to form an insulating layer 563.

In filling the insulating material to form the insulating layer 563, a deposition process such as physical vapor deposition (physical vapor deposition, PVD), chemical vapor deposition (chemical vapor deposition, CVD), or electrochemical deposition (electro-chemcial deposition, ECD) may be selected.

As shown in fig. 20d, the second trench 102 is opened, and the second trench 102 is opened between adjacent insulating layers 563, and the second trench 102 penetrates the insulating layer 562, the gate 55, and the insulating layer 561.

As shown in fig. 20e, the ferroelectric layer 54 is formed in the second trench 102.

In the case of the ferroelectric layer 54, the ferroelectric layer 54 may be formed by deposition, sputtering, or the like, for example, when the deposition method is used, the ferroelectric layer 54 is formed on the bottom surface, the side surface, and the upper surface of the insulating layer 562 of the second trench 102.

As shown in fig. 20f, the bottom surface of the second trench 102 and the upper surface of the insulating layer 562 need to be removed, for example, by dry etching, to remove the bottom surface of the second trench 102 and the ferroelectric layer 54 on the upper surface of the insulating layer 562 to obtain the structure shown in fig. 20 f.

As shown in fig. 20g, a semiconductor layer 53 is formed.

As in the process of forming the ferroelectric layer 54, deposition, sputtering, or the like may be employed, so that the semiconductor layer 53 is formed on the bottom surface of the second trench 102, the side wall surface of the ferroelectric layer 54, and the upper surface of the insulating layer 562, as shown in fig. 20 g.

As shown in fig. 20h, the bottom surface of the second trench 102 and the semiconductor layer 53 on the upper surface of the insulating layer 562 are removed, thereby obtaining the structure shown in fig. 20 h.

As shown in fig. 20i, the space remaining in the second trench 102 is filled with an insulating material to form an insulating layer 564.

As shown in fig. 20j, a second pole 52 is formed on the insulating layer 562. The second pole 52 here forms the source line SL or bit line BL of the memory array.

Based on the above description of the process steps, a plurality of memory cells arranged in the Y direction can be fabricated, and the first poles 51 of the memory cells are connected to form one of the bit line BL or the source line SL, and the second poles 52 of the memory cells are connected to form the other of the bit line BL or the source line SL.

Fig. 21a to 21j are cross-sectional views illustrating a process structure after each step is completed in a process for manufacturing another memory cell according to the present application.

As shown in fig. 21a, the first electrode 51, the insulating layer 561, the gate electrode 55, and the insulating layer 562 are sequentially stacked in a first direction Z perpendicular to the substrate.

As shown in fig. 21b, a plurality of first grooves 101 are formed along a second direction Y parallel to the substrate, the first grooves 101 penetrating through the insulating layer 562, the gate electrode 55, and the insulating layer 561.

As shown in fig. 21c, an insulating material is filled in the first trench 101 to form an insulating layer 563.

As shown in fig. 21d, the second trench 102 is opened, and the second trench 102 is opened between adjacent insulating layers 563, and the second trench 102 penetrates the insulating layer 562, the gate 55, and the insulating layer 561.

The process steps of fig. 21a to 21d are the same as those of fig. 20a to 20d described above, and the same process means may be used in each of the same process steps.

As shown in fig. 21e, the ferroelectric layer 54, the semiconductor layer 55, and the insulating layer 564 are sequentially formed in the second trench 102.

Unlike the above-described process method, in this process structure, after the ferroelectric layer 54 is formed, the ferroelectric layer 54 formed on the bottom surface of the second trench 102 does not need to be removed, but the semiconductor layer 55 is directly formed on the ferroelectric layer 54, so that the ferroelectric layer 54 on the side wall surface of the second trench 102 is not contaminated by the etching process when the ferroelectric layer 54 on the bottom surface of the second trench 102 is removed, and the memory performance of the final ferroelectric layer 54 is not affected.

As shown in fig. 21f, the insulating layer 564, the semiconductor layer 55, and the ferroelectric layer 53 on the bottom surface of the second trench 102, and the insulating layer 564, the semiconductor layer 55, and the ferroelectric layer 53 on the upper surface of the insulating layer 562 are removed, so that the ferroelectric layer 53, the semiconductor layer 55, and the insulating layer 564 are sequentially formed only on the side wall surface of the second trench 102 as shown in fig. 21 f.

As shown in fig. 21g, the connection electrode 59 is formed so that the connection electrode 59 is formed on the bottom surface of the second groove 102, the insulating layer 564, and the upper surface of the insulating layer 562.

As shown in fig. 21h, the bottom surface of the second trench 102 is removed, and the connection electrode 59 near the opening of the second trench 102 is removed, and the connection electrode 59 is formed by removing the upper surface of the insulating layer 562. In this way, the semiconductor layer 53 can be electrically connected to the first electrode 51 through the connection electrode 59.

As shown in fig. 21i, the space remaining in the second trench 102 is filled with an insulating material to form an insulating layer 564.

As shown in fig. 21j, a second pole 52 is formed on the insulating layer 562.

Based on the above-described process steps, a plurality of memory cells arranged in the Y-direction may also be manufactured, the first poles 51 being electrically connected to the second poles 52 through the semiconductor layer 53 and the connection electrode 59, and the first poles 51 of the memory cells being connected to form one of the bit lines BL or the source lines SL, and the second poles 52 of the memory cells being connected to form the other of the bit lines BL or the source lines SL.

Fig. 22a to 22j are cross-sectional views illustrating a process structure after each step is completed in the process of manufacturing another memory cell according to the present application.

As shown in fig. 22a, the conductive layer 581, the first electrode 51, the sacrificial layer 57, and the second electrode 52 are stacked in this order along a first direction Z perpendicular to the substrate.

As shown in fig. 22b, a plurality of first trenches 101 are formed at intervals in the second direction Y parallel to the substrate, and the first trenches 101 penetrate the second electrode 52, the sacrificial layer 57 and the first electrode 51, that is, the first trenches 101 cannot penetrate the conductive layer 581, because the conductive layer 581 is ultimately used as the source line SL or the bit line BL of the memory array.

As shown in fig. 22c, the first trench 101 is filled with an insulating material to form an insulating layer 562, and a second trench 102 is opened, wherein the second trench 102 is located between two adjacent insulating layers 562, and the second trench 102 penetrates through the second pole 52, the sacrificial layer 57 and the first pole 51.

As shown in fig. 22d, the sacrificial layer 57 in contact with the insulating layer 562 is removed to form a plurality of cavities 103 shown in fig. 22 d. In this way, a semiconductor layer, a ferroelectric layer, and a gate electrode can be formed in the cavity 103.

In some alternative embodiments, the sacrificial layer 57 may be removed by a selective etching process, for example, when the material of the sacrificial layer 57 is silicon oxide, a hydrofluoric acid etching medium may be used for etching.

As shown in fig. 22e, a semiconductor layer 53 is formed on the wall surface of the cavity 8.

Since a deposition process such as PVD, CVD, or ECD may be used to form the semiconductor layer 53, the semiconductor layer 53 is formed not only on the wall surface of the cavity 103 but also on the side surface of the second electrode 52 and the first electrode 51 away from the insulating layer 562.

As shown in fig. 22f, a ferroelectric layer 54 is formed again, and the ferroelectric layer 54 is formed on the semiconductor layer 53. After the formation of the semiconductor layer 53 and the ferroelectric layer 54, there is also a space in the cavity 103 for accommodating the gate.

As shown in fig. 22g, the gate 55 is formed in the space remaining in the cavity 103.

In fig. 22g, the gates 55 of two adjacent memory cells in the Y direction are integrally connected to each other when the gates 55 are formed, and further, as shown in fig. 22h, the third grooves 103 are formed so that the gates 55 of two adjacent memory cells in the Y direction are disconnected.

As shown in fig. 22i, an insulating layer 563 is formed in the third trench 103 to insulate between the gates 55 of adjacent two memory cells in the Y direction.

As shown in fig. 22j, a conductive layer 582 is formed on the upper surface of the second pole 52, and the conductive layer 582 serves as a source line SL or a bit line BL of the memory array.

Based on the above-formed memory cell, the semiconductor layer 53 is formed with a recess in which the ferroelectric layer 54 and the gate electrode 55 are located. Also, a plurality of memory cells share one source line SL by forming the source line SL (or the bit line BL) at a side near the first pole 51, and a plurality of memory cells share one bit line BL by forming the bit line BL (or the source line SL) at a side near the second pole 51.

Fig. 23a to 23j are cross-sectional views showing a process structure after each step is completed in the process of manufacturing another memory cell according to the present application.

As shown in fig. 23a, the conductive layer 581, the first electrode 51, the sacrificial layer 57, and the second electrode 52 are stacked in this order along a first direction Z perpendicular to the substrate.

As shown in fig. 23b, a plurality of first grooves 101 are formed along a second direction Y parallel to the substrate, the first grooves 101 penetrating the second electrode 52, the sacrificial layer 57 and the first electrode 51. I.e. the first trench 101 cannot penetrate the conductive layer 581, since this conductive layer 581 eventually serves as a source line SL or bit line BL of the memory array.

As shown in fig. 23c, the semiconductor layer 53 is formed on the sidewall surface of the first trench 101, the insulating layer 562 is formed in the remaining space of the first trench 101, the second trench 102 is opened, the second trench 102 is located between two adjacent insulating layers 562, and the second trench 102 penetrates the second pole 52, the sacrificial layer 57, and the first pole 51.

As shown in fig. 23d, the sacrificial layer 57 in contact with the semiconductor layer 53 is removed to form a plurality of cavities 103 shown in fig. 23 d. In this way, ferroelectric layers and gates may be formed within the cavity 103.

As shown in fig. 23e, a ferroelectric layer 54 is formed on the wall surface of the cavity 8.

Since a deposition process such as PVD, CVD, or ECD may be used in forming the ferroelectric layer 54, the ferroelectric layer 54 is formed not only on the wall surface of the cavity 103 but also on the side of the second pole 52 and the first pole 51 away from the insulating layer 562.

As shown in fig. 23f, the gate 55 is formed in the space remaining in the cavity 103.

In fig. 23f, the gates 55 of two adjacent memory cells in the Y direction are integrally connected to each other when the gates 55 are formed, and further, as shown in fig. 23g, the third grooves 103 are formed so that the gates 55 of two adjacent memory cells in the Y direction are disconnected.

As shown in fig. 23h, an insulating layer 563 is formed in the third trench 103 to insulate between the gates 55 of adjacent two memory cells in the Y direction.

As shown in fig. 23i, a conductive layer 582 is formed on the upper surface of the second pole 52, and the conductive layer 582 serves as a source line SL or a bit line BL of the memory array.

Fig. 24a to 24g are cross-sectional views showing a process structure after each step in a process of manufacturing a memory cell according to the present application.

As shown in fig. 24a, the second pole 52, the sacrificial layer 57, and the first pole 51 are stacked in this order in a first direction Z direction perpendicular to the substrate.

As shown in fig. 24b, a plurality of first grooves 101 are formed along a second direction Y parallel to the substrate, the first grooves 101 penetrating the first pole 51, the sacrificial layer 57 and the second pole 52.

As shown in fig. 24c, the ferroelectric layer 54 and the gate electrode 55 are sequentially formed at the side of the first trench 101, and an insulating material is filled in the remaining space of the first trench 101 to form an insulating layer 581. And a second slot 102 is opened again, and the second slot 102 is opened in an adjacent structure having the ferroelectric layer 54 and the gate electrode 55, and the second slot 102 penetrates the first pole 51, the sacrificial layer 57 and the second pole 52.

As shown in fig. 24d, the sacrificial layer 57 is removed to form a cavity 103 having an opening between the first pole 51 and the second pole 52.

The surface of the first pole 51 facing the second pole 52 is a first wall surface, and the surface of the second pole 52 facing the first pole 51 is a second wall surface.

As shown in fig. 24e, the semiconductor layer 53 is formed in the cavity 103. The semiconductor layer 53 is formed on the first wall surface of the first electrode 51, the second wall surface of the second electrode 52, and the side surface of the ferroelectric layer 54 away from the gate electrode 55. In forming the semiconductor layer 53, a deposition process or the like may be used, for example, when a deposition method is used, as shown in fig. 24e, the semiconductor layer 53 is formed on the side surface of the first electrode 51 and on the side surface of the second electrode 52, respectively.

As shown in fig. 24f, the semiconductor layer 53 on the side of the first pole 51 and the side of the second pole 52 needs to be removed, for example, dry etching, to obtain the structure shown in fig. 24 f.

As shown in fig. 24g, insulating material is filled in the remaining space of the cavity and between the divided first poles 51 and the divided second poles 52 to form an insulating layer 582.

In some alternative embodiments, when the process steps shown in fig. 24a are performed, a metal layer may be formed on a side of the second electrode 52 remote from the first electrode 51 when stacking the second electrode 52, the sacrificial layer 57 and the first electrode 51, and when the first trench 101 and the second trench 102 are opened, none of these trenches can penetrate the metal layer, and in the finally formed memory, the metal layer may serve as a bit line BL for electrically connecting the second electrodes 52 of the plurality of memory cells arranged in the Y direction.

Based on the memory cells with different structures manufactured by adopting different process means, the semiconductor layer is arranged on one of two opposite sides of the grid along the second direction instead of surrounding the semiconductor along the periphery of the grid, so that more memory cells can be manufactured above the substrate, the storage capacity of the memory is improved, and the reading and writing speed of the memory is improved.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A ferroelectric memory, comprising:

a substrate;

a plurality of memory cells formed on the substrate;

each of the memory cells includes: a ferroelectric field effect transistor;

wherein the ferroelectric field effect transistor includes: a gate electrode, a semiconductor layer, first and second electrodes, and a ferroelectric layer;

The first pole and the second pole are arranged along a first direction perpendicular to the substrate, the grid electrode is positioned between the first pole and the second pole, one of two opposite sides of the grid electrode along a second direction is provided with the semiconductor layer, the semiconductor layer is respectively and electrically connected with the first pole and the second pole, the grid electrode and the semiconductor layer are separated by the ferroelectric layer, and the second direction is a direction parallel to the substrate.
The ferroelectric memory according to claim 1, wherein the semiconductor layer is a vertical-like structure extending in the first direction, and one of opposite ends of the semiconductor layer in the first direction is in contact with the first pole and the other end is in contact with the second pole.
The ferroelectric memory according to claim 2, wherein a surface of the first pole opposite to the second pole is a first wall surface, and a surface of the second pole opposite to the first pole is a second wall surface;

one of opposite ends of the semiconductor layer in the first direction is in contact with the first wall surface, and the other end is in contact with the second wall surface.
The ferroelectric memory according to claim 2, wherein a face of the first pole opposite to the second pole is a first wall face, and a first side face of the first pole adjacent to the first wall face;

a second side surface adjacent to the second wall surface in the second pole, wherein the first side surface and the second side surface are positioned on the same side;

one of opposite ends of the semiconductor layer in the first direction is in contact with the first side surface, and the other end is in contact with the second side surface.
The ferroelectric memory according to claim 1, wherein the semiconductor layer includes a first portion and a second portion each extending in the second direction, and a third portion extending in the first direction and connected to both the first portion and the second portion;

a surface of the first pole facing the second pole is a first wall surface, and a surface of the second pole facing the first pole is a second wall surface;

the first portion is disposed on the first wall and the second portion is disposed on the second wall.
The ferroelectric memory of claim 5, wherein said first portion, said second portion, and said third portion are joined in an integrally formed structure.
The ferroelectric memory according to claim 1, wherein the semiconductor layer includes a first portion extending in the second direction, and a third portion extending in the first direction and connected to the first portion;

a surface of the first pole facing the second pole is a first wall surface, and a surface of the second pole facing the first pole is a second wall surface;

the ferroelectric memory further comprises a connecting electrode, wherein the connecting electrode is arranged on the second wall surface;

the third portion is in contact with the first wall surface, and the first portion is in contact with the connection electrode.
The ferroelectric memory according to any one of claims 1 to 7, wherein a face opposite to the second pole in the first pole is a first wall face, and a face opposite to the first pole in the second pole is a second wall face;

the gate is located in an area between the first wall and the second wall.
The ferroelectric memory of any one of claims 1-7, wherein a face of the first pole opposite the second pole is a first wall face and a first side face of the first pole adjacent the first wall face;

A second side surface adjacent to the second wall surface in the second pole, wherein the first side surface and the second side surface are positioned on the same side;

the gate is located on one side of the first side and the second side.
The ferroelectric memory according to any one of claims 1 to 9, wherein the ferroelectric field effect transistor is fabricated using a post-process.
The ferroelectric memory of any one of claims 1-10, further comprising:

bit lines, source lines, and word lines;

wherein the gate is electrically connected to the word line, the first pole is electrically connected to the source line, and the second pole is electrically connected to the bit line.
The ferroelectric memory according to claim 11, wherein,

the source line and the bit line both extend along the second direction;

the word line extends along a third direction parallel to the substrate, and the second direction is perpendicular to the third direction;

the first poles of the plurality of memory cells arranged along the second direction are electrically connected with the same source line;

The second pole of the plurality of memory cells arranged along the second direction is electrically connected with the same bit line;

the gates of the plurality of memory cells arranged along the third direction are electrically connected to the same word line.
The ferroelectric memory according to claim 12, wherein the plurality of memory cells form a first-layer memory array and a second-layer memory array arranged along the first direction;

the source line extending along the second direction in the first-layer memory array is close to the source line extending along the second direction in the second-layer memory array;

the source lines in the first-layer memory array and the source lines in the second-layer memory array share the same signal line.
The ferroelectric memory according to claim 12, wherein the plurality of memory cells form a first-layer memory array and a second-layer memory array arranged along the first direction;

the source line extending along the second direction in the first-layer memory array is close to the bit line extending along the second direction in the second-layer memory array;

the source lines in the first-layer memory array and the bit lines in the second-layer memory array are independent signal lines.
The ferroelectric memory of any one of claims 11-14, further comprising a controller to:

outputting a word line control signal to control a voltage on the word line;

outputting a source line control signal to control a voltage on the source line; and

a bit line control signal is output to control the voltage on the bit line.
An electronic device, comprising:

a processor; and

the ferroelectric memory of any one of claims 1-15, the processor and the ferroelectric memory being electrically connected.
The electronic device of claim 16, wherein the electronic device comprises a memory device,

the processor and the ferroelectric memory are integrated in the same chip.
A method of forming a ferroelectric memory, comprising:

forming a first pole and a second pole along a first direction perpendicular to a substrate, and forming a semiconductor layer, a gate electrode and a ferroelectric layer, wherein one of two opposite sides of the gate electrode along the second direction is formed with the semiconductor layer, the semiconductor layer is respectively electrically connected with the first pole and the second pole, and the ferroelectric layer is formed between the gate electrode and the semiconductor layer to form a ferroelectric field effect transistor.
The method of forming a ferroelectric memory according to claim 18, wherein before forming the ferroelectric field effect transistor, the forming method further comprises:

forming a control circuit on the substrate;

an interconnect line electrically connecting the control circuit and the ferroelectric field effect transistor is formed on the control circuit.