CN117616895A

CN117616895A - Three-dimensional memory device and method of manufacturing the same

Info

Publication number: CN117616895A
Application number: CN202380008960.XA
Authority: CN
Inventors: 赵冬雪; 杨涛; 周文犀; 杨远程; 夏志良; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-06-22
Filing date: 2023-03-24
Publication date: 2024-02-27
Also published as: US20230422524A1

Abstract

Three-dimensional (3D) memory devices and methods of manufacture are disclosed. The disclosed 3D storage device includes: a first semiconductor structure, comprising: an array of first type through-stack structures in a first region of the storage stack; an array of second type through-stack structures in a second region of the storage stack; a semiconductor layer comprising a first portion on the array of first type through-stack structures and a second portion on the array of second type through-stack structures; a plurality of vias, each via penetrating the semiconductor layer and contacting a corresponding one of the first type through-stack structure or the array of second type through-stack structures; and a slit structure separating the array of first type through-stack structures from the array of second type through-stack structures and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

Description

Three-dimensional memory device and method of manufacturing the same

Cross Reference to Related Applications

The present application claims the benefit of priority from chinese application No.202210714042.6 filed on 22 th month 2022 and U.S. provisional application No.63/433,096 filed on 16 th month 2022, the disclosures of both of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a three-dimensional (3D) memory device and a method for manufacturing the same.

Background

With the continuous rise and development of Artificial Intelligence (AI), big data, internet of things, mobile devices and communications, cloud storage, etc., the demand for storage capacity has grown exponentially.

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

A three-dimensional (3D) memory architecture may address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuitry for facilitating operation of the memory array.

Disclosure of Invention

In one aspect, the present disclosure provides a method for forming a three-dimensional (3D) memory device, comprising: forming a first semiconductor structure, comprising: forming an array of first type through-stack structures in a first region of the storage stack and forming an array of second type through-stack structures in a second region of the storage stack, forming a semiconductor layer comprising a first portion over the array of first type through-stack structures and a second portion over the array of second type through-stack structures; forming a plurality of vias, each via penetrating the semiconductor layer and contacting a corresponding one of the first type through-stack structure or the second type through-stack structure; and forming a slit structure to separate the array of the first type through-stack structure from the array of the second type through-stack structure and to separate the first portion of the semiconductor layer from the second portion of the semiconductor layer.

In some embodiments, forming the first semiconductor structure further comprises forming a dielectric stack comprising a plurality of alternating dielectric layers and sacrificial layers stacked on the first substrate, wherein the array of first type through-stack structures and the array of second type through-stack structures penetrate the dielectric stack; forming a slit vertically penetrating the dielectric stack and laterally separating the array of first type through-stack structures from the array of second type through-stack structures; and replacing the plurality of sacrificial layers with a plurality of conductive layers to convert the dielectric stack into a storage stack; wherein the slit structure is formed to fill the slit.

In some embodiments, the method further comprises: forming a second semiconductor structure including peripheral circuitry on a second substrate; and bonding the second semiconductor structure to the first semiconductor structure.

In some embodiments, forming the first type and the second type of through-stack structure includes: forming a plurality of through-stack holes, each through-stack hole penetrating the dielectric stack; filling a second subset of the through-stack holes with a sacrificial material; forming a first type of through-stack structure in a first subset of through-stack holes; removing the sacrificial material in the second subset of through-stack holes; and forming a second type of through-stack structure in a second subset of the through-stack holes.

In some embodiments, forming the first type of through-stack structure includes forming a NAND channel structure; and forming the second type of through-stack structure includes forming a capacitor type ferroelectric through-stack structure.

In some embodiments, forming the first type of through-stack structure includes forming a NAND channel structure; and forming the second type through-stack structure includes forming a FET-type ferroelectric through-stack structure.

In some embodiments, the method further comprises: forming a via, comprising: forming a plurality of through holes, wherein each through hole penetrates through the semiconductor layer and exposes the corresponding first type or second type through stacked structure; filling the through hole with a dielectric material; and forming vias surrounded by dielectric material in the corresponding through holes.

In some embodiments, the method further includes forming a plurality of kerf structures, each kerf structure extending laterally between the vias and vertically separating portions of the semiconductor layer.

In some embodiments, forming the first semiconductor structure further comprises: forming a first interconnect layer including a plurality of first interconnects in contact with the vias; and forming a first bonding layer comprising a plurality of first bonding contacts in contact with the first interconnect; forming the second semiconductor structure includes: forming a second interconnect layer in contact with a plurality of second interconnects of the plurality of transistors of the peripheral circuit; and forming a second bonding layer comprising a plurality of second bonding contacts in contact with the second interconnect; and bonding the second semiconductor structure to the first semiconductor structure includes bonding the first bonding layer to the second bonding layer such that each first bonding contact engages with a corresponding second bonding contact.

Another aspect of the present disclosure provides a three-dimensional (3D) storage device, including: a first semiconductor structure, comprising: an array of first type through-stack structures in a first region of the storage stack and an array of second type through-stack structures in a second region of the storage stack; a semiconductor layer including a first portion on the array of first type through-stack structures and a second portion on the array of second type through-stack structures; a plurality of vias, each via penetrating the semiconductor layer and contacting a corresponding one of the first type through-stack structure or the array of second type through-stack structures; and a slit structure separating the array of first type through-stack structures from the array of second type through-stack structures and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

In some embodiments, the storage device further comprises: a second semiconductor structure including peripheral circuitry; wherein the second semiconductor structure is bonded to the first semiconductor structure.

In some embodiments, the first type of through-stack structure is a NAND channel structure; and the second type of through-stack structure is a capacitor type ferroelectric through-stack structure.

In some embodiments, each capacitor-type ferroelectric through stack structure includes: a ferroelectric layer; and a conductive structure laterally surrounded by the dielectric film.

In some embodiments, the first type of through-stack structure is a NAND channel structure; and the second type of through-stack structure is a FET-type ferroelectric through-stack structure.

In some embodiments, each FET-type ferroelectric through stack structure includes: a ferroelectric layer; a conductive layer laterally surrounded by the ferroelectric layer; and a dielectric fill structure laterally surrounded by the conductive layer.

In some embodiments, a dielectric layer on the semiconductor layer, wherein the vias each penetrate the dielectric layer and are isolated from the semiconductor layer by a dielectric material; and a plurality of kerf structures, each kerf structure extending laterally between the vias and the vertically spaced apart portions of the semiconductor layer.

In some embodiments, the first semiconductor structure further comprises: a first interconnect layer including a plurality of first interconnects in contact with the vias; and a first bonding layer including a plurality of first bonding contacts in contact with the first interconnect.

In some embodiments, the second semiconductor structure further comprises: a second interconnect layer including a plurality of second interconnects in contact with a plurality of transistors of the peripheral circuit; and a second bonding layer comprising a plurality of second bonding contacts in contact with the second interconnect, wherein the first bonding layer and the second bonding layer are bonded at a bonding interface such that each first bonding contact engages a corresponding second bonding contact.

Another aspect of the present disclosure provides a memory system, comprising: a storage device configured to store data, and comprising: an array of first type through-stacked structures in a first region and an array of second type through-stacked structures in a second region; a semiconductor layer including a first portion on the array of first type through-stack structures and a second portion on the array of second type through-stack structures; a plurality of vias each penetrating the semiconductor layer and contacting a corresponding one of the first type through-stack structure or the array of second type through-stack structures; and a slit structure separating the array of first type through-stacked structures from the array of second type through-stacked structures and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer; and a memory controller coupled to the storage device and configured to control the storage device.

In some embodiments, the first type of through-stack structure is a NAND channel structure; and the second type of through-stack is a capacitor type ferroelectric through-stack or a FET type ferroelectric through-stack.

Another aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device, comprising: forming a first semiconductor structure comprising an array of first type through-stack structures in a first region of the storage stack and an array of second type through-stack structures in a second region of the storage stack; forming a second semiconductor structure including peripheral circuitry; and bonding the second semiconductor structure to the first semiconductor structure.

In some embodiments, forming the first semiconductor structure includes: forming an array of NAND channel structures in the first region as an array of first type through-stack structures; and forming an array of FET-type ferroelectric through-stacks as an array of second-type through-stacks in the second region.

In some embodiments, forming the first semiconductor structure further comprises: forming a dielectric stack comprising a stacked plurality of alternating dielectric layers and sacrificial layers, wherein the array of first type through-stack structures and the array of second type through-stack structures penetrate the dielectric stack; forming a slit vertically penetrating the dielectric stack and laterally separating the array of first type through-stack structures from the array of second type through-stack structures; and replacing the plurality of sacrificial layers with a plurality of conductive layers to convert the dielectric stack into a storage stack; a slit structure is formed to fill the slit.

In some embodiments, the method further comprises: forming a plurality of kerf structures, each kerf structure extending vertically to separate top conductive layers of the storage stack, wherein the plurality of kerf structures comprises: a first kerf structure extending laterally between the first type through-stack structure and the second type through-stack structure; a second kerf structure extending laterally between the first type through-stack structures; and a third kerf structure extending laterally between the second type through-stack structures.

In some embodiments, forming the first semiconductor structure further comprises: forming a first interconnect layer comprising a plurality of first interconnects in contact with the first type through-stack structure and the second type through-stack structure; and forming a first bonding layer comprising a plurality of first bonding contacts in contact with the first interconnect; forming the second semiconductor structure includes: forming a second interconnect layer including a plurality of second interconnects in contact with a plurality of transistors of the peripheral circuit; and forming a second bonding layer comprising a plurality of second bonding contacts in contact with the second interconnect; and bonding the second semiconductor structure to the first semiconductor structure includes bonding the first bonding layer to the second bonding layer such that each first bonding contact engages with a corresponding second bonding contact.

In some embodiments, forming the second type of through-stack structure includes: forming a ferroelectric layer on sidewalls of each of the second subset of through-stack vias; forming a conductive layer to cover the ferroelectric layer; and forming a dielectric fill structure on the ferroelectric layer to fill the second subset of through-stack vias.

Another aspect of the present disclosure provides a three-dimensional (3D) storage device, including: a first semiconductor structure, comprising: a memory stack comprising a plurality of alternating dielectric and conductive layers, an array of first type through-stack structures in a first region of the memory stack, and an array of second type through-stack structures in a second region of the memory stack; and a second semiconductor structure including peripheral circuitry, wherein the second semiconductor structure is bonded to the first semiconductor structure.

In some embodiments, the first type through stack structure and the second type through stack structure are located in adjacent memory blocks separated by a spacer.

In some embodiments, the storage device further comprises: a plurality of kerf structures, each kerf structure extending vertically to separate top conductive layers of the storage stack, wherein the plurality of kerf structures comprises: a first kerf structure extending laterally between the first type through-stack structure and the second type through-stack structure; a second kerf structure extending laterally between the first type through-stack structures; and a third kerf structure extending laterally between the second type through-stack structures.

In some embodiments, the first semiconductor structure further comprises: a first interconnect layer including a plurality of first interconnects in contact with the first type through-stack structure and the second type through-stack structure; and a first bonding layer including a plurality of first bonding contacts in contact with the first interconnect.

Another aspect of the present disclosure provides a memory system, comprising: a storage device configured to store data, and comprising: a first semiconductor structure, comprising: a memory stack comprising a plurality of alternating dielectric and conductive layers, an array of first type through-stack structures in a first region of the memory stack, and an array of second type through-stack structures in a second region of the memory stack; and a second semiconductor structure including peripheral circuitry, wherein the second semiconductor structure is bonded to the first semiconductor structure; a memory controller coupled to the storage device and configured to control the storage device.

In some implementations, the memory system further includes: a plurality of kerf structures, each kerf structure extending vertically to separate top conductive layers of the storage stack, wherein the plurality of kerf structures comprises: a first kerf structure extending laterally between the first type through-stack structure and the second type through-stack structure; a second kerf structure extending laterally between the first type through-stack structures; and a third kerf structure extending laterally between the second type through-stack structures.

Other aspects of the present disclosure will be appreciated by those skilled in the art from the specification, claims and drawings of the present disclosure.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a schematic diagram of a cross-sectional view of an exemplary 3D memory device, in accordance with aspects of the present disclosure.

Fig. 2A is a schematic cross-sectional view of an exemplary 3D memory device according to some aspects of the present disclosure.

Fig. 2B is a schematic top view of an exemplary 3D storage device according to some aspects of the present disclosure.

Fig. 2C is a schematic cross-sectional view of another exemplary 3D memory device according to some other aspects of the present disclosure.

Fig. 2D is a schematic top view of another exemplary 3D storage device according to some other aspects of the present disclosure.

Fig. 3A is a schematic cross-sectional view of a portion of an exemplary 3D memory device, according to some aspects of the present disclosure.

Fig. 3B is a schematic cross-sectional view of another portion of an exemplary 3D memory device according to some aspects of the present disclosure.

Fig. 3C is a schematic cross-sectional view of a portion of an exemplary 3D memory device, according to some aspects of the present disclosure.

Fig. 4 illustrates a block diagram of an exemplary system having a storage device, in accordance with aspects of the present disclosure.

Fig. 5A illustrates a diagram of an exemplary memory card with a memory device, in accordance with aspects of the present disclosure.

Fig. 5B illustrates a diagram of an exemplary Solid State Drive (SSD) with a storage device, according to some aspects of the disclosure.

Fig. 6A-6C illustrate a flowchart of a method for forming an exemplary 3D memory device, according to some aspects of the present disclosure.

Fig. 7A-7L illustrate a fabrication process for forming an exemplary 3D memory device according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

Generally, terms may be understood, at least in part, from the use of context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a" or "an" may be equally understood as conveying a singular usage or a plural usage, depending at least in part on the context. In addition, also depending at least in part on the context, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described.

It should be readily understood that the meanings of "on", "over" and "over" in this disclosure should be interpreted in the broadest sense so that "on" means not only directly on "something but also includes the meaning of having an intermediate feature or layer therebetween, and" over "or" over "means not only the meaning of" over "or" over "something, but also the meaning of" over "or" over "something and no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as "below," "lower," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers in which interconnect lines and/or vertical interconnect access (via) contacts are formed, and one or more dielectric layers.

The term "dynamic random access memory" or "DRAM" as used herein refers to a volatile memory that uses charge stored on a capacitor to represent information. The DRAM stores each bit in a memory cell that includes a transistor and a capacitor (e.g., 1T 1C). The 1T1C design may be based on Metal Oxide Semiconductor (MOS) technology. A charge level greater than a certain threshold may represent a first logic level (e.g., a 1 state) and a charge level less than another threshold amount may represent a second logic level (e.g., a 0 state). Leakage currents and various parasitics can limit the length of time that a capacitor can hold charge.

The term "NAND" as used herein refers to a memory design or architecture that is similar to NAND logic gates (e.g., inverting AND gates) AND connects memory cells in series (e.g., memory strings). In NAND flash memory, the relationship between bit lines and word lines is similar to that of NAND logic gates, and can be used for fast writing and high density arrays. NAND flash memory can sequentially access data because the transistors in the array are connected in series (e.g., a memory string). NAND flash memory can be read, programmed (written) and erased in blocks or pages. NAND flash memory may have a smaller cell size than DRAM, but may require additional circuitry to implement.

The term "surrounding gate transistor" or "SGT" as used herein refers to a memory device having a gate surrounding the channel region of the transistor on all sides.

The term "dynamic flash" or "DFM" as used herein refers to volatile memory that uses a dual-gate SGT or a multi-gate SGT. The double gates of the double gate SGT may include Word Line (WL) gates and Plate Line (PL) gates. The multiple gates of the multi-gate SGT may include Word Line (WL) gates and multi-Plate Line (PL) gates. The DFM may have no capacitor and may store charge on the channel region of the transistor. DFM may still require a refresh period, but may provide longer retention times, faster operating speeds, and higher densities than DRAM or other types of volatile memory. Further, similar to flash memory, DFM may provide block refresh and block erase operations.

The term "bit line" or "BL" as used herein indicates an array connection used to address a particular memory cell in a memory array. The bit line may be connected to the drain of the transistor. The bit line may be connected to two or more memory cells (e.g., memory strings) connected in series. The different combinations of voltages applied to the bit lines may define read, program (write) and erase operations in the memory cell.

The term "source line" or "SL" as used herein indicates an array connection for addressing a particular memory cell in a memory array. The source line may be connected to a source of the transistor. The source line may be connected to two or more memory cells (e.g., memory strings) connected in series. The different combinations of voltages applied to the source lines may define read, program (write) and erase operations in the memory cell.

The term "word line" or "WL" as used herein indicates an array connection for providing a voltage to a particular memory cell in a memory array to select which row of bits to read, program, or erase. The word line may act as a Top Select Gate (TSG). The word line may be connected to a portion of the channel or a portion of the body of a transistor (e.g., DFM device). The different combinations of voltages applied to the word lines may define read, program (write) and erase operations in the memory cell. When the word line is activated, current will flow only when charge has been on the memory cell. If there is charge on the channel or body of the memory cell, the read operation will recharge the memory cell and be non-destructive. If there is no charge on the channel or body of the memory cell, no current flows and the read is also non-destructive.

The term "plate line" or "PL" as used herein indicates an array connection for providing a voltage to a particular memory cell in a memory array to read, program, or erase the charge on the memory cell. The plate line may be connected to a portion of a channel or a portion of a body of a transistor (e.g., a DFM device). The different voltage combinations applied to the plate lines may define read, program (write) and erase operations in the memory cell. When the plate line is activated, charge flows from the source line (source) to the bit line (drain). When the plate line is deactivated, any remaining charge is stored in the channel or body of the memory cell.

The term "dummy line" or "DMY" as used herein indicates an array connection separate from the word line that provides additional voltage to a particular memory cell in the memory array to improve operating efficiency. The dummy line may be used for impact ionization programming to rapidly increase charge (e.g., holes) conduction generated at the word line contact to flow and increase charge (e.g., holes) in the channel of the memory cell. The dummy line may increase the programming (writing) rate of the memory cell.

The term "top select gate line" or "TSG" as used herein indicates an array connection for providing a voltage to a particular memory cell in a memory array to select which row of bits to read, program, or erase. The top select gate line may be used for Gate Induced Drain Leakage (GIDL) programming to create a charge (e.g., hole) barrier to provide selective programming (writing) in the channel of the memory cell. The top select gate line may provide selective programming (writing) and increase the programming (writing) rate. The top select gate line may provide charge separation between the plate line and the bit line, thereby increasing charge retention time and decreasing refresh rate in the memory cell. The top select gate line may provide charge separation between the plate line and the bit line, thereby reducing junction leakage. The top select gate line may increase the depletion region of the memory cell.

The term "bottom select gate line" or "BSG" as used herein indicates an array connection for providing a voltage to a particular memory cell in a memory array to select which row of bits to read, program, or erase. The bottom select gate line may be used for Gate Induced Source Leakage (GISL) programming to create a charge (e.g., hole) barrier to provide selective programming (writing) in the channel of the memory cell. The bottom select gate line may provide selective programming (writing) and increase the programming (writing) rate. The bottom select gate line may provide charge separation between the plate line and the source line, thereby increasing charge retention time and reducing refresh rate in the memory cell. The bottom select gate line may provide charge separation between the plate line and the source line, thereby reducing junction leakage. The bottom select gate line may increase the depletion region of the memory cell.

The term "substrate" as used herein refers to a planar wafer on which subsequent layers may be deposited, formed, or grown. The substrate may be formed of a single element (e.g., si) or a compound material (e.g., gaAs), and may be doped or undoped. For example, the substrate may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP+), gallium antimonide (GaSb), indium phosphide (InP+), indium antimonide (InSb), group IV semiconductors, group III-V semiconductors, group II-VI semiconductors, graphene, sapphire, and/or any other semiconductor material. The substrate may be a monocrystalline material (e.g., monocrystalline silicon).

The term "group III-V semiconductor" As used herein is meant to include one or more materials from group III of the periodic table (e.g., group 13 elements: boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl)) and one or more materials from group V of the periodic table (e.g., group 15 elements: nitrogen (N), phosphorus (p+), arsenic (As), antimony (Sb), bismuth (Bi)). The compounds have a 1:1 combination of groups III and V, regardless of the number of elements per group. The subscripts in the chemical symbols of the compounds indicate the proportions of the elements within the family. For example, al _0.25 GaAs means that the group III part comprises 25% aluminum and thus 75% gallium, while the group V part comprises 100% arsenic.

The term "group IV semiconductor" as used herein is meant to include two or more materials from group IV of the periodic table (e.g., group 14 elements: carbon (C), silicon (Si), germanium (Ge), tin (Sn), lead (Pb)). The subscripts in the chemical symbols of the compounds indicate the proportions of the elements. For example, si _0.25 Ge _0.75 The group IV portion is indicated to include 25% Si and thus 75% Ge.

The term "group II-VI semiconductor" as used herein is meant to include one or more materials from group II of the periodic table (e.g., group 12 elements: zinc (Zn), cadmium (Cd), mercury (Hg)) and one or more materials from group VII of the periodic table (e.g., group 16 elements: oxygen (O), sulfur (S), selenium (Se), tellurium (Te)). The compounds have a 1:1 combination of groups II and VI, regardless of the number of elements per group. The subscripts in the chemical symbols of the compounds indicate the proportions of the elements within the family.

The term "doped" or "doped" as used herein indicates that the layer or material contains another element (dopant) of low impurity concentration that provides (donor) or extracts (acceptor) charge carriers from the parent material and thus alters the conductivity. The carriers may be electrons or holes. The doped material with additional electrons is referred to as n-type, while the doped material with additional holes (fewer electrons) is referred to as p-type.

The term "crystalline" as used herein refers to a material or layer having a single crystal orientation. In epitaxial growth or deposition, subsequent layers having the same or similar lattice constants follow the recording (registry) of the previously crystallized layer and thus grow with the same crystal orientation or crystallinity.

The term "single crystal" as used herein refers to a material or layer having a continuous lattice throughout the material or layer. The single crystal may be indicative of a single crystal or a single crystal (e.g., si, ge, gaAs, etc.).

The term "monolithic" as used herein indicates that the entire layer, element or substrate comprises a bulk (e.g., unitary) material. The monolithic element (e.g., semiconductor body) may be formed from a single bulk material (e.g., si).

The term "deposition" as used herein indicates the deposition or growth of one layer on another layer or substrate. Deposition may include vacuum deposition, thermal evaporation, arc evaporation, ion beam deposition, electron beam deposition, sputtering, laser ablation, pulsed Laser Deposition (PLD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), metal Organic Chemical Vapor Deposition (MOCVD), liquid source atomized chemical deposition, spin coating, epitaxy, vapor Phase Epitaxy (VPE), liquid Phase Epitaxy (LPE), solid Phase Epitaxy (SPE), MBE, atomic Layer Epitaxy (ALE), molecular Beam Epitaxy (MBE), powder bed deposition, and/or other known techniques for depositing materials in layers.

The term "dielectric" as used herein indicates an electrically insulating layer. Dielectrics may include oxides, nitrides, oxynitrides, ceramics, glass, spin-on glass (SOG), polymers, plastics, thermoplastics, resins, laminates, high-k dielectrics, and/or any other electrically insulating material.

The term "high-k dielectric" as used herein indicates, for example, a dielectric layer that is formed with respect to silicon dioxide (SiO ₂ ) Has a high dielectric constant k or k (kappa). The high-k dielectric may be used as a gate dielectric or another dielectric layer in an electronic device.

The term "high-k metal gate" or "high-k dielectric and conductive gate" or "HKMG" as used herein indicates the process of forming a high-k dielectric layer and conductive (metal) layer stack in a memory device. HKMG technology can reduce gate leakage, increase transistor capacitance, and provide low power consumption for devices. Two process flows for patterning HKMG stacks are gate-first and gate-last.

The term "epitaxial" or "epitaxially" as used herein indicates the crystalline growth of a material, for example, via high temperature deposition.

The term "selective epitaxial growth" or "SEG" as used herein indicates the localized growth of an epitaxial layer on a substrate or layer through a patterned mask. The SEG provides epitaxial growth only on the exposed substrate or layer and other areas are masked by dielectric films or other materials that are non-reactive to the epitaxial.

The term "dielectric stack" as used herein indicates a stack of successive different alternating dielectric layers. For example, the first dielectric layer may be an oxide (e.g., silicon oxide) and the second dielectric layer may be a nitride (e.g., silicon nitride). The dielectric stacks may be arranged in a stair step pattern.

The term "gate line trench" as used herein indicates a trench or hole extending through a dielectric stack of a memory device. The gate line trench may be used to form a gate slit in the memory device.

The term "gate slit" or "GLS" as used herein indicates a conductive path through the dielectric stack, for example, between adjacent memory blocks or adjacent memory cells. GLS may provide a connection to HKMG stacks in a storage device. The GLS may extend vertically through the dielectric stack and horizontally between two adjacent arrays of memory blocks or memory cells.

Aspects of the present disclosure may be implemented in hardware, firmware, software, or any combination thereof. Aspects of the disclosure may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include: read Only Memory (ROM); random Access Memory (RAM); a magnetic disk storage medium; an optical storage medium; a flash memory device; a Dynamic Flash Memory (DFM) device; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, and/or instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from execution of firmware, software, routines, instructions, etc. by a computing device, processor, controller, or other device.

In 3D NAND flash memory, memory cells can be programmed for data storage based on charge trapping technology. The storage information of the memory cell depends on the amount of charge trapped in the storage layer. Although 3D NAND memory can be high density and cost efficient, it suffers from low writing speed and high power consumption at the system level due to the need for peripheral devices (e.g., charge pumps). In addition, as the number of 3D flash memory layers increases, the area of the NAND array decreases as the planar direction of the memory array decreases. But where the area reduction on the logic side does not match the NAND array side. Therefore, there is a need to address these issues while maintaining the advantages of 3D NAND technology.

On the other hand, a Dynamic Random Access Memory (DRAM) is a random access semiconductor memory that can store data of each bit in one memory cell. Some types of memory cells include capacitors and array transistors. The capacitor may be set to a charged or discharged state representing bit values of zero and one, respectively. Under a traditional von neumann computing architecture, the smaller the capacity of the DRAM, the faster the DRAM can be read and written. There is a huge memory barrier between DRAM and NAND, and it is important to find a new type of memory device with a large memory capacity and a fast read-write speed.

Ferroelectric random access memory (FeRAM) is a high performance and low power consumption non-volatile memory that can combine the benefits of conventional non-volatile memory (e.g., flash and EEPROM) and high speed RAM (e.g., SRAM and DRAM). The FeRAM can perform better than existing memories such as EEPROM and flash memory, with lower power consumption, faster response, and greater endurance to multiple read and write operations. FeRAM is of two types: capacitor type and Field Effect Transistor (FET) type. The capacitor type FeRAM memory cell comprises at least one ferroelectric capacitor and at least one MOSFET for cell selection, also referred to as nTnC FeRAM memory cell. The FET FeRAM cell contains no capacitor and only a single ferroelectric gate FET (FeFET). FET-type FeRAM can be integrated into high density because fefets can be scaled down using scaling rules.

Ferroelectricity is a property observed in non-centrosymmetric dielectric crystals that exhibit spontaneous electrical polarization, in which the polarization direction can be changed by an externally applied electric field. In ferroelectric materials, some atoms in the unit cell are dislocated due to charge distribution to create a permanent electric dipole. The macroscopic manifestation of charge separation is the surface charge of the ferroelectric material, described by the electrical polarization P. Typical ferroelectric materials, e.g. lead zirconate titanate (PZT), strontium bismuth tantalate (SrBi) ₂ Ta ₂ O ₉ Or SBT), barium titanate (BaTiO) ₃ ) And PbTiO ₃ Has a perovskite-type crystal structure in which the cation in the center of the unit cell has two positions, both of which are in a stable low energy state. These two low energy states correspond to two opposite directions of the electric dipole. Under the action of an external electric field, the cations can move along the direction of the electric field. Thus, by applying an external electric field across the crystal, cations in the unit cell can move from one low energy position to another and if the applied electric field is high enough, the direction of the electric dipole can be reversed. As a result, the electric polarization P in the ferroelectric material can be aligned with the direction of the external electric field.

The existing ferroelectric memory chip is generally of a two-dimensional architecture and is difficult to scale down. The signal margin of FeRAM decreases with decreasing cell area because of the challenges of increasing the inherent polarization of ferroelectric materials. That is, the memory array and the logic circuit are on the same plane, and the chip area increases sharply with an increase in memory capacity. That is, the memory density of FeRAM is not high enough compared to 3D NAND memory. The ferroelectric memory can use 3D NAND architecture to realize high-density storage, fully utilize the advantage of reduced capacitor height, and realize a multi-capacitor stacked structure.

Structures and methods of fabrication for integrated 3D memory devices including both 3D ferroelectric memory cell arrays and 3D NAND memory cell arrays are provided according to various embodiments of the present disclosure. The 3D ferroelectric memory cell array may be of a capacitor type (e.g., a 1TnC structure) or FET type (e.g., a multi-gate vertical 1T structure without a capacitor). By integrating the 3D ferroelectric memory cell array and the 3D NAND memory cell array on the same chip, a larger memory capacity can be realized while satisfying the high operation speed requirement.

Fig. 1 illustrates a schematic diagram of a cross-section of a 3D memory device 100 according to some aspects of the present disclosure. The 3D memory device 100 represents an example of a bonded chip. In some implementations, at least some of the components of the 3D memory device 100 (e.g., the memory cell array and peripheral circuitry) are separately formed in parallel on different substrates and then bonded to form a bonded chip (this process is referred to herein as a "parallel process"). In some embodiments, at least one semiconductor layer is attached to another semiconductor structure using transfer bonding, and then some components of the 3D memory device 100 (e.g., memory cell array and peripheral circuitry) are formed on the attached semiconductor layer (this process is referred to herein as a "serial process"). It is understood that in some examples, the components of the 3D memory device 100 (e.g., the memory cell array and peripheral circuitry) may be formed from a hybrid process that combines parallel and serial processes.

Note that the z-axis and x/y-axis are added in fig. 1 to further illustrate the spatial relationship of the components of the semiconductor device. A substrate of a semiconductor device (e.g., 3D memory device 100) includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in an x/y direction (lateral direction). As used herein, the x-direction represents the word line direction (WL direction) and the y-direction represents the bit line direction (BL direction). As used herein, when a substrate of a semiconductor device is located in the lowest plane of the semiconductor device in the z-direction (vertical direction or thickness direction), whether one component (e.g., layer or device) of the semiconductor device is "on", "above" or "below" another component (e.g., layer or device) in the z-direction is determined relative to the substrate. The same concepts used to describe spatial relationships are applied throughout this disclosure.

The 3D memory device 100 may include a first semiconductor structure 110, the first semiconductor structure 110 including a first array of memory cells (also referred to herein as a "first memory cell array 112") and a second array of memory cells (also referred to herein as a "second memory cell array 114"). The first memory cell array 112 and the second memory cell array 114 may be separated by a spacer 118. In some embodiments, the first memory cell array 112 may include an array of NAND flash memory cells, and the second memory cell array 114 may include an array of ferroelectric memory cells. In some other embodiments, the first memory cell array may include an array of ferroelectric memory cells, and the second memory cell array may include an array of NAND flash memory cells. The ferroelectric memory cell may be a cell or a FET-type ferroelectric memory cell.

In some implementations, the array of NAND memory cells is an array of 3D NAND memory strings, each memory string extending vertically through a stacked structure (e.g., a NAND memory stack) in a 3D fashion over a substrate. In accordance with 3D NAND technology (e.g., the number of layers/steps in a memory stack), a 3D NAND memory string typically includes a number of NAND memory cells, each cell including a floating gate transistor or a charge trapping transistor.

In some implementations, the array of ferroelectric memory cells is an array of 3D ferroelectric memory strings, each 3D ferroelectric memory string extending vertically through a stacked structure (e.g., ferroelectric memory stack) in a 3D manner over a substrate. Depending on the 3D ferroelectric memory technology (e.g., the number of layers/steps in the memory stack), a 3D ferroelectric memory string typically includes 1TnC FeRAM cells comprising a gate transistor and a plurality of ferroelectric capacitors in an array of capacitor-type ferroelectric memory cells, or a number of FeFET cells, each comprising a ferroelectric FET in an array of FET-type ferroelectric memory cells.

As shown in fig. 1, the 3D memory device 100 may further include a second semiconductor structure 120 including peripheral circuits of the first memory cell array 112 and the second memory cell array 114. The peripheral circuitry (also known as control and sensing circuitry) may include any suitable digital, analog, and/or mixed signal circuitry for facilitating operation of the memory cell array. For example, the peripheral circuitry may include one or more of page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), I/O circuits, charge pumps, voltage sources or generators, current or voltage references, any portion of the functional circuitry described above (e.g., subcircuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry in the second semiconductor structure 120 may be implemented using CMOS technology, for example, which may be implemented in logic processes in any suitable technology node.

As shown in fig. 1, the first and second semiconductor structures 110 and 120 may be stacked in a vertical direction according to some embodiments. As a result, the first and second memory cell arrays 112 and 114 in the first semiconductor structure 110, and the peripheral circuits in the second semiconductor structure 120 may be stacked on top of each other in different planes, thereby reducing the planar size of the 3D memory device 100 as compared to a memory device in which all the peripheral circuits are disposed in the same plane.

As shown in fig. 1, in some embodiments, the 3D memory device 100 further includes a bonding interface 130 between the first semiconductor structure 110 and the second semiconductor structure 120. The bonding interface 130 may be an interface between two semiconductor structures formed by any suitable bonding technique, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding, to name a few.

Fig. 2A illustrates a schematic diagram of a cross-sectional side view of an exemplary 3D storage device 200A, in accordance with some aspects of the present disclosure. The 3D storage device 200A may be an example of the 3D storage device 100 in fig. 1. According to some embodiments, the 3D memory device 200A is a bonded chip including a first semiconductor structure 210 and a second semiconductor structure 220 stacked in a vertical direction (e.g., a z-direction in fig. 2A).

As shown in fig. 2A, the first semiconductor structure 510 may include a first memory array (e.g., a 3D NAND flash memory cell array) 260 and a second memory array (e.g., a 3D ferroelectric memory cell array) 270 on the first semiconductor layer 231. The first memory array (e.g., 3D NAND flash memory cell array) 260 and the second memory array (e.g., 3D ferroelectric memory cell array) 270 are separated by a spacer 280.

In some embodiments, the first semiconductor layer 231 may have any suitable semiconductor material, such as silicon (e.g., single crystal silicon, c-silicon, or polysilicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable semiconductor material. In some embodiments, the first semiconductor layer 231 includes monocrystalline silicon and/or polycrystalline silicon. The first and second memory arrays 260 and 270 may be formed on different regions of the first semiconductor layer 231.

In some embodiments, the first memory array 260 may include an array of 3D NAND flash memory cells, such as an array of NAND memory strings 265 on the first semiconductor layer 231. The source of NAND memory string 265 may be in contact with first semiconductor layer 231. In some embodiments, NAND memory strings 265 are vertically disposed on the first semiconductor layer 531. According to some embodiments, each NAND memory string 265 extends vertically through multiple pairs, each pair including a conductive layer and a dielectric layer. The stacked and staggered conductive and dielectric layers are also referred to herein as a stacked structure, such as memory stack 233.

FIG. 3A illustrates an enlarged schematic 300A of a cross-sectional side view of a portion of an exemplary NAND memory string 265 in accordance with some aspects of the present disclosure. Storage stack 333 may be an example of a portion of storage stack 233 in fig. 2A. The conductive layer and the dielectric layer in the memory stack 333 may be examples of the conductive layer 310 and the dielectric layer 320 in the memory stack 333, respectively. According to some embodiments, alternating conductive layers 310 and dielectric layers 320 in the memory stack 333 alternate in a vertical direction. Each conductive layer 310 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of conductive layer 310 may extend laterally as a word line, terminating in one or more stair step structures (not shown) of memory stack 333.

The number of pairs of conductive layers 310 and dielectric layers 320 in the memory stack 333 may determine the number of NAND memory cells in the 3D NAND flash memory cell array 260. The conductive layer 310 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), platinum (Pt), ruthenium (Ru), tantalum nitride (TaN), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each conductive layer 310 includes a metal layer, such as a tungsten layer. In some embodiments, each conductive layer 310 includes a doped polysilicon layer. Each conductive layer 310 may include a control gate surrounding a memory cell and may extend laterally as a word line.

As shown in FIG. 3A, NAND memory string 265 includes NAND memory channel structures 365 extending vertically through memory stack 333. In some implementations, the NAND memory channel structure 365 includes a through-stack hole filled with semiconductor material(s) (e.g., as semiconductor channel 350) and dielectric material(s) (e.g., as storage film 340). In some embodiments, semiconductor channel 350 comprises silicon, such as polysilicon. In some embodiments, storage film 340 is a composite dielectric layer including tunneling layer 341, storage layer 343 (also referred to as a "charge trapping/storage layer"), and blocking layer 345. The NAND memory channel structure 365 may have a cylindrical shape (e.g., pillar shape). According to some embodiments, the semiconductor channel 350, the tunneling layer 341, the storage layer 343, the blocking layer 345 are arranged radially from the center of the pillar towards the outer surface in this order. The tunneling layer 341 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 343 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 345 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, memory film 340 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO). Dielectric fill structure 355 may be disposed between semiconductor channels 350. In some implementations, the dielectric fill structure 355 may include one or more air gaps (not shown).

Referring back to fig. 2a, nand memory strings 265 may extend vertically through the memory stack 233 over the first semiconductor layer 231. In some embodiments, each NAND memory string 265 is a "charge trapping" type NAND memory string, including any suitable channel structure, such as a bottom plug channel structure, a sidewall plug channel structure, or a bottom open channel structure. It is to be appreciated that NAND memory string 265 is not limited to "charge trapping" type NAND memory strings, and may be "floating gate" type NAND memory strings in other examples. It is also understood that in some examples, trench isolation and doped regions (not shown) may also be formed in the first semiconductor layer 231.

As shown in fig. 2A, the first semiconductor structure 210 further includes an isolation layer 240 over the 3D NAND flash memory cell array 260 and a semiconductor layer 241 on the isolation layer 240. In some embodiments, isolation layer 240 may comprise any suitable dielectric material that may have an electrical isolation function, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. Semiconductor layer 241 may be of any suitable semiconductor material, such as silicon (e.g., monocrystalline silicon, c-silicon, or polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable semiconductor material. In some embodiments, semiconductor layer 241 includes monocrystalline silicon and/or polycrystalline silicon.

As shown in fig. 2A, the first semiconductor structure 210 further includes a plurality of through contacts 243, each through contact 243 vertically penetrating the semiconductor layer 241 and the isolation layer 240, respectively, and contacting the drain terminal of a corresponding NAND memory string 265. Notably, each of the through contacts 243 may be surrounded by a spacer to be isolated from the semiconductor layer 241. A plurality of top select gate contacts 248 may be embedded in semiconductor layer 241. A plurality of top select gate cuts 245 may penetrate the semiconductor layer 241 and extend into the isolation layer 240 to separate the semiconductor layer 241 into a plurality of segments. In this manner, the plurality of through contacts 243, the plurality of top select gate contacts 248, and the plurality of segments of the semiconductor layer 241 may form a plurality of top select transistors that are separated from one another by a plurality of top select gate cuts 245. The plurality of top select gate contacts 248 may serve as top select gates for the plurality of top select transistors.

It should be noted that each NAND memory string 265 may also include a semiconductor plug (not shown) on its source terminal that is in contact with the semiconductor channel 250 and the first semiconductor layer 231. A semiconductor plug (also referred to as Selective Epitaxial Growth (SEG)) may be selectively grown from the first semiconductor layer 231 and thus have the same material as the first semiconductor layer 231, e.g., single crystal silicon or polycrystalline silicon.

As shown in fig. 2A, the first semiconductor structure 210 may further include an interconnect layer including a plurality of interconnects 253 in contact with the plurality of top select gate contacts 248 and the through contacts 243 to transfer electrical signals to and from the top select transistors and NAND memory strings 265. The interconnect 253 may include lateral lines and vertical vias. As used herein, the term "interconnect" may broadly include any suitable type of interconnect, such as a medium end-of-line (MEOL) interconnect and a back end-of-line (BEOL) interconnect. In some embodiments, the interconnect 253 further includes local interconnects, such as bit line contacts and word line contacts. It is noted that the interconnect layer may also include one or more inter-layer dielectric (ILD) layers (also referred to as "inter-metal dielectric (IMD) layers") in which lateral lines and vias may be formed. The interconnect 253 may comprise a conductive material including, but not limited to W, co, cu, al, silicide, or any combination thereof. ILD layers in the interconnect layers may comprise dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, interconnect 253 includes W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (fewer defects, such as voids) in the conductive metal material.

In some embodiments, the second memory array 270 may include a 3D ferroelectric memory cell array, such as a capacitor type ferroelectric memory cell array or a FET type ferroelectric memory cell array. The 3D ferroelectric memory cell array 270 may have a similar structure as compared to the 3D NAND flash memory cell array 260, but has a different through-stacked structure in each ferroelectric memory cell string.

In the capacitor type ferroelectric memory cell array, each transistor formed in the semiconductor layer 241 may be used as a transistor of one 1TnC capacitor type ferroelectric memory string 275. Fig. 3B illustrates an enlarged schematic diagram 300B of a cross-sectional side view of a portion of an exemplary capacitor-type ferroelectric memory string 275 according to some aspects of the present disclosure. As shown in fig. 3B, each capacitor-type ferroelectric memory string 275 includes a FeRAM through-stack structure 370 that extends vertically through the memory stack 333. In some embodiments, feRAM through-stack structure 370 includes through-stack holes filled with ferroelectric or antiferroelectric material(s) (e.g., as ferroelectric layer 372) and conductive material(s) (e.g., as conductive structure 378).

In some embodiments, ferroelectric layer 372 may comprise a high-k (i.e., high dielectric constant) dielectric material, which may comprise a transition metal oxide, such as hafnium zirconium oxide (HfZrO), hafnium oxide (HfO) ₂ ) Alumina (Al) ₂ O ₃ ) Zirconium oxide (ZrO) ₂ ) Titanium oxide (TiO) ₂ ) Niobium oxide (Nb) ₂ O ₅ ) Tantalum oxide (Ta) ₂ O ₅ ) Tungsten oxide (WO) ₃ ) Molybdenum Oxide (MO) ₃ ) Vanadium oxide (V) ₂ O ₃ ) Lanthanum oxide (La) ₂ O ₃ ) And/or any combination thereof. In some embodiments, the high-k dielectric material may be doped in order to improve ferroelectric properties. For example, the ferroelectric layer 372 may be HZO or HfO doped with silicon (Si), yttrium (Y), gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof ₂ . In some embodiments, the ferroelectric layer 372 may include zirconium titanate (PZT), strontium bismuth tantalate (SrBi) ₂ Ta ₂ O ₉ ) Barium titanate (BaTiO) ₃ )、PbTiO ₃ And BLT ((Bi, la) ₄ Ti ₃ O ₁₂ ) Or any combination thereof.

In some embodiments, the ferroelectric layer 372 may be provided by Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD), low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), or the like. Ferroelectric layer 372 may also be provided by Atomic Layer Deposition (ALD), sputtering, evaporation, or any combination thereof. In some embodiments, the ferroelectric layer 372 may have a thickness in a range between 5nm and 100 nm. Note that in some embodiments, as shown in fig. 2A and 3B, ferroelectric layer 372 is located on the sidewalls of each through hole in memory stack 333. In some other embodiments not shown in fig. 2A and 3B, a ferroelectric layer 372 may also be located on the bottom of each through hole in the memory stack 333 and may be in contact with the first semiconductor layer 231.

In some embodiments, conductive structure 378 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), platinum (Pt), ruthenium (Ru), tantalum nitride (TaN), polysilicon, doped silicon, silicide, or any combination thereof. A dielectric film 374 may be sandwiched between the ferroelectric layer 372 and the conductive structure 378. In some embodiments, dielectric film 374 may comprise any suitable dielectric material, such as TiN. As shown in fig. 3B, according to some embodiments, the ferroelectric layer 372, the dielectric film 374, and the conductive structure 378 are arranged radially from the center of the pillar toward the outer surface in this order.

As shown in fig. 3B, a plurality of conductive layers 310 and conductive structures 378 separated by ferroelectric layers 372 and dielectric films 374 may form a plurality of parallel connected capacitors of the 1TnC capacitor-type ferroelectric memory string 275 as shown in fig. 2A. Each conductive layer 310 may serve as a plate line for the 1TnC capacitor type ferroelectric memory string 275. In some embodiments, the number n of the plurality of parallel connected capacitors of the 1TnC capacitor-type ferroelectric memory string 275 may be adjusted by connecting a number of plate lines via a step contact (not shown) in the step area. The conductive structures 378, along with the corresponding through contacts 243, serve as channels for the 1TnC capacitor type ferroelectric memory string 275. The top select gate contact 248 may serve as a word line for the 1TnC capacitor-type ferroelectric memory string 275, and the interconnect line 253 in contact with the pass-through contact 243 may serve as a bit line for the 1TnC capacitor-type ferroelectric memory string 275.

In the FET-type ferroelectric memory cell array, each transistor formed in the semiconductor layer 241 may function as a top select transistor of one capacitor-less FeFET cell string 275' (not shown, but replacing the 1TnC capacitor-type ferroelectric memory string 275 in fig. 2A). Fig. 3C illustrates an enlarged schematic diagram 300C of a cross-sectional side view of a portion of an exemplary FeFET cell string 275' in accordance with some aspects of the present disclosure. As shown in fig. 3C, feFET cell string 275' includes FeFET through-stack structure 380 that extends vertically through memory stack 333. Each of the plurality of conductive layers 310 may act as a word line for a corresponding FeFET cell. In some embodiments, feFET through-stack structure 380 includes through-stack vias filled with ferroelectric or antiferroelectric material(s) (e.g., as ferroelectric layer 372) and conductive material(s) (e.g., as conductive layer 384).

In some embodiments, ferroelectric layer 382 may comprise a high-k (i.e., high dielectric constant) dielectric material, which may comprise a transition metal oxide, such as hafnium zirconium oxide (HfZrO), hafnium oxide (HfO) ₂ ) Alumina (Al) ₂ O ₃ ) Zirconium oxide (ZrO) ₂ ) Titanium oxide (TiO) ₂ ) Niobium oxide (Nb) ₂ O ₅ ) Tantalum oxide (Ta) ₂ O ₅ ) Tungsten oxide (WO) ₃ ) Molybdenum Oxide (MO) ₃ ) Vanadium oxide (V) ₂ O ₃ ) Lanthanum oxide (La) ₂ O ₃ ) And/or any combination thereof. In some embodiments, the high-k dielectric material may be doped in order to improve ferroelectric properties. For example, the ferroelectric layer 382 may be HZO or HfO doped with silicon (Si), yttrium (Y), gadolinium (Gd), lanthanum (La), zirconium (Zr), or aluminum (Al), or any combination thereof ₂ . In some embodiments, the ferroelectric layer 382 may include zirconium titanate (PZT), strontium bismuth tantalate (SrBi) ₂ Ta ₂ O ₉ ) Barium titanate (BaTiO) ₃ )、PbTiO ₃ And BLT ((Bi, la) ₄ Ti ₃ O ₁₂ ) Or any combination thereof.

In some embodiments, ferroelectric layer 382 may be provided by Chemical Vapor Deposition (CVD), such as Metal Organic Chemical Vapor Deposition (MOCVD), low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), or the like. Ferroelectric layer 382 may also be provided by Atomic Layer Deposition (ALD), sputtering, evaporation, or any combination thereof. In some embodiments, the ferroelectric layer 382 may have a thickness in a range between 5nm and 100 nm.

In some embodiments, the conductive layer 384 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), platinum (Pt), ruthenium (Ru), tantalum nitride (TaN), polysilicon, doped silicon, silicide, or any combination thereof. Dielectric fill structure 386 may be surrounded by conductive layer 384. In some implementations, the dielectric fill structure 386 can include one or more air gaps (not shown). As shown in fig. 3C, according to some embodiments, ferroelectric layer 382, conductive layer 384, and dielectric fill structure 386 are arranged radially from the center of the pillar toward the outer surface in this order.

Referring back to fig. 2A, the first semiconductor structure 210 may further include a first bonding layer including a conductive bonding contact 277 and a dielectric electrically isolating the conductive bonding contact 277, which may be used for hybrid bonding as described in detail below. The conductive bonding contacts 277 may be MEOL/BEOL interconnects and/or contact pads comprising any suitable conductive material including, but not limited to W, co, cu, al, silicide, or any combination thereof.

As shown in fig. 2A, the second semiconductor structure 220 may be bonded in a face-to-face manner on top of the first semiconductor structure 210 at a bonding interface 290. The second semiconductor structure 220 may include a second semiconductor layer 221 having a semiconductor material. In some embodiments, the second semiconductor layer 221 is a monocrystalline silicon or polycrystalline silicon layer.

As shown in fig. 2A, the second semiconductor structure 220 may include a device layer on and in contact with the second semiconductor layer 221. In some embodiments, the device layer includes one or more peripheral circuits of the 3D ferroelectric memory cell array 270 and the 3D NAND flash memory cell array 260. In some embodiments, the one or more peripheral circuits may include a plurality of transistors 223 formed to be in contact with the second semiconductor layer 221. In some embodiments, trench isolation (e.g., STI, not shown) and doped regions (e.g., wells, sources, and drains of the transistor 223, not shown) may also be formed on the second semiconductor layer 221 or in the second semiconductor layer 221.

In some embodiments, the second semiconductor structure 220 further includes an interconnect layer including a plurality of interconnects 285, such as MEOL interconnects and BEOL interconnects, to transmit electrical signals to and from the one or more first peripheral circuits. As shown in fig. 2A, interconnect 285 may be coupled to transistor 223 of one or more first peripheral circuits in the device layer. The interconnect layer may also include one or more ILD layers in which lateral lines and vias may be formed. In some embodiments, transistors 223 in the device layer are coupled to each other by interconnects 285 in the interconnect layer. Interconnect 285 may comprise a conductive material including, but not limited to W, co, cu, al, silicide, or any combination thereof. The ILD layer in the interconnect layer may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. In some embodiments, interconnect 285 includes W, which has a relatively high thermal budget (compatible with high temperature processes) and good quality (fewer defects, e.g., voids) in the conductive metal material.

In some embodiments, the second semiconductor structure 220 may further include a second bonding layer including a dielectric that electrically isolates the bonding contacts 288 and electrically conductive bonding contacts 288, which may be used for hybrid bonding as described in detail below. Conductive bonding contacts 288 may be MEOL/BEOL interconnects and/or contact pads comprising any suitable conductive material including, but not limited to W, co, cu, al, silicide, or any combination thereof.

In some embodiments, the bonding interface 290 is disposed vertically between the first bonding layer of the first semiconductor structure 210 and the second bonding layer of the second semiconductor layer 221 due to hybrid bonding. That is, the conductive bonding contacts 277 of the first bonding layer may contact the bonding contacts 288 of the second bonding layer at the bonding interface 290. As a result, the plurality of bond contacts across the bond interface 290 may form a direct short-range (e.g., micron-scale) electrical connection between the first and second semiconductor structures 210 and 220. In some implementations, dielectric layer(s) (e.g., silicon oxide layer) are formed vertically between bonding interfaces 290. Thus, it is to be appreciated that in some examples, the bonding interface 290 may include a surface of the dielectric layer(s).

Referring to fig. 2B, a schematic diagram of a top view of a portion of an exemplary 3D storage device 200B is shown, according to some aspects of the present disclosure. It is noted that fig. 2B shows a top view of the first semiconductor structure 210 shown in fig. 2A. The first memory array 260 (e.g., a 3D NAND flash memory cell array) and the second memory array 270 (e.g., a ferroelectric memory cell array) may be separated by a spacer 280. Top select gate notch 245 may extend in the x-direction (i.e., WL-direction) between NAND memory strings 265 or ferroelectric memory strings 275 to divide semiconductor layer 241 into a plurality of segments. A through contact 243 connected to NAND memory string 265 is coupled to a plurality of bit lines 251. In some embodiments, a through contact 243 connected to the capacitor-type ferroelectric memory string 275 is coupled to a plurality of bit lines 259. In some other embodiments, a pass-through contact 243 connected to the FET-type ferroelectric memory string 275' is coupled to a plurality of bit lines 259.

Fig. 2C illustrates a schematic diagram of a cross-sectional side view of another exemplary 3D storage device 200C, in accordance with some other aspects of the present disclosure. The 3D storage device 200C may be another example of the 3D storage device 100 in fig. 1. As shown in fig. 2C, in some embodiments, the first memory array 260 is a NAND memory cell array and the second memory array 270 (e.g., ferroelectric memory cell array) is a FET-type ferroelectric memory cell array that includes a plurality of FeFET ferroelectric memory strings 275' described above in connection with fig. 3C.

In such an embodiment, each transistor formed in one or more top conductive layers 235 (top conductive layer 235 shown in fig. 2C, by way of example) of memory stack 233 may be used as a top select transistor for one NAND memory string 265 or one capacitor-less FeFET ferroelectric memory string 275'. The remaining conductive layers of the plurality of conductive layers of memory stack 233 may be used as word lines for NAND memory string 265 and FeFET ferroelectric memory string 275'. In this way, the semiconductor layer 240 and the corresponding through contact 243 as shown in fig. 2A may be omitted. In addition, since the word line can be shared by the NAND memory cell array 260 and the FET-type ferroelectric memory cell array 270, the spacer 280 between the two memory arrays shown in fig. 2A may also be omitted. A plurality of top select gate cutouts 284 may be formed to divide one or more top conductive layers 235 into a plurality of portions along the bit line direction (i.e., the y-direction). In some other embodiments not shown in fig. 2C, a spacer (e.g., spacer 280 as shown in fig. 2A) may be formed under one select gate cutout 284 between the first memory array 260 and the second memory array 270. In some other embodiments not shown in fig. 2C, the select gate kerfs 284 between the first and second memory arrays 260, 270 may be replaced with spacers (e.g., spacers 280 as shown in fig. 2A) to separate the first and second memory arrays 260, 270.

Referring to fig. 2D, a schematic diagram of a top view of a portion of another exemplary 3D storage device 200D is shown, according to some aspects of the present disclosure. Note that fig. 2D shows a top view of the first semiconductor structure 210 shown in fig. 2C. The first memory array 260 (e.g., a 3D NAND flash memory cell array) and the second memory array 270 (e.g., a FET-type ferroelectric memory cell array) may be formed in a single memory block between adjacent gate slit cuts 281. The top select gate kerf 284 extends in the x-direction (i.e., WL-direction) between the NAND memory strings 265 and/or the FeFET ferroelectric memory strings 275' to divide the top conductive layer 235 of the memory stack 233 into a plurality of segments. Contacts 249 connected to corresponding NAND memory strings 265 or FeFET ferroelectric memory strings 275' are coupled to a plurality of bit lines 259.

Fig. 4 illustrates a block diagram of a system 400 having a storage device, in accordance with some aspects of the present disclosure. The system 400 may be a cell phone, desktop computer, notebook computer, tablet computer, vehicle computer, gaming machine, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having a memory therein. As shown in fig. 4, system 400 may include a host 408 and a memory system 402 having one or more storage devices 404 and a memory controller 406. Host 408 may be a processor of an electronic device, such as a Central Processing Unit (CPU), or may be a system on a chip (SoC), such as an Application Processor (AP). Host 408 can be configured to send data to storage device 404 or receive data from storage device 404.

Storage 404 may be any storage disclosed herein, such as 3D storage 100. In some embodiments, each memory device 404 includes an array of memory cells and peripheral circuits of the array of memory cells stacked on top of each other in different planes, as described in detail above.

According to some embodiments, memory controller 406 is coupled to storage 404 and host 408 and is configured to control storage 404. The memory controller 406 may manage data stored in the storage 404 and communicate with the host 408. In some implementations, the memory controller 406 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium used in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller 406 is designed to operate in a high duty cycle environment SSD, or an embedded multimedia card (eMMC) that is used as a mobile device such as a smart phone, tablet, notebook computer, and a data storage device for an enterprise storage array. The memory controller 406 may be configured to control operations of the memory device 404, such as read, erase, and program operations. In some implementations, the memory controller 406 is configured to control the array of memory cells through the first peripheral circuitry and the second peripheral circuitry. The memory controller 406 may also be configured to manage various functions with respect to data stored or to be stored in the storage 404, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, the memory controller 406 is also configured to process Error Correction Codes (ECC) with respect to data read from or written to the storage device 404. The memory controller 406 may also perform any other suitable function, such as formatting the storage device 404. The memory controller 406 may communicate with external devices (e.g., the host 408) according to a particular communication protocol. For example, the memory controller 406 may communicate with external devices through at least one of various interface protocols, such as a USB protocol, a multimedia card (MMC) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a firewire protocol, and the like.

The memory controller 406 and the one or more storage devices 404 may be integrated into various types of storage devices, e.g., included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 402 may be implemented and packaged into different types of terminal electronics.

In one example shown in fig. 5A, memory controller 406 and single storage 404 may be integrated into memory card 502. Memory card 502 may include a PC card (PCMCIA, personal computer memory card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, or the like. Memory card 502 may also include a memory card connector 504 that couples memory card 502 with a host (e.g., host 408 in fig. 4). In another example, as shown in fig. 5B, memory controller 406 and plurality of storage devices 404 may be integrated into SSD 506. SSD 506 may also include SSD connector 508 that couples SSD 506 with a host (e.g., host 408 in FIG. 4). In some implementations, the storage capacity and/or operating speed of SSD 506 is greater than the storage capacity and/or operating speed of memory card 502.

Referring to fig. 6A-6C, a flowchart of an exemplary method for forming a first semiconductor structure is shown, in accordance with some embodiments of the present disclosure. It should be understood that the operations illustrated in fig. 6A-6C are not exhaustive and that other operations may be performed before, after, or between any of the illustrated operations. Further, some operations may be performed simultaneously or in a different order than shown in fig. 6A-6C. Fig. 7A-7L illustrate schematic cross-sectional views of an exemplary first semiconductor structure at certain stages of manufacture of the method of fig. 6A-6C, in accordance with some embodiments of the present disclosure.

Referring to fig. 6A, a method 600A may begin at operation 601, where a dielectric stack may be formed on a first substrate, and a plurality of through-stack vias may be formed to penetrate the dielectric stack.

As shown in fig. 7A, in some embodiments, the first substrate 710 may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multilayer substrate, and the like. In some embodiments, a dielectric stack 720 including staggered stacked dielectric layers 722 and stacked sacrificial layers 724 may be formed on the first substrate 710. The dielectric stack 720 may include a plurality of pairs of first dielectric layers 724 (referred to herein as "stacked sacrificial layers" 724) and second dielectric layers 722 (referred to herein as "stacked dielectric layers" 722, collectively referred to herein as "dielectric layer pairs"). Stacked dielectric layers 722 and stacked sacrificial layers 724 may be alternately deposited on the first substrate 710 to form a dielectric stack 720. In some embodiments, each stacked dielectric layer 722 includes a silicon oxide layer, and each stacked sacrificial layer 724 includes a silicon nitride layer. Dielectric stack 720 may be formed by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof.

As shown in fig. 7A, in some embodiments, a plurality of through-stack holes 730 may be formed in the dielectric stack 720. Each through-stack hole 730 may vertically penetrate the dielectric stack 720 and be exposed or extend into the first substrate 710. In some embodiments, the plurality of through-stack apertures 730 may be arranged in one or more arrays in the core region. In some embodiments, the fabrication process for forming the through-stack via 730 includes wet etching and/or dry etching.

In some embodiments not shown in fig. 7A, one or more stepped structures may be formed on one or more sides of dielectric stack 720. The stepped structure may be formed by performing a plurality of so-called "trim etch" cycles on the dielectric layer pairs of the dielectric stack 720 towards the first substrate 710. The dielectric stack 720 may have one or more beveled edges and a top dielectric layer pair that is shorter than the bottom dielectric layer due to repeated trim etch cycles applied to the dielectric layer pair of the dielectric stack 720.

Referring back to fig. 6A, at operation 603, a second subset of the through-stack vias may be filled with a sacrificial material, and at operation 605, a plurality of first type through-stack structures may be formed in the first subset of through-stack vias.

As shown in fig. 7B, a first subset of the through-stack holes in the first region 718 may be covered by a mask, while a second subset of the through-stack holes in the second region 714 may be filled with a sacrificial material 733. In some embodiments, a first subset of the through-stack holes in the first region 718 are used to form a first type of memory cell array in a subsequent process, and a second subset of the through-stack holes in the second region 714 are used to form a second type of memory cell array in a subsequent process. The sacrificial material 733 may be different from the material of the stacked dielectric layer 722 and the stacked sacrificial layer 724. The etching process in the subsequent process may have a sufficiently high etch selectivity to the sacrificial material 733 relative to the stacked dielectric layer 722 and the stacked sacrificial layer 724 such that the etching process has minimal impact on the dielectric stack 720.

As shown in fig. 7C, a plurality of NAND memory channel structures 780 are formed in a first subset of the through stack vias in the first region 718. In the following description, the NAND memory channel structure 780 is used as an example of a first type through stack structure. It is noted that other types of through-stack structures, such as capacitor-type ferroelectric through-stack structures or FET-type ferroelectric through-stack structures, may also be formed in the first subset of through-stack holes in the first region 718 as examples of the first type of through-stack structures.

In some embodiments, the structure of NAND memory channel structure 780 may be as described above in connection with fig. 3A. The barrier layer, the memory layer, the tunneling layer, and the semiconductor channel may be sequentially formed in this order along the sidewall and bottom surface of each through-stack via. In some embodiments, the barrier layer, the storage layer, and the tunneling layer may first be deposited in this order along the sidewalls and bottom surface of the through-stack via using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to form the storage film. The semiconductor channel may then be formed by depositing a semiconductor material such as polysilicon (e.g., undoped polysilicon) using one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("ONOS" structure) are deposited in sequence to form a barrier layer, a storage layer, a tunneling layer, and a semiconductor channel.

Referring back to fig. 6A, at operation 607, sacrificial material may be removed from the second subset of through-stack vias, and at operation 609, a plurality of second type memory through-stack structures may be formed in the second subset of through-stack vias.

As shown in fig. 7D, the sacrificial material 733 may be removed from the second subset of through-stack holes by using any suitable etching process to expose the second subset of through-stack holes 730 in the second region 714. As shown in fig. 7E, a plurality of second-type through-stack structures 740 may be formed in a second subset of the through-stack holes 730 in the second region 714. In some embodiments, the second type through-stack 740 may be a capacitor type ferroelectric through-stack as described above in connection with fig. 3B. In some other embodiments, the second type through-stack 740 may be the FET-type ferroelectric through-stack described above in connection with fig. 3C.

Referring back to fig. 6A, the method 600A proceeds to step 611, where a gap may be formed between the first type through-stack structure and the second type through-stack structure, and the dielectric stack may be converted to a storage stack, and in operation 613, a gap structure may be formed in the gap to isolate the first type through-stack structure from the second type through-stack structure.

As shown in fig. 7F, a gap 750 may be formed between the first region 718 and the second region 714 to separate the first type through stack 780 in the first region 718 from the second type through stack 740 in the second region 714. The slit may vertically penetrate the dielectric stack 720 and the first substrate 710, and may extend laterally in a straight line manner in an x-direction (i.e., WL-direction) between two arrays of different types of through-stack structures 740 and 780. The aperture 750 may be formed by forming a mask layer (not shown) over the dielectric stack 720 and patterning the mask using, for example, photolithography to form openings corresponding to the plurality of apertures in the patterned mask layer. A suitable etching process, such as a dry etching and/or a wet etching, may be performed to remove the dielectric stack 720 and the portion of the first substrate 710 exposed by the opening. The mask layer may be removed after the formation of the slit 750.

Gate replacement may then be performed through the aperture 750 to replace the stacked sacrificial layer 724 in the dielectric stack 720 with the plurality of gate structures 726. After gate replacement, dielectric stack 720 may become storage stack 725, as shown in fig. 7F. In some embodiments, the stack sacrificial layer 724 in the dielectric stack 720 may be removed by applying an etchant through the gap 750. Any suitable etching process, such as isotropic dry etching or wet etching, may be used to remove the stacked sacrificial layer 724. The etching process may have a sufficiently high etching selectivity to the material of the stack sacrificial layer 724 relative to the material of the stack dielectric layer 722 such that the impact of the etching process on the stack dielectric layer 722 may be minimal. Isotropic dry etching and/or wet etching may remove the stacked sacrificial layers 724 in various directions to expose the top and bottom surfaces of each stacked dielectric layer 722. In this manner, a plurality of horizontal trenches may then be formed interleaved between the stacked dielectric layers 722. Each horizontal trench may extend in a horizontal direction and may serve as a space for a gate structure 726 formed in a subsequent process. Note that the term "horizontal" as used herein refers to being nominally parallel to the lateral surface of the first substrate 710.

In some embodiments, the stacked sacrificial layer 724 comprises silicon nitride, and the etchant package of isotropic dry etchingIncluding CF ₄ 、CHF ₃ 、C ₄ F ₈ 、C ₄ F ₆ And CH (CH) ₂ F ₂ One or more of the following. In some embodiments, the stacked sacrificial layer 724 includes silicon nitride, and the etchant of the wet etch includes phosphoric acid. After removing the stacked sacrificial layer 724, the slit 750 and the plurality of horizontal trenches may be cleaned by using any suitable cleaning process. For example, a phosphoric acid rinse process may be performed to remove impurities on the inner walls of the horizontal trenches.

In some implementations, the gate structure 726 may be formed in a horizontal trench, as shown in fig. 7F. In some embodiments, each gate structure 726 may include a gate electrode (also referred to as a stacked conductive layer) surrounded by an insulating film (not shown) and a high-k dielectric layer (not shown). The insulating film and the high-k dielectric layer may serve as one or more gate dielectric layers for insulating the respective gate electrodes. In some embodiments, an insulating film and a high-k dielectric layer may be formed to cover the exposed surfaces of the horizontal trenches with one or more suitable insulating materials. For example, one or more suitable deposition processes, such as CVD, PVD, and/or ALD, may be utilized to deposit one or more insulating materials into the horizontal trenches. In some embodiments, a recess etch process and/or a CMP process may be used to remove excess insulating material(s). The one or more insulating materials may comprise any suitable material that provides an electrical insulating function.

In some embodiments, the gate electrodes may be formed in the horizontal trenches, respectively. The gate electrode may be formed by filling the horizontal trench with a suitable gate electrode metal material. The gate electrode metal material may comprise any suitable conductive material for forming word lines, such as tungsten, aluminum, copper, cobalt, or any combination thereof. The gate electrode material may be deposited into the horizontal trenches using suitable deposition methods such as CVD, PVD, plasma Enhanced CVD (PECVD), sputtering, metal Organic Chemical Vapor Deposition (MOCVD), and/or ALD.

In some embodiments, as shown in fig. 7G, a dielectric material may be filled into the gap 750 by performing a deposition process to form a gap structure 755 (also referred to as a spacer 755). Slit structures 755 may be used to provide electrical insulation between an array of first type through-stack structures in first region 718 and an array of second type through-stack structures in second region 714. In some implementations, the dielectric material also covers the storage stack 725, and the array of first type through-stack structures in the first region 718 and the array of second type through-stack structures in the second region 714 to form the insulating layer 728.

Referring to fig. 6B, at operation 615 a semiconductor layer may be formed on the first type through-stack structure and the second type through-stack structure, at operation 617 one or more plugs in contact with the semiconductor layer may be formed, and a plurality of vias may be formed to penetrate the semiconductor layer and make contact with the first or second type through-stack structure.

As shown in fig. 7G, an isolation layer 760 may be formed over the insulating layer 728, and a semiconductor layer 762 may be formed over the isolation layer 760. Isolation layer 760 may comprise any suitable dielectric material that may have an electrical isolation function including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The semiconductor layer 762 may be of any suitable semiconductor material, such as silicon (e.g., single crystal silicon, c-silicon, or polysilicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable semiconductor material. In some embodiments, isolation layer 760 and semiconductor layer 762 may be formed by any suitable deposition process, such as CVD, PVD, plasma Enhanced CVD (PECVD), sputtering, metal Organic Chemical Vapor Deposition (MOCVD), and/or ALD.

As shown in fig. 7I, one or more plugs 767 may be formed in the semiconductor layer 762. A plurality of vias 765 may be formed to penetrate the semiconductor layer 762, the isolation layer 760, and the insulating layer 728. Each via 765 may be in contact with a corresponding first type through-stack or a corresponding second type through-stack. In some embodiments, plug 767 may be used as a top select gate contact and via 765 may be used as a through contact. Note that each of the through contacts 243 may be surrounded by a spacer to be isolated from the semiconductor layer 241. In some embodiments, the one or more plugs 767 and the plurality of vias 765 may be formed by any suitable patterning process. For example, a mask layer (not shown) may be used in one or more etching processes to form openings at locations for forming one or more plugs 767 and a plurality of vias 765, and a subsequent deposition process may fill conductive material into the openings to form the one or more plugs 767 and the plurality of vias 765.

Referring to fig. 6B, method 600B may proceed to operation 819 where the gap structure may be extended to separate a first portion of the semiconductor layer in the first region from a second portion of the semiconductor layer in the second region. Method 600B may then proceed to operation 621, wherein a plurality of kerf structures may be further formed to divide the first and second portions of the semiconductor layer into a plurality of segments.

As shown in fig. 7I, the slit structure 755 may extend in a vertical direction to further separate a first portion of the semiconductor layer 762 on the array of first type through-stack structures located in the first region 718 from a second portion of the semiconductor layer 762 on the array of second type through-stack structures located in the second region 714. A plurality of kerf structures 769 may be formed to penetrate the semiconductor layer 762 and extend into the isolation layer 760 to further divide the first and second portions of the semiconductor layer 762 into a plurality of segments. In some embodiments, the extended slit structures 755 and the plurality of slit structures 769 may be formed by any suitable patterning process. For example, a mask layer (not shown) may be used in one or more etching processes to form trenches extending laterally in the x-direction (WL-direction) and vertically through the semiconductor layer 762, and a subsequent deposition process may fill dielectric material into the trenches to form the extended slit structures 755 and the plurality of kerf structures 769. A CMP process may then be performed to planarize the top surface of the one or more plugs 767, the plurality of vias 765, the slit structure 755, the plurality of kerf structures 769, and the top surface of the semiconductor layer 762.

Referring to fig. 6B, the method 600B may proceed to operation 623, wherein a first interconnect layer including a plurality of first interconnects may be formed on the semiconductor layer. Method 600B may then proceed to operation 625, wherein a first bonding layer may be formed on the first interconnect layer.

As shown in fig. 7J, a first interconnect layer 790 is formed over the semiconductor layer 762. The first interconnect layer 790 may include first interconnects 791 of MEOLs and/or BEOLs in the plurality of ILD layers to form electrical connections with the top select gate contacts 767 and/or vias 765. In some implementations, the first interconnect layer 790 includes a plurality of ILD layers and first interconnects 791 formed therein in a plurality of processes. For example, the first interconnect 791 in the first interconnect layer 790 may include a conductive material deposited by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the first interconnect 791 may also include photolithography, CMP, wet/dry etching, or any other suitable process. The ILD layer may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. The ILD layer and interconnect shown in fig. 7J may be collectively referred to as a first interconnect layer 790.

A first bonding layer 795 may be formed on the first interconnection layer 790. The first bonding layer 795 may include a first bonding contact 799 and a dielectric electrically isolating the first bonding contact 799, which may be used for hybrid bonding as described in detail below. The first bond contact 799 may be a MEOL/BEOL interconnect and/or contact pad comprising any suitable conductive material including, but not limited to W, co, cu, al, silicide, or any combination thereof. In this way, a first semiconductor structure may be formed.

Referring to fig. 6C, the method 600C proceeds to operation 627, wherein a peripheral circuit layer may be formed on the second substrate. The method 600C proceeds to operation 629, wherein a second interconnect layer including a plurality of second interconnects may be formed on the peripheral circuit layer.

As shown in fig. 7K, in some embodiments, the second substrate 810 may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multilayer substrate, and the like. The peripheral circuit layer 825 is formed on the second substrate 810. The peripheral circuit layer 825 may include a plurality of transistors 820. Transistor 820 may be formed by a variety of processes including, but not limited to, photolithography, dry/wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in the second substrate 810 by ion implantation and/or thermal diffusion, which serve, for example, as well and source/drain regions for the transistor 820. In some embodiments, isolation regions (e.g., STI, not shown) are also formed in the second substrate 810 by wet/dry etching and thin film deposition. It is to be appreciated that the details of fabricating the different transistors 820 may vary depending on the type of transistor 820 (e.g., planar transistor or 3D transistor), and thus, for ease of description, will not be described in detail.

In some implementations, a second interconnect layer 830 is formed over the transistor 820. The second interconnect layer 830 may include a plurality of second interconnects 835 of MEOL and/or BEOL in one or more ILD layers to electrically connect with the transistors 820. In some implementations, the second interconnect layer 830 includes a plurality of ILD layers and second interconnects 835 formed therein in a plurality of processes. For example, the second interconnect 835 in the second interconnect layer 830 may include a conductive material deposited by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process for forming the second interconnect 835 may also include photolithography, CMP, wet/dry etching, or any other suitable process. The ILD layer may comprise a dielectric material deposited by one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. The ILD layer and the second interconnect 835 shown in fig. 7K may be collectively referred to as a second interconnect layer 830.

Referring back to fig. 6C, the method 600C proceeds to operation 631, wherein a second bonding layer may be formed on the second interconnect layer of the second semiconductor structure. The method 600C then proceeds to operation 633, where the second bonding layer of the second semiconductor structure may be bonded to the first bonding layer of the first semiconductor structure. Bonding may include hybrid bonding.

In some embodiments, as shown in fig. 7K, a second bonding layer 895 may be formed on the second interconnect layer 830. The second bonding layer 895 may include a second bonding contact 899 and a dielectric electrically isolating the second bonding contact 899, which may be used for hybrid bonding as described in detail below. The second bonding contact 899 may be a MEOL/BEOL interconnect and/or contact pad comprising any suitable conductive material including, but not limited to W, co, cu, al, silicide, or any combination thereof. In this manner, the second semiconductor structure 800 may be formed.

As shown in fig. 7L, the second semiconductor structure 800 may be flipped upside down. The second bonding layer 895 in the second semiconductor structure 800 facing downward is bonded to the first bonding layer 795 in the first semiconductor structure 700 facing upward, i.e., in a face-to-face manner, thereby forming a bonding interface 850. The first bond contact 799 in the first bond layer 795 contacts the second bond contact 899 in the second bond layer 895 at the bond interface 850. In some embodiments, a treatment process, such as plasma treatment, wet treatment, and/or heat treatment, is applied to the bonding surface prior to bonding.

As a result of bonding (e.g., hybrid bonding), the first and second bonding contacts 799 and 899 on opposite sides of the bonding interface 850 may be intermixed. According to some embodiments, after bonding, the first bonding contact 799 in the first bonding layer 795 and the second bonding contact 899 in the second bonding layer 895 are aligned and in contact with each other such that the memory stack 725 and the NAND memory cell array and ferroelectric memory cell array formed therethrough can be coupled to the transistor 820 through the bonded bonding contacts 799 and 899 across the bonding interface 850. Thus, a 3D memory structure is formed.

The foregoing description of specific embodiments may be readily modified and/or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure may also be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, modified, and rearranged relative to each other in a manner consistent with the scope of the disclosure.

Claims

1. A method for forming a three-dimensional (3D) memory device, comprising:

forming a first semiconductor structure, comprising:

forming an array of first type through-stack structures in a first region of a storage stack and forming an array of second type through-stack structures in a second region of the storage stack;

Forming a semiconductor layer comprising a first portion over the array of first type through-stack structures and a second portion over the array of second type through-stack structures;

forming a plurality of vias, each via penetrating the semiconductor layer and contacting a corresponding one of the first type through-stack structure or the second type through-stack structure; and

a slit structure is formed to separate the array of first type through-stack structures from the array of second type through-stack structures and to separate the first portion of the semiconductor layer from the second portion of the semiconductor layer.

2. The method of claim 1, wherein forming the first semiconductor structure further comprises:

forming a dielectric stack comprising a plurality of alternating dielectric layers and sacrificial layers stacked on a first substrate, wherein the array of first type through-stack structures and the array of second type through-stack structures penetrate the dielectric stack;

forming a slit vertically penetrating the dielectric stack and laterally separating the array of first type through-stack structures from the array of second type through-stack structures; and

Replacing the plurality of sacrificial layers with a plurality of conductive layers to convert the dielectric stack into the storage stack;

wherein the slit structure is formed to fill the slit.

3. The method of claim 2, further comprising:

forming a second semiconductor structure including peripheral circuitry on a second substrate; and

the second semiconductor structure is bonded to the first semiconductor structure.

4. The method of claim 3, wherein forming the first type of through-stack and the second type of through-stack comprises:

forming a plurality of through-stack holes, each through-stack hole penetrating the dielectric stack;

filling a second subset of the through-stack holes with a sacrificial material;

forming the first type of through-stack structures in a first subset of through-stack holes;

removing the sacrificial material in the second subset of through-stack holes; and

the second type of through-stack structures are formed in the second subset of through-stack holes.

5. The method according to claim 1, wherein:

forming the first type of through-stack structure includes forming a NAND channel structure; and is also provided with

Forming the second type of through-stack structure includes forming a capacitor type ferroelectric through-stack structure.

6. The method according to claim 1, wherein:

Forming the second type through-stack structure includes forming a FET-type ferroelectric through-stack structure.

7. The method of claim 3, wherein forming the via comprises:

forming a plurality of through holes, wherein each through hole penetrates through the semiconductor layer and exposes a corresponding first type through stacked structure or second type through stacked structure;

filling the through holes with a dielectric material; and

and forming the via holes, wherein the via holes are positioned in the corresponding through holes and are surrounded by the dielectric material.

8. The method of claim 7, further comprising:

a plurality of kerf structures are formed, each kerf structure extending laterally between the vias and vertically separating portions of the semiconductor layer.

9. A method according to claim 3, wherein:

forming the first semiconductor structure further includes:

forming a first interconnect layer including a plurality of first interconnects contacting the via holes, an

Forming a first bonding layer comprising a plurality of first bonding contacts in contact with the first interconnect;

Forming the second semiconductor structure includes:

forming a second interconnect layer including a plurality of second interconnects contacting a plurality of transistors of the peripheral circuit, an

Forming a second bonding layer comprising a plurality of second bonding contacts in contact with the second interconnect; and is also provided with

Bonding the second semiconductor structure to the first semiconductor structure includes bonding the first bonding layer to the second bonding layer such that each first bonding contact engages with a corresponding second bonding contact.

10. A three-dimensional (3D) storage device, comprising:

a first semiconductor structure, the first semiconductor structure comprising:

an array of first type through-stack structures in a first region of the storage stack;

an array of second type through-stack structures in a second region of the storage stack;

a semiconductor layer comprising a first portion on the array of first type through-stack structures and a second portion on the array of second type through-stack structures;

a plurality of vias, each via penetrating the semiconductor layer and contacting a corresponding one of the first type through-stack structure or the array of second type through-stack structures; and

A slit structure separating the array of first type through-stack structures from the array of second type through-stack structures and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.

11. The storage device of claim 10, further comprising:

a second semiconductor structure including peripheral circuitry;

wherein the second semiconductor structure is bonded to the first semiconductor structure.

12. The storage device of claim 10, wherein:

the first type of through-stack structure is a NAND channel structure; and is also provided with

The second type of through-stack structure is a capacitor type ferroelectric through-stack structure.

13. The memory device of claim 12, wherein each capacitor-type ferroelectric through stack structure comprises:

a ferroelectric layer; and

a conductive structure laterally surrounded by the dielectric film.

14. The storage device of claim 10, wherein:

The second type of through-stack is a FET-type ferroelectric through-stack.

15. The memory device of claim 14, wherein each FET-type ferroelectric through stack structure comprises:

A ferroelectric layer;

a conductive layer laterally surrounded by the ferroelectric layer; and

a dielectric fill structure laterally surrounded by the conductive layer.

16. The storage device of claim 10, further comprising:

a dielectric layer on the semiconductor layer, wherein the vias each penetrate the dielectric layer and are isolated from the semiconductor layer by a dielectric material; and

a plurality of kerf structures, each kerf structure extending laterally between the vias and vertically separating portions of the semiconductor layer.

17. The memory device of claim 11, wherein the first semiconductor structure further comprises:

a first interconnect layer including a plurality of first interconnects in contact with the vias; and

a first bonding layer including a plurality of first bonding contacts in contact with the first interconnect.

18. The memory device of claim 17, wherein the second semiconductor structure further comprises:

a second interconnect layer including a plurality of second interconnects contacting a plurality of transistors of the peripheral circuit, an

A second bonding layer comprising a plurality of second bonding contacts in contact with the second interconnect;

Wherein the first bonding layer and the second bonding layer are bonded at a bonding interface such that each first bonding contact engages a corresponding second bonding contact.

19. A memory system, comprising:

a storage device configured to store data, and comprising:

an array of first type through-stacked structures in a first region and an array of second type through-stacked structures in a second region;

a slit structure separating the array of first type through-stack structures from the array of second type through-stack structures and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer; and

a memory controller coupled to the storage device and configured to control the storage device.

20. The memory system of claim 19, wherein:

The second type of through-stack is a capacitor type ferroelectric through-stack or a FET type ferroelectric through-stack.

21. A method for forming a three-dimensional (3D) memory device, comprising:

forming a first semiconductor structure comprising an array of first type through-stack structures in a first region of a storage stack and an array of second type through-stack structures in a second region of the storage stack;

forming a second semiconductor structure including peripheral circuitry; and

22. The method of claim 21, wherein forming the first semiconductor structure comprises:

forming an array of NAND channel structures in the first region as an array of the first type through-stack structures; and

an array of FET-type ferroelectric through-stack structures is formed in the second region as an array of the second-type through-stack structures.

23. The method of claim 21, wherein forming the first semiconductor structure further comprises:

Forming a dielectric stack comprising a plurality of staggered dielectric layers and sacrificial layers stacked, wherein the array of first type through-stack structures and the array of second type through-stack structures penetrate the dielectric stack;

replacing the plurality of sacrificial layers with a plurality of conductive layers to convert the dielectric stack into a storage stack;

a slit structure is formed to fill the slit.

24. The method of claim 23, wherein forming the first type of through-stack and the second type of through-stack comprises:

filling a second subset of the through-stack holes with a sacrificial material;

25. The method of claim 23, further comprising:

forming a plurality of incision structures, each incision structure extending vertically to separate a top conductive layer of the storage stack, wherein the plurality of incision structures comprises:

a first kerf structure extending laterally between the first type through-stack structure and the second type through-stack structure;

a second kerf structure extending laterally between the first type through-stack structures; and

and third cutout structures extending laterally between the second type through-stack structures.

26. The method according to claim 21, wherein:

forming the first semiconductor structure further includes:

forming a first interconnect layer comprising a plurality of first interconnects in contact with the first type through-stack structure and the second type through-stack structure; and

forming the second semiconductor structure includes:

forming a second interconnect layer including a plurality of second interconnects in contact with a plurality of transistors of the peripheral circuit; and

27. The method of claim 24, wherein forming the second type of through-stack structure comprises:

forming a ferroelectric layer on sidewalls of each of the second subset of through-stack vias;

forming a conductive layer to cover the ferroelectric layer; and

a dielectric fill structure is formed on the ferroelectric layer to fill the second subset of through-stack vias.

28. A three-dimensional (3D) storage device, comprising:

a first semiconductor structure, comprising:

a memory stack comprising a plurality of alternating dielectric and conductive layers,

an array of first type through-stack structures in a first region of the storage stack, an

An array of second type through-stack structures in a second region of the storage stack; and

a second semiconductor structure comprising peripheral circuitry, wherein the second semiconductor structure is bonded to the first semiconductor structure.

29. The storage device of claim 28, wherein:

The second type of through-stack is a FET-type ferroelectric through-stack.

30. The memory device of claim 29, wherein each FET-type ferroelectric through stack structure comprises:

a ferroelectric layer;

a conductive layer laterally surrounded by the ferroelectric layer; and

a dielectric fill structure laterally surrounded by the conductive layer.

31. The storage device of claim 28, wherein:

the first type through stack structure and the second type through stack structure are located in adjacent memory blocks separated by spacers.

32. The storage device of claim 31, further comprising:

a plurality of kerf structures, each kerf structure extending vertically to separate top conductive layers of the storage stack, wherein the plurality of kerf structures comprises:

33. The memory device of claim 28, wherein the first semiconductor structure further comprises:

a first interconnect layer including a plurality of first interconnects in contact with the first type through-stack structure and the second type through-stack structure; and

34. The memory device of claim 33, wherein the second semiconductor structure further comprises:

35. A memory system, comprising:

a storage device configured to store data, and comprising:

A first semiconductor structure, the first semiconductor structure comprising:

a second semiconductor structure comprising peripheral circuitry, wherein the second semiconductor structure is bonded to the first semiconductor structure; a memory controller coupled to the storage device and configured to control the storage device.

36. The memory system of claim 35, wherein:

The second type of through-stack is a FET-type ferroelectric through-stack.

37. The memory system of claim 36, wherein each FET-type ferroelectric through stack structure comprises:

a ferroelectric layer;

a conductive layer laterally surrounded by the ferroelectric layer; and

a dielectric fill structure laterally surrounded by the conductive layer.

38. The memory system of claim 35, further comprising:

39. The memory system of claim 35, wherein the first semiconductor structure further comprises:

40. The memory system of claim 39 wherein the second semiconductor structure further comprises: