CN117678333A

CN117678333A - Memory device with vertical transistor and method of forming the same

Info

Publication number: CN117678333A
Application number: CN202380009542.2A
Authority: CN
Inventors: 刘威; 朱宏斌; 王言虹; 颜丙杰; 华文宇; 刘藩东; 汪亚
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-05-19
Filing date: 2023-05-15
Publication date: 2024-03-08

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a vertical transistor array. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure positioned adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected to each other and extend in a first lateral direction to form a word line. The first word line of the first row of vertical transistors is located on a first side of the semiconductor body of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located on a second side of the semiconductor body of the second row of vertical transistors along a second lateral direction.

Description

Memory device with vertical transistor and method of forming the same

Cross Reference to Related Applications

The present application claims priority from U.S. provisional application No.63/343,848 filed on day 19 5 of 2022 and U.S. provisional application No.63/351,604 filed on day 13 of 2022, the disclosures of both of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to memory devices and methods of manufacturing the same.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cells approaches the lower limit, planar processing and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

A three-dimensional (3D) memory architecture may address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral circuitry for facilitating operation of the memory array.

Disclosure of Invention

In one aspect, a semiconductor device includes a vertical transistor array. Each vertical transistor includes a semiconductor body extending in a vertical direction, and a gate structure positioned adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected to each other and extend in a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located on a first side of the semiconductor body of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located on a second side of the semiconductor body of the second row of vertical transistors along the second lateral direction.

In another aspect, a method for forming a semiconductor device is disclosed. The method comprises the following steps: forming a plurality of spacers extending in a first lateral direction, each spacer extending vertically in an upper portion of the semiconductor layer; forming a plurality of first trenches extending in the first lateral direction, each first trench extending vertically in the upper portion of the semiconductor layer and being sandwiched by two adjacent spacers in a second lateral direction; and forming two disconnected conductive structures in each first trench, the two disconnected conductive structures extending laterally along the first lateral direction, each conductive structure extending vertically along one sidewall of the corresponding first trench.

In yet another aspect, another method for forming a semiconductor device is disclosed. The method comprises the following steps: forming a plurality of first trenches extending in a first lateral direction, each first trench extending vertically in an upper portion of the semiconductor layer; forming a plurality of spacers extending in the first lateral direction, each spacer extending vertically in the upper portion of the semiconductor layer and sandwiched by two adjacent first trenches in a second lateral direction; and forming two disconnected conductive structures in each first trench, the two disconnected conductive structures extending laterally along the first lateral direction, each conductive structure extending vertically along one sidewall of the corresponding first trench.

In yet another aspect, another method for forming a semiconductor device is disclosed. The method comprises the following steps: forming a plurality of spacers and a plurality of first trenches in an upper portion of the semiconductor layer, each spacer and each first trench extending laterally in a first lateral direction, wherein the plurality of first trenches and the plurality of spacers are alternately arranged in a second lateral direction; forming a gate dielectric layer in each first trench by oxidizing sidewalls of each first trench; forming two disconnected conductive structures in each first trench, each of the two disconnected conductive structures extending laterally along the first lateral direction and vertically covering the gate dielectric layer on one sidewall of the corresponding first trench, respectively; and removing the plurality of spacers to form a plurality of second trenches.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a schematic diagram of a cross-section of a 3D memory device, according to some aspects of the present disclosure.

Fig. 2 illustrates a schematic diagram of a cross-section of another 3D memory device, in accordance with aspects of the present disclosure.

Fig. 3 illustrates a schematic diagram of a memory device including peripheral circuitry and a memory cell array each having vertical transistors, in accordance with some aspects of the present disclosure.

Fig. 4A illustrates a plan view of an array of memory cells each including a vertical transistor in a memory device in accordance with some aspects of the present disclosure.

Fig. 4B illustrates a side view of a cross section of a 3D memory device including vertical transistors, in accordance with some aspects of the present disclosure.

Fig. 4C illustrates a side view of a cross section of yet another 3D memory device including vertical transistors, in accordance with aspects of the present disclosure.

Fig. 5A-5J and 5A '-5J' illustrate a fabrication process for forming a 3D memory device including vertical transistors in accordance with some aspects of the present disclosure.

Fig. 6 illustrates a flow chart of a method for forming an array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure.

Fig. 7A-7J and 7A '-7J' illustrate another fabrication process for forming a 3D memory device including vertical transistors in accordance with some aspects of the present disclosure.

Fig. 8 illustrates a flow chart of another method for forming an array of memory cells each including a vertical transistor in accordance with some aspects of the present disclosure.

Fig. 9A-9I and 9A '-9I' illustrate yet another fabrication process for forming a 3D memory device including vertical transistors in accordance with some aspects of the present disclosure.

Fig. 10 illustrates a flow chart of yet another method for forming an array of memory cells each including a vertical transistor in accordance with some aspects of the present disclosure.

Fig. 11A-11I and 11A '-11I' illustrate yet another fabrication process for forming a 3D memory device including vertical transistors in accordance with some aspects of the present disclosure.

Fig. 12 illustrates a flow chart of yet another method for forming an array of memory cells each including a vertical transistor in accordance with some aspects of the present disclosure.

Fig. 13A-13J and 13A '-13J' illustrate yet another fabrication process for forming a 3D memory device including vertical transistors in accordance with some aspects of the present disclosure.

Fig. 14 illustrates a flow chart of yet another method for forming an array of memory cells each including a vertical transistor in accordance with some aspects of the present disclosure.

Fig. 15A-15J and 15A '-15J' illustrate yet another fabrication process for forming a 3D memory device including vertical transistors in accordance with some aspects of the present disclosure.

Fig. 16 illustrates a flow chart of yet another method for forming an array of memory cells each including a vertical transistor in accordance with some aspects of the present disclosure.

Fig. 17 illustrates a block diagram of an exemplary system having a memory device in accordance with aspects of the disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the present disclosure may also be used in a variety of other applications. The functional and structural features described in the present disclosure may be combined, adjusted, and modified with each other and in a manner not specifically depicted in the drawings so that such combinations, adjustments, and modifications are within the scope of the present disclosure.

Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" are also to be construed as expressing singular or plural uses depending, at least in part, on the context. In addition, the term "based on" may be understood as not necessarily intended to express an exclusive set of factors, but rather may allow for additional factors not necessarily explicitly described to be present, again depending at least in part on the context.

It should be readily understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only "directly on something" but also includes the meaning of "on something" with intermediate features or layers therebetween, and "over … …" or "over … …" means not only "over something" or "over something" but also may include the meaning of "it over something" or "it over something" (e.g., directly on something) without intermediate features or layers therebetween.

Moreover, spatially relative terms such as "under … …," "under … …," "lower," "above … …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to one or more additional elements or features as illustrated. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductor and contact layers in which interconnect lines and/or vertical interconnect via (via) contacts are formed, and one or more dielectric layers.

Transistors are used as switches or select devices in memory cells of some memory devices, such as DRAM, PCM, and ferroelectric DRAM (FRAM). However, planar transistors commonly used in existing memory cells typically have a horizontal structure with buried word lines in the substrate and bit lines above the substrate. Since the source and drain of the planar transistor are laterally disposed at different locations, this increases the area occupied by the transistor. The design of planar transistors also complicates the placement of interconnect structures (such as word lines and bit lines) coupled to memory cells, e.g., limits the pitch of word lines and/or bit lines, thereby increasing manufacturing complexity and reducing yield. In addition, because the bit line and the memory cell (e.g., capacitor or PCM element) are disposed on the same side of the planar transistor (above the transistor and substrate), the bit line process margin is limited by the memory cell and the coupling capacitance between the bit line and the memory cell (such as capacitor) increases. As saturated drain currents continue to increase, planar transistors may also suffer from high leakage currents, which is undesirable for the performance of the memory device.

On the other hand, the memory cell array and peripheral circuits for controlling the memory cell array are generally arranged side by side in the same plane. As the number of memory cells continues to increase, the size of components (e.g., transistors, word lines, and/or bit lines) in the memory cell array need to be reduced in order to maintain the same chip size so as not to significantly reduce the memory cell array efficiency.

To address one or more of the foregoing problems, the present disclosure introduces a solution in which vertical transistors replace conventional planar transistors as switching and selection devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and FRAM). Vertically arranged transistors (e.g., drain and source overlap in plan view) may reduce the area of the transistor and simplify the layout of interconnect structures (e.g., word lines and bit lines of metal wiring) as compared to planar transistors, which may reduce manufacturing complexity and increase yield. For example, the pitch of the word lines and/or bit lines may be reduced for ease of fabrication. The vertical structure of the transistor also allows the bit line and the memory cell (such as a capacitor) to be arranged on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and one below the transistor) so that the process margin of the bit line can be increased and the coupling capacitance between the bit line and the memory cell can be reduced.

Consistent with the scope of this disclosure, memory cell arrays having vertical transistors and peripheral circuits of the memory cell arrays may be formed on different wafers and bonded together in a face-to-face fashion, in accordance with some aspects of this disclosure. Thus, the thermal budget used to fabricate the memory cell array does not affect the fabrication of the peripheral circuitry. The stacked memory cell array and peripheral circuits may also reduce chip size compared to a side-by-side arrangement, thereby improving array efficiency. In some implementations, more than one memory cell array is stacked on top of each other using bonding techniques to further increase array efficiency. In some embodiments, the word lines and bit lines are disposed proximate to the bonding interface due to vertically disposed transistors that can be coupled to peripheral circuitry through a large number (e.g., millions) of parallel bonding contacts across the bonding interface so that direct short-distance (e.g., micron-scale) electrical connections can be made between the memory cell array and the peripheral circuitry to increase throughput and input/output (I/O) speed of the memory device.

In some embodiments, the vertical transistors disclosed herein include multi-gate transistors (e.g., full-gate-all-around (GAA) transistors, tri-gate transistors, or dual-gate transistors) that may have a larger gate control region to achieve better channel control with a smaller sub-threshold swing. During the off state, the leakage current of the multi-gate transistor can also be significantly reduced because the channel is fully depleted. Thus, using a multi-gate transistor instead of a planar transistor can achieve much better speed (saturated drain current)/leakage current performance.

In some implementations, the vertical transistors disclosed herein include single-gate transistors (also referred to as single-side gate transistors) arranged mirror-symmetrically with respect to adjacent transistors in the bit line direction, as a result of the use of trench isolation extending along the word line direction to segment the multi-gate transistors (e.g., dual-gate transistors). Mirror symmetric single gate transistors have a larger process window for word line, bit line, and transistor pitch reduction than conventional planar transistors or multi-gate vertical transistors (e.g., with double sided or full ring gates).

Fig. 1 illustrates a schematic diagram of a cross-section of a 3D memory device 100 in accordance with some aspects of the present disclosure. The 3D memory device 100 represents an example of a bonded chip. The components of the 3D memory device 100 (e.g., the memory cell array 110 and the peripheral circuitry 108) may be formed separately on different substrates and then bonded to form a bonded chip. The 3D memory device 100 may include a first semiconductor structure 102 including peripheral circuitry 108 of an array of memory cells. The 3D memory device 100 may also include a second semiconductor structure 104 including a memory cell array 110. Peripheral circuitry 108 (also referred to as control and sense circuitry) may include any suitable digital, analog, and/or mixed signal circuitry for facilitating operation of the memory cell array. For example, the peripheral circuitry 108 may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input/output (I/O) circuits, charge pumps, voltage sources or generators, current or voltage references, any portion of the functional circuits (e.g., sub-circuits) mentioned above, or any active or passive component of the circuit (e.g., transistors, diodes, resistors, or capacitors). According to some implementations, the peripheral circuitry 108 in the first semiconductor structure 102 is implemented using Complementary Metal Oxide Semiconductor (CMOS) technology, which may be implemented, for example, with logic technology (e.g., technology nodes of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

As shown in fig. 1, the 3D memory device 100 may also include a second semiconductor structure 104 that includes an array of memory cells (memory cell array 110) that may use transistors as switching and selection devices. In some implementations, the memory cell array 110 includes an array of DRAM cells. For ease of description, a DRAM cell array may be used as an example for describing a memory cell array in the present disclosure. It should be understood that memory cell array 110 is not limited to a DRAM cell array and may include any other suitable type of memory cell array that may use transistors as switching and selection devices, such as a PCM cell array, a Static Random Access Memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a Spin Transfer Torque (STT) memory cell array, or any combination thereof, to name a few.

The second semiconductor structure 104 may be a DRAM device in which the memory cells are provided in the form of an array of DRAM cells. In some implementations, each DRAM cell includes a capacitor for storing a data bit as positive or negative charge and one or more transistors (also referred to as pass transistors) that control (e.g., switch and select) access thereto. In some embodiments, each DRAM cell is a single transistor, single capacitor (1T 1C) cell. Since the transistor always leaks a small amount of charge, the capacitor will slowly discharge, resulting in leakage of the information stored therein. Thus, according to some embodiments, the DRAM cells must be refreshed, for example, by peripheral circuitry 108 in first semiconductor structure 102, to retain the data.

As shown in fig. 1, the 3D memory device 100 further includes a bonding interface 106 vertically between the first semiconductor structure 102 and the second semiconductor structure 104 (in a vertical direction, e.g., the z-direction in fig. 1). The first semiconductor structure 102 and the second semiconductor structure 104 may be fabricated separately (and in parallel in some embodiments) such that the thermal budget for fabricating one of the first semiconductor structure 102 and the second semiconductor structure 104 does not limit the process of fabricating the other of the first semiconductor structure 102 and the second semiconductor structure 104. Further, a large number of interconnects (e.g., bond contacts) may be formed through the bond interface 106 to make direct short-range (e.g., micron-sized) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, rather than long-range (e.g., millimeter or centimeter-sized) chip-to-chip data buses on a circuit board (e.g., a Printed Circuit Board (PCB)), thereby eliminating chip interface delays and achieving high-speed I/O throughput with reduced power consumption. Data transfer between the memory cell array 110 in the second semiconductor structure 104 and the peripheral circuitry 108 in the first semiconductor structure 102 may be performed through interconnections (e.g., bond contacts) across the bond interface 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the chip size can be reduced and the memory cell density can be increased.

It should be appreciated that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited. Fig. 2 illustrates a schematic diagram of a cross-section of another exemplary 3D memory device 200, according to some embodiments. Unlike the 3D memory device 100 in fig. 1, in which the second semiconductor structure 104 including the memory cell array is over the first semiconductor structure 102 including the peripheral circuitry, in the 3D memory device 200 in fig. 2, the first semiconductor structure 202 including the peripheral circuitry 208 is over the second semiconductor structure 204 including the memory cell array 210. However, according to some embodiments, the bonding interface 206 is formed vertically between the first semiconductor structure 202 and the second semiconductor structure 204 in the 3D memory device 200, and the first semiconductor structure 202 and the second semiconductor structure 204 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal/dielectric hybrid bonding", is a direct bonding technique (e.g., bonding between surfaces without the use of an intermediate layer such as solder or adhesive) and metal-metal (e.g., copper-to-copper) bonding and dielectric-dielectric (e.g., silicon oxide-to-silicon oxide) bonding can be achieved simultaneously. Data transfer between the memory cell array 210 in the second semiconductor structure 204 and the peripheral circuitry 208 in the first semiconductor structure 202 may be performed through interconnections (e.g., bond contacts) across the bond interface 206.

It should be noted that the x, y, and z axes are included in fig. 1 and 2 to further illustrate the spatial relationship of the components in 3D memory devices 100 and 200. The substrate of the 3D memory device includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, on which the semiconductor device may be formed; and a bottom surface on a backside opposite the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when a substrate is located in the lowest plane of a 3D memory device in the z-direction (a perpendicular direction perpendicular to the x-y plane, e.g., the thickness direction of the substrate), it is determined in the z-direction whether one component (e.g., a layer or device) is "on", "above" or "below" another component (e.g., a layer or device) of the 3D memory device with respect to the substrate of the 3D memory device. The same concepts used to describe spatial relationships are applied throughout this disclosure.

Fig. 3 illustrates a schematic diagram of a memory device 300 including peripheral circuitry 208 and an array 302 of memory cells each having a vertical transistor 304, in accordance with some aspects of the present disclosure. The memory device 300 may include a memory cell array 301 and peripheral circuitry 208 coupled to the memory cell array 301. The 3D memory devices 100 and 200 may be examples of the memory device 300 in which the memory cell array 301 and the peripheral circuitry 208 may be included in the second semiconductor structure 104/204 and the first semiconductor structure 102/202, respectively. In some embodiments, memory cell array 301 is a DRAM cell array having memory cells 306, memory cells 306 being capacitors for storing charge as binary information stored by the respective DRAM cells. In some implementations, the memory cell array 301 is a PCM cell array having memory cells 306 made of PCM elements (e.g., including chalcogenide alloys) for storing binary information of the respective PCM cells based on different resistivities of the PCM elements in the amorphous and crystalline phases. In some embodiments, memory cell array 301 is a FRAM cell array having memory cells/capacitors 306, the memory cells/capacitors 306 being ferroelectric capacitors for storing binary information of the respective FRAM cells based on switching between two polarization states of ferroelectric material under an external electric field.

As shown in fig. 3, memory cells 302 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 300 may include a word line 310 that couples the peripheral circuitry 208 and the memory cell array 301 for controlling the switching of the vertical transistors 304 in the memory cells 302 located in a row, and a bit line 308 that couples the peripheral circuitry 208 and the memory cell array 301 for sending data to the memory cells 302 located in a column and/or receiving data from the memory cells 302 located in a column. That is, each word line 310 is coupled to a respective row of memory cells 302, and each bit line is coupled to a respective column of memory cells 302.

In some embodiments, as shown in fig. 3, each memory cell 302 is a DRAM cell that includes a vertical transistor 304 and a capacitor 306. The gate of vertical transistor 304 may be coupled to word line 310, one of the source and drain of vertical transistor 304 may be coupled to bit line 308, the other of the source and drain of vertical transistor 304 may be coupled to one electrode of capacitor 306, and the other electrode of capacitor 306 may be coupled to ground.

Peripheral circuitry 208 may be coupled to memory cell array 301 by bit lines 308, word lines 310, and any other suitable metal routing. Peripheral circuitry 208 may include any suitable circuitry for facilitating operation of memory cell array 301 by applying voltage signals and/or current signals to each memory cell 302 and sensing voltage signals and/or current signals from each memory cell 302 via word line 310 and bit line 308. The peripheral circuitry 208 may include various types of peripheral circuitry formed using CMOS technology.

According to some aspects of the present disclosure, the vertical transistors of the memory cells in a memory device (e.g., 3D memory device 200) are single gate transistors, and the gate dielectric of the vertical transistors in the word line direction is continuous. For example, fig. 4A illustrates a plan view of an array of memory cells 402, each memory cell 402 including a vertical transistor in memory device 400, and fig. 4B illustrates a cross-sectional view along line AA' of fig. 4A, in accordance with aspects of the present disclosure. As shown in fig. 4A, the memory device 400 may include a plurality of word lines 410, each word line 410 extending in a first lateral direction (x-direction, referred to as a word line direction). The memory device 400 may also include a plurality of bit lines 408, each bit line 408 extending in a second lateral direction (y-direction, referred to as a bit line direction) perpendicular to the first lateral direction.

Memory cell 402 may be formed at an intersection of a word line 410 and a bit line 408. In some implementations, each memory cell 402 includes a vertical transistor (e.g., vertical transistor 304 in fig. 3) having a semiconductor body 407 and a gate structure 404. The semiconductor body 407 may extend in a vertical direction (z-direction, as shown in fig. 4B) in the substrate perpendicular to the first and second lateral directions. The semiconductor body 407 may have a first lateral dimension along a first lateral direction (e.g., x-direction) and a second lateral dimension along a second lateral direction (e.g., y-direction). The first lateral dimension and the second lateral dimension of the different semiconductor bodies 407 are substantially identical along the x-direction and the y-direction, respectively (error within a margin of + -10%). The vertical transistor may be a single gate transistor in which the gate structure 404 is in contact with a single side (e.g., one of the four sides in fig. 4A) of the semiconductor body 407 in which the active region of the channel is formed. As shown in fig. 4A and 4B, the vertical transistor is a single gate transistor, wherein the gate structure 404 adjoins one side of the semiconductor body 407 in the bit line direction (y-direction). According to some embodiments, gate structure 404 does not surround and contact the other three sides of semiconductor body 407. The gate structure 404 may include a gate dielectric 405 and a gate electrode 406 in contact with the gate dielectric 405. In some implementations, the gate dielectric 405 is located laterally between the gate electrode 406 and the isolation structure 416 in the bit line direction (y-direction). As described above, the gate electrode 406 may be part of the word line 410, and the word line 410 may be an extension of the gate electrode 406. That is, the gate electrodes 406 of adjacent vertical transistors in the word line direction (x-direction) are continuous, e.g., portions of the continuous conductive layer having gate electrodes 406 (e.g., portions of word line 410) abut vertical transistors in the same row on the same side. As shown in fig. 4A, the gate dielectrics 405 of adjacent vertical transistors in the word line direction are continuous, e.g., portions of the continuous dielectric layer having the gate dielectrics 405 and extending in the word line direction. Thus, the gate structure 404 may be considered part of a continuous structure extending in the word line direction where the continuous structure adjoins vertical transistors in the same row on the same side.

As shown in fig. 4A, according to some embodiments, two adjacent vertical transistors (e.g., 402A and 402B, or 402B and 402C) of a memory cell in the bit line direction (y-direction) are mirror symmetric with each other. As described below with respect to the fabrication process, the semiconductor body 407 of each pair of two adjacent vertical transistors (e.g., 402A and 402B, or 402B and 402C) of a memory cell in the bit line direction (y-direction) may be formed by separating them using isolation structures 416 or spacers 414 extending in the word line direction (x-direction) and parallel to the word lines 410. The isolation structures 416 and word lines 410 may be arranged in a staggered fashion in the bit line direction. In some embodiments, isolation structures 416 are formed intermediate the two gate structures 404 such that the resulting pair of gate structures are mirror images of each other with respect to the isolation structures 416. When the respective gate structures 404 are mirror symmetric to each other with respect to the isolation structures 416, the pair of vertical transistors having the semiconductor body 407 are also mirror symmetric to each other.

Fig. 4B illustrates a side view of a cross section of a memory device 400 including vertical transistors, in accordance with some aspects of the present disclosure. The memory device 400 may include a single gate vertical transistor in which the conductive structure abuts a single side of the semiconductor body in plan view. It should be understood that fig. 4B is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnection) in practice.

In some implementations, the memory device 400 includes an array of memory cells 402, each memory cell 402 including a vertical transistor 403. Each memory cell 402 may be a 1T1C cell composed of one transistor and one capacitor. It should be appreciated that the memory unit 402 may have any suitable configuration, such as a 2T1C unit, a 3T1C unit, and the like.

The vertical transistor 403 may be a MOSFET for switching the corresponding memory cell 402. In some implementations, the vertical transistor 403 includes a semiconductor body 407 extending vertically (in the z-direction) (e.g., an active region in which a channel may be formed), and a gate structure 404 in contact with one side of the semiconductor body 407 in the bit line direction (y-direction). The semiconductor body 407 may have a rectangular parallelepiped shape or a cylindrical shape, and the gate structure 404 may abut a single side of the semiconductor body 407 in plan view, as shown in fig. 4A.

As shown in fig. 4A and 4B, in some embodiments, the semiconductor body 407 has two ends (an upper end and a lower end) in a vertical direction (z-direction), and at least one end (e.g., the upper end in fig. 4A and 4B) extends beyond the gate dielectric 405 in the vertical direction (z-direction). In some implementations, one end (e.g., an upper end in fig. 4B) of the semiconductor body 407 is flush with a corresponding end (e.g., an upper end in fig. 4B) of the gate dielectric 405. In some embodiments, both ends (upper and lower ends) of the semiconductor body 407 extend beyond the gate electrode 406 in a vertical direction (z-direction), respectively. That is, the semiconductor body 407 may have a vertical dimension (e.g., depth) that is greater than a vertical dimension (e.g., in the z-direction) of the gate electrode 406, and neither an upper end nor a lower end of the semiconductor body 407 is flush with a corresponding end of the gate electrode 406. Thus, a short circuit between the bit line 408 and the word line/gate electrode 410 can be avoided. The vertical transistor 403 may further include a source and a drain (both referred to as 411 because their positions may be interchanged) disposed at both ends (upper and lower ends) of the semiconductor body 407, respectively, in a vertical direction (z-direction). In some implementations, one of the source and drain 411 (e.g., at the upper end in fig. 4B) is coupled to a capacitor (not shown), and the other of the source and drain 411 is coupled to the bit line 408.

In some embodiments, as shown in FIG. 4B, semiconductor body 407 includes semiconductor material 407-1 and doped semiconductor material 407-2. The semiconductor material 407-1 may comprise monocrystalline silicon, polycrystalline silicon, amorphous silicon, ge, any other semiconductor material, or any combination thereof. In one example, semiconductor body 407 may comprise single crystal silicon. The semiconductor material 407-2 may include silicon doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level and may be used to form a source or drainA pole 411. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain 411 and the bit line 408 or gate electrode 406 to reduce contact resistance. In some embodiments, gate dielectric 405 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al ₂ O ₃ 、HfO ₂ 、Ta ₂ O ₅ 、ZrO ₂ 、TiO ₂ Or any combination thereof. In some implementations, the gate electrode 406 includes a conductive material including, but not limited to W, co, cu, al, ti, tiN, taN, polysilicon, silicide, or any combination thereof. In some embodiments, gate electrode 406 includes a plurality of conductive layers, such as a W layer over a TiN layer. In one example, gate structure 404 may be a "gate oxide/gate polysilicon" gate, where gate dielectric 405 comprises silicon oxide and gate electrode 406 comprises doped polysilicon. In another example, gate structure 404 may be a high-k metal gate (HKMG), where gate dielectric 405 comprises a high-k dielectric and gate electrode 406 comprises a metal.

As described above, since the gate electrode 406 may be a part of or extend as a word line in the word line direction, as shown in fig. 4A, the memory device 400 may further include a plurality of word lines each extending in the word line direction (x direction). Each word line 410 may be coupled to a row of memory cells 402. That is, the bit line 408 and the word line 410 may extend in two perpendicular lateral directions, and the semiconductor body 407 of the vertical transistor 403 may extend in a perpendicular direction perpendicular to the two lateral directions in which the bit line 408 and the word line 410 extend. According to some embodiments, word line 410 is in contact with a word line contact (not shown). In some implementations, the word line 410 includes a conductive material including, but not limited to W, co, cu, al, ti, tiN, taN, polysilicon, silicide, or any combination thereof. In some implementations, the word line 410 includes a plurality of conductive layers, such as a W layer over a TiN layer, as shown in fig. 4A.

As shown in fig. 4B, according to some embodiments, vertical transistor 403 extends vertically through and contacts word line 410, and the source or drain of vertical transistor 403 contacts bit line 408 (or bit line contact, if any) at its lower end (not shown). Accordingly, due to the vertical arrangement of the vertical transistors 403, the word lines 410 and the bit lines 408 can be disposed in different planes in the vertical direction, which simplifies the wiring of the word lines 410 and the bit lines 408. In some embodiments, bit line 408 is disposed vertically between a bonding layer (not shown) and word line 410, and word line 410 is disposed vertically between bit line 408 and a capacitor (not shown). Word line 410 may be coupled to peripheral circuitry through word line contacts (not shown). Similarly, bit line 408 may also be coupled to peripheral circuitry.

As shown in fig. 4A and 4B, the vertical transistors 403 may be arranged in a mirror-symmetrical manner to increase the density of the memory cells 402 in the bit line direction (y-direction). As shown in fig. 4B, two adjacent vertical transistors 403 in the bit line direction are mirror symmetric with respect to each other with respect to the isolation structure 416, according to some embodiments. That is, the memory device 400 may include a plurality of isolation structures 416, each isolation structure 416 extending parallel to the word line 410 in the word line direction (x-direction) and disposed between the semiconductor bodies 407 of two adjacent rows of vertical transistors 403. In some embodiments, the rows of vertical transistors 403 separated by isolation structures 416 are mirror images of each other with respect to isolation structures 416. Isolation structures 416 may be formed using a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. It should be appreciated that the isolation structures 416 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 407. As described below with respect to the manufacturing process, an air gap may be formed due to the relatively small pitch of the vertical transistor 403 in the bit line direction (e.g., y-direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times the dielectric constant of silicon oxide) may improve the insulating effect between the vertical transistors 403 (and the rows of memory cells 402) as compared to some dielectrics (e.g., silicon oxide). Similarly, in some embodiments, an air gap is also formed laterally between the word line/gate electrodes 406 in the bit line direction, depending on the spacing of the word line/gate electrodes 406 in the bit line direction.

Fig. 4C illustrates a side view of a cross section of yet another 3D memory device 400' including vertical transistors, in accordance with aspects of the present disclosure. The 3D memory device 400' may be one example of a memory device including a single gate vertical transistor in which the gate structure abuts a single side of the semiconductor body in plan view. It should be understood that fig. 4C is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnection) in practice. As one example of the 3D memory device 100 described above with respect to fig. 1, the 3D memory device 400' is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked over the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are joined at a bonding interface 106 therebetween. As shown in fig. 4C, the first semiconductor structure 102 may include a substrate 4010, and the substrate 4010 may include silicon (e.g., single crystal silicon, C-Si), siGe, gaAs, ge, SOI, or any other suitable material.

The first semiconductor structure 102 may include peripheral circuitry 4012 on a substrate 4010. In some implementations, the peripheral circuitry 4012 includes a plurality of transistors 4014 (e.g., planar transistors and/or 3D transistors). Trench isolation (e.g., shallow Trench Isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistor 4014) may also be formed on substrate 4010 or in substrate 4010.

In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 4016 over the peripheral circuitry 4012 to transmit electrical signals to the peripheral circuitry 4012 and from the peripheral circuitry 4012. Interconnect layer 4016 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnect lines and via contacts. Interconnect layer 4016 may further comprise one or more ILD layers in which interconnect lines and via contacts may be formed. That is, interconnect layer 4016 may include interconnect lines and via contacts in multiple ILD layers. In some implementations, the peripheral circuits 4012 are coupled to each other by interconnects in the interconnect layer 4016. The interconnect in interconnect layer 4016 may comprise a conductive material including, but not limited to W, co, cu, al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof.

As shown in fig. 4C, the first semiconductor structure 102 may further include a bonding layer 4018 at the bonding interface 106 and over the interconnect layer 4016 and the peripheral circuitry 4012. The bonding layer 4018 may include a plurality of bonding contacts 4019. The bond contact 4019 may comprise a conductive material, such as Cu. The remaining region of the bonding layer 4018 may be formed of a dielectric material, such as silicon oxide. The bond contacts 4019 in the bond layer 4018 and the surrounding dielectric can be used for hybrid bonding. Similarly, as shown in fig. 4C, the second semiconductor structure 104 may also include a bonding layer 4020 at the bonding interface 106 and over the bonding layer 4018 of the first semiconductor structure 102. The bonding layer 4020 may include a plurality of bonding contacts 4021. The bonding contact 4021 may include a conductive material such as Cu. The remaining region of the bonding layer 4020 may be formed of a dielectric material such as silicon oxide. The bond contacts 4021 and surrounding dielectric in the bonding layer 4020 may be used for hybrid bonding. According to some embodiments, the bonding contact 4021 is in contact with the bonding contact 4019 at the bonding interface 106.

The second semiconductor structure 104 may be bonded in a face-to-face manner on top of the first semiconductor structure 102 at a bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 4020 and 4018 as a result of hybrid bonding (also referred to as "metal/dielectric hybrid bonding"), which is a direct bonding technique (e.g., bonding between surfaces without the use of an intermediate layer such as solder or adhesive), and metal-metal bonding and dielectric-dielectric bonding may be achieved simultaneously. In some implementations, the bonding interface 106 is the location where the bonding layers 4020 and 4018 meet and bond. In practice, the bonding interface 106 may be a layer having a thickness that includes a top surface of the bonding layer 4018 of the first semiconductor structure 102 and a bottom surface of the bonding layer 4020 of the second semiconductor structure 104.

In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 4022, the interconnect layer 4022 including a bit line 4023 over the bonding layer 4020 to transmit an electrical signal. The interconnect layer 4022 may include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. In some implementations, the interconnects in interconnect layer 4022 also include local interconnects, such as bit lines 4023 and word line contacts (not shown). Interconnect layer 4022 may also include one or more ILD layers in which interconnect lines and via contacts may be formed. The interconnects in interconnect layer 4022 may include conductive materials including, but not limited to W, co, cu, al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed of a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. In some implementations, the peripheral circuitry 4012 includes a word line driver/row decoder coupled to word line contacts in the interconnect layer 4022 through bond contacts 4021 and 4019 in the bond layers 4020 and 4018 and the interconnect layer 4016. In some implementations, the peripheral circuitry 4012 includes a bit line driver/column decoder coupled to the bit lines 4023 and bit line contacts (if any) in the interconnect layer 4022 through bond contacts 4021 and 4019 in the bond layers 4020 and 4018 and the interconnect layer 4016.

In some embodiments, the second semiconductor structure 104 comprises a DRAM device in which memory cells are disposed over the interconnect layer 4022 and the bonding layer 4020 in the form of an array of DRAM cells 4024. That is, an interconnect layer 4022 including bit lines 4023 may be disposed between bonding layer 4020 and the array of DRAM cells 4024. It should be appreciated that a cross-section of the 3D memory device 400' in fig. 4C may be taken along the bit line direction (y-direction), and that one bit line 4023 in the interconnect layer 4022 extending laterally in the y-direction may be coupled to a column of DRAM cells 4024.

Each DRAM cell 4024 may include a vertical transistor 4026 (e.g., an example of vertical transistor 403 in fig. 4B) and a capacitor 4028 (e.g., an example of memory cell 306 in fig. 3) coupled to vertical transistor 4026. The DRAM cell 4024 may be a 1T1C cell composed of one transistor and one capacitor. It should be appreciated that DRAM cell 4024 may have any suitable configuration, such as a 2T1C cell, a 3T1C cell, and the like.

The vertical transistor 4026 may be a MOSFET for switching the corresponding DRAM cell 4024. In some implementations, the vertical transistor 4026 includes a semiconductor body 4030 extending vertically (in the z-direction) (i.e., an active region in which a channel may be formed), and a gate structure 4036 in contact with one side of the semiconductor body 4030 in the bit line direction (the y-direction). In a single gate vertical transistor, the semiconductor body 4030 may have a cuboid shape or a cylindrical shape, and the gate structure 4036 may abut a single side of the semiconductor body 4030. According to some embodiments, the gate structure 4036 includes a gate electrode 4034 and a gate dielectric 4032 located laterally between the gate electrode 4034 and the semiconductor body 4030 in the bit line direction. In some implementations, the gate dielectric 4032 abuts a side of the semiconductor body 4030 and the gate electrode 4034 abuts the gate dielectric 4032.

As shown in fig. 4C, in some embodiments, the semiconductor body 4030 has two ends (an upper end and a lower end) in a vertical direction (z-direction), and at least one end (e.g., the lower end in fig. 4C) extends beyond the gate dielectric 4032 into the ILD layer in the vertical direction (z-direction). In some implementations, one end (e.g., the upper end in fig. 4C) of the semiconductor body 4030 is flush with a corresponding end of the gate dielectric 4032. In some implementations, both ends (upper and lower ends) of the semiconductor body 4030 extend beyond the gate electrode 4034 into the ILD layer in a vertical direction (z-direction), respectively. That is, the semiconductor body 4030 may have a vertical dimension (e.g., depth) that is greater than a vertical dimension (e.g., in the z-direction) of the gate electrode 4034, and neither the upper end nor the lower end of the semiconductor body 4030 is flush with the corresponding end of the gate electrode 4034. Thus, a short circuit between the bit line 4023 and the word line/gate electrode 4034 or between the word line/gate electrode 4034 and the capacitor 4028 can be avoided. The vertical transistor 4026 may further include a source and a drain (both referred to as 4038 because their positions are interchangeable) provided at both end portions (upper end portion and lower end portion) of the semiconductor body 4030, respectively, in the vertical direction (z direction). In some implementations, one of the source and drain 4038 is coupled to the capacitor 4028 and the other of the source and drain 4038 is coupled to the bit line 4023.

In some implementations, the semiconductor body 4030 includes a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 4030 can include monocrystalline silicon. The source and drain 4038 may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source and drain electrodes 4038 and the bit line 4023 or the first electrode 4042 to reduce contact resistance. In some embodiments, gate dielectric 4032 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al ₂ O ₃ 、HfO ₂ 、Ta ₂ O ₅ 、ZrO ₂ 、TiO ₂ Or any combination thereof. In some embodiments, the gate electrode 4034 includes a conductive material including, but not limited to, W, co, cu, al, tiN, taN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 4034 includes a plurality of conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 4036 may be a "gate oxide/gate polysilicon" gate, wherein the gate dielectric 4032 comprises silicon oxide and the gate electrode 4034 comprises doped polysilicon. In another example, the gate structure 4036 may be HKMG, wherein the gate dielectric 4032 comprises a high-k dielectric and the gate electrode 4034 comprises a metal.

The gate electrode 4034 may be part of or extend as a word line in a word line direction (e.g., x-direction), and the second semiconductor structure 104 of the 3D memory device 400' may also include a plurality of word lines, each extending in the word line direction (x-direction). Each word line 4034 may be coupled to a row of DRAM cells 4024. That is, the bit line 4023 and the word line 4034 may extend in two perpendicular lateral directions, and the semiconductor body 4030 of the vertical transistor 4026 may extend in a perpendicular direction perpendicular to the two lateral directions in which the bit line 4023 and the word line 4034 extend. According to some embodiments, word line 4034 is in contact with a word line contact (not shown). In some implementations, the word lines 4034 include a conductive material including, but not limited to W, co, cu, al, tiN, taN, polysilicon, silicide, or any combination thereof. In some implementations, the word line 4034 includes a plurality of conductive layers, such as a W layer over a TiN layer.

As shown in fig. 4C, according to some embodiments, vertical transistor 4026 extends vertically through and contacts word line 4034, and the source or drain 4038 of vertical transistor 4026 is in contact with bit line 4023 (or bit line contact, if any) at its lower end. Accordingly, due to the vertical arrangement of the vertical transistor 4026, the word line 4034 and the bit line 4023 can be disposed in different planes in the vertical direction, which simplifies wiring of the word line 4034 and the bit line 4023. In some embodiments, the bit line 4023 is disposed vertically between the bonding layer 4020 and the word line 4034, and the word line 4034 is disposed vertically between the bit line 4023 and the capacitor 4028. The word line 4034 may be coupled to the peripheral circuitry 4012 in the first semiconductor structure 102 through word line contacts (not shown) in the interconnect layer 4022, bond contacts 4021 and 4019 in the bond layers 4020 and 4018, and interconnects in the interconnect layer 4016. Similarly, bit line 4023 in interconnect layer 4022 may be coupled to peripheral circuitry 4012 in first semiconductor structure 102 through bond contacts 4021 and 4019 in bond layers 4020 and 4018 and through interconnects in interconnect layer 4016.

As described above with respect to fig. 4A and 4B, vertical transistors 4026 may be arranged in a mirror symmetrical fashion to increase the density of DRAM cells 4024 in the bit line direction (y-direction). As shown in fig. 4C, two adjacent vertical transistors 4026 in the bit line direction are mirror symmetric with each other with respect to the trench isolation 4060, according to some embodiments. That is, the second semiconductor structure 104 may include a plurality of trench isolations 4060, each trench isolation 4060 extending parallel to the word line 4034 in the word line direction (x-direction) and disposed between the semiconductor bodies 4030 of two adjacent rows of vertical transistors 4026. In some implementations, the rows of vertical transistors 4026 separated by trench isolation 4060 are mirror images of each other with respect to trench isolation 4060. The trench isolation 4060 may be formed from a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. It should be appreciated that the trench isolation 4060 may include air gaps, each air gap being laterally disposed between adjacent semiconductor bodies 4030. As described below with respect to the manufacturing process, an air gap may be formed due to the relatively small pitch of the vertical transistor 4026 in the bit line direction (e.g., the y-direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times the dielectric constant of silicon oxide) may improve the insulating effect between the vertical transistors 4026 (and the rows of DRAM cells 4024) as compared to some dielectrics (e.g., silicon oxide). Similarly, in some embodiments, an air gap is also formed laterally in the bit line direction between the word line/gate electrodes 4034, depending on the spacing of the word line/gate electrodes 4034 in the bit line direction.

As shown in fig. 4C, in some embodiments, the capacitor 4028 includes a first electrode 4042 above the source or drain 4038 (e.g., upper end portion of the semiconductor body 4030) of the vertical transistor 4026 and in contact with the source or drain 4038 of the vertical transistor 4026. The capacitor 4028 may also include a capacitor dielectric 4044 over the first electrode 4042 and in contact with the first electrode 4042 and a second electrode 4046 over the capacitor dielectric 4044 and in contact with the capacitor dielectric 4044. That is, the capacitor 4028 may be a vertical capacitor in which the electrodes 4042 and 4046 and the capacitor dielectric 4044 are vertically stacked (in the z-direction), and the capacitor dielectric 4044 may be sandwiched between the electrodes 4042 and 4046. In some embodiments, each first electrode 4042 is coupled to the source or drain 4038 of a corresponding vertical transistor 4026 in the same DRAM cell, while all second electrodes 4046 are part of a common plate coupled to ground (e.g., common ground). As shown in fig. 4C, the second semiconductor structure 104 may further include a capacitor contact 4047 in contact with the common plate of the second electrode 4046 for coupling the second electrode 4046 of the capacitor 4028 to the peripheral circuit 4012 or directly to ground. In some implementations, the ILD layer in which the capacitor 4028 is formed has the same dielectric material, such as silicon oxide, as the two ILD layers into which the semiconductor body 4030 extends.

It should be appreciated that the structure and configuration of capacitor 4028 is not limited to that in FIG. 4CBy way of example, and may include any suitable structure and configuration, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate plate capacitors. In some embodiments, capacitor dielectric 4044 includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric including, but not limited to, al ₂ O ₃ 、HfO ₂ 、Ta ₂ O ₅ 、ZrO ₂ 、TiO ₂ Or any combination thereof. It should be appreciated that in some examples, capacitor 4028 may be a ferroelectric capacitor used in a FRAM cell, and capacitor dielectric 4044 may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes 4042 and 4046 include a conductive material including, but not limited to, W, co, cu, al, tiN, taN, polysilicon, silicide, or any combination thereof.

As shown in fig. 4C, according to some embodiments, vertical transistor 4026 extends vertically through and contacts word line 4034, source or drain 4038 of vertical transistor 4026 contacts bit line 4023 at its lower end, and source or drain 4038 of vertical transistor 4026 contacts electrode 4042 of capacitor 4028 at its upper end. That is, due to the vertical arrangement of the vertical transistor 4026, the bit line 4023 and the capacitor 4028 may be disposed in different planes in the vertical direction and coupled to opposite ends of the vertical transistor 4026 of the DRAM cell 4024 in the vertical direction. In some embodiments, the bit line 4023 and the capacitor 4028 are disposed on opposite sides of the vertical transistor 4026 in a vertical direction, which simplifies wiring of the bit line 4023 and reduces coupling capacitance between the bit line 4023 and the capacitor 4028 as compared to conventional DRAM cells in which the bit line and the capacitor are disposed on the same side of a planar transistor.

As shown in fig. 4C, in some embodiments, a vertical transistor 4026 is disposed vertically between capacitor 4028 and bonding interface 106. That is, the vertical transistor 4026 may be disposed closer to the peripheral circuit 4012 of the first semiconductor structure 102, and the bonding interface 106 than the capacitor 4028. Since bit line 4023 and capacitor 4028 are coupled to opposite ends of vertical transistor 4026, as described above, bit line 4023 (as part of interconnect layer 4022) is vertically disposed between vertical transistor 4026 and bonding interface 106 in accordance with some embodiments. As a result, the interconnect layer 4022 including the bit lines 4023 may be disposed close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

In some embodiments, the second semiconductor structure 104 further includes a substrate 4048 disposed over the DRAM cell 4024. The substrate 4048 may be part of a carrier wafer, as described below with respect to the manufacturing process. It should be appreciated that in some examples, the substrate 4048 may not be included in the second semiconductor structure 104.

As shown in fig. 4C, the second semiconductor structure 104 may also include a substrate 4048 and a pad output interconnect layer 4050 over the DRAM cells 4024. The pad output interconnect layer 4050 may include interconnects in one or more ILD layers, such as contact pads 4054. Pad output interconnect layer 4050 and interconnect layer 4022 may be formed on opposite sides of DRAM cell 4024. According to some embodiments, the capacitor 4028 is vertically disposed between the vertical transistor 4026 and the pad output interconnect layer 4050. In some implementations, the interconnects in the pad output interconnect layer 4050 may transmit electrical signals between the 3D memory device 400' and external circuitry, e.g., for pad output purposes. In some embodiments, the second semiconductor structure 104 further includes one or more contacts 4052 extending through a portion of the substrate 4048 and the pad output interconnect layer 4050 to couple the pad output interconnect layer 4050 to the DRAM cells 4024 and the interconnect layer 4022. Thus, peripheral circuitry 4012 can be coupled to DRAM cell 4024 through interconnect layers 4016 and 4022 and bonding layers 4020 and 4018, and peripheral circuitry 4012 and DRAM cell 4024 can be coupled to external circuitry through contacts 4052 and pad output interconnect layer 4050. The contact pads 4054 and contacts 4052 may include conductive material including, but not limited to, W, co, cu, al, silicide, or any combination thereof. In one example, the contact pad 4054 may include Al and the contact 4052 may include W. In some implementations, the contacts 4052 include vias surrounded by dielectric spacers (e.g., with silicon oxide) to electrically separate the vias from the substrate 4048. Depending on the thickness of the substrate 4048, the contacts 4052 may be ILVs having a depth on the order of submicron (e.g., between 10nm and 1 μm) or TSVs having a depth on the order of microns or tens of microns (e.g., between 1 μm and 100 μm).

Although not shown, it should be understood that the pad output of the 3D memory device is not limited to from the second semiconductor structure 104 having the DRAM cell 4024 as shown in fig. 4C, and may be from the first semiconductor structure 102 having the peripheral circuitry 4012. Although not shown, it should also be appreciated that the air gaps between the word lines 4034 and/or between the semiconductor bodies 4030 may be partially or completely filled with a dielectric. Although not shown, it is further understood that more than one array of DRAM cells 4024 may be stacked on top of each other to vertically scale up the number of DRAM cells 4024.

Fig. 6 illustrates a flow chart of a method 600 for forming an array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure. At operation 602 in fig. 6, a plurality of spacers are formed. The plurality of spacers extend in a first lateral direction, and each of the spacers extends vertically in an upper portion of the semiconductor layer. The semiconductor layer may include a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. In some embodiments, to form the plurality of spacers, an upper portion of the semiconductor layer is etched in a first lateral direction to form a plurality of recesses, and then a sacrificial layer is deposited to fill the plurality of recesses and form the plurality of spacers.

Fig. 5A and 5A' illustrate a semiconductor layer 501 comprising a substrate 501-1, a first dielectric layer 501-2 on top of the substrate 501-1, and a second dielectric layer 501-3 on top of the first dielectric layer 501-2. In some embodiments, the first dielectric layer 501-2 and the second dielectric layer 501-3 are removed in a subsequent process, allowing the capacitor structure to be effectively connected to the source. Fig. 5A shows a plan view of the semiconductor layer 501, and fig. 5A' shows a side view of the semiconductor layer 501. To form the semiconductor layer 501, silicon oxide and silicon nitride are then deposited onto the silicon substrate 501-1 using one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the silicon oxide layer 501-2 is formed by using a dry oxidation and/or a wet oxidation, such as an In Situ Steam Generation (ISSG) oxidation process, of a top portion of the silicon oxide substrate 501-1.

As shown in fig. 5B and 5B', a plurality of parallel trenches are formed in the y-direction (e.g., bit line direction) to form a plurality of parallel semiconductor walls 505 in the y-direction. In some implementations, for example based on a bit line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the trenches and semiconductor walls 505, and one or more dry etching and/or wet etching processes (such as RIE) are performed to etch the trenches in semiconductor layer 501. Accordingly, the semiconductor wall 505 extending vertically in the semiconductor layer 501 can be formed. Since the semiconductor wall 505 is formed by etching the semiconductor layer 501, the semiconductor wall 505 may have the same material as the semiconductor layer 501. In some implementations, the plurality of parallel trenches are filled by depositing a third dielectric layer (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to form the plurality of parallel trench isolations 504. In some implementations, a planarization process (e.g., CMP) is performed to remove excess third dielectric layer deposited beyond the top surface of semiconductor layer 501. As a result, parallel semiconductor walls 505 may be separated by trench isolation 504. Fig. 5B and 5B 'show a plan view in the x-y plane and a side view of a section along the x-direction (word line direction, e.g., along line AA'), respectively.

As shown in fig. 5C and 5C', a plurality of parallel grooves 510 having a first depth are formed in the x-direction (e.g., the word line direction) to form an array of semiconductor pillars 503 each extending vertically in the semiconductor layer 501. In some implementations, for example, based on the design of the word lines, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the recesses 510 perpendicular to the trench isolation 504, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 501 and the trench isolation 504 to etch the recesses in the semiconductor layer 501. Accordingly, semiconductor walls 505 (shown in fig. 5B) may be cut by grooves 510 to form an array of semiconductor pillars 503 each extending vertically in semiconductor layer 501. Since the semiconductor pillars 503 are formed by etching the semiconductor layer 501, the semiconductor pillars 503 may have the same material as the semiconductor layer 501. Fig. 5C shows a plan view in the x-y plane, and fig. 5C' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 5D and 5D', a sacrificial layer is deposited in the grooves 510 to form a plurality of spacers 511. The sacrificial layer may be deposited using a dielectric (e.g., silicon oxide) to fill the recess 510 by using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In some embodiments, a planarization process (such as CMP) is performed to remove excess dielectric deposited beyond the top surface of semiconductor layer 501. Fig. 5D and 5D' show a plan view in the x-y plane and a side view of a section along the x direction (word line direction), respectively.

At operation 604 in fig. 6, a plurality of first trenches are formed. The plurality of first trenches extend in a first lateral direction, and each of the first trenches extends vertically in an upper portion of the semiconductor layer. In some embodiments, to form the plurality of first trenches, an upper portion of the semiconductor layer is etched in a first lateral direction to form the plurality of first trenches sandwiched between two adjacent spacers. After forming the plurality of first trenches, the semiconductor pillars are divided by the plurality of first trenches to form a plurality of semiconductor bodies.

As shown in fig. 5E and 5E', a plurality of first trenches 506 having a second depth sandwiched between two spacers 511 are formed in the x-direction (e.g., the word line direction), and each first trench extends vertically in the semiconductor layer 501 and cuts one semiconductor pillar into two semiconductor bodies 507. Each semiconductor body 507 extends in a vertical direction (e.g., the z-direction as shown in fig. 5E'). Each semiconductor body 507 has a first lateral dimension along a first lateral direction (e.g., x-direction) and a second lateral dimension along a second lateral direction (e.g., y-direction). The first lateral dimension and the second lateral dimension of the different semiconductor bodies 507 are substantially identical along the x-direction and the y-direction, respectively (error within a margin of + -10%). In some implementations, for example, based on the design of the word lines, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the first trenches 506 parallel to the spacers 511 and perpendicular to the trench isolation 504, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 501 and the trench isolation 504 to etch the first trenches in the semiconductor layer 501. Fig. 5E shows a plan view in the x-y plane, and fig. 5E' shows a side view of a section in the y direction (bit line direction).

At operation 606 of fig. 6, two disconnected conductive structures are formed in each first trench. The two disconnected conductive structures extend laterally in a first lateral direction and each of the conductive structures extends vertically along one sidewall of a corresponding first trench.

As shown in fig. 5F and 5F', a dielectric layer 509 is formed at the bottom of the first trench 506, for example by depositing a dielectric (such as silicon oxide) to fill the first trench 506 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In some embodiments, a dielectric layer 519 is deposited on the sidewalls of each first trench 506 to partially fill each first trench 506, followed by deposition of a dielectric layer 509 to completely fill each first trench 506. In some embodiments, dielectric layers 519 and 509 may be made of different materials (e.g., silicon oxide and silicon nitride), respectively. In some embodiments, dielectric layers 519 and 509 may be made of the same material (e.g., silicon oxide or silicon nitride). In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric layer 509 deposited beyond the top surface of semiconductor layer 501. The dielectric layer 509 is then etched back such that the dielectric layer 509 covers the bottom surface of each first trench 506. In some embodiments, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to etch back the dielectric layer 509, or one or more dry etching and/or wet etching processes (such as RIE) are performed on the dielectric layer 509 until the etch back reaches a third depth. Fig. 5F shows a plan view in the x-y plane, and fig. 5F' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 5G and 5G', a gate dielectric layer 514 is formed in each first trench 506. The gate dielectric layer 514 may be part of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 507. In some embodiments, a wet oxidation and/or dry oxidation process, such as an In Situ Steam Generation (ISSG) oxidation, is performed to form a native oxide (e.g., silicon oxide) on the sidewalls of each first trench 506.

As shown in fig. 5G and 5G', one or more conductive layers 515 are formed over the gate dielectric layer 514 in the first trench 506. In some embodiments, conductive layer 515 is formed by depositing one or more conductive materials, such as metals and/or metal compounds (e.g., W and TiN), over gate dielectric layer 514 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof, to partially fill first trench 506. For example, a TiN layer and a W layer may be sequentially deposited to form the conductive layer 515. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of semiconductor layer 501.

As shown in fig. 5H and 5H', in some embodiments, the conductive layer 515 is etched back, for example using a punch etch, a dry etch, and/or a wet etch (e.g., RIE), to form two open conductive structures in each first trench 506. In some embodiments, a bottom punch etch process is performed to etch away some of the metal of the conductive layer 515 at the bottom of the first trench until the dielectric layer 509 is exposed. In some embodiments, the conductive layer 515 is etched back to form an indentation such that an upper end of the conductive layer 515 is below the top surface of the semiconductor body 507. In some embodiments, since the gate dielectric layer 514 is not etched, the upper end of the conductive layer 515 is also below the upper end of the gate dielectric layer 514 (which is flush with the top surface of the semiconductor body 507). As a result, the etched back conductive layer 515 may become word lines each extending in a word line direction (x-direction), and a portion of the etched back conductive layer 515 facing the semiconductor body 507 may become a gate electrode. Thereby gate structures may be formed that each include a respective gate dielectric layer 514 and a respective gate electrode (e.g., a portion of conductive layer 515) over gate dielectric layer 514.

In some embodiments, as shown in fig. 5I and 5I', a dielectric layer 516 is formed in the remaining space of the first trench 506 and the indentation resulting from the etch back of the conductive layer 515, for example by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. It should be appreciated that depending on the pitch of the word lines (e.g., the size of the first trenches 506), an air gap may be formed in the dielectric layer 516.

In some embodiments, as shown in fig. 5J and 5J', the sacrificial layer in the spacer 511 is removed to form a second trench, and a dielectric layer or a metal shield layer is deposited to fill the second trench. In some embodiments, a photolithography process is performed using an etching mask (e.g., a photoresist mask and/or a hard mask) to remove the sacrificial layer inside the spacer 511, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the spacer 511 to etch away the sacrificial layer and form the second trench. For example, the second trench isolation 517 is formed in the second trench by depositing a dielectric layer (such as silicon oxide) using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof to fill the second trench. A planarization process may be performed to remove excess dielectric over the top surface of semiconductor layer 501. It should be appreciated that the air gap 518 may be formed in the second trench isolation 517 depending on the pitch of the semiconductor bodies 507 (e.g., the size of the second trench).

Fig. 8 illustrates a flow chart of a method 800 for forming an array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure. At operation 802 in fig. 8, a plurality of first trenches are formed. The plurality of first trenches extend in a first lateral direction, and each of the first trenches extends vertically in an upper portion of the semiconductor layer. The semiconductor layer may include a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. In some embodiments, to form the plurality of first trenches, an upper portion of the semiconductor layer is etched in a first lateral direction.

Fig. 7A and 7A' illustrate a semiconductor layer 701 including a substrate 701-1, a first dielectric layer 701-2 on top of the substrate 701-1, and a second dielectric layer 701-3 on top of the first dielectric layer 701-2. In some embodiments, the first dielectric layer 701-2 and the second dielectric layer 701-3 are removed in a subsequent process, allowing the capacitor structure to be effectively connected to the source. Fig. 7A shows a plan view of the semiconductor layer 701, and fig. 7A' shows a side view of the semiconductor layer 701. To form the semiconductor layer 701, silicon oxide and silicon nitride are then deposited onto the silicon substrate 701-1 using one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the silicon oxide layer 701-2 is formed by using a dry oxidation and/or a wet oxidation, such as an In Situ Steam Generation (ISSG) oxidation process, of a top portion of the silicon oxide substrate 701-1.

As shown in fig. 7B and 7B', a plurality of parallel trenches are formed in the y-direction (e.g., bit line direction) to form a plurality of parallel semiconductor walls 705 in the y-direction. In some implementations, for example based on a bit line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the trenches and semiconductor walls 705, and one or more dry etching and/or wet etching processes (such as RIE) are performed to etch the trenches in the semiconductor layer 701. Accordingly, the semiconductor wall 705 extending vertically in the semiconductor layer 701 can be formed. Since the semiconductor wall 705 is formed by etching the semiconductor layer 701, the semiconductor wall 705 may have the same material as the semiconductor layer 701. In some implementations, the plurality of parallel trenches are filled by depositing a third dielectric layer (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to form a plurality of parallel trench isolations 704. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess third dielectric layer deposited beyond the top surface of semiconductor layer 701. As a result, parallel semiconductor walls 705 may be separated by trench isolation 704. Fig. 7B and 7B 'show a plan view in the x-y plane and a side view of a section along the x-direction (word line direction, e.g., along line AA'), respectively.

As shown in fig. 7C and 7C', a plurality of first trenches 706 having a second depth are formed in the x-direction (e.g., the word line direction) to form an array of semiconductor pillars 703 each extending vertically in semiconductor layer 701. In some implementations, for example, based on the design of the word lines, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the first trenches 706 perpendicular to the trench isolation 704, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 701 and the trench isolation 704 to etch the first trenches 706 in the semiconductor layer 701. Accordingly, semiconductor wall 705 (shown in fig. 7B) may be cut by first trench 706 to form an array of semiconductor pillars 703, each semiconductor pillar 703 extending vertically in semiconductor layer 701. Since the semiconductor column 703 is formed by etching the semiconductor layer 701, the semiconductor column 703 may have the same material as the semiconductor layer 701. Fig. 7C shows a plan view in the x-y plane, and fig. 7C' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 7D and 7D', a dielectric layer 709 is formed in each first trench 706, for example by depositing a dielectric (such as silicon oxide) to fill the first trench 706 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In some embodiments, a dielectric layer 719 is deposited on the sidewalls of each first trench 706 to partially fill each first trench 706, followed by deposition of a dielectric layer 709 to completely fill each first trench 706. In some embodiments, dielectric layers 719 and 709 may be made of different materials (e.g., silicon oxide and silicon nitride), respectively. In some embodiments, dielectric layers 719 and 709 may be made of the same material (e.g., silicon oxide or silicon nitride). In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric layer 709 deposited beyond the top surface of semiconductor layer 701.

At operation 804 in fig. 8, a plurality of spacers are formed. The plurality of spacers extend in a first lateral direction, and each of the spacers extends vertically in an upper portion of the semiconductor layer. In some embodiments, to form the plurality of spacers, an upper portion of the semiconductor layer is etched in a first lateral direction to form a plurality of grooves sandwiched between two adjacent first trenches. The plurality of recesses are then filled with a sacrificial layer to form a plurality of spacers.

As shown in fig. 7E and 7E', a plurality of parallel grooves 710 having a first depth are formed in the x-direction (e.g., the word line direction), and each groove extends vertically in the semiconductor layer 701 and cuts one semiconductor pillar 703 into two semiconductor bodies 707. Each semiconductor body 707 extends in a vertical direction (e.g., the z-direction as shown in fig. 7E'). Each semiconductor body 707 has a first lateral dimension along a first lateral direction (e.g., x-direction) and a second lateral dimension along a second lateral direction (e.g., y-direction). The first lateral dimension and the second lateral dimension of the different semiconductor body 707 are substantially identical in the x-direction and the y-direction, respectively (error within a margin of + -10%). In some implementations, for example based on a word line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the recesses 710 perpendicular to the trench isolation 704, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 701 and the trench isolation 704 to etch the recesses in the semiconductor layer 701. Fig. 7E shows a plan view in the x-y plane, and fig. 7E' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 7F and 7F', the plurality of parallel grooves 710 are filled with a sacrificial layer to form a plurality of spacers 711. The sacrificial layer may be deposited using a dielectric such as silicon oxide to fill the recess 710 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In some embodiments, a planarization process (such as CMP) is performed to remove excess dielectric deposited beyond the top surface of semiconductor layer 701. Fig. 7F and 7F' show a plan view in the x-y plane and a side view of a section along the x direction (word line direction), respectively.

At operation 806 of fig. 8, two disconnected conductive structures are formed in each first trench. The two disconnected conductive structures extend laterally in a first lateral direction and each of the conductive structures extends vertically along one sidewall of a corresponding first trench.

As shown in fig. 7G and 7G', the dielectric layer 709 is etched back such that the dielectric layer 709 covers the bottom surface of each first trench 706. In some implementations, a photolithography process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to etch back dielectric layer 709, or one or more dry etching and/or wet etching processes (such as RIE) are performed on dielectric layer 709 until the etch back reaches a third depth. Fig. 7F shows a plan view in the x-y plane, and fig. 7F' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 7H and 7H', a gate dielectric layer 714 is formed in each first trench 706. The gate dielectric layer 714 may be part of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 707. In some embodiments, a wet oxidation and/or dry oxidation process, such as an In Situ Steam Generation (ISSG) oxidation, is performed to form a native oxide (e.g., silicon oxide) on the sidewalls of each first trench 706. One or more conductive layers 715 are then formed over the gate dielectric layer 714 in the first trench 706. In some implementations, the conductive layer 715 is formed by depositing one or more conductive materials (e.g., metals and/or metal compounds (e.g., W and TiN)) over the gate dielectric layer 714 to partially fill the first trench 706 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. For example, a TiN layer and a W layer may be sequentially deposited to form the conductive layer 715. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of semiconductor layer 701.

As shown in fig. 7I and 7I', in some embodiments, the conductive layer 715 is etched back, for example using a punch etch, a dry etch, and/or a wet etch (e.g., RIE), to form two open conductive structures in each first trench 706. In some implementations, a bottom punch etch process is performed to etch away some of the metal of the conductive layer 715 at the bottom of the first trench until the dielectric layer 709 is exposed. In some implementations, the conductive layer 715 is etched back to form an indent such that an upper end of the conductive layer 715 is below the top surface of the semiconductor body 707. In some embodiments, since the gate dielectric layer 714 is not etched, the upper end of the conductive layer 715 is below the upper end of the gate dielectric layer 714. Accordingly, the etched back conductive layer 715 may become word lines each extending in a word line direction (x-direction), and a portion of the etched back conductive layer 715 facing the semiconductor body 707 may become a gate electrode. Gate structures may thereby be formed that each include a respective gate dielectric layer 714 and a respective gate electrode (e.g., a portion of conductive layer 715) over gate dielectric layer 714.

In some embodiments, as shown in fig. 7I and 7I', a dielectric layer 716 is formed in the remaining space of the first trench 706 and the indentation resulting from the etch back of the conductive layer 715, for example by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. It should be appreciated that depending on the pitch of the word lines (e.g., the size of the first trenches 706), an air gap 720 may be formed in the dielectric layer 716.

In some embodiments, as shown in fig. 7J and 7J ', the sacrificial layer in the spacer 711 (as shown in fig. 7F') is removed to form a second trench, and a dielectric layer is deposited to fill the second trench. In some embodiments, a photolithography process is performed using an etching mask (e.g., a photoresist mask and/or a hard mask) to remove the sacrificial layer inside the spacer 711, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the spacer 711 to etch away the sacrificial layer and form the second trench. For example, the second trench isolation 717 is formed in the second trench by depositing a dielectric layer (such as silicon oxide) to fill the second trench using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. A planarization process may be performed to remove excess dielectric over the top surface of semiconductor layer 701. It should be appreciated that depending on the pitch of the semiconductor body 707 (e.g., the size of the second trench), an air gap 718 may be formed in the second trench isolation 717.

Fig. 10 illustrates a flow chart of a method 1000 for forming an array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure. At operation 1002 in fig. 10, a plurality of first trenches are formed. The plurality of first trenches extend in a first lateral direction, and each of the first trenches extends vertically in an upper portion of the semiconductor layer. The semiconductor layer may include a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. In some embodiments, to form the plurality of first trenches, an upper portion of the semiconductor layer is etched in a first lateral direction.

Fig. 9A and 9A' illustrate a semiconductor layer 901 comprising a substrate 901-1, a first dielectric layer 901-2 on top of the substrate 901-1, and a second dielectric layer 901-3 on top of the first dielectric layer 901-2. In some embodiments, the first dielectric layer 901-2 and the second dielectric layer 901-3 are removed in a subsequent process, allowing the capacitor structure to be effectively connected to the source electrode. Fig. 9A shows a plan view of the semiconductor layer 901, and fig. 9A' shows a side view of the semiconductor layer 901. To form the semiconductor layer 901, silicon oxide and silicon nitride are then deposited onto the silicon substrate 901-1 using one or more thin film deposition processes, including but not limited to Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the silicon oxide layer 901-2 is formed by using a dry oxidation and/or a wet oxidation, such as an In Situ Steam Generation (ISSG) oxidation process, of a top portion of the silicon oxide substrate 901-1.

As shown in fig. 9B and 9B', a plurality of parallel trenches are formed in the y-direction (e.g., bit line direction) to form a plurality of parallel semiconductor walls 905 in the y-direction. In some implementations, for example based on a bit line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the trenches and semiconductor walls 905, and one or more dry etching and/or wet etching processes (such as RIE) are performed to etch the trenches in the semiconductor layer 901. Accordingly, a semiconductor wall 905 extending vertically in the semiconductor layer 901 can be formed. Since the semiconductor wall 905 is formed by etching the semiconductor layer 901, the semiconductor wall 905 may have the same material as the semiconductor layer 901. In some implementations, the plurality of parallel trenches are filled by depositing a third dielectric layer (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to form a plurality of parallel trench isolations 904. In some implementations, a planarization process (e.g., CMP) is performed to remove excess third dielectric layer deposited beyond the top surface of semiconductor layer 901. As a result, parallel semiconductor walls 905 may be separated by trench isolation 904. Fig. 9B and 9B 'show a plan view in the x-y plane and a side view of a section along the x-direction (word line direction, e.g., along line AA'), respectively.

As shown in fig. 9C and 9C', a plurality of first trenches 906 having a second depth are formed in the x-direction (e.g., the word line direction) to form an array of semiconductor pillars 903, each semiconductor pillar 903 extending vertically in the semiconductor layer 901. In some implementations, for example, based on the design of the word lines, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the first trenches 906 perpendicular to the trench isolation 904, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 901 and the trench isolation 904 to etch the first trenches 906 in the semiconductor layer 901. Thus, the semiconductor walls 905 (shown in fig. 9B) may be cut by the first trenches 906 to form an array of semiconductor pillars 903, each semiconductor pillar 903 extending vertically in the semiconductor layer 901. Since the semiconductor pillar 903 is formed by etching the semiconductor layer 901, the semiconductor pillar 903 may have the same material as the semiconductor layer 901. Fig. 9C shows a plan view in the x-y plane, and fig. 9C' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 9D and 9D', a dielectric layer 909 is formed in each first trench 906, for example, by depositing a dielectric (such as silicon oxide) to fill the first trenches 906 using one or more thin film deposition processes (including, but not limited to CVD, PVD, ALD or any combination thereof). In some embodiments, a dielectric layer 919 is deposited on the sidewalls of each first trench 906 to partially fill each first trench 906, followed by deposition of a dielectric layer 909 to completely fill each first trench 906. In some embodiments, dielectric layers 919 and 909 may be made of different materials (e.g., silicon oxide and silicon nitride), respectively. In some embodiments, dielectric layers 919 and 909 may be made of the same material (e.g., silicon oxide or silicon nitride). In some implementations, a planarization process (e.g., CMP) is performed to remove excess dielectric layer 909 deposited beyond the top surface of semiconductor layer 901. Then, the dielectric layer 909 is etched back so that the dielectric layer 909 covers the bottom surface of each first trench 906. In some embodiments, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to etch back dielectric layer 909, or one or more dry etching and/or wet etching processes (such as RIE) are performed on dielectric layer 909 until the etch back reaches a third depth. Fig. 9D shows a plan view in the x-y plane, and fig. 9D' shows a side view of a section in the y direction (bit line direction).

At operation 1004 of fig. 10, two disconnected conductive structures are formed in each first trench. The two disconnected conductive structures extend laterally in a first lateral direction and each of the conductive structures extends vertically along one sidewall of a corresponding first trench.

As shown in fig. 9E and 9E', a gate dielectric layer 914 is formed in each first trench 906. The gate dielectric layer 914 may be part of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 907. Each semiconductor body 907 extends in a vertical direction (e.g., the z-direction as shown in fig. 9E'). Each semiconductor body 907 has a first lateral dimension along a first lateral direction (e.g., x-direction) and has a second lateral dimension along a second lateral direction (e.g., y-direction). The first lateral dimension and the second lateral dimension of the different semiconductor bodies 907 are substantially the same in the x-direction and the y-direction, respectively (the error is within a margin of + -10%). In some embodiments, a wet oxidation and/or dry oxidation process, such as an In Situ Steam Generation (ISSG) oxidation, is performed to form a native oxide (e.g., silicon oxide) on the sidewalls of each first trench 906. One or more conductive layers 915 are then formed over the gate dielectric layer 914 in the first trench 906. In some embodiments, the conductive layer 915 is formed by depositing one or more conductive materials, such as metals and/or metal compounds (e.g., W and TiN), over the gate dielectric layer 914 to partially fill the first trench 906 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. For example, a TiN layer and a W layer may be sequentially deposited to form the conductive layer 915. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the semiconductor layer 901.

As shown in fig. 9F and 9F', in some embodiments, the conductive layer 915 is etched back, for example using a punch etch, a dry etch, and/or a wet etch (e.g., RIE), to form two open conductive structures in each first trench 906. In some embodiments, a bottom punch etch process is performed to etch away some of the metal of the conductive layer 915 at the bottom of the first trench until the dielectric layer 909 is exposed. In some embodiments, conductive layer 915 is etched back to form an indentation such that an upper end of conductive layer 915 is below a top surface of semiconductor body 907. In some embodiments, since the gate dielectric layer 914 is not etched, the upper end of the conductive layer 915 is below the upper end of the gate dielectric layer 914. As a result, the etched-back conductive layer 915 may become word lines each extending in the word line direction (x-direction), and the portion of the etched-back conductive layer 915 facing the semiconductor body 907 may become a gate electrode. Thereby gate structures may be formed that each include a respective gate dielectric layer 914 and a respective gate electrode (e.g., a portion of conductive layer 915) over gate dielectric layer 914.

In some embodiments, as shown in fig. 9G and 9G', a dielectric layer 916 is formed in the remaining space of the first trench 906 and the indentation created by the etch back of the conductive layer 915, for example by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. It should be appreciated that depending on the pitch of the word lines (e.g., the size of the first trenches 906), air gaps 920 may be formed in the dielectric layer 916.

At operation 1006 in fig. 10, a plurality of spacers are formed. The plurality of spacers extend in a first lateral direction, and each of the spacers extends vertically in an upper portion of the semiconductor layer.

As shown in fig. 9H and 9H', a plurality of parallel grooves 910 having a first depth are formed in the x-direction (e.g., the word line direction), and each groove extends vertically in the semiconductor layer 901 and cuts one semiconductor pillar 903 into two semiconductor bodies 907. In some implementations, for example based on a word line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the recesses 910 perpendicular to the trench isolation 904, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 901 and the trench isolation 904 to etch the recesses in the semiconductor layer 901. Fig. 9H shows a plan view in the x-y plane, and fig. 9H' shows a side view of a section in the y direction (bit line direction).

In some embodiments, as shown in fig. 9I and 9I', a dielectric layer is deposited to fill the recess 910. In some implementations, the second trench isolation 917 is formed in the recess, for example, by depositing a dielectric layer (such as silicon oxide) to fill the recess 910 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof). A planarization process may be performed to remove excess dielectric over the top surface of the semiconductor layer 901. It should be appreciated that an air gap 918 may be formed in the second trench isolation 917 depending on the pitch of the semiconductor body 907 (e.g., the size of the recess).

Fig. 12 illustrates a flow chart of a method 1200 for forming an array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure. At operation 1202 in fig. 12, a plurality of first trenches and a plurality of grooves are formed in a semiconductor layer by using a single etching process. The plurality of first trenches and the plurality of grooves extend in a first lateral direction, and each of the first trenches and the grooves extends vertically in an upper portion of the semiconductor layer. The plurality of first grooves and the plurality of grooves are alternately arranged in the second lateral direction. The semiconductor layer may include a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer.

Fig. 11A and 11A' illustrate a semiconductor layer 1101 including a substrate 1101-1, a first dielectric layer 1101-2 on top of the substrate 1101-1, and a second dielectric layer 1101-3 on top of the first dielectric layer 1101-2. In some embodiments, the first dielectric layer 1101-2 and the second dielectric layer 1101-3 are removed in a subsequent process, allowing the capacitor structure to be effectively connected to the source. Fig. 11A shows a plan view of the semiconductor layer 1101, and fig. 11A' shows a side view of the semiconductor layer 1101. To form the semiconductor layer 1101, silicon oxide and silicon nitride are then deposited onto the silicon substrate 1101-1 using one or more thin film deposition processes, including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the silicon oxide layer 1101-2 is formed by using a top portion of a silicon oxide substrate 1101-1 that is dry oxidized and/or wet oxidized, such as an In Situ Steam Generation (ISSG) oxidation process.

As shown in fig. 11B and 11B', a plurality of parallel trenches are formed in the y-direction (e.g., bit line direction) to form a plurality of parallel semiconductor walls 1105 in the y-direction. In some implementations, for example based on the design of the bit lines, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the trenches and semiconductor walls 1105, and one or more dry etching and/or wet etching processes (such as RIE) are performed to etch the trenches in the semiconductor layer 1101. Thus, the semiconductor wall 1105 extending vertically in the semiconductor layer 1101 can be formed. Since the semiconductor wall 1105 is formed by etching the semiconductor layer 1101, the semiconductor wall 1105 may have the same material as the semiconductor layer 1101. In some implementations, the plurality of parallel trenches are filled by depositing a third dielectric layer (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to form a plurality of parallel trench isolations 1104. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess third dielectric layer deposited beyond the top surface of semiconductor layer 1101. As a result, parallel semiconductor walls 1105 may be separated by trench isolation 1104. Fig. 11B and 11B 'show a plan view in the x-y plane and a side view of a section along the x-direction (word line direction, e.g., along line AA'), respectively.

As shown in fig. 11C and 11C', a plurality of recesses 1110 having a first depth and a plurality of first trenches 1106 having a second depth are formed in an x-direction (e.g., a word line direction) by using a single etching process such as a self-aligned double pattern (SADP) process to form an array of semiconductor bodies 1107, each semiconductor body 1107 extending vertically in the semiconductor layer 1101. Each semiconductor body 1107 extends in a vertical direction (e.g., the z-direction as shown in fig. 11C'). Each semiconductor body 1107 has a first lateral dimension along a first lateral direction (e.g., x-direction) and a second lateral dimension along a second lateral direction (e.g., y-direction). The first lateral dimension and the second lateral dimension of the different semiconductor body 1107 are substantially identical (within a margin of + -10%) along the x-direction and the y-direction, respectively. In some embodiments, the first depth is less than the second depth. In some embodiments, each groove has a third lateral dimension along the second lateral direction (e.g., bit line direction), each first trench has a fourth lateral dimension along the second lateral direction (e.g., bit line direction), and the third lateral dimension is less than the fourth lateral dimension. In some implementations, for example based on a design of the word lines, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the first trenches 1106 and the recesses 1110 perpendicular to the trench isolation 1104, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 1101 and the trench isolation 1104 to etch the first trenches 1106 and the recesses 1110 in the semiconductor layer 1101. As a result, the semiconductor walls 1105 (shown in fig. 11B) may be cut by the first trenches 1106 and the grooves 1110 to form an array of semiconductor bodies 1107, each semiconductor body 1107 extending vertically in the semiconductor layer 1101. Since the semiconductor body 1107 is formed by etching the semiconductor layer 1101, the semiconductor body 1107 may have the same material as the semiconductor layer 1101. Fig. 11C shows a plan view in the x-y plane, and fig. 11C' shows a side view of a section in the y direction (bit line direction).

At operation 1204 in fig. 12, a plurality of spacers are formed. The plurality of spacers extend in a first lateral direction, and each of the spacers extends vertically in an upper portion of the semiconductor layer.

As shown in fig. 11D and 11D', in some embodiments, the sacrificial layer 1108 is formed in each first trench 1106 and each recess 1110, for example, by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to partially fill each first trench 1106 and completely fill each recess 1110. In some embodiments, a dielectric layer 1119 is deposited on the sidewalls of each first trench 1106 to partially fill each first trench 1106. In some embodiments, each recess 1110 is completely filled with a sacrificial layer to form a plurality of spacers 1111. In some embodiments, partially filling the first trench 1106 and completely filling the recess 1110 are performed in a single deposition process. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess sacrificial layer deposited beyond the top surface of semiconductor layer 1101.

At operation 1206 of fig. 12, two disconnected conductive structures are formed in each first trench. The two disconnected conductive structures extend laterally in a first lateral direction and each of the conductive structures extends vertically along one sidewall of a corresponding first trench.

As shown in fig. 11E and 11E', a dielectric layer 1109 is formed in each first trench 1106, for example, by depositing a dielectric (such as silicon oxide) to fill the first trenches 1106 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric layer 1109 deposited beyond the top surface of semiconductor layer 1101.

As shown in fig. 11F and 11F', the dielectric layer 1109 is etched back such that the dielectric layer 1109 covers the bottom surface of each first trench 1106. In some embodiments, a photolithography process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to etch back the dielectric layer 1109, or one or more dry etching and/or wet etching processes (such as RIE) are performed on the dielectric layer 1109 until the etch back reaches a third depth. Fig. 11F shows a plan view in the x-y plane, and fig. 11F' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 11G and 11G', a gate dielectric layer 1114 is formed in each first trench 1106. The gate dielectric layer 1114 may be part of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 1107. In some embodiments, a wet oxidation and/or dry oxidation process, such as an In Situ Steam Generation (ISSG) oxidation, is performed to form a native oxide (e.g., silicon oxide) on the sidewalls of each first trench 1106. One or more conductive layers 1115 are then formed over the gate dielectric layer 1114 in the first trench 1106. In some implementations, the conductive layer 1115 is formed by depositing one or more conductive materials, such as metals and/or metal compounds (e.g., W and TiN), over the gate dielectric layer 1114 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof, to partially fill the first trench 1106. For example, a TiN layer and a W layer may be deposited sequentially to form conductive layer 1115. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of semiconductor layer 1101.

As shown in fig. 11H and 11H', in some embodiments, the conductive layer 1115 is etched back, for example using a punch etch, a dry etch, and/or a wet etch (e.g., RIE), to form two open conductive structures in each first trench 1106. In some embodiments, a bottom punch etch process is performed to etch away some of the metal of the conductive layer 1115 at the bottom of the first trench until the dielectric layer 1109 is exposed. In some implementations, the conductive layer 1115 is etched back to form an indent such that an upper end of the conductive layer 1115 is below the top surface of the semiconductor body 1107. In some embodiments, since gate dielectric layer 1114 is not etched, the upper end of conductive layer 1115 is below the upper end of gate dielectric layer 1114. Thus, the etched back conductive layer 1115 may become word lines each extending in a word line direction (x-direction), and the portion of the etched back conductive layer 1115 facing the semiconductor body 1107 may become a gate electrode. A gate structure may thereby be formed that each includes a respective gate dielectric layer 1114 and a respective gate electrode (e.g., a portion of conductive layer 1115) over gate dielectric layer 1114.

In some embodiments, as shown in fig. 11H and 11H', a dielectric layer 1116 is formed in the remaining space of the first trench 1106 and the indentation resulting from the etch back of the conductive layer 1115, for example by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. It should be appreciated that depending on the pitch of the word lines (e.g., the size of the first trenches 1106), air gaps 1120 may be formed in the dielectric layer 1116.

In some embodiments, as shown in fig. 11I and 11I ', the sacrificial layer in the spacers 1111 (as shown in fig. 11F') is removed to form a second trench, and a dielectric layer is deposited to fill the second trench. In some embodiments, a photolithography process is performed using an etching mask (e.g., a photoresist mask and/or a hard mask) to remove the sacrificial layer inside the spacers 1111, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the spacers 1111 to etch away the sacrificial layer and form the second trenches. For example, second trench isolation 1117 is formed in the second trench by depositing a dielectric layer (such as silicon oxide) to fill the second trench using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. A planarization process may be performed to remove excess dielectric over the top surface of semiconductor layer 1101. It should be appreciated that an air gap 1118 may be formed in the second trench isolation 1117 depending on the pitch of the semiconductor body 1107 (e.g., the size of the second trench).

Fig. 14 illustrates a flow chart of a method 1400 for forming an array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure. At operation 1402 in fig. 14, a plurality of first trenches and a plurality of grooves are formed in a semiconductor layer by using a single etching process. The plurality of first trenches and the plurality of grooves extend in a first lateral direction, and each of the first trenches and the grooves extends vertically in an upper portion of the semiconductor layer. The plurality of first grooves and the plurality of grooves are alternately arranged in the second lateral direction. The semiconductor layer may include a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer.

Fig. 13A and 13A' illustrate a semiconductor layer 1301 that includes a substrate 1301-1, a first dielectric layer 1301-2 on top of the substrate 1301-1, and a second dielectric layer 1301-3 on top of the first dielectric layer 1301-2. In some embodiments, the first and second dielectric layers 1301-2 and 1301-3 are removed in a subsequent process, allowing the capacitor structure to be effectively connected to the source. Fig. 13A shows a plan view of the semiconductor layer 1301, and fig. 13A' shows a side view of the semiconductor layer 1301. To form the semiconductor layer 1301, silicon oxide and silicon nitride are then deposited onto the silicon substrate 1301-1 using one or more thin film deposition processes, including but not limited to Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the silicon oxide layer 1301-2 is formed by using a top portion of the silicon oxide substrate 1301-1 by dry oxidation and/or wet oxidation, such as an In Situ Steam Generation (ISSG) oxidation process.

As shown in fig. 13B and 13B', a plurality of parallel trenches are formed in the y-direction (e.g., bit line direction) to form a plurality of parallel semiconductor walls 1305 in the y-direction. In some implementations, for example based on a bit line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the trenches and semiconductor walls 1305, and one or more dry etching and/or wet etching processes (such as RIE) are performed to etch the trenches in the semiconductor layer 1301. Accordingly, a semiconductor wall 1305 extending vertically in the semiconductor layer 1301 may be formed. Since the semiconductor wall 1305 is formed by etching the semiconductor layer 1301, the semiconductor wall 1305 may have the same material as the semiconductor layer 1301. In some implementations, the plurality of parallel trenches are filled by depositing a third dielectric layer (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to form a plurality of parallel trench isolations 1304. In some embodiments, a planarization process (such as CMP) is performed to remove excess third dielectric layer deposited beyond the top surface of semiconductor layer 1301. As a result, the parallel semiconductor walls 1305 may be separated by trench isolation 1304. Fig. 13B and 13B 'show a plan view in the x-y plane and a side view of a section along the x direction (word line direction, for example, along line AA'), respectively.

As shown in fig. 13C and 13C', a plurality of grooves 1310 having a first depth and a plurality of first trenches 1306 having a second depth are formed in an x-direction (e.g., a word line direction) by using a single etching process such as a self-aligned double pattern (SADP) process to form an array of semiconductor bodies 1307, each semiconductor body 1307 extending vertically in the semiconductor layer 1301. Each semiconductor body 1307 extends in a vertical direction (e.g., a z-direction as shown in fig. 13C'). Each semiconductor body 1307 has a first lateral dimension along a first lateral direction (e.g., x-direction) and a second lateral dimension along a second lateral direction (e.g., y-direction). The first lateral dimension and the second lateral dimension of the different semiconductor bodies 1307 are substantially identical along the x-direction and the y-direction, respectively (the error is within a margin of + -10%). In some embodiments, the first depth is less than the second depth. In some embodiments, each groove has a third lateral dimension along the second lateral direction (e.g., bit line direction), each first trench has a fourth lateral dimension along the second lateral direction (e.g., bit line direction), and the third lateral dimension is less than the fourth lateral dimension. In some implementations, for example based on a word line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the first trenches 1306 and the recesses 1310 perpendicular to the trench isolation 1304, and one or more dry etching and/or wet etching processes (such as RIE) are performed on the semiconductor layer 1301 and the trench isolation 1304 to etch the first trenches 1306 and the recesses 1310 in the semiconductor layer 1301. As a result, the semiconductor walls 1305 (shown in fig. 13B) may be cut by the first trenches 1306 and the grooves 1310 to form an array of semiconductor bodies 1307, each semiconductor body 1307 extending vertically in the semiconductor layer 1301. Since the semiconductor body 1307 is formed by etching the semiconductor layer 1301, the semiconductor body 1307 may have the same material as the semiconductor layer 1301. Fig. 13C shows a plan view in the x-y plane, and fig. 13C' shows a side view of a section in the y direction (bit line direction).

At operation 1404 in fig. 14, a sacrificial layer is formed in each first trench and each recess, an upper portion of the sacrificial layer in each recess is removed, and then a cap layer is formed on top of the remaining portion of the sacrificial layer in each recess.

As shown in fig. 13D and 13D', in some embodiments, the sacrificial layer 1308 is formed in each first trench 1306 and each recess 1310, for example, by depositing a dielectric (such as silicon oxide) to completely fill each first trench 1306 and each recess 1310 using one or more thin film deposition processes (including, but not limited to CVD, PVD, ALD, or any combination thereof). In some implementations, a sacrificial layer 1308 is formed in each first trench 1306 and completely fills each first trench 1306. In some embodiments, each recess 1310 is completely filled with a sacrificial layer 1308 to form a plurality of spacers 1311. In some implementations, completely filling the first trench 1306 and the recess 1310 is performed in a single deposition process. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess sacrificial layer deposited beyond the top surface of semiconductor layer 1301.

As shown in fig. 13E and 13E', a cap layer 1325 is formed in the recess 1310. The sacrificial layer 1308 in the first trench 1306 is protected by depositing a protective layer (such as photoresist or hard mask) while the sacrificial layer 1308 in the upper portion of the recess 1310 is removed. In some embodiments, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to remove sacrificial layer 1308 inside spacer 1311, and one or more dry etching and/or wet etching processes (such as RIE) are performed on spacer 1311 to etch away sacrificial layer 1308 in the upper portion of spacer 1311. Cap layer 1325 is then deposited using a dielectric, such as silicon nitride, to cover and protect the remaining sacrificial layer 1308 in recess 1310 by using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof.

At operation 1406 in fig. 14, the sacrificial layer in each first trench is removed.

As shown in fig. 13F and 13F', the sacrificial layer 1308 in the first trench 1306 is removed. In some embodiments, the sacrificial layer 1308 in the first trench 1306 may be completely removed. To completely remove the sacrificial layer 1308 in the first trench 1306, a photolithography process is performed using an etching mask (e.g., a photoresist mask and/or a hard mask), or one or more dry etching and/or wet etching processes (such as RIE) are performed to etch away the sacrificial layer 1308 in the first trench 1306.

At operation 1408 of fig. 14, two disconnected conductive structures are formed in each first trench. The two disconnected conductive structures extend laterally in a first lateral direction and each of the conductive structures extends vertically along one sidewall of a corresponding first trench.

As shown in fig. 13G and 13G', a dielectric layer 1309 is formed in each first trench 1306, for example by depositing a dielectric (such as silicon oxide) to fill the first trenches 1306 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof). In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric layer 1309 deposited beyond the top surface of semiconductor layer 1301. In some embodiments, a dielectric layer 1319 is deposited on the sidewalls of each first trench 1306 to partially fill each first trench 1306 prior to depositing the dielectric layer 1309.

As shown in fig. 13G and 13G', the dielectric layer 1309 is etched back such that the dielectric layer 1309 covers the bottom surface of each first trench 1306. In some embodiments, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to etch back the dielectric layer 1309, or one or more dry etching and/or wet etching processes (such as RIE) are performed on the dielectric layer 1309 until the etch back reaches a third depth. Fig. 13G shows a plan view in the x-y plane, and fig. 13G' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 13H and 13H', a gate dielectric layer 1314 is formed in each first trench 1306. The gate dielectric layer 1314 may be part of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 1307. In some embodiments, a wet oxidation and/or dry oxidation process, such as an In Situ Steam Generation (ISSG) oxidation, is performed to form a native oxide (e.g., silicon oxide) on the sidewalls of each first trench 1306. One or more conductive layers 1315 are then formed over the gate dielectric layer 1314 in the first trench 1306. In some implementations, the conductive layer 1315 is formed by depositing one or more conductive materials, such as metals and/or metal compounds (e.g., W and TiN), over the gate dielectric layer 1314 to partially fill the first trench 1306 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. For example, a TiN layer and a W layer may be sequentially deposited to form the conductive layer 1315. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the semiconductor layer 1301.

As shown in fig. 13I and 13I', in some embodiments, the conductive layer 1315 is etched back, for example using a punch etch, a dry etch, and/or a wet etch (e.g., RIE), to form two open conductive structures in each first trench 1306. In some embodiments, a bottom punch etch process is performed to etch away some of the metal of the conductive layer 1315 at the bottom of the first trench until the dielectric layer 1309 is exposed. In some embodiments, the conductive layer 1315 is etched back to form an indent such that an upper end of the conductive layer 1315 is below a top surface of the semiconductor body 1307. In some embodiments, since the gate dielectric layer 1314 is not etched, an upper end portion of the conductive layer 1315 is below an upper end portion of the gate dielectric layer 1314. Accordingly, the etched back conductive layer 1315 may become word lines each extending in a word line direction (x-direction), and a portion of the etched back conductive layer 1315 facing the semiconductor body 1307 may become a gate electrode. Gate structures may thus be formed that each include a respective gate dielectric layer 1314 and a respective gate electrode (e.g., a portion of conductive layer 1315) over gate dielectric layer 1314.

In some embodiments, as shown in fig. 13I and 13I', a dielectric layer 1316 is formed in the remaining space of the first trench 1306 and the dent created by the etch back of the conductive layer 1315, for example by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. It should be appreciated that depending on the pitch of the word lines (e.g., the size of the first trenches 1306), air gaps 1320 may be formed in the dielectric layer 1316.

In some embodiments, as shown in fig. 13J and 13J ', cap layer 1325 and sacrificial layer 1308 in spacer 1311 (shown in fig. 13D') are removed to form a second trench, and a dielectric layer is deposited to fill the second trench. In some embodiments, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to remove cap layer 1325 and/or sacrificial layer within spacer 1311, and one or more dry etching and/or wet etching processes (such as RIE) are performed on spacer 1311 to etch away cap layer 1325 and/or sacrificial layer 1308 and form a second trench. For example, second trench isolation 1317 is formed in the second trench by depositing a dielectric layer (such as silicon oxide) to fill the second trench using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. A planarization process may be performed to remove excess dielectric over the top surface of the semiconductor layer 1301. It should be appreciated that the air gap 1318 may be formed in the second trench isolation 1317 depending on the pitch of the semiconductor bodies 1307 (e.g., the size of the second trench).

Fig. 16 illustrates a flow chart of a method 1600 for forming an array of memory cells each including a vertical transistor, in accordance with some aspects of the present disclosure. At operation 1602 in fig. 16, a plurality of recesses are formed in a semiconductor layer using a single etching process. The plurality of grooves extend in a first lateral direction, and each groove extends vertically in an upper portion of the semiconductor layer. The plurality of grooves are arranged in a second transverse direction. The semiconductor layer may include a substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer.

Fig. 15A and 15A' illustrate a semiconductor layer 1501 including a substrate 1501-1, a first dielectric layer 1501-2 on top of the substrate 1501-1, and a second dielectric layer 1501-3 on top of the first dielectric layer 1501-2. In some embodiments, the first and second dielectric layers 1501-2 and 1501-3 are removed in a subsequent process, allowing the capacitor structure to be effectively connected to the source. Fig. 15A shows a plan view of the semiconductor layer 1501, and fig. 15A' shows a side view of the semiconductor layer 1501. To form the semiconductor layer 1501, silicon oxide and silicon nitride are then deposited onto the silicon substrate 1501-1 using one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the silicon oxide layer 1501-2 is formed by using a top portion of the silicon oxide substrate 1501-1 by dry oxidation and/or wet oxidation, such as an In Situ Steam Generation (ISSG) oxidation process.

As shown in fig. 15B and 15B', a plurality of parallel trenches are formed in the y-direction (e.g., bit line direction) to form a plurality of parallel semiconductor walls 1505 in the y-direction. In some implementations, for example based on the design of the bit lines, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern the trenches and semiconductor walls 1505, and one or more dry etching and/or wet etching processes (such as RIE) are performed to etch the trenches in the semiconductor layer 1501. Accordingly, a semiconductor wall 1505 extending vertically in the semiconductor layer 1501 may be formed. Since the semiconductor wall 1505 is formed by etching the semiconductor layer 1501, the semiconductor wall 1505 may have the same material as the semiconductor layer 1501. In some implementations, the plurality of parallel trenches are filled by depositing a third dielectric layer (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to form the plurality of parallel trench isolations 1504. In some embodiments, a planarization process (such as CMP) is performed to remove excess third dielectric layer deposited beyond the top surface of semiconductor layer 1501. As a result, parallel semiconductor walls 1505 may be separated by trench isolation 1504. Fig. 15B and 15B 'show a plan view in the x-y plane and a side view of a section along the x direction (word line direction, for example, along line AA'), respectively.

As shown in fig. 15C and 15C', a plurality of recesses having a first depth and a first lateral dimension are formed in an x-direction (e.g., a word line direction) by using a single etch process, such as a self-aligned double pattern (SADP) process, to form an array of semiconductor bodies 1507, each semiconductor body 1507 extending vertically in the semiconductor layer 1501. Each semiconductor body 1507 extends in a vertical direction (e.g., the z-direction as shown in fig. 15C'). Each semiconductor body 1507 has a first lateral dimension along a first lateral direction (e.g., x-direction) and a second lateral dimension along a second lateral direction (e.g., y-direction). The first lateral dimension and the second lateral dimension of the different semiconductor bodies 1507 are substantially the same along the x-direction and the y-direction, respectively (the error is within a margin of + -10%). In some implementations, for example based on a word line design, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to pattern grooves 1510 perpendicular to trench isolation 1504, and one or more dry etching and/or wet etching processes (such as RIE) are performed on semiconductor layer 1501 and trench isolation 1504 to etch grooves 1510 in semiconductor layer 1501. As a result, the semiconductor walls 1505 (shown in fig. 15B) may be cut by the grooves 1310 to form an array of semiconductor bodies 1507, each semiconductor body 1507 extending vertically in the semiconductor layer 1501. Since the semiconductor body 1507 is formed by etching the semiconductor layer 1501, the semiconductor body 1507 may have the same material as the semiconductor layer 1501. Fig. 15C shows a plan view in the x-y plane, and fig. 15C' shows a side view of a section in the y direction (bit line direction).

At operation 1604 in fig. 16, a sacrificial layer is formed in each groove and a cap layer is formed to alternately protect the sacrificial layer in a first subset of the plurality of grooves having a first parity.

As shown in fig. 15D and 15D', in some embodiments, a sacrificial layer 1508 is formed in each recess 1510, for example, by depositing a dielectric (such as silicon oxide) to completely fill each recess 1510 using one or more thin film deposition processes (including, but not limited to CVD, PVD, ALD, or any combination thereof). In some embodiments, each recess 1510 is completely filled with a sacrificial layer 1508 to form a plurality of spacers 1511. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess sacrificial layer deposited beyond the top surface of semiconductor layer 1501.

As shown in fig. 15E and 15E', cap layers 1525 are formed to alternately cover the sacrificial layers 1508 in a first subset of grooves 1510 having a first parity. In some embodiments, a photolithography process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to remove the sacrificial layer 1508 in an upper portion of the grooves 1510 having the first parity. In some embodiments, one or more dry etching and/or wet etching processes (such as RIE) are performed on the grooves 1510 having the first parity to etch away the sacrificial layer in the upper portion of the spacers 1511. Cap layer 1525 is then deposited using a dielectric, such as silicon nitride, using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof, to cover and protect the remaining sacrificial layer 1508 in recess 1510 having the first parity.

At operation 1606 in fig. 16, the sacrificial layer in the unprotected second subset of the plurality of grooves having the second parity is removed and the unprotected second subset of the plurality of grooves is enlarged during removal of the sacrificial layer.

As shown in fig. 15F and 15F', in some embodiments, the sacrificial layer 1508 in the unprotected second subset of the plurality of grooves 1510 having the second parity is completely removed. To completely remove the sacrificial layer 1508 in the recess 1510 having the second parity, a photolithography process is performed using an etching mask (e.g., a photoresist mask and/or a hard mask), or one or more dry etching and/or wet etching processes (such as RIE) are performed to etch away the sacrificial layer 1508 in the unprotected recess 1510 having the second parity. In some embodiments, during removal of the sacrificial layer 1508, an unprotected second subset of the plurality of grooves 1510 is enlarged and deepened to form a plurality of first trenches 1506 having a second depth and a second lateral dimension.

At operation 1608 of fig. 16, two disconnected conductive structures are formed in each first trench. The two disconnected conductive structures extend laterally in a first lateral direction and each of the conductive structures extends vertically along one sidewall of a corresponding first trench.

As shown in fig. 15G and 15G', a dielectric layer 1509 is formed in each first trench 1506, for example, by depositing a dielectric (such as silicon oxide) to fill the first trenches 1506 using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. In some embodiments, a planarization process (e.g., CMP) is performed to remove excess dielectric layer 1509 deposited beyond the top surface of semiconductor layer 1501. In some embodiments, a dielectric layer 1519 is deposited on the sidewalls of each first trench 1506 to partially fill each first trench 1506 prior to depositing the dielectric layer 1509.

As shown in fig. 15G and 15G', the dielectric layer 1509 is etched back such that the dielectric layer 1509 covers the bottom surface of each first trench 1506. In some embodiments, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to etch back dielectric layer 1509, or one or more dry and/or wet etching processes (such as RIE) are performed on dielectric layer 1509 until the etch back reaches a third depth. Fig. 15G shows a plan view in the x-y plane, and fig. 15G' shows a side view of a section in the y direction (bit line direction).

As shown in fig. 15H and 15H', a gate dielectric layer 1514 is formed in each first trench 1506. The gate dielectric layer 1514 may be part of a continuous dielectric layer formed over the sidewalls of each row of semiconductor bodies 1507. In some embodiments, a wet oxidation and/or dry oxidation process, such as an In Situ Steam Generation (ISSG) oxidation, is performed to form a native oxide (e.g., silicon oxide) on the sidewalls of each first trench 1506. One or more conductive layers 1515 are then formed over the gate dielectric layer 1514 in the first trench 1506. In some implementations, the conductive layer 1515 is formed by depositing one or more conductive materials, such as metals and/or metal compounds (e.g., W and TiN), over the gate dielectric layer 1514 to partially fill the first trenches 1506 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof. For example, a TiN layer and a W layer may be sequentially deposited to form the conductive layer 1515. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the semiconductor layer 1501.

As shown in fig. 15I and 15I', in some embodiments, the conductive layer 1515 is etched back, for example using a punch etch, a dry etch, and/or a wet etch (e.g., RIE), to form two open conductive structures in each first trench 1506. In some embodiments, a bottom punch etch process is performed to etch away some of the metal of the conductive layer 1515 at the bottom of the first trench until the dielectric layer 1509 is exposed. In some embodiments, the conductive layer 1515 is etched back to form an indent such that an upper end of the conductive layer 1515 is below the top surface of the semiconductor body 1507. In some embodiments, since gate dielectric layer 1514 is not etched, the upper end of conductive layer 1515 is below the upper end of gate dielectric layer 1514. As a result, the etched back conductive layer 1515 may become word lines each extending in the word line direction (x-direction), and a portion of the etched back conductive layer 1515 facing the semiconductor body 1507 may become a gate electrode. Thereby gate structures may be formed that each include a respective gate dielectric layer 1514 and a respective gate electrode (e.g., a portion of conductive layer 1515) over gate dielectric layer 1514.

In some embodiments, as shown in fig. 15I and 15I', a dielectric layer 1516 is formed in the remaining space of the first trench 1506 and the recess resulting from the etch back of the conductive layer 1515, for example by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes including, but not limited to CVD, PVD, ALD or any combination thereof. It should be appreciated that depending on the pitch of the word lines (e.g., the size of the first trenches 1506), air gaps 1520 may be formed in the dielectric layer 1516.

In some embodiments, as shown in fig. 15J and 15J ', cap layer 1525 and sacrificial layer in spacer 1511 are removed (as shown in fig. 15D') to form a second trench, and a dielectric layer is deposited to fill the second trench. In some embodiments, a photolithographic process is performed using an etch mask (e.g., a photoresist mask and/or a hard mask) to remove cap layer 1525 and/or a sacrificial layer within spacer 1511, and one or more dry etching and/or wet etching processes (such as RIE) are performed on spacer 1511 to etch away cap layer 1525 and/or sacrificial layer and form a second trench. For example, a second trench isolation 1517 is formed in the second trench by depositing a dielectric layer (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD or any combination thereof) to fill the second trench. A planarization process may be performed to remove excess dielectric over the top surface of semiconductor layer 1501. It should be appreciated that an air gap 1518 may be formed in the second trench isolation 1517 depending on the pitch of the semiconductor body 1507 (e.g., the size of the second trench).

Fig. 17 illustrates a block diagram of a system 1700 with a memory device in accordance with some aspects of the disclosure. The system 1700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other suitable electronic device having a memory bank therein. As shown in fig. 17, the system 1700 may include a host 1708 and a memory system 1702 having one or more memory devices 1704 and a memory controller 1706. The host 1708 may be a processor of an electronic device, such as a Central Processing Unit (CPU), or a system on a chip (SoC), such as an Application Processor (AP). The host 1708 may be configured to send data to the memory device 1704 or to receive data from the memory device 1704.

Memory device 1704 may be any memory device disclosed herein, such as 3D memory devices 100 and 200. In some implementations, the memory device 1704 includes an array of memory cells, each including a vertical transistor, as described in detail above.

According to some implementations, a memory controller 1706 is coupled to the memory device 1704 and the host 1708 and is configured to control the memory device 1704. The memory controller 1706 may manage data stored in the memory device 1704 and communicate with the host 1708. The memory controller 1706 may be configured to control operations of the memory device 1704, such as read, write, and refresh operations. The memory controller 1706 may also be configured to manage various functions related to storing or to be stored data in the memory device 1704, including, but not limited to, refresh and timing control, command/request conversion, buffering and scheduling, and power management. In some implementations, the memory controller 1706 is also configured to determine a maximum memory capacity that the computer system can use, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters. Any other suitable function may also be performed by the memory controller 1706. The memory controller 1706 may communicate with external devices (e.g., host 1708) according to a particular communication protocol. For example, the memory controller 1706 may communicate with external devices via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a firewire protocol, and the like.

The foregoing description of specific embodiments may be readily modified and/or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising:

an array of vertical transistors, each vertical transistor comprising a semiconductor body extending in a vertical direction, and a gate structure positioned adjacent to a sidewall of the semiconductor body, wherein:

the gate structures of each row of vertical transistors are connected to each other and extend in a first lateral direction to form a word line;

a first word line of a first row of vertical transistors is located on a first side of the semiconductor body of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and is also provided with

A second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located on a second side of the semiconductor body of the second row of vertical transistors along the second lateral direction.

2. The semiconductor device according to claim 1, further comprising:

an isolation structure extending in the first lateral direction and separating the first word line from the second word line.

3. The semiconductor device according to claim 1, wherein:

a third word line of a third row of vertical transistors adjacent to the second row of vertical transistors is separated from the second word line by the second row of vertical transistors and the semiconductor body of the third row of vertical transistors.

4. The semiconductor device according to claim 3, wherein:

the semiconductor bodies of the second row of vertical transistors are separated from the semiconductor bodies of the third row of vertical transistors by spacers extending in the first lateral direction.

5. The semiconductor device of claim 2, wherein the gate structure comprises a gate electrode and a gate dielectric between the gate electrode and a corresponding semiconductor body.

6. The semiconductor device of claim 2, wherein adjacent two gate electrodes are separated by the isolation structure.

7. The semiconductor device of claim 2, wherein each vertical transistor further comprises a source and a drain respectively disposed at both ends of the corresponding semiconductor body.

8. The semiconductor device of claim 2, wherein the isolation structure comprises an air gap.

9. The semiconductor device of claim 4, wherein the spacer comprises an air gap.

10. The semiconductor device according to claim 5, wherein the gate electrode comprises a first gate electrode layer and a second gate electrode layer.

11. The semiconductor device of claim 1, wherein two adjacent rows of vertical transistors comprise one of a common source or a common drain.

12. A method for forming a semiconductor device, comprising:

forming a plurality of spacers extending in a first lateral direction, each spacer extending vertically in an upper portion of the semiconductor layer;

forming a plurality of first trenches extending in the first lateral direction, each first trench extending vertically in the upper portion of the semiconductor layer and being sandwiched by two adjacent spacers in a second lateral direction; and

two disconnected conductive structures are formed in each first trench, the two disconnected conductive structures extending laterally along the first lateral direction, each conductive structure extending vertically along one sidewall of the corresponding first trench.

13. The method of claim 12, wherein forming the plurality of spacers comprises forming each spacer having a first lateral dimension along the second lateral direction, and forming the plurality of first trenches comprises forming each first trench having a second lateral dimension along the second lateral direction, the first lateral dimension being smaller than the second lateral dimension.

14. The method of claim 13, wherein forming the plurality of spacers comprises forming each spacer having a first depth in a vertical direction, and forming the plurality of first trenches comprises forming each first trench having a second depth in the vertical direction, the first depth being less than the second depth.

15. The method of claim 14, further comprising:

a plurality of second trenches extending laterally along the second lateral direction, the second lateral direction being perpendicular to the first lateral direction, are formed in the upper portion of the semiconductor layer prior to forming the plurality of first trenches.

16. The method of claim 15, wherein forming the plurality of spacers comprises:

forming a plurality of grooves extending laterally along the first lateral direction, each groove extending vertically to divide the upper portion of the semiconductor layer into a plurality of semiconductor pillars; and

The plurality of recesses are filled by depositing a sacrificial layer.

17. The method of claim 16, wherein forming the plurality of first trenches comprises:

the plurality of first trenches extending laterally along the first lateral direction are formed, wherein each first trench extends vertically between two adjacent spacers and divides each semiconductor pillar into two semiconductor bodies.

18. The method of claim 15, wherein forming the two disconnected conductive structures in each first trench comprises:

forming a continuous conductive structure within each first trench covering sidewalls of each first trench; and

a portion of the bottom of the continuous conductive structure is removed to separate the continuous conductive structure into the two disconnected conductive structures in each first trench.

19. The method of claim 18, wherein prior to forming the continuous conductive structure in each first trench, the method comprises forming a gate dielectric layer by oxidizing sidewalls of each first trench, wherein the gate dielectric layer and the corresponding disconnected conductive structure form a gate structure.

20. The method of claim 19, wherein forming the plurality of first trenches further comprises:

Depositing an initial dielectric structure in the plurality of first trenches; and

an upper portion of the initial dielectric structure is removed until a third depth is reached in each first trench to form a bottom dielectric structure in a lower portion of the first trench, the third depth being less than the second depth and greater than the first depth.

21. The method of claim 20, wherein forming the continuous conductive structure in each first trench comprises:

forming a first conductive layer to cover the gate dielectric layer and the bottom dielectric structure; and

a second conductive layer is formed to cover the first conductive layer.

22. The method of claim 18, wherein removing portions of the bottom of the continuous conductive structure in each first trench comprises: a punch etch or dry etch process is used to etch through the bottom of the continuous conductive structure.

23. The method of claim 18, further comprising forming isolation structures extending in the first lateral direction between the disconnected conductive structures in each first trench.

24. The method of claim 23, wherein forming the isolation structure comprises forming an air gap embedded in the isolation structure.

25. A method for forming an array of memory cells, comprising:

forming a plurality of first trenches extending in a first lateral direction, each first trench extending vertically in an upper portion of the semiconductor layer;

forming a plurality of spacers extending in the first lateral direction, each spacer extending vertically in the upper portion of the semiconductor layer and sandwiched by two adjacent first trenches in a second lateral direction; and

26. The method of claim 25, wherein forming the plurality of spacers comprises forming each spacer having a first lateral dimension along the second lateral direction, and forming the plurality of first trenches comprises forming each first trench having a second lateral dimension along the second lateral direction, the first lateral dimension being smaller than the second lateral dimension.

27. The method of claim 26, wherein forming the plurality of spacers comprises forming each spacer having a first depth in a vertical direction, and forming the plurality of first trenches comprises forming each first trench having a second depth in the vertical direction, the first depth being less than the second depth.

28. The method of claim 27, further comprising:

a plurality of second trenches extending laterally along the second lateral direction, the second lateral direction being perpendicular to the first lateral direction, are formed in the upper portion of the semiconductor layer prior to forming the plurality of first trenches, wherein the plurality of first trenches and the plurality of second trenches separate the upper portion of the semiconductor layer into a plurality of semiconductor pillars.

29. The method of claim 28, wherein forming the plurality of spacers comprises:

forming a plurality of grooves extending laterally along the first lateral direction, wherein each groove extends vertically along the vertical direction and divides each semiconductor pillar into two semiconductor bodies; and

the plurality of grooves are filled by depositing a filling layer.

30. The method of claim 28, wherein forming the two disconnected conductive structures in each first trench comprises:

forming a continuous conductive structure in each first trench covering sidewalls of each first trench; and

a portion of the bottom of the continuous conductive structure is removed to separate the continuous conductive structure into the two disconnected conductive structures.

31. The method of claim 30, wherein prior to forming the continuous conductive structure in each first trench, the method comprises forming a gate dielectric layer by oxidizing sidewalls of each first trench, wherein the gate dielectric layer and the corresponding disconnected conductive structure form a gate structure.

32. The method of claim 31, wherein forming the plurality of spacers comprises: forming a plurality of grooves, each groove extending vertically between two adjacent gate structures and parallel to the first trench; and

the plurality of recesses are filled by depositing a fill layer to form the plurality of spacers.

33. The method of claim 31, wherein forming the plurality of first trenches further comprises:

an upper portion of the initial dielectric structure is removed until a third depth is reached in each first trench to form a bottom dielectric structure in a lower portion of the first trench, the third depth being less than the first depth and greater than the second depth.

34. The method of claim 33, wherein forming the continuous conductive structure in each first trench comprises:

a second conductive layer is formed to cover the first conductive layer.

35. The method of claim 30, wherein removing the portion of the bottom of the continuous conductive structure in each first trench comprises: a punch etch or dry etch process is used to etch through the bottom of the continuous conductive structure.

36. The method of claim 30, further comprising forming isolation structures extending in the first lateral direction between the disconnected conductive structures in each first trench.

37. The method of claim 36, wherein forming the isolation structure comprises forming an air gap embedded in the isolation structure.

38. A method for forming a semiconductor device, comprising:

forming a plurality of spacers and a plurality of first trenches in an upper portion of the semiconductor layer, each spacer and each first trench extending laterally in a first lateral direction, wherein the plurality of first trenches and the plurality of spacers are alternately arranged in a second lateral direction;

forming a gate dielectric layer in each first trench by oxidizing sidewalls of each first trench;

Forming two disconnected conductive structures in each first trench, each of the two disconnected conductive structures extending laterally along the first lateral direction and vertically covering the gate dielectric layer on one sidewall of the corresponding first trench, respectively; and

the plurality of spacers are removed to form a plurality of second trenches.

39. The method of claim 38, wherein forming the plurality of spacers comprises forming each spacer having a first lateral dimension along the second lateral direction, and wherein forming the plurality of first trenches comprises forming each first trench having a second lateral dimension along the second lateral direction, the first lateral dimension being smaller than the second lateral dimension.

40. The method of claim 39, wherein forming the plurality of spacers comprises forming each spacer having a first depth in a vertical direction, and forming the plurality of first trenches comprises forming each first trench having a second depth in the vertical direction, the first depth being less than the second depth.

41. The method of claim 40, further comprising:

before the plurality of first trenches are formed, a plurality of second trenches extending laterally in the second lateral direction and arranged in parallel in the first lateral direction are formed, each second trench extending vertically in the vertical direction, the second lateral direction being perpendicular to the first lateral direction.

42. The method of claim 41, wherein forming the plurality of spacers comprises:

forming a plurality of grooves extending laterally along the first lateral direction and arranged in parallel along the second lateral direction, each groove extending vertically along the vertical direction to separate the upper portion of the semiconductor layer into a plurality of semiconductor bodies; and

the plurality of grooves are filled by depositing a filling layer.

43. The method of claim 41, wherein forming the two disconnected conductive structures in each first trench comprises:

44. The method of claim 43 wherein prior to forming the continuous conductive structure in each first trench, the method comprises forming the gate dielectric layer by oxidizing sidewalls of each first trench.

45. The method of claim 44, wherein forming the plurality of first trenches further comprises:

46. The method of claim 45 wherein forming the continuous conductive structure in each first trench comprises:

a second conductive layer is formed to cover the first conductive layer.

47. The method of claim 43, wherein removing the portion of the bottom of the continuous conductive structure in each first trench comprises etching through the bottom of the continuous conductive structure using a punch etch or a dry etch process.

48. The method of claim 42, further comprising forming isolation structures extending in the first lateral direction between the disconnected conductive structures in each first trench.

49. The method of claim 48, wherein forming the isolation structure comprises forming an air gap embedded in the isolation structure.