CN116745847A

CN116745847A - Ferroelectric memory, control method thereof and electronic equipment

Info

Publication number: CN116745847A
Application number: CN202180086911.9A
Authority: CN
Inventors: 景蔚亮; 吕杭炳; 殷士辉; 方亦陈; 卜思童; 黄凯亮; 刘晓真; 徐亮; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-21
Filing date: 2021-05-21
Publication date: 2023-09-12
Also published as: WO2022241796A1

Abstract

The embodiment of the application provides a ferroelectric memory, a control method thereof and electronic equipment comprising the ferroelectric memory. The method is mainly used for improving the storage density of the ferroelectric memory. The ferroelectric memory includes: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a first transistor, a second transistor, and a floating gate, and a first ferroelectric capacitor; the floating gate extends along the direction perpendicular to the substrate, and the first transistor and the second transistor are arranged along the extending direction of the floating gate and are positioned at two opposite ends of the floating gate, and the first transistor and the second transistor are electrically connected with the floating gate, that is, the first transistor is electrically connected with the second transistor through the floating gate; the first ferroelectric capacitor is arranged at the periphery of the floating gate and is electrically connected with the floating gate. In this way, by arranging the floating gate vertically to the substrate, the area occupied by each memory cell on the substrate can be reduced, and the memory density can be further improved.

Description

Ferroelectric memory, control method thereof and electronic equipment

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a ferroelectric memory, a control method thereof, and an electronic device including the ferroelectric memory.

Background

Ferroelectric memory is a new type of memory, and is being used more and more widely than traditional dynamic random access memory (dynamic random access memory, DRAM) because of the advantages of non-volatility, high speed, low power consumption, etc. The existing ferroelectric memories mainly include ferroelectric random access memories (ferroelectric random access memory, feRAM) and ferroelectric field effect transistor (FeFET) memories.

As shown in fig. 1a, a circuit diagram of a FeRAM is schematically shown, which comprises a memory array of 4 memory cells, each of which comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and a ferroelectric capacitor connected to the MOSFET. For each memory cell, its MOSFET has a first terminal connected to a Bit Line (BL), a second terminal connected to a Source Line (SL) through a ferroelectric capacitor, and a control terminal connected to a Word Line (WL).

As shown in fig. 1b, a circuit diagram of a FeFET memory is shown, again showing a memory array comprising 4 memory cells. Unlike fig. 1a, the control terminal of each MOSFET in the FeFET memory is connected via a ferroelectric capacitor and WL, the first terminal is connected to the source line SL, and the second terminal is connected to the bit line BL.

Because the capacitors in the FeRAM and the FeFET memories are ferroelectric capacitors, compared with the dielectric material of the DRAM, the nonvolatile property of the ferroelectric material can obviously reduce the power consumption caused by the memory refresh. However, both the FeRAM shown in fig. 1a and the FeFET memory shown in fig. 1b have lower memory densities, thereby affecting the improvement of the memory capacity.

Disclosure of Invention

The application provides a ferroelectric memory, a control method thereof and electronic equipment comprising the ferroelectric memory, and mainly aims to provide the ferroelectric memory which can improve the storage density and the storage capacity.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

in a first aspect, the present application provides a ferroelectric memory comprising: a substrate and a plurality of memory cells formed on the substrate, each memory cell including a first transistor, a second transistor, and a floating gate, and a first ferroelectric capacitor; the floating gate extends along a direction perpendicular to the substrate, for example, a gate of the first transistor or the second transistor can be used as the floating gate, and the first transistor and the second transistor are arranged along an extending direction of the floating gate and are positioned at two opposite ends of the floating gate, and the first transistor and the second transistor are electrically connected with the floating gate, that is, the first transistor is electrically connected with the second transistor through the floating gate; the first ferroelectric capacitor is arranged at the periphery of the floating gate and is electrically connected with the floating gate.

In the memory cell of the ferroelectric memory provided by the application, the floating gate is arranged along the direction vertical to the substrate instead of the direction parallel to the substrate, the first transistor and the second transistor are respectively arranged at two opposite ends of the floating gate, and the first ferroelectric capacitor is arranged at the periphery of the floating gate and is positioned in the region between the position of the first transistor and the position of the second transistor in terms of space position. That is, the whole memory cell is arranged along the direction perpendicular to the substrate, and the area occupied by the memory cell on the substrate is smaller, so that more memory cells can be integrated on the unit area of the substrate to improve the memory density, and finally, the memory capacity of the ferroelectric memory is improved.

In a possible implementation manner of the first aspect, the ferroelectric memory further includes a first word line layer, and the first word line layer is located in a first plane parallel to the substrate; a plurality of first ferroelectric capacitors located in a first plane are interconnected by a first word line layer.

That is, the word line is shared by a plurality of ferroelectric capacitors in a plane parallel to the substrate, and in the present application, a word line layer (WL plate) parallel to the substrate is formed to electrically connect the plurality of ferroelectric capacitors. In this way, the number of word lines can be reduced, so that the phenomenon that more word lines occupy a larger space is avoided, and further, the storage density of the memory can be further improved by the word line layer (WL plate) structure provided by the application.

In a possible implementation manner of the first aspect, the first ferroelectric capacitor includes a ferroelectric film layer surrounding a portion of the floating gate; the first word line layer covers the plurality of ferroelectric film layers located in the first plane.

In this way, the word line layer (WL plate) is wrapped around the ferroelectric film layer, so that the word line layer is electrically connected to the plurality of ferroelectric capacitors.

In a possible implementation manner of the first aspect, each memory cell further includes a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor are arranged at intervals along an extending direction of the floating gate; the ferroelectric memory further comprises a second word line layer, wherein the second word line layer is positioned in a second plane, and the second plane is parallel to the first plane; a plurality of second ferroelectric capacitors located in a second plane are interconnected by said second word line layer.

That is, when each memory cell includes a plurality of ferroelectric capacitors, a plurality of word line layers parallel to each other may be provided, each of the word line layers being electrically connected to the plurality of ferroelectric capacitors located in the plane thereof. Therefore, each memory cell can store multi-bit data, and data reading and writing of a certain bit in the memory cell can be realized through selection of the ferroelectric capacitor.

In a possible implementation manner of the first aspect, the ferroelectric memory further includes a source line layer, where the source line layer is located in a third plane parallel to the substrate; first ends of the plurality of second transistors located in the third plane are interconnected by the source line layer.

It will be appreciated that the first ends of the second transistors lying in the same plane may share a source line, i.e. the first ends of the plurality of second transistors are electrically connected to each other, an alternative embodiment of the application is to provide a source line layer (SL plate) through which the plurality of second transistors lying in the same plane are electrically connected.

In a possible implementation manner of the first aspect, the ferroelectric memory further includes: precharge lines, write bit lines, read bit lines, and source lines, and word lines; the control end of the first transistor is electrically connected with the pre-charge line, the first end of the first transistor is electrically connected with the floating gate, and the second end of the first transistor is electrically connected with the write bit line; the control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with the source line, the second end of the second transistor is electrically connected with the read bit line, the first end of the first ferroelectric capacitor is electrically connected with the floating gate, and the second end of the first ferroelectric capacitor is electrically connected with the word line.

The ferroelectric memory according to the present application has a precharge line and a write bit line controlling the first transistor, a source line and a read bit line controlling the second transistor, and whether or not the polarization state of the ferroelectric capacitor is changed depends on the voltage difference between the write bit line WBL and the word line WL.

In a possible implementation manner of the first aspect, the write bit line extends along a first direction parallel to the substrate, the precharge line extends along a second direction parallel to the substrate, and the first direction is perpendicular to the second direction; the second ends of the first transistors in the plurality of memory cells arranged along the first direction are electrically connected with the write bit line, and the control ends of the first transistors in the plurality of memory cells arranged along the second direction are electrically connected with the precharge line.

The precharge line is extended along the second direction, and then the control ends of the first transistors of the memory cells in the second direction are electrically connected, and similarly, the write bit line is extended along the first direction, so that the second ends of the first transistors of the memory cells in the first direction are electrically connected, and the number of the precharge lines and the write bit lines can be reduced, and the storage density is improved.

In a possible implementation manner of the first aspect, the read bit line extends along a first direction parallel to the substrate; the second ends of the second transistors in the plurality of memory cells arranged along the first direction are electrically connected with the read bit line.

As the arrangement mode of the pre-charge line and the write bit line is the same, the read bit line extends along the first direction, so that the second ends of the second transistors of the memory cells positioned in the first direction are electrically connected, the number of the read bit lines can be reduced, and the memory density is improved.

In a possible implementation manner of the first aspect, the first transistor, the second transistor, the floating gate, and the first ferroelectric capacitor are all fabricated by using a subsequent process.

When the first transistor, the second transistor, the floating gate and the first ferroelectric capacitor are all manufactured by adopting a back-pass process, the control circuit is manufactured by adopting a front-pass process. The control circuitry may include one or more of decoders, drivers, timing controllers, buffers, or input-output drivers, as well as other functional circuitry. The control circuit can control signal lines, namely source lines, word lines, precharge lines, write bit lines, read bit lines and the like in the embodiment of the application. After the front end of line FEOL is completed, the interconnect lines, as well as the memory array, are fabricated by the back end of line BEOL. The memory array herein, as previously described, includes ferroelectric capacitors and transistors in the memory cells, as well as portions of the signal lines. The interconnect line includes both an interconnect line connecting devices in the control circuit and other portions of the signal line. The transistors in the memory array are manufactured through a subsequent process, so that the circuit density in the unit area is higher, and the performance of the unit area is improved.

In a possible implementation manner of the first aspect, each storage unit further includes: a second ferroelectric capacitor and a second word line; the first end of the second ferroelectric capacitor is electrically connected with the floating gate, and the second end of the second ferroelectric capacitor is electrically connected with the second word line.

In a possible implementation manner of the first aspect, the ferroelectric memory includes a first memory array and a second memory array arranged along a first direction, and each of the first memory array and the second memory array includes a plurality of memory cells; the word lines of the first memory array extending in the first direction are disconnected from the word lines of the second memory array extending in the first direction; the write bit lines of the first memory array extending in the first direction are connected with the write bit lines of the second memory array extending in the first direction; the read bit lines of the first memory array extending along the first direction are connected with the read bit lines of the second memory array extending along the first direction; the ferroelectric memory further includes: a third transistor, a multiplexer control line, and a global read bit line; the control end of the third transistor is electrically connected with the control line of the multiplexer, the first end of the third transistor is electrically connected with the global read bit line, and the second end of the third transistor is electrically connected with the read bit line connected with the first memory array and the second memory array.

That is, when there are a plurality of memory arrays and the word lines are not connected, the memory array to be read and written can be selected using the third transistor when the read bit line and the write bit line are electrically connected.

In a possible implementation manner of the first aspect, the ferroelectric memory includes a first memory array and a second memory array arranged along a first direction, and each of the first memory array and the second memory array includes the plurality of memory cells; the word lines of the first memory array extending along the first direction are connected with the word lines of the second memory array extending along the first direction; the write bit lines of the first memory array extending in the first direction are disconnected from the write bit lines of the second memory array extending in the first direction; the read bit lines of the first memory array extending along the first direction are disconnected from the read bit lines of the second memory array extending along the first direction; the ferroelectric memory further includes: a third transistor, a fourth transistor, a multiplexer control line and a global read bit line, and a global write bit line; the control end of the third transistor is electrically connected with the control line of the multiplexer, the first end of the third transistor is electrically connected with the global read bit line, the second end of the third transistor is electrically connected with the read bit line in the first memory array, the control end of the fourth transistor is electrically connected with the control line of the multiplexer, the first end of the fourth transistor is electrically connected with the global write bit line, and the second end of the fourth transistor is electrically connected with the write bit line in the first memory array.

In this way, when there are a plurality of memory arrays and the word lines are connected, and neither the read bit line nor the write bit line is electrically connected, the memory array to be read or written can be selected using the third transistor and the fourth transistor that are matched.

In a possible implementation manner of the first aspect, during a writing phase, the precharge line is configured to receive a first precharge control signal, so that the first transistor is turned on, the write bit line is configured to receive a first write bit line control signal, the word line is configured to receive a first word line control signal, and a voltage difference between the first word line control signal and the first write bit line control signal causes a positive polarization or a negative polarization of a ferroelectric film layer of the first ferroelectric capacitor to write different logic information in the first ferroelectric capacitor.

For example, a logic signal "0" is written when the ferroelectric film layer is positively polarized, and for example, a logic signal "1" is written when the ferroelectric film layer is negatively polarized.

In a possible implementation manner of the first aspect, if the read data is "0", in the first reading stage, the precharge line is configured to receive a first precharge control signal, so that the first transistor is turned on, the write bit line is configured to receive a second write bit line control signal, the word line is configured to receive a second word line control signal, and a voltage difference between the second word line control signal and the second write bit line control signal is configured to make the ferroelectric film layer of the first ferroelectric capacitor in a half-selected state, and the polarity of the ferroelectric film layer is not inverted, that is, the polarization state is kept unchanged; in a second reading stage, the precharge line is used for receiving a second precharge control signal so that the first transistor is disconnected, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal with smaller voltage than that of the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line enables the first ferroelectric capacitor to be turned from positive polarization to negative polarization, so that the voltage of the floating gate control signal on the floating gate is reduced, and the second transistor is disconnected; in the third reading stage, the precharge line is used for receiving a first precharge control signal, so that the first transistor is conducted, the write bit line is used for receiving a first write bit line control signal, the word line is used for receiving a first word line control signal, and the voltage difference of the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate positive polarization. And is read as "0" according to the read bit line potential signal.

In a possible implementation manner of the first aspect, if the read data is "1", in the first reading stage, the precharge line is configured to receive a first precharge control signal, so that the first transistor is turned on, the write bit line is configured to receive a second write bit line control signal, the word line is configured to receive a second word line control signal, a voltage difference between the second word line control signal and the second write bit line control signal is configured to enable the ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, the polarity of the ferroelectric film layer is not turned over, and the polarization state is kept unchanged; in the second reading stage, the precharge line is used for receiving a second precharge control signal so that the first transistor is disconnected, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal with smaller voltage than the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line keeps the negative polarity state of the first ferroelectric capacitor unchanged, the voltage of the floating gate control signal on the floating gate is unchanged, and the second transistor is turned on; in the third reading stage, the precharge line is used for receiving a first precharge control signal, so that the first transistor is conducted, the write bit line is used for receiving a first write bit line control signal, the word line is used for receiving a first word line control signal, and the voltage difference of the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate negative polarization. And is read as "1" according to the read bit line potential signal.

In a possible implementation manner of the first aspect, in the standby stage, the write bit line is configured to receive the first write bit line control signal, the word line is configured to receive the first word line control signal, and a voltage difference between the first word line control signal and the first write bit line control signal makes a polarity of the ferroelectric film layer of the first ferroelectric capacitor not flip, and a polarization state remains unchanged. The first transistor and the second transistor are both off.

In a possible implementation manner of the first aspect, in a writing phase, a first reading phase, a third reading phase and a standby phase; the source line is used for receiving a source line control signal, the read bit line is used for receiving a second read bit line control signal, and the voltage values of the source line control signal and the second read bit line control signal are equal. Thus, leakage current can be reduced, and power consumption can be reduced.

In a possible implementation manner of the first aspect, the ferroelectric memory further includes a controller, where the controller is configured to: outputting a precharge control signal to control a voltage on the precharge line; outputting a write bit line control signal to control a voltage on the write bit line; outputting a word line control signal to control a voltage on the word line; outputting a source line control signal to control a voltage on the source line; and outputting a read bit line control signal to control a voltage on the read bit line.

In a possible implementation manner of the first aspect, the ferroelectric memory further includes: precharge lines, word lines, bit lines, and source lines; the control end of the first transistor is electrically connected with the bit line, the first end of the first transistor is electrically connected with the floating gate, and the second end of the first transistor is electrically connected with the precharge line; the control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the bit line; the first end of the first ferroelectric capacitor is electrically connected with the floating gate, and the second end of the first ferroelectric capacitor is electrically connected with the word line.

The precharge line and the bit line control the first transistor, the source line and the bit line control the second transistor, and whether the polarization state of the ferroelectric capacitor is changed depends on the voltage difference of the precharge line and the word line.

In a possible implementation manner of the first aspect, the bit line includes a first portion of the bit line disposed near the first transistor, and a second portion of the bit line near the second transistor, the first portion of the bit line and the second portion of the bit line each extend along a first direction parallel to the substrate, and the first portion of the bit line and the second portion of the bit line are electrically connected through the conductive channel; the control ends of the first transistors in the memory cells arranged along the first direction are electrically connected with a first part of bit lines; first ends of second transistors in the plurality of memory cells arranged along the first direction are electrically connected to the second part of bit lines.

In a possible implementation manner of the first aspect, the precharge line extends along a second direction parallel to the substrate, and the first direction is perpendicular to the second direction; the second terminals of the first transistors in the plurality of memory cells arranged in the second direction are electrically connected to the precharge line.

The precharge lines extend along the second direction, and are electrically connected with the second ends of the first transistors of the memory cells in the second direction, so that the number of precharge lines can be reduced, and the memory density can be improved.

In a second aspect, the present application also provides a ferroelectric memory comprising: precharge line, write bit line, read bit line, source line, and word line; and a plurality of memory cells, each memory cell comprising: the memory cell comprises a first transistor, a second transistor, a floating gate and a first ferroelectric capacitor, wherein the control end of the first transistor is electrically connected with a pre-charge line, the first end of the first transistor is electrically connected with the floating gate, the second end of the first transistor is electrically connected with a write bit line, the first end of the first ferroelectric capacitor is electrically connected with the floating gate, the second end of the first ferroelectric capacitor is electrically connected with a word line, the control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with a source line, and the second end of the second transistor is electrically connected with a read bit line.

In the ferroelectric memory provided by the application, the precharge line and the write bit line control the first transistor, the source line and the read bit line control the second transistor, and whether the polarization state of the ferroelectric capacitor is changed depends on the voltage difference of the write bit line WBL and the word line WL.

In a possible implementation manner of the second aspect, the write bit line extends along a first direction, the precharge line extends along a second direction, and the first direction is perpendicular to the second direction; the second ends of the first transistors in the memory cells arranged along the first direction are electrically connected with the write bit line; the control terminals of the first transistors in the plurality of memory cells arranged in the second direction are electrically connected to the precharge line.

In a possible implementation manner of the second aspect, the read bit line extends along the first direction; the second ends of the second transistors in the plurality of memory cells arranged along the first direction are electrically connected with the read bit line.

In a possible implementation manner of the second aspect, the first transistor, the second transistor, the floating gate, and the first ferroelectric capacitor are all fabricated by using a subsequent process.

In a possible implementation manner of the second aspect, during a writing phase, the precharge line is configured to receive a first precharge control signal, so that the first transistor is turned on, the write bit line is configured to receive a first write bit line control signal, the word line is configured to receive a first word line control signal, and a voltage difference between the first word line control signal and the first write bit line control signal causes a positive polarization or a negative polarization of a ferroelectric film layer of the first ferroelectric capacitor to write different logic information in the first ferroelectric capacitor.

In a possible implementation manner of the second aspect, if the read data is "0", in the first reading stage, the precharge line is configured to receive a first precharge control signal, so that the first transistor is turned on, the write bit line is configured to receive a second write bit line control signal, the word line is configured to receive a second word line control signal, and a voltage difference between the second word line control signal and the second write bit line control signal is configured to enable the ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, and polarity of the ferroelectric film layer is not inverted, that is, a polarization state is kept unchanged; in a second reading stage, the precharge line is used for receiving a second precharge control signal so that the first transistor is disconnected, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal with smaller voltage than that of the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line enables the first ferroelectric capacitor to be turned from positive polarization to negative polarization, so that the voltage of the floating gate control signal on the floating gate is reduced, and the second transistor is disconnected; in the third reading stage, the precharge line is used for receiving a first precharge control signal, so that the first transistor is conducted, the write bit line is used for receiving a first write bit line control signal, the word line is used for receiving a first word line control signal, and the voltage difference of the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate positive polarization. And is read as "0" according to the read bit line potential signal.

In a possible implementation manner of the second aspect, if the read data is "1", in the first reading stage, the precharge line is configured to receive a first precharge control signal, so that the first transistor is turned on, the write bit line is configured to receive a second write bit line control signal, the word line is configured to receive a second word line control signal, and a voltage difference between the second word line control signal and the second write bit line control signal is configured to enable the ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, the polarity of the ferroelectric film layer is not turned over, and the polarization state is kept unchanged; in the second reading stage, the precharge line is used for receiving a second precharge control signal so that the first transistor is disconnected, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal with smaller voltage than the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line keeps the negative polarity state of the first ferroelectric capacitor unchanged, the voltage of the floating gate control signal on the floating gate is unchanged, and the second transistor is turned on; in the third reading stage, the precharge line is used for receiving a first precharge control signal, so that the first transistor is conducted, the write bit line is used for receiving a first write bit line control signal, the word line is used for receiving a first word line control signal, and the voltage difference of the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate negative polarization. And is read as "1" according to the read bit line potential signal.

In a possible implementation manner of the second aspect, in the standby stage, the write bit line is configured to receive the first write bit line control signal, the word line is configured to receive the first word line control signal, and a voltage difference between the first word line control signal and the first write bit line control signal makes a polarity of the ferroelectric film layer of the first ferroelectric capacitor not flip, and a polarization state remains unchanged. The first transistor and the second transistor are both off.

In a possible implementation manner of the second aspect, in a writing phase, a first reading phase, a third reading phase and a standby phase; the source line is used for receiving a source line control signal, the read bit line is used for receiving a second read bit line control signal, and the voltage values of the source line control signal and the second read bit line control signal are equal. Thus, leakage current can be reduced, and power consumption can be reduced.

In a possible implementation manner of the second aspect, the ferroelectric memory further includes a controller, where the controller is configured to: outputting a precharge control signal to control a voltage on the precharge line; outputting a write bit line control signal to control a voltage on the write bit line; outputting a word line control signal to control a voltage on the word line; outputting a source line control signal to control a voltage on the source line; and outputting a read bit line control signal to control a voltage on the read bit line.

In a third aspect, the present application further provides an electronic device, including a processor and a ferroelectric memory in any one of the above implementations of the first aspect, where the processor is electrically connected to the ferroelectric memory.

The electronic device provided by the embodiment of the application comprises the ferroelectric memory manufactured by the embodiment of the first aspect or the embodiment of the second aspect, so that the electronic device provided by the embodiment of the application and the ferroelectric memory of the technical scheme can solve the same technical problems and achieve the same expected effects.

In a fourth aspect, the present application also provides a control method of a ferroelectric memory, the ferroelectric memory comprising: precharge line, write bit line, read bit line, source line, and word line; and a plurality of memory cells, each memory cell comprising: the memory device comprises a first transistor, a second transistor, a floating gate and a first ferroelectric capacitor, wherein the control end of the first transistor is electrically connected with a pre-charge line, the first end of the first transistor is electrically connected with the floating gate, the second end of the first transistor is electrically connected with a write bit line, the first end of the first ferroelectric capacitor is electrically connected with the floating gate, the second end of the first ferroelectric capacitor is electrically connected with a word line, the control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with a source line, and the second end of the second transistor is electrically connected with a read bit line;

The control method comprises the following steps: outputting a first precharge control signal to the precharge line to turn on the first transistor; outputting a first write bit line control signal to the write bit line; and outputting a first word line control signal to the word line, wherein the voltage difference of the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate positive polarization or negative polarization so as to write different logic information in the first ferroelectric capacitor.

In a possible implementation manner of the fourth aspect, the control method further includes: outputting a first precharge control signal to the precharge line to turn on the first transistor in the first reading stage if the read data is "0"; outputting a second write bit line control signal to the write bit line; outputting a second word line control signal to the word line, wherein the voltage difference between the second word line control signal and the second write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, the polarity of the ferroelectric film layer is not turned over, and the polarization state is kept unchanged; in the second reading stage, outputting a second precharge control signal to the precharge line to turn off the first transistor; outputting a first read bit line control signal to the read bit line; outputting a word line control signal smaller than the voltage of a second word line control signal to the word line, wherein the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line causes the first ferroelectric capacitor to be inverted from positive polarization to negative polarization so as to reduce the voltage of the floating gate control signal on the floating gate, and the second transistor is disconnected; in a third reading stage, outputting a first precharge control signal to the precharge line to turn on the first transistor; outputting a first write bit line control signal to the write bit line; outputting a first word line control signal to the word line; the voltage difference between the first word line control signal and the first write bit line control signal causes the ferroelectric film layer of the first ferroelectric capacitor to generate positive polarization.

In a possible implementation manner of the fourth aspect, the control method further includes: outputting a first precharge control signal to the precharge line to turn on the first transistor in the first reading stage if the read data is "1"; outputting a second write bit line control signal to the write bit line; outputting a second word line control signal to the word line, wherein the voltage difference between the second word line control signal and the second write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, the polarity of the ferroelectric film layer is not turned over, and the polarization state is kept unchanged; in the second reading stage, outputting a second precharge control signal to the precharge line to turn off the first transistor; outputting a first read bit line control signal to the read bit line; outputting a word line control signal smaller than the voltage of a second word line control signal to the word line, wherein the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line keeps the negative polarity state of the first ferroelectric capacitor unchanged, the voltage of the floating gate control signal on the floating gate is unchanged, and the second transistor is turned on; in a third reading stage, outputting a first precharge control signal to the precharge line to turn on the first transistor; outputting a first write bit line control signal to the write bit line; outputting a first word line control signal to the word line; the voltage difference between the first word line control signal and the first write bit line control signal causes the ferroelectric film layer of the first ferroelectric capacitor to generate negative polarization.

In a possible implementation manner of the fourth aspect, the control method further includes: outputting a first word line control signal to the word line in a standby stage; and outputting a first write bit line control signal to the write bit line, wherein the voltage difference of the first word line control signal and the first write bit line control signal ensures that the polarity of the ferroelectric film layer of the first ferroelectric capacitor is not inverted, and the polarization state is kept unchanged.

In a possible implementation manner of the fourth aspect, the control method further includes: in the writing phase, the first reading phase, the third reading phase and the standby phase, the source line and the reading bit line are controlled so that the voltage values of the source line control signal of the source line and the second reading bit line control signal of the reading bit line are equal.

Drawings

FIG. 1a is a circuit diagram of a FeRAM of the prior art;

FIG. 1b is a circuit diagram of a FeFET of the prior art;

fig. 2 is a circuit diagram of an electronic device according to an embodiment of the present application;

fig. 3 is a circuit diagram of a ferroelectric memory according to an embodiment of the present application;

fig. 4 is a circuit diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 5 is a circuit diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 6 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

FIG. 7 is a timing chart of voltage variation during reading and writing of a ferroelectric memory according to an embodiment of the present application;

fig. 8 is a circuit diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 9 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 10 is a circuit diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

FIG. 11 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 12 is a circuit diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 13 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 14 is a cross-sectional view of a transistor according to an embodiment of the present application;

fig. 15 is a cross-sectional view of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 16 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 17 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 18 is a cross-sectional view of a memory cell of a ferroelectric memory according to an embodiment of the present application;

Fig. 19 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 20 is a cross-sectional view of a transistor according to an embodiment of the present application;

fig. 21 is a cross-sectional view of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 22 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 23 is a cross-sectional view of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 24 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 25 is a circuit diagram of a memory cell of a ferroelectric memory according to an embodiment of the present application;

fig. 26 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 27 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 28 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 29 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

fig. 30 is a circuit diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

Fig. 31 is a process structure diagram of a memory array of a ferroelectric memory according to an embodiment of the present application;

FIG. 32 is a schematic diagram of a chip process according to an embodiment of the present application;

fig. 33 is a schematic process diagram of another chip according to an embodiment of the present application.

Detailed Description

Ferroelectric memories store data based on the ferroelectric effect of ferroelectric materials. Ferroelectric memories are expected to be a major competitor to DRAM due to their ultra-high memory density, low power consumption, and high speed. The memory cell in a ferroelectric memory comprises a ferroelectric capacitor comprising two electrodes and a ferroelectric material, such as a ferroelectric film layer, arranged between the two electrodes. Due to the non-linear nature of the ferroelectric material, the dielectric constant of the ferroelectric material can be adjusted, and the difference between before and after the polarization state of the ferroelectric film layer is reversed is very large, which makes the ferroelectric capacitor have a smaller volume compared with other capacitors, for example, the capacitor for storing charges in the DRAM is much smaller.

In ferroelectric memories, the ferroelectric film layer may be formed using a common ferroelectric material. When an electric field is applied to the ferroelectric film layer of the memory cell, the central atom is stopped in a low energy state along the electric field, whereas when an electric field reversal is applied to the transistor, the central atom moves in the crystal along the direction of the electric field and is stopped in another low energy state. A large number of central atoms are mobile-coupled in the crystal unit cell to form ferroelectric domains (ferroelectric domains), which form polarized charges under the action of an electric field. The ferroelectric domain has higher polarized charge formed by inversion under the electric field, the ferroelectric domain has lower polarized charge formed by non-inversion under the electric field, and the binary stable state of the ferroelectric material enables the ferroelectric to be used as a memory.

The embodiment of the application provides an electronic device comprising a ferroelectric memory. Fig. 2 shows an electronic device 200 according to an embodiment of the present application, where the electronic device 200 may be a terminal device, such as a mobile phone, a tablet computer, a smart band, or a personal computer (personal computer, PC), a server, a workstation, etc. The electronic device 200 includes a bus 205, a System On Chip (SOC) 210 and a read-only memory (ROM) 220 connected to the bus 205. The SOC210 may be used to process data, such as data of processing applications, process image data, and buffer temporary data. The ROM220 may be used to hold non-volatile data such as audio files, video files, and the like. ROM220 may be a PROM (programmable read-only memory), EPROM (erasable programmable read-only memory ), flash memory (flash memory), or the like.

In addition, the electronic device 200 may further include a communication chip 230 and a power management chip 240. The communication chip 230 may be used for processing the protocol stack, amplifying, filtering, etc. the analog radio frequency signal, or simultaneously implementing the above functions. The power management chip 240 may be used to power other chips.

In one embodiment, the SOC210 may include an application processor (application processor, AP) 211 for processing applications, an image processing unit (graphics processing unit, GPU) 212 for processing image data, and a random access memory (random access memory, RAM) 213 for caching data.

The AP211, GPU212, and RAM213 may be integrated into one die (die), or may be integrated into multiple dies (die), respectively, and packaged in a package structure, for example, using 2.5D (dimension), 3D packaging, or other advanced packaging techniques. In one embodiment, the AP211 and the GPU212 are integrated in one die, the RAM213 is integrated in another die, and the two die are packaged in a package structure, so as to obtain a faster inter-die data transmission rate and a higher data transmission bandwidth.

Fig. 3 is a schematic diagram of a ferroelectric memory 300 according to an embodiment of the present application. The ferroelectric memory 300 may be a RAM213 as shown in fig. 2, belonging to FeRAM. In one embodiment, ferroelectric memory 300 may also be a RAM disposed external to SOC 210. The present application does not limit the location of ferroelectric memory 300 in the device and the positional relationship with SOC 210.

Continuing with fig. 3, ferroelectric memory 300 includes memory array 310, decoder 320, driver 330, timing controller 340, buffer 350, and input-output driver 360. The memory array 310 includes a plurality of memory cells 400 arranged in an array, wherein each memory cell 400 may be used to store 1bit or more of data. The memory array 310 further includes signal lines such as Word Lines (WL), bit Lines (BL), source Lines (SL), and precharge lines (CL). Each memory cell 400 is electrically connected to a corresponding word line WL, bit line BL, source line SL, and precharge line CL. One or more of the word line WL, the bit line BL, the source line SL or the precharge line CL is used for selecting the memory cell 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the polarization direction of the ferroelectric capacitor in the memory cell 400, thereby realizing the read and write operation of data. For convenience, the word line WL, the bit line BL, the source line SL, and the precharge line CL described above are collectively referred to as signal lines in the embodiments of the present application.

In the ferroelectric memory 300 structure shown in fig. 3, the decoder 320 is configured to decode according to the received address to determine the memory cell 400 that needs to be accessed. The driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby realizing access to the designated memory cell 400. The buffer 350 is used for buffering the read data, and may be, for example, a first-in first-out (FIFO) buffer. The timing controller 330 is used for controlling the timing of the buffer 350 and controlling the driver 330 to drive the signal lines in the memory array 310. The input-output driver 360 is used to drive transmission signals, such as to drive received data signals and to drive data signals to be transmitted, so that the data signals can be transmitted over a long distance.

The memory array 310, the decoder 320, the driver 330, the timing controller 340, the buffer 350, and the input/output driver 360 may be integrated into one chip or may be integrated into a plurality of chips.

Fig. 4 is a circuit diagram of a memory cell 400 according to an embodiment of the present application. The memory cell 400 includes a first transistor T1, a second transistor T2, and a ferroelectric capacitor C1, floating Gate (FG). The control terminal of the first transistor T1 is electrically connected to the precharge line CL, the first terminal of the first transistor T1 is electrically connected to the floating gate FG, the second terminal is electrically connected to a Write Bit Line (WBL), the first terminal of the ferroelectric capacitor C1 is electrically connected to the floating gate FG, and the second terminal of the ferroelectric capacitor C1 is electrically connected to the word line WL.

After the control signal in the precharge line CL controls the first transistor T1 to be turned on, the level on the write bit line WBL is equal to the level of the first terminal of the first transistor T1 and the level of the first terminal of the ferroelectric capacitor C1.

After a certain voltage difference is formed between the first end of the ferroelectric capacitor C1 and the word line WL, namely, after the voltage difference is formed between the two ends of the ferroelectric capacitor C1, the polarization direction of ferroelectric materials in the ferroelectric capacitor is changed, so that the reading and writing operation of data is realized.

As further shown in fig. 4, the first terminal of the second transistor T2 is electrically connected to the source line SL, the second terminal is electrically connected to a Read Bit Line (RBL), and the control terminal of the second transistor T2 is electrically connected to the floating gate FG.

The first transistor T1 and the second transistor T2 in the memory cell 400 according to the present application may be selected from NMOS (N-channel metal oxide semiconductor ) transistors or from PMOS (P-channel metal oxide semiconductor, P-channel metal oxide semiconductor) transistors. For example, in the memory cell 400 shown in fig. 4, the first transistor T1 selects an NMOS transistor, and the second transistor T2 also selects an NMOS transistor. At this time, the first transistor T1 is turned on when the precharge line CL is at a high level, and turned off when the precharge line CL is at a low level.

In the memory cell 400, as in fig. 4, a ferroelectric capacitor C2 may be further included, and the unselected word line ensel WL electrically connected to the ferroelectric capacitor C2 is correspondingly included. Wherein, the first end of ferroelectric capacitor C2 is connected with floating gate FG, and the second end of ferroelectric capacitor C2 is connected with unselected word line Unsel WL. Fig. 4 exemplarily shows that the ferroelectric capacitor C2 is included in addition to the ferroelectric capacitor C1.

Of course, in order to further improve the storage density, for example, as shown in fig. 5, the memory device may further include more ferroelectric capacitors, for example, in addition to the ferroelectric capacitor C1 and the ferroelectric capacitor C2, further include a ferroelectric capacitor C3 and a ferroelectric capacitor C4, where the connection relationship between the ferroelectric capacitor C3 and the ferroelectric capacitor C4 and the unselected word line ensel WL and the floating gate FG is the same as the connection relationship between the ferroelectric capacitor C1 and the ferroelectric capacitor C2 described above, and will not be described herein.

That is, as shown in fig. 4 and 5, a plurality of ferroelectric capacitors (e.g., four, eight, sixteen) share one first transistor T1 and one second transistor T2 to form one memory cell 400, and the one memory cell 400 can be used to store multi-bit data, increasing memory capacity.

In the above-mentioned memory cell 400, the logic level of the unselected word line un WL is opposite to the logic level of the word line WL, for example, in fig. 4, the ferroelectric memory 300 may control only the reading and writing of the ferroelectric capacitor C1 through the word line WL, and keep the state of the ferroelectric capacitor C2 unchanged through the unselected word line un WL, so as to implement the reading and writing of the data of multiple bits in one memory cell 400.

In an actual structural implementation, these word lines WL and unselected word lines ensel WL are not structurally distinct. When the read-write operation is required to be performed on the data of a certain bit, the word line WL corresponding to the read-write ferroelectric capacitor receives a corresponding control signal, and the word line WL corresponding to the read-write ferroelectric capacitor can be regarded as an unselected word line Unsel WL without the need of the read-write ferroelectric capacitor.

In the embodiment of the present application, the control terminals of the first transistor T1 and the second transistor T2 are gates, and one of the drain (drain) or the source (source) of the MOS transistor is referred to as a first terminal, and the other is referred to as a second terminal. For example, the first terminal of the first transistor T1 in fig. 4 and 5 may be a source and the second terminal is a drain; or the first end is a drain electrode and the second end is a source electrode. In practice, for PMOS transistors, the terminal with the lower voltage of the first and second terminals may be considered as the source, and the terminal with the higher voltage may be considered as the drain. Accordingly, for an NMOS transistor, the terminal with the lower voltage of the first and second terminals may be considered as the drain, and the terminal with the higher voltage may be considered as the source.

In the memory cell 400 shown in fig. 4 and 5, the ferroelectric film layer between the first end and the second end of each ferroelectric capacitor may be any ferroelectric film layer structure in the prior art, and the material and the manufacturing process of the ferroelectric film layer are not limited in the present application. When the polarization direction of the ferroelectric film layer is reversed, a potential domain wall region is arranged between the reversed region and the non-reversed region, and when the polarization direction is opposite, the domain wall is opened to be in a conductive state, namely a low-resistance state; when the polarization directions are the same, the domain wall is closed and is in an insulating state, namely a high-resistance state. The high-low resistance states are used for representing the stored 0 and 1 states respectively, for example, the high resistance state corresponds to 0, the low resistance state corresponds to 1, or the high resistance state corresponds to 1, and the low resistance state corresponds to 0, so that the storage function is realized.

The memory array 310 may be obtained by arranging the memory cells 400 shown in fig. 4 or fig. 5 according to an array, where the circuit structure of each memory cell 400 is the same, for example, in the memory array 310 shown in fig. 6, the structure of each memory cell 400 may be a structure including two ferroelectric capacitors shown in fig. 4.

In the memory array 310 in the ferroelectric memory, a plurality of memory cells arranged in an array may be included, for example in fig. 6, a memory array including four memory cells of the memory cell 401, the memory cell 402, the memory cell 403 and the memory cell 404 is exemplarily given. One skilled in the art can design the arrangement of the memory cells 400 and the number of memory cells 400 in the memory array 310 according to the storage capacity requirements of the ferroelectric memory. In one embodiment, the memory array 310 may further include more memory cells 400, and the memory cells 400 may be arranged in an X direction, a Y direction, and a Z direction perpendicular to each other to form a three-dimensional memory array.

The X-direction according to embodiments of the present application may be positioned as a first direction and the Y-direction may be defined as a second direction.

In the memory array 310 shown in fig. 6, two precharge lines are included, respectively, the selected precharge line CL and the unselected precharge line un CL, and each precharge line extends along the Y direction, and when the memory array 310 further includes more memory cells, then the corresponding further includes further unselected precharge lines un CL, which are arranged in parallel along the X direction perpendicular to the Y direction, and further, the plurality of memory cells arranged along the Y direction may share one precharge line, for example, the memory cell 401 and the memory cell 402 share the selected precharge line CL, and the memory cell 403 and the memory cell 404 share the unselected precharge line un CL.

With continued reference to FIG. 6, the memory array 310 includes two write bit lines, a selected write bit line WBL and an unselected write bit line Unsel WBL, each write bit line extending in the X direction, and further includes more unselected write bit lines Unsel WBL running in parallel in the Y direction perpendicular to the X direction, and further, multiple memory cells running in the X direction may share one write bit line WBL, e.g., memory cell 401 and memory cell 403 share the selected write bit line WBL, and memory cell 402 and memory cell 404 share the unselected write bit line Unsel WBL.

Similarly, the read bit line RBL and the write bit line WBL are arranged in the same manner, and will not be described herein.

Note that, regarding the source line SL in this memory array, not only the source line SL of a plurality of memory cells laid in the X direction but also the source line SL of a plurality of memory cells laid in the Y direction are shared, for example, the source line SL of the memory cell 401 and the source line SL of the memory cell 402 are shared here, and the source line SL of the memory cell 401 and the source line SL of the memory cell 403 are also shared, that is, the source lines SL of the memory cell 401, the memory cell 402, the memory cell 403, and the memory cell 404 are connected to each other here.

Note that, regarding the word lines WL in this memory array, not only the word lines WL of a plurality of memory cells laid in the X direction but also the word lines WL of a plurality of memory cells laid in the Y direction are shared, for example, the word line WL connected to the ferroelectric capacitor C1 of the memory cell 401 and the word line WL connected to the ferroelectric capacitor C1 of the memory cell 402 are shared, and the word line WL connected to the ferroelectric capacitor C1 of the memory cell 401 and the word line WL connected to the ferroelectric capacitor C1 of the memory cell 403 are shared, that is, the selected word lines WL connected to the four ferroelectric capacitors C1 of the memory cell 401, the memory cell 402, the memory cell 403, and the memory cell 404 are connected to each other.

The selected source line SL, the unselected source line un SL, the selected precharge line CL, the unselected precharge line un CL, the selected word line WL, the unselected word line un WL, the selected read bit line RBL, the unselected read bit line un sel RBL, the selected write bit line WBL, and the unselected write bit line un sel WBL may each receive different control signals. These control signals may be output by a controller, such as may be controlled by timing controller 340 shown in fig. 3.

In some implementations, the timing controller 340 includes one or more sub-controllers for controlling the signal lines. The one or more sub-controllers may be in one-to-one correspondence with the signal lines, or in many-to-many correspondence with the signal lines. For example, the timing controller 340 may control all signal lines through only one sub-controller. Alternatively, the timing controller 340 may also include 5 sub-controllers, a word line sub-controller for controlling voltages on all types of word lines, a write bit line sub-controller for controlling voltages on all types of write bit lines, a read bit line sub-controller for controlling voltages on all types of read bit lines, a read bit line sub-controller for controlling voltages on all types of source lines, a source line sub-controller for controlling voltages on all types of source lines, and a precharge sub-line controller for controlling voltages on all types of precharge lines.

The following describes in detail the read-write operation procedure of the memory cell in the structure shown in fig. 6, respectively. And the first transistor and the second transistor of each memory cell in fig. 6 are NMOS transistors.

The voltage value list shown in table 1 is a voltage value on each signal line corresponding to the memory cell 401 when the memory cell 401 in the memory array 310 in fig. 6 is subjected to the read and write operations. Where Vdd is the first operating voltage, vw is the second operating voltage, and Vpre is the read precharge voltage. In one embodiment, the first operating voltage Vdd may be equal to the second operating voltage Vw, or the first operating voltage Vdd may also be approximately equal to the second operating voltage Vw, vpre may be greater than Vw/2, and less than Vw. The present application is not limited to specific values of the first and second operating voltages Vdd and Vw and the read precharge voltage Vpre, but the first operating voltage Vdd is equal to the second operating voltage Vw is described as an example. For the memory cells of the selected floating gate FG column, the voltage value before "or" is the voltage when the read data is "0", and the voltage value after "or" is the voltage when the read data is "1".

Operation of	WL	Unsel WL	CL	WBL	SL	RBL	FG
Write 0	Vw	Vw/2	Vdd	V0	Vw/2	Vw/2	V0
Write 1	V0	Vw/2	Vdd	Vw	Vw/2	Vw/2	Vw
Read precharge	Vw/2	Vw/2	Vdd	Vpre	Vw/2	Vw/2	Vpre

Read 0/1	V0	Vw/2	V0	Vpre	Vw/2	Vw	Vpre→V1orVpre
Write back	Vw	Vw/2	Vdd	V0orVw	Vw/2	Vw/2	V0orVw
Standby priming	Vw/2	Vw/2	Vdd	Vw/2	Vw/2	Vw/2	Vw/2
Standby	Vw/2	Vw/2	V0	Vw/2	Vw/2	Vw/2	Vw/2

TABLE 1

Fig. 7 is a timing chart showing the voltage variation on each signal line of the memory cell 401 to be read and written during a typical read/write operation. The overall read/write operation procedure is described with reference to table 1 and fig. 7.

Note that in the timing chart shown in fig. 7, as an example, the voltage on each signal line changes at the rising edge of the clock signal CLK. In one embodiment, the voltage on each signal line may also vary on the falling edge of the clock signal CLK. The solid line shown in fig. 7 shows the voltage change on the signal line when "0" is written or "0" is read, and the broken line shows the voltage change on the signal line when "1" is written or "1" is read.

As shown in fig. 7, the memory cell 401 is written at time t 0. The write operation to the memory cell 401 is actually to change the polarization state of the ferroelectric film layer in the ferroelectric capacitor to which data is to be written. When the absolute value of the voltage difference between the two ends of the ferroelectric capacitor is larger than the coercive electric field of the ferroelectric film layer, the polarization state of the ferroelectric film layer is changed; when the absolute value of the voltage difference across the ferroelectric capacitor is less than or equal to the coercive electric field of the ferroelectric film layer, the polarization state of the ferroelectric film layer is not changed. The strength of the coercive electric field can be measured from the material of the ferroelectric film layer, and then an operating voltage Vw/2 (Vdd/2) is set. When the voltage across the ferroelectric capacitor (i.e., the voltage across the ferroelectric film layer) is greater than Vw/2, the polarization state of the ferroelectric film layer changes; when the voltage across the ferroelectric capacitor (i.e., across the ferroelectric film layer) is less than or equal to Vw/2, the polarization state of the ferroelectric film layer does not change.

As shown in table 1 and fig. 7, when the ferroelectric capacitor C1 in the memory cell 401 is subjected to the write "0" operation, the selected precharge line CL receives the first operating voltage Vdd such that the first transistor T1 is turned on, the voltage of the bit line control signal received by the selected write bit line WBL is V0 (v0=0), and the bit line control voltage received by the selected write bit line WBL is transferred to the floating gate FG through the first transistor T1. For the ferroelectric capacitor C1, the voltage of the selected word line WL connected thereto is the second operating voltage Vw, and since the absolute value of the voltage difference between the voltage of the selected word line WL and the voltage of the selected write bit line WBL is Vw and Vw is greater than the operating voltage Vw/2, the polarization state of the ferroelectric film layer of the ferroelectric capacitor C1 becomes positive polarization, thereby realizing the write "0" operation on the ferroelectric capacitor C1.

In addition, since the operation of writing "0" to the ferroelectric capacitor C2 in the memory cell 401 is not performed, the voltage on the unselected word line ensel WL electrically connected to the ferroelectric capacitor C2 is Vw/2, the absolute value of the voltage difference between the voltage on the unselected word line ensel WL and the voltage on the selected write bit line WBL is Vw/2, that is, the voltage across the ferroelectric capacitor C2 is Vw/2, and the absolute value of the voltage difference is less than or equal to the operation voltage Vw/2, which does not cause the change of the polarization state of the ferroelectric film layer in the ferroelectric capacitor C2, and thus the operation of writing "0" to the ferroelectric capacitor C2 is not performed.

In addition, in the case of performing the write "0" operation, the voltages on the selected read bit line RBL and the source line SL are Vw/2, and further, the first terminal and the second terminal of the second transistor T2 have no voltage difference, so that the second transistor T2 is turned off. The driver 330 may drive the selected read bit line RBL and the source line SL such that the voltage on the selected read bit line RBL and the voltage on the source line SL are equal, thereby effectively reducing the current flowing through the second transistor T2 to reduce the power consumption of the ferroelectric memory.

Continuing with table 1 and fig. 7, when the ferroelectric capacitor C1 in the memory cell 401 is subjected to the write "1" operation, the selected precharge line CL receives the first operating voltage Vdd, so that the first transistor T1 is turned on, the voltage of the bit line control signal received by the selected write bit line WBL is Vw, and the bit line control voltage received by the selected write bit line WBL is transferred to the floating gate FG through the first transistor T1. For the ferroelectric capacitor C1, the voltage of the selected word line WL connected thereto is V0 (v0=0), and since the voltage difference between the selected word line WL and the selected write bit line WBL is-Vw, the absolute value of the voltage difference is greater than the aforementioned operation voltage 1/2Vdd (Vw/2) and is negative, the polarization state of the ferroelectric film layer becomes negative polarization, thereby realizing the write "1" operation for the ferroelectric capacitor C1.

In addition, since the operation of writing "1" to the ferroelectric capacitor C2 in the memory cell 401 is not performed, the voltage on the unselected word line ensel WL electrically connected to the ferroelectric capacitor C2 is Vw/2, the absolute value of the voltage difference between the voltage on the unselected word line ensel WL and the voltage on the selected write bit line WBL is Vw/2, that is, the voltage across the ferroelectric capacitor C2 is Vw/2, and the absolute value of the voltage difference is less than or equal to the operation voltage Vw/2, which does not cause the change of the polarization state of the ferroelectric film layer in the ferroelectric capacitor C2, and thus the operation of writing "1" to the ferroelectric capacitor C2 is not performed.

Since the floating gate FG has a voltage Vw, the voltages on the selected read bit line RBL and the source line SL are Vw/2, and there is no voltage difference between the first and second terminals of the second transistor T2, the second transistor T2 is turned off. As described in the embodiment of the write "0" operation, the driver 330 may also drive the selected read bit line RBL signal such that the voltage on the selected read bit line RBL is equal to the voltage on the source line SL, thereby effectively reducing the current through the second transistor T2 and reducing the power consumption of the ferroelectric memory.

The read data operation on the memory cell 401 requires 3 steps of read precharge, read and write back.

When the ferroelectric capacitor C1 in the memory cell 401 is read, a read precharge (pre-charge) operation is performed. In the read pre-charge stage, in order to provide a reference potential for the floating gate FG, the first transistor T1 is turned on by selecting the pre-charge line CL to receive the voltage Vdd, the voltage of the bit line control signal received by the selected write bit line WBL is the pre-charge read voltage Vpre, and the bit line control voltage received by the selected write bit line WBL is transferred to the floating gate FG through the first transistor T1 to make the voltage on the floating gate FG Vpre. Since the state of the ferroelectric film layers in all the ferroelectric capacitors does not need to be changed, the voltages on the selected word line WL and the unselected word line un WL are in a half-gating state of Vw/2, and the polarities of the ferroelectric capacitor C1 and the ferroelectric capacitor C2 are not inverted.

Since the floating gate FG has a voltage of Vpre, the voltages on the selected read bit line BL and the source line SL are both Vw/2, and therefore the second transistor T2 is turned off. The driver 330 drives the selected read bit line RBL and the source line SL to remain at Vw/2 all the time, thus reducing current and power consumption.

After the read precharge operation is performed, a read phase operation is performed, the voltage of the selected precharge line CL is reduced to V0 (v0=0), and then the first transistor T1 is turned off, so that the floating gate FG is in a floating state, the bit line control voltage Vw received by the selected read bit line RBL, the voltage on the selected word line WL is V0 (v0=0), and the source line control voltage received by the source line SL is Vw/2.

In the reading stage, if the ferroelectric film layer of the ferroelectric capacitor C1 is in the negative polarization state, that is, the data stored in the ferroelectric capacitor C1 is "1", the voltage difference WL-FG at both ends of the ferroelectric capacitor C1 is the same as the negative polarization direction of the ferroelectric film layer, so that the state of the ferroelectric film layer in the ferroelectric capacitor C1 is not changed, the voltages on other signal lines are not changed, and the second transistor is turned on.

In the reading stage, if the ferroelectric film of the ferroelectric capacitor C1 is in the positive state, that is, the data stored in the ferroelectric capacitor C1 is "0", the polarization state of the ferroelectric film of the ferroelectric capacitor C1 changes from the positive state to the negative state, and during the polarization state transition of the ferroelectric film, the charges on the floating gate FG accumulate in the ferroelectric capacitor C1, resulting in the voltage on the floating gate FG decreasing from Vpre to V1, and the second transistor is turned off. This process may be referred to as a corruption process prior to reading.

After the destruction is completed, a reading process can be executed, in a reading stage, the voltage on the read bit line RBL can be confirmed through a sense amplifier SA connected with the read bit line RBL, when information '1' is read, the voltage on the floating gate FG is kept at Vpre, the voltage on the read bit line RBL is Vw, the voltage on the source line SL is Vw/2, the second transistor T2 is conducted, and the current on the read bit line RBL is larger; when reading information "0", the voltage on the floating gate FG is reduced to V1, the voltage on the read bit line RBL is Vw, the voltage on the source line SL is Vw/2, the second transistor T2 is in a subthreshold state, the current on the read bit line RBL is smaller, and then the current on the read bit line RBL can be read through the current SA externally connected to the read bit line RBL to confirm the read information.

After the reading phase is completed, a write-back process is performed, and in the write-back phase, the voltage on the selected precharge line CL is raised from 0 to Vdd in the reading phase, so that the first transistor T1 is turned on, and the voltage on the selected word line WL is raised from V0 to Vw in the reading phase.

If the data read from the ferroelectric capacitor C1 is "0", the voltage on the selected write bit line WBL is reduced to V0 (v0=0), the voltage on the selected write bit line WBL is transferred to the floating gate FG through the first transistor T1, so that the voltage on the floating gate FG is V0 (v0=0), and for the ferroelectric capacitor C1, since the voltage of the selected word line WL and the voltage difference of the selected write bit line WBL are Vw, the ferroelectric film layer whose polarization direction is reversed during the reading process is positively polarized, thereby writing back "0".

If the data read from the ferroelectric capacitor C1 is "1", the voltage on the selected write bit line WBL is raised to Vw, and the voltage on the selected write bit line WBL is transferred to the floating gate FG via the first transistor T1, so that the voltage on the floating gate FG is Vw, and for the ferroelectric capacitor C1, since the voltage difference between the voltage of the selected word line WL and the selected write bit line WBL is 0, the polarization direction is not changed during the reading process, and thus "1" is written back.

In one embodiment, when reading data from memory cell 401, the data is read, pre-charge, read, and write back are performed in that order. In another embodiment, the order of the two phases read and write back may be interchanged, i.e., in the order of read precharge, write back, and read. The data is written back to the memory unit 401 first, and then the data is read, so that the reading of the data is not influenced, and the storage of the data is not influenced.

Before the standby phase is performed, a standby precharge phase may be performed, as shown in table 1 and fig. 7, in which the voltage on the precharge line CL is Vdd to turn on the first transistor T1, the voltage on the selected write bit line WBL is Vw/2, and further, the voltage on the floating gate FG is kept at Vw/2, and in the standby precharge phase, no read/write operation is required for the memory cell 401, so that the voltages on both the selected read bit line BL and the source line SL are kept at Vw/2, and thus, the voltage difference between both ends of the ferroelectric capacitor C1 and the ferroelectric capacitor C2 is 0, which satisfies the condition of being less than or equal to the above-mentioned operation voltage, and thus the polarization state is kept unchanged.

After the standby precharge is performed, a standby phase may be performed in which the voltage on the precharge line CL is V0 (v0=0) to turn off the first transistor T1, the voltage on the selected write bit line WBL is Vw/2, the selected read bit line BL and the source line SL are both maintained at Vw/2, and the second transistor T1 is also turned off.

In the case of performing the read/write operation on the memory cell 401 shown in fig. 7, the other three memory cells, i.e., the memory cell 402, the memory cell 403 and the memory cell 404 are not written with any data nor read with any data. Therefore, by controlling the voltages on the respective signal lines corresponding to the memory cell 402, the memory cell 403, and the memory cell 404, the data of the three memory cells are held.

The voltage value list shown in table 2 is a voltage value on each signal line corresponding to the memory cell 403 when the memory cell 401 in the memory array 310 is read and written. Where Vdd is the first operating voltage, vw is the second operating voltage, and Vpre is the read precharge voltage.

TABLE 2

Since the memory cell 403 and the memory cell 401 share the selected word line WL, the unselected word line insel WL and the selected write bit line WBL, the source line SL and the selected read bit line RBL, the selected word line WL, the unselected word line insel WL and the selected write bit line WBL, the source line SL and the selected read bit line RBL corresponding to (connected to) the memory cell 403 are the same as those of the memory cell 401 in table 1 when the read/write operation is performed on the memory cell 401, and thus, the description thereof will not be repeated. Only in the read/write operation stage or the standby stage, the voltage on the unselected precharge line CL connected to the memory cell 403 is V0 (v0=0) to turn off the first transistor T1 in the memory cell 403.

The voltage value list shown in table 3 is a voltage value on each signal line corresponding to the memory cell 402 when the memory cell 401 in the memory array 310 is read and written. Where Vdd is the first operating voltage, vw is the second operating voltage, and Vpre is the read precharge voltage.

TABLE 3 Table 3

Since memory cell 402 and memory cell 401 share the selected word line WL, unselected word line ensel WL, selected precharge line CL, and source line SL. Therefore, in performing the read/write operation on the memory cell 402, the voltages received by the common selected word line WL, the unselected word line ensel WL, the selected precharge line CL and the source line SL corresponding to (connected to) the memory cell 402 are the same as those of the memory cell 401 in table 1, and will not be described herein.

In addition, when writing data to the memory cell 401, the voltages on the unselected write bit line Unsel WBL and the unselected read bit line Unsel corresponding to the memory cell 402 are Vw/2, regardless of whether data "0" or data "1" is written. In the data writing phase, the absolute value of the voltage difference across either ferroelectric capacitor in memory cell 402 is Vw/2, i.e., less than or equal to the operating voltage Vw/2, which does not result in a change in polarization state of the ferroelectric film layer in either ferroelectric capacitor in memory cell 402. In the read data phase and the standby phase, the voltages on the source line SL and the unselected read bit line ensel RBL are Vw/2, i.e., the second transistor T2 is in an off state, so that the polarization state of the ferroelectric film layer of any ferroelectric capacitor in the memory cell 402 is not affected, and the storage of data in the memory cell 402 is not affected.

The voltage value list shown in table 4 is a voltage value on each signal line corresponding to the memory cell 404 when the memory cell 401 in the memory array 310 is read and written. Where Vdd is the first operating voltage, vw is the second operating voltage, and Vpre is the read precharge voltage.

TABLE 4 Table 4

Since memory cell 404 and memory cell 403 share the selected word line WL, unselected word line ensel WL, unselected precharge line CL, and source line SL, and memory cell 404 shares the unselected write bit line WBL, and bit-selected read bit line RBL with memory cell 402. Therefore, in performing the read/write operation on the memory cell 401, voltages received by the selected word line WL, the unselected word line ensel WL, and the unselected precharge line CL and the source line SL corresponding to (connected to) the memory cell 404 are the same as those of the memory cell 402 in table 2, and will not be described herein. Since the memory cell 404 and the memory cell 402 share the unselected write bit line WBL and the bit-selected read bit line RBL, the shared unselected write bit line WBL corresponding to (connected to) the memory cell 404 and the bit-selected read bit line RBL are the same as those of the memory cell 403 in table 3 when performing the read/write operation on the memory cell 401, and thus, the details thereof will not be repeated here.

Fig. 8 is a circuit diagram of another memory cell 400 according to an embodiment of the present application. The memory cell 400 is similar in circuit configuration to the memory cell 400 shown in fig. 4 and 5 described above. In contrast, the first transistor T1 in the memory cell 400 of fig. 8 is a PMOS transistor, and the second transistor T2 is a PMOS transistor. Accordingly, the first transistor T1 is turned on when the precharge line CL is at a low level, and is turned off when the precharge line CL is at a high level. For the read/write operation of the memory unit 400, reference may be made to the foregoing adaptive adjustment of the read/write logic of the memory units 401, and 401, which is not described herein.

The memory array 310 shown in fig. 9 includes the memory cells shown in fig. 8. The arrangement of the individual signal lines in the memory array shown in fig. 9 is similar to that of fig. 6. The difference is that the transistor types of the first transistor T1 and the second transistor T2 are adjusted, i.e. the first transistor T1 is a PMOS transistor and the second transistor T2 is a PMOS transistor.

Fig. 10 is a circuit diagram of another memory cell 400 according to an embodiment of the present application. The memory cell 400 is similar in circuit configuration to the memory cell 400 shown in fig. 8 and described above. In contrast, the first transistor T1 in the memory cell 400 of fig. 10 is a PMOS transistor, and the second transistor T2 is an NMOS transistor. Accordingly, the first transistor T1 is turned on when the precharge line CL is at a low level, and is turned off when the precharge line CL is at a high level. For the read/write operation of the memory unit 400, the read/write logic of the memory units 401, 401 and 401 may be adaptively adjusted according to the present application, which is not described herein.

The memory array 310 shown in fig. 11 includes the memory cells shown in fig. 10. The arrangement of the individual signal lines in the memory array shown in fig. 11 is similar to that of fig. 9. The difference is that the transistor types of the first transistor T1 and the second transistor T2 are adjusted, i.e. the first transistor T1 is a PMOS transistor and the second transistor T2 is an NMOS transistor.

Fig. 12 is a circuit diagram of another memory cell 400 according to an embodiment of the present application. The memory cell 400 is similar in circuit configuration to the memory cell 400 shown in fig. 10 described above. In contrast, the first transistor T1 in the memory cell 400 of fig. 12 is an NMOS transistor, and the second transistor T2 is a PMOS transistor. Accordingly, the first transistor T1 is turned on when the precharge line CL is at a high level, and is turned off when the precharge line CL is at a low level. For the read/write operation of the memory unit 400, the read/write logic of the memory units 401, 401 and 401 may be adaptively adjusted according to the present application, which is not described herein.

The memory array 310 shown in fig. 13 includes the memory cells shown in fig. 12. The arrangement of the individual signal lines in the memory array shown in fig. 13 is similar to that of fig. 11. The difference is that the transistor types of the first transistor T1 and the second transistor T2 are adjusted, i.e. the first transistor T1 is an NMOS transistor and the second transistor T2 is a PMOS transistor.

In the present application, the first transistor T1 and the second transistor T2 may be Gate-All-Around Field-Effect Transistor (GAA FET) or may be Channel-All-Around Field-Effect Transistor (CAA FET).

Fig. 14 illustrates an alternative CAA FET structure of the first transistor T1 and the second transistor T2, which includes a first electrode layer 11, a dielectric layer 12 and a second electrode layer 13 stacked in this order, where one of the first electrode layer 11 and the second electrode layer 13 may be a source of the transistor and the other electrode layer may be a drain of the transistor. Grooves are formed in the stacked first electrode layer 11, dielectric layer 12 and second electrode layer 13, channel layers 14 are formed on the side wall surfaces and bottom surfaces of the grooves, gate layers 16 are formed on the channel layers 14, and the gate layers 16 and the channel layers 14 are isolated by gate insulating layers 15, that is, the channel layers 14 surround the periphery of the gate layers 16.

Fig. 15 shows a process configuration diagram of the first transistor T1 and the second transistor T2 in the memory cell 400, and the write bit line WBL, the read bit line RBL, the precharge line CL, the source line SL, and the word line WL when the first transistor T1 and the second transistor T2 each adopt the transistor structure shown in fig. 14.

In connection with the memory cell 400 structure of fig. 15, the first transistor T1 and the second transistor T2 are arranged along the Z direction, the gate layer 116 of the first transistor T1 is electrically connected to the precharge line CL located thereon, and the write bit line WBL is wound around the periphery of the second electrode layer 113 of the first transistor T1 and is electrically connected thereto. The gate layer 216 of the second transistor T2 is electrically connected to the first electrode layer 111 of the first transistor T1 through the floating gate FG, and the source line SL surrounds and is electrically connected to the outer periphery of the second electrode layer 213 of the second transistor T2, and the read bit line RBL is located under and is electrically connected to the first electrode layer 211 of the second transistor T2.

With continued reference to fig. 15, a Floating Gate (FG) structure is provided between the gate layer 216 of the second transistor T2 and the first electrode layer 111 of the first transistor T1, that is, the gate layer 216 of the second transistor T2 and the first electrode layer 111 of the first transistor T1 are electrically connected through the floating gate FG. In the achievable process, the floating gate FG may be made of at least one of tungsten W, titanium nitride TiN, polysilicon, cobalt Co, nickel Ni, and copper Cu, and the gate layer 216 may be made of at least one of tungsten W, titanium nitride TiN, polysilicon, cobalt Co, nickel Ni, and copper Cu.

In combination with the memory cell 400 of fig. 15, the ferroelectric film layer 2 for storing charges is disposed around the floating gate FG, and the word line WL is disposed around the periphery of the ferroelectric film layer 2, the floating gate FG serves as one electrode of the ferroelectric capacitor, and writing of stored information is completed by a voltage difference with the word line WL; in addition, the floating gate FG is electrically connected to the gate layer 216 of the second transistor T2, and in the reading stage, the voltages on the floating gate FG are different due to the difference of the stored information, so as to control the on or off of the second transistor T2, so as to realize the reading of the stored information in the ferroelectric film layer 2. In the memory cell 400 shown in fig. 15, four ferroelectric capacitors are exemplarily shown, and these ferroelectric capacitors are arranged at intervals along the extending direction of the floating gate FG.

Fig. 16 shows a process structure diagram of a memory array 310, in which memory array 310 includes memory cells having the structure shown in fig. 15, for example, in memory array 310 shown in fig. 16, four memory cells, namely, memory cell 401, memory cell 402, memory cell 403 and memory cell 404 are arranged along the X direction, and three memory cells, namely, memory cell 404, memory cell 405 and memory cell 406 are arranged along the Y direction perpendicular to the X direction, so that a 4X3 memory array is formed.

As shown in fig. 16, in the memory array 310, the floating gate FG extends in a Z direction perpendicular to both the X direction and the Y direction, and when the memory array is formed on the substrate of the memory, the Z direction is a direction perpendicular to the substrate, that is, the floating gate FG extends in a direction perpendicular to the substrate, and further, the ferroelectric capacitors such as the ferroelectric capacitor C1, the ferroelectric capacitor C2, the ferroelectric capacitor C3, and the ferroelectric capacitor C4 in each memory cell are arranged at intervals in a direction perpendicular to the substrate, so that more ferroelectric capacitors can be provided in each memory cell to improve the storage density of the ferroelectric memory and the storage capacity.

In the memory array 310 shown in fig. 16, each write bit line WBL extends in the X direction so that a plurality of memory cells arranged in the X direction can share the write bit line WBL. Each of the read bit lines RBL extends in the X direction, and thus a plurality of memory cells arranged in the X direction may share the read bit line RBL. Each of the precharge lines CL extends in the Y direction so that a plurality of memory cells arranged in the Y direction may share the precharge line CL.

Continuing with fig. 16, in the memory array, all source lines SL are connected to each other, and in implementation, a metal layer may be disposed along a plane parallel to the substrate, where the metal layer is a source line SL layer (SL plate) structure, and the source line SL layer structure surrounds the first electrode layer 211 of all the second transistors T2 in the memory array to form a common source line SL structure.

Referring again to fig. 16, since each memory cell has a plurality of ferroelectric capacitors arranged in the Z direction, for example, each memory cell in fig. 16 has four ferroelectric capacitors, and thus, a plurality of ferroelectric capacitors are provided in an X-Y plane perpendicular to the Z direction, and the plurality of ferroelectric capacitors located in the X-Y plane share a word line WL, in a possible structure, for example, as shown in fig. 10, a metal layer may be disposed in the X-Y plane as a word line WL layer (WL plate) structure surrounding all of the ferroelectric film layers of the ferroelectric capacitors of the X-Y plane to form a shared word line WL structure.

In the structure shown in fig. 16, the second transistor T2 may be disposed close to the substrate with respect to the first transistor T1. In other alternative embodiments, the first transistor T1 may be disposed closer to the substrate than the second transistor T2.

In order to facilitate the electrical connection of the plurality of word line WL layer structures with the controller for controlling the voltage thereof, as shown in fig. 17, a plurality of word lines WL extending in the Y direction may be provided, and the word lines WL may be in the same plane as the precharge lines CL, since the word line WL and the word line WL layer structures are in different planes, it is necessary to provide conductive paths to electrically connect the word lines WL and the corresponding word line WL layer structures.

Fig. 18 shows another process configuration diagram of the first transistor T1 and the first transistor T2 in the memory cell 400, and the write bit line WBL, the read bit line RBL, the precharge line CL, the source line SL, and the word line WL when the first transistor T1 and the first transistor T2 each adopt the transistor configuration shown in fig. 14, and fig. 19 shows a process configuration diagram of the memory array 310 including the memory cell of fig. 18.

The structure shown in fig. 18 and 19 is different from the structure shown in fig. 15 and 16 described above in that the arrangement positions of the read bit line RBL and the source line SL are different, and in the structure shown in fig. 18 and 19, the read bit line RBL is wound around and electrically connected to the outer periphery of the second electrode layer 213 of the second transistor T2, and the source line SL is located under and electrically connected to the first electrode layer 211 of the second transistor T2. Similarly, in the memory array 310, as shown in fig. 19, all the source lines SL are connected to each other, for example, a source line SL layer structure may be formed, which surrounds the first electrode layers 211 of all the second transistors T2 in the memory array to form a common source line SL structure.

Fig. 20 illustrates an alternative structure of the first transistor T1 and the second transistor T2, which is a gate-all-around field effect transistor GAA FET structure, as shown in fig. 20, which includes a stacked first electrode layer 11 and second electrode layer 13, where one of the first electrode layer 11 and the second electrode layer 13 may be a source of the transistor and the other electrode layer may be a drain of the transistor. Between the stacked first electrode layer 11 and second electrode layer 13, there is a channel layer 14, and a gate layer 16 surrounding the periphery of the channel layer 14, and isolated between the channel layer 14 and the gate layer 16 by a gate insulating layer 15.

Fig. 21 shows a process configuration of the first transistor T1 and the first transistor T2 in the memory cell 400, and the write bit line WBL, the read bit line RBL, the precharge line CL, the source line SL, and the word line WL when the first transistor T1 adopts the transistor structure shown in fig. 20 and the second transistor T2 adopts the transistor structure shown in fig. 14.

In the memory cell 400 shown in fig. 21, the floating gate FG for electrically connecting the first transistor T1 and the second transistor T2 also extends along the Z direction, and the plurality of ferroelectric capacitors are also arranged at intervals along the Z direction, so that, like the above-mentioned memory cell structure, the number of integration of the ferroelectric capacitors can be increased, and the memory density can be further increased.

In a possible process, when the second transistor T2 is manufactured, the gate layer 216 on the second transistor T2 may be extended along the Z direction to form the floating gate FG, so that the first transistor T1 and the second transistor T2 are electrically connected through the floating gate FG, which may be understood as an integral structure with the gate layer 261 of the second transistor T2.

Since the first transistor T1 shown in fig. 21 adopts a gate-all-around FET GAA structure, the precharge line CL surrounds and is electrically connected to the periphery of the gate layer 116 of the first transistor T1, and the write bit line WBL is located above and is electrically connected to the second electrode layer 113 of the first transistor T1, as shown in fig. 21.

Fig. 22 shows a process structure diagram of a memory array 310, in which memory cells of the structure shown in fig. 21 are included in the memory array 310, and as can be seen from fig. 22, each write bit line WBL extends in the X direction so that a plurality of memory cells arranged in the X direction can share the write bit line WBL. Each of the precharge lines CL extends in the Y direction so that a plurality of memory cells arranged in the Y direction may share the precharge line CL. Each of the read bit lines RBL extends in the X direction, and thus a plurality of memory cells arranged in the X direction may share the read bit line RBL.

As in the process configuration of the memory array shown above, in the memory array, the source lines SL of the plurality of memory cells are connected to each other, and for example, a common source line SL structure may be formed by forming a one-layer source line SL layer structure. Also includes the following components: the multi-layer word line WL layer structure is arranged such that each of the word line WL layer structures is electrically connected to a ferroelectric film layer of a ferroelectric capacitor in the X-Y plane.

Fig. 23 shows another process configuration diagram of the first transistor T1 and the first transistor T2 in the memory cell 400, and the write bit line WBL, the read bit line RBL, the precharge line CL, the source line SL, and the word line WL when the first transistor T1 adopts the transistor configuration shown in fig. 20 and the second transistor T2 adopts the transistor configuration shown in fig. 14, and fig. 24 shows a process configuration diagram of the memory array 310 including the memory cell of fig. 23.

The structure shown in fig. 23 and 24 is different from the structure shown in fig. 21 and 22 described above in that the arrangement positions of the read bit line RBL and the source line SL are different, and in the structure shown in fig. 23 and 24, the read bit line RBL is wound around and electrically connected to the outer periphery of the second electrode layer 213 of the second transistor T2, and the source line SL is located under and electrically connected to the first electrode layer 211 of the second transistor T2.

Fig. 25 is a circuit diagram of another memory cell 400 according to an embodiment of the present application, where the memory cell 400 includes a first transistor T1, a second transistor T2, a ferroelectric capacitor C1, and a floating gate FG. The first end of the first transistor T1 is electrically connected to the floating gate FG, the second end is electrically connected to the precharge line CL, and the control end of the first transistor T1 is electrically connected to a Bit Line (BL). In addition, a first terminal of the second transistor T2 is electrically connected to the source line SL, a second terminal is electrically connected to the bit line BL, a control terminal of the second transistor T2 is electrically connected to the floating gate FG, a first terminal of the ferroelectric capacitor C1 is electrically connected to the floating gate FG, and a second terminal of the ferroelectric capacitor C1 is electrically connected to the word line WL.

In other alternative embodiments, the memory cell 400 may further include more ferroelectric capacitors, and the exemplary illustration of fig. 25 further includes a ferroelectric capacitor C2, and a first terminal of the ferroelectric capacitor C2 is also electrically connected to the floating gate FG, and a second terminal of the ferroelectric capacitor C2 is electrically connected to the unselected word line ensel WL.

Shown in fig. 26 is a circuit diagram of a memory array 310 comprising the memory cells shown in fig. 25. The memory array 310 may include a plurality of memory cells arranged in an array, such as in fig. 26, a memory array including four memory cells of memory cell 401, memory cell 402, memory cell 403, and memory cell 404 is exemplarily shown. One skilled in the art can design the arrangement of the memory cells 400 and the number of memory cells 400 in the memory array 310 according to the storage capacity requirements of the ferroelectric memory. In one embodiment, the memory array 310 may further include more memory cells 400, and the memory cells 400 may be arranged in an X direction, a Y direction, and a Z direction perpendicular to each other to form a three-dimensional memory array.

In the memory array 310 shown in fig. 26, each precharge line CL extends along the Y direction, and when the memory array 310 further includes more memory cells, then the memory array further includes more unselected precharge lines Unsel CL, which are arranged in parallel along the X direction perpendicular to the Y direction, and further, the plurality of memory cells arranged along the Y direction may share one precharge line, for example, the memory cell 401 and the memory cell 402 share the selected precharge line CL, and the memory cell 403 and the memory cell 404 share the unselected precharge line Unsel CL.

With continued reference to fig. 26, the memory array 310 includes two bit lines BL, each of which extends in the X direction, and further includes further bit lines BL which are arranged in parallel in the Y direction perpendicular to the X direction, and further, a plurality of memory cells arranged in the X direction may share one bit line BL, for example, the memory cell 401 and the memory cell 403 share a selected bit line BL, and the memory cell 402 and the memory cell 404 share an unselected bit line unel BL.

The first transistor T1 and the second transistor T2 in the memory cell 400 shown in fig. 25 and 26 may be the transistor structures shown in fig. 14 or 20, and the two transistor structures will not be described in detail herein.

Fig. 27 is a process structure diagram of an alternative to the structure shown in fig. 25, and it can be seen from fig. 27 that the floating gate FG extends in a Z direction perpendicular to both the X direction and the Y direction, and when the memory array is formed on the substrate of the memory, the Z direction may be a direction perpendicular to the substrate, that is, the floating gate FG extends in a direction perpendicular to the substrate, and further, the ferroelectric capacitors such as the ferroelectric capacitor C1, the ferroelectric capacitor C2, the ferroelectric capacitor C3, and the ferroelectric capacitor C4 in each memory cell are arranged at intervals in a direction perpendicular to the substrate, so that more ferroelectric capacitors can be disposed in each memory cell to improve the storage density and the storage capacity of the ferroelectric memory.

Also, as shown in fig. 27, in the memory array, all source lines SL are connected to each other, and in implementation, a source line SL layer structure may be formed, and the source line SL layer structure surrounds the first electrode layers 211 of all the second transistors T2 in the memory array to form a common source line SL structure.

Referring again to fig. 27, a plurality of ferroelectric capacitors located in the X-Y plane share a word line WL, so as in fig. 26, a word line WL layer structure may be disposed in the X-Y plane, and the word line WL layer structure surrounds all ferroelectric capacitor ferroelectric film layers of the X-Y plane to form a shared word line WL structure.

Since the first transistor T1 and the second transistor T2 are both required to be electrically connected to the bit line BL, in an alternative process structure, in combination with fig. 27, the bit line BL includes a first portion bit line BL and a second portion bit line BL, the first portion bit line BL is disposed close to the first transistor T1, the second portion bit line BL is disposed close to the second transistor T2, and both the first portion bit line BL and the second portion bit line BL extend in the X direction, and both the first portion bit line BL and the second portion bit line BL are electrically connected through conductive paths so that both the first transistor T1 and the second transistor T2 are electrically connected to the bit line BL.

In fig. 27, control terminals of first transistors T1 in a plurality of memory cells arranged in the X direction are electrically connected to a first part of bit lines BL; first ends of the second transistors T2 in the plurality of memory cells arranged in the X direction are electrically connected to the second partial bit line BL.

From the above-described process structure of memory cells, and the process structure of memory arrays, it can be seen that each memory cell 400 includes a first transistor T1, a second transistor T2, a floating gate FG, and at least one ferroelectric capacitor. And the floating gate FG is arranged in a direction perpendicular to the substrate, and the first transistor T1 and the second transistor T2 are respectively located at opposite ends of the floating gate FG, and when there are a plurality of ferroelectric capacitors, the plurality of ferroelectric capacitors are arranged at intervals along the extending direction of the floating gate FG, i.e., along the direction perpendicular to the substrate. In this way, the occupied area of each memory cell on the substrate can be reduced, so that more memory cells are integrated in a unit area, the memory density is improved, and the memory capacity is improved.

In addition, in the memory array provided by the application, a plurality of ferroelectric capacitors positioned in a plane parallel to the substrate can share one word line WL, for example, a layer of word line WL layer structure can be arranged to electrically connect a plurality of ferroelectric capacitors positioned in the same plane, so that the number of word lines WL can be reduced, the wiring mode of the word lines WL can be simplified, and the memory density can be further improved.

Similarly, in the memory array provided by the application, a plurality of source lines SL located in a plane parallel to the substrate may be connected to each other, for example, by providing a layer of word line source line SL layer structure as shown above, so that the number of source lines SL may be reduced, and the wiring manner of the source lines SL may be simplified, so as to further improve the memory density. In addition, in the memory cell provided by the application, the reading window can be increased on the basis of improving the memory density.

In some alternative embodiments, more memory cells may be required to form a larger area memory array, thereby further increasing memory capacity. For example, as shown in fig. 28, the memory includes a memory array 3101 and a memory array 3102 arranged along the X direction, and the memory array 3101 and the memory array 3102 may be formed by using the memory cell of any one of fig. 4 to 24. Of course, the memory may include more memory arrays, which are arranged in three dimensions along the X direction, the Y direction, and the Z direction perpendicular to each other when there are a plurality of memory arrays as shown in fig. 28.

In the structure shown in fig. 28, in the memory arrays 3101 and 3102, a plurality of memory cells arranged in the X direction share the write bit line WBL, for example, the memory cell 401 in the memory array 3101, the memory cell 403, and the memory cell 401 and the memory cell 403 in the memory array 3102 share the write bit line WBL0. Also, in the memory arrays 3101 and 3102, a plurality of memory cells arranged in the X direction share the read bit line RBL, for example, the memory cell 401 in the memory array 3101, the memory cell 403, and the memory cell 401 and the memory cell 403 in the memory array 3102 share the Local read bit line (Local RBL 0). In the plurality of memory arrays shown in fig. 28, the word lines WL located in the same X-Y plane are not electrically connected, for example, the word line WL1 in the memory array 3101 and the word line WL3 in the memory array 3102 in fig. 28 are independent of each other, and are not electrically connected and coupled.

Then, in the memory shown in fig. 28, when performing a read/write operation, it is required to select whether to read/write the memory array 3101 or to read/write the memory array 3102, and further, in the memory shown in fig. 28, a third transistor T3 is further included, for example, in fig. 28, a third transistor T31 and a third transistor T32 are shown, where a first end of the third transistor T31 is electrically connected to the Local read bit line Local RBL0, a second end is electrically connected to the global read bit line (global RBL 0), a control end of the third transistor T31 is electrically connected to the multiplexer control line (multiplexor control line, MUX CNTL), and an electrical connection relationship between the third transistor T32 and the Local read bit line Local RBL1 and the multiplexer control line is similar to the third transistor T31, which is not explained herein.

So designed, when the voltages of the multiplexer control line and the local read bit line can select whether the third transistor T31 is turned on or the third transistor T32 is turned on, the memory array to be read or written is determined.

Fig. 29 shows a process configuration diagram including the circuit configuration shown in fig. 28, and in conjunction with fig. 29, local write bit lines (Local WBL) of a plurality of memory arrays located in the X direction are electrically connected through global write bit lines (global WBL), local multiplexer control lines (MUX CNTL) are formed between the global write bit lines (global WBL) and global read bit lines (global RBL) in order to increase the memory density, and the Local multiplexer control lines (MUX CNTL) are electrically connected to a plurality of third transistors T3 through a plurality of conductive paths.

Fig. 30 shows another memory circuit diagram including a plurality of memory arrays, in which a memory array 3101 and a memory array 3102 arranged along the X direction are also illustrated, and the memory array 3101 and the memory array 3102 may be formed using the memory array structure formed by any of the memory cells in fig. 4 to 24 described above. Of course, it is also possible to include more memory arrays, which are arranged in three dimensions along the X direction, the Y direction, and the Z direction perpendicular to each other when there are a plurality of memory arrays as shown in fig. 30.

The memory shown in fig. 30 is different from the memories shown in fig. 28 and 29 described above in that, among the plurality of memory arrays laid out in the X direction, the word lines WL located in the same X-Y plane are electrically connected, for example, the word line in the memory array 3101 of fig. 30 and the word line of the memory array 3102 share the word line WL0, and the word line WL0 in the memory array 3101 and the memory array 3102 and share the word line WL1.

In this memory, the read bit line RBL of the memory array 3101 and the read bit line RBL of the memory array 3102 are disconnected from each other, and are not connected to each other; the write bit line WBL of the memory array 3101 and the write bit line WBL of the memory array 3102 are disconnected and not connected. For example, in fig. 30, the Local read bit line Local RBL0 is disconnected from the Local read bit line Local RBL2, the Local read bit line Local RBL1 is disconnected from the Local read bit line Local RBL3, the Local write bit line Local WBL0 is disconnected from the Local write bit line Local WBL2, and the Local write bit line Local WBL1 is disconnected from the Local write bit line Local WBL 3.

Then, in the memory shown in fig. 30, when performing a read/write operation, it is necessary to select whether to read/write the memory array 3101 or to read/write the memory array 3102, and further, in the memory shown in fig. 30, not only the third transistor T3 but also the fourth transistor T4 are included, for example, in fig. 30, the third transistor T31 and the third transistor T32, and the fourth transistor T41 and the fourth transistor T42 are illustrated.

Wherein the Local read bit line Local RBL0 is disconnected from the Local read bit line Local RBL2, the Local read bit line Local RBL1 is disconnected from the Local read bit line Local RBL3, a first terminal of the third transistor T31 is electrically connected to the Local read bit line Local RBL0, a second terminal is electrically connected to the global read bit line (global RBL 0), a control terminal of the third transistor T31 is electrically connected to the multiplexer control line (MUX CNTL), an electrical connection relationship between the third transistor T32 and the Local read bit line Local RBL1 and the multiplexer control line is similar to that of the third transistor T31.

The fourth transistor T41 has a first terminal electrically connected to the Local write bit line Local WBL0, a second terminal electrically connected to the global write bit line (global WBL 0), a control terminal electrically connected to the multiplexer control line (MUX CNTL) of the fourth transistor T41, and a fourth transistor T42 electrically connected to the Local write bit line Local WBL1 and the Local multiplexer control line, similar to the fourth transistor T41. In this way, the memory array to be read from or written to can be selected by matching the third transistor and the fourth transistor.

Fig. 31 shows a process structure diagram including the circuit structure shown in fig. 30, in order to enhance the memory density, a multiplexer control line (MUX CNTL) is formed between a global write bit line (global WBL) and a global read bit line (global RBL), a third transistor T3 is disposed close to the global read bit line and the local read bit line, and a fourth transistor T4 is disposed close to the global write bit line and the local write bit line, and the third transistor T3 and the fourth transistor T4 are electrically connected to the multiplexer control line (MUX CNTL), and further, a conductive path needs to be provided between the global write bit line and the global read bit line, so that the multiplexer control line (MUX CNTL) is electrically connected to the third transistor T3 and the fourth transistor T4 at different positions. Of course, other arrangements may be used in addition to the arrangement shown in fig. 31.

The ferroelectric memory according to the present application can be manufactured by back end of line (BEOL), and fig. 32 shows a schematic diagram of the back end of line. In fig. 32, the control circuit is fabricated on the substrate by the front end of line FEOL. The control circuitry may include one or more of the decoder 320, the driver 330, the timing controller 340, the buffer 350, or the input-output driver 360 as shown in fig. 3, and may also include other functional circuitry. The control circuit may control the signal lines (word line WL, source line SL, write bit line WBL, read bit line RBL, precharge line CL, etc.) in the embodiment of the present application. After the front end of line FEOL is completed, both interconnect lines and memory arrays are fabricated by the back end of line BEOL. The memory array herein, as previously described, includes ferroelectric capacitors and transistors in the memory cells, as well as portions of the signal lines. The interconnect lines include both interconnect lines connecting devices in the control circuit and other portions of the signal lines. The transistors in the memory array are manufactured through a subsequent process, so that the circuit density in the unit area is higher, and the performance of the unit area is improved.

Another process structure cross-section corresponding to memory cell 400 is shown in fig. 33, wherein the control circuit is fabricated by a front end of line FEOL and the transistors in the memory array are also fabricated by a front end of line FEOL, where the transistors refer to the transistors in the memory cell that are disposed near the substrate. Furthermore, the interconnect line, as well as the ferroelectric capacitor in the memory array and the other transistor in the memory cell, are fabricated by the back-end-of-line BEOL. Because the ferroelectric capacitors in the memory array and one transistor in each memory cell are fabricated by the back-end-of-line BEOL, the circuit density per unit area can be made larger, thereby improving the performance per unit area.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A ferroelectric memory, comprising:

a substrate;

a plurality of memory cells formed on the substrate;

each of the memory cells includes: a first transistor, a second transistor, and a floating gate, and a first ferroelectric capacitor;

the floating gate extends along the direction perpendicular to the substrate, the first transistor and the second transistor are positioned at two opposite ends of the floating gate, and the first transistor and the second transistor are electrically connected with the floating gate;

the first ferroelectric capacitor is arranged at the periphery of the floating gate and is electrically connected with the floating gate.
The ferroelectric memory of claim 1, further comprising: a first word line layer in a first plane parallel to the substrate;

a plurality of the first ferroelectric capacitors located in the first plane are interconnected by the first word line layer.
The ferroelectric memory of claim 2, wherein the first ferroelectric capacitor comprises a ferroelectric film layer surrounding a portion of the floating gate;

the first word line layer encapsulates the plurality of ferroelectric film layers in the first plane.
The ferroelectric memory according to claim 2 or 3, wherein each of the memory cells further includes a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor are arranged at intervals along an extending direction of the floating gate;

the ferroelectric memory further comprises a second word line layer, wherein the second word line layer is positioned in a second plane, and the second plane is parallel to the first plane;

a plurality of the second ferroelectric capacitors located in the second plane are interconnected by the second word line layer.
The ferroelectric memory of any one of claims 1-4, further comprising: the source line layer is positioned in a third plane parallel to the substrate;

First ends of the plurality of second transistors located in the third plane are interconnected by the source line layer.
The ferroelectric memory of any one of claims 1-5, wherein the first transistor, the second transistor, and the floating gate, and the first ferroelectric capacitor are fabricated using a back-end process.
The ferroelectric memory of any one of claims 1-6, further comprising:

precharge lines, write bit lines, read bit lines, and source lines, and word lines;

the control end of the first transistor is electrically connected with the pre-charge line, the first end of the first transistor is electrically connected with the floating gate, and the second end of the first transistor is electrically connected with the write bit line;

the control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the read bit line;

the first end of the first ferroelectric capacitor is electrically connected with the floating gate, and the second end of the first ferroelectric capacitor is electrically connected with the word line.
The ferroelectric memory of claim 7, wherein the write bit line extends in a first direction parallel to the substrate, the precharge line extends in a second direction parallel to the substrate, the first direction being perpendicular to the second direction;

Second ends of the first transistors in the plurality of memory cells arranged along the first direction are electrically connected with the write bit line;

the control terminals of the first transistors in the plurality of memory cells arranged in the second direction are electrically connected to the precharge line.
The ferroelectric memory of claim 8, wherein the read bit line extends along the first direction;

the second ends of the second transistors in the plurality of memory cells arranged along the first direction are electrically connected with the read bit line.
The ferroelectric memory according to claim 8 or 9, wherein the ferroelectric memory comprises a first memory array and a second memory array arranged along the first direction, each of the first memory array and the second memory array comprising the plurality of memory cells;

the word lines of the first memory array extending in the first direction are disconnected from the word lines of the second memory array extending in the first direction;

the write bit lines of the first memory array extending in the first direction are connected to the write bit lines of the second memory array extending in the first direction;

The read bit lines of the first memory array extending in the first direction are connected to the read bit lines of the second memory array extending in the first direction;

the ferroelectric memory further includes:

a third transistor, a multiplexer control line, and a global read bit line; the control end of the third transistor is electrically connected with the multiplexer control line, the first end of the third transistor is electrically connected with the global read bit line, and the second end of the third transistor is electrically connected with the read bit line connected with the first memory array and the second memory array.
The ferroelectric memory according to claim 8 or 9, wherein the ferroelectric memory comprises a first memory array and a second memory array arranged along the first direction, each of the first memory array and the second memory array comprising the plurality of memory cells;

the word lines of the first memory array extending in the first direction are connected to the word lines of the second memory array extending in the first direction;

the write bit lines of the first memory array extending in the first direction are disconnected from the write bit lines of the second memory array extending in the first direction;

The read bit lines of the first memory array extending in the first direction are disconnected from the read bit lines of the second memory array extending in the first direction;

the ferroelectric memory further includes:

a third transistor, a fourth transistor, a multiplexer control line and a global read bit line, and a global write bit line; the control end of the third transistor is electrically connected with the multiplexer control line, the first end of the third transistor is electrically connected with the global read bit line, the second end of the third transistor is electrically connected with the read bit line in the first memory array, the control end of the fourth transistor is electrically connected with the multiplexer control line, the first end of the fourth transistor is electrically connected with the global write bit line, and the second end of the fourth transistor is electrically connected with the write bit line in the first memory array.
Ferroelectric memory according to any one of claims 7 to 11, characterized in that,

in the writing stage, the precharge line is used for receiving a first precharge control signal so that the first transistor is conducted, the writing bit line is used for receiving a first writing bit line control signal, the word line is used for receiving a first word line control signal, and the voltage difference of the first word line control signal and the first writing bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to be polarized.
The ferroelectric memory according to claim 12, wherein,

in a first reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is conducted, the write bit line is used for receiving a second write bit line control signal, the word line is used for receiving a second word line control signal, the voltage difference between the second word line control signal and the second write bit line control signal enables a ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, and the polarization state of the ferroelectric film layer is kept unchanged;

in a second reading stage, the precharge line is used for receiving a second precharge control signal so that the first transistor is turned off, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal smaller than the voltage of the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line enables the first ferroelectric capacitor to be turned from positive polarization to negative polarization so that the voltage of the floating gate control signal on the floating gate is reduced, and the second transistor is turned off;

in a third reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is turned on, the write bit line is used for receiving the first write bit line control signal, the word line is used for receiving the first word line control signal, and the voltage difference between the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate positive polarization.
The ferroelectric memory according to claim 12, wherein,

in a first reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is conducted, the write bit line is used for receiving a second write bit line control signal, the word line is used for receiving a second word line control signal, the voltage difference between the second word line control signal and the second write bit line control signal enables a ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, and the polarization state of the ferroelectric film layer is kept unchanged;

in a second reading stage, the precharge line is used for receiving a second precharge control signal, so that the first transistor is turned off, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal smaller than the voltage of the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line keeps the negative polarity state of the first ferroelectric capacitor unchanged, the voltage of the floating gate control signal on the floating gate is unchanged, and the second transistor is turned on;

in a third reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is turned on, the write bit line is used for receiving the first write bit line control signal, the word line is used for receiving the first word line control signal, and the voltage difference between the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate negative polarization.
Ferroelectric memory according to any one of claims 12 to 14, characterized in that,

in the standby stage, the write bit line is used for receiving the first write bit line control signal, the word line is used for receiving the first word line control signal, and the voltage difference between the first word line control signal and the first write bit line control signal enables the polarization state of the ferroelectric film layer of the first ferroelectric capacitor to be kept unchanged.
The ferroelectric memory according to claim 15, wherein in the writing phase, the first reading phase, the third reading phase, and the standby phase;

the source line is used for receiving a source line control signal, the read bit line is used for receiving a second read bit line control signal, and the voltage values of the source line control signal and the second read bit line control signal are equal.
The ferroelectric memory of any one of claims 12-16, further comprising a controller to:

outputting a precharge control signal to control a voltage on the precharge line;

outputting a write bit line control signal to control a voltage on the write bit line;

outputting a word line control signal to control a voltage on the word line;

Outputting a source line control signal to control a voltage on the source line; and

a read bit line control signal is output to control a voltage on the read bit line.
The ferroelectric memory of any one of claims 1-6, further comprising:

precharge lines, word lines, bit lines, and source lines;

the control end of the first transistor is electrically connected with the bit line, the first end of the first transistor is electrically connected with the floating gate, and the second end of the first transistor is electrically connected with the pre-charge line;

the control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the bit line;

the first end of the first ferroelectric capacitor is electrically connected with the floating gate, and the second end of the first ferroelectric capacitor is electrically connected with the word line.
The ferroelectric memory of claim 18, wherein the bit line comprises a first portion of bit lines disposed proximate to the first transistor and a second portion of bit lines proximate to the second transistor, the first portion of bit lines and the second portion of bit lines each extending in a first direction parallel to the substrate, and the first portion of bit lines and the second portion of bit lines being electrically connected by conductive vias;

The control ends of the first transistors in the memory cells arranged along the first direction are electrically connected with the first part of bit lines;

first ends of the second transistors in the plurality of memory cells arranged along the first direction are electrically connected to the second part of bit lines.
The ferroelectric memory of claim 19, wherein the precharge line extends in a second direction parallel to the substrate, the first direction being perpendicular to the second direction;

the second terminals of the first transistors in the plurality of memory cells arranged in the second direction are electrically connected to the precharge line.
A ferroelectric memory, comprising:

precharge lines, write bit lines, read bit lines, and source lines, and word lines;

a plurality of memory cells, each of the memory cells comprising:

a first transistor, a second transistor, and a floating gate, and a first ferroelectric capacitor;

the control end of the first transistor is electrically connected with the pre-charge line, the first end of the first transistor is electrically connected with the floating gate, and the second end of the first transistor is electrically connected with the write bit line;

The control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the read bit line;

the first end of the first ferroelectric capacitor is electrically connected with the floating gate, and the second end of the first ferroelectric capacitor is electrically connected with the word line.
The ferroelectric memory of claim 21, wherein the write bit line extends in a first direction and the precharge line extends in a second direction, the first direction being perpendicular to the second direction;

second ends of the first transistors in the plurality of memory cells arranged along the first direction are electrically connected with the write bit line;

the control terminals of the first transistors in the plurality of memory cells arranged in the second direction are electrically connected to the precharge line.
The ferroelectric memory of claim 22, wherein the read bit line extends along the first direction;

the second ends of the second transistors in the plurality of memory cells arranged along the first direction are electrically connected with the read bit line.
The ferroelectric memory of any one of claims 21-23, wherein the first transistor, the second transistor, and the floating gate, and the first ferroelectric capacitor are fabricated using a back-end process.
Ferroelectric memory according to any one of claims 21 to 24, characterized in that,

in the writing stage, the precharge line is used for receiving a first precharge control signal so that the first transistor is conducted, the writing bit line is used for receiving a first writing bit line control signal, the word line is used for receiving a first word line control signal, and the voltage difference of the first word line control signal and the first writing bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to be polarized.
The ferroelectric memory of claim 25, wherein,

in a first reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is conducted, the write bit line is used for receiving a second write bit line control signal, the word line is used for receiving a second word line control signal, the voltage difference between the second word line control signal and the second write bit line control signal enables a ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, and the polarization state of the ferroelectric film layer is kept unchanged;

in a second reading stage, the precharge line is used for receiving a second precharge control signal so that the first transistor is turned off, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal smaller than the voltage of the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line enables the first ferroelectric capacitor to be turned from positive polarization to negative polarization so that the voltage of the floating gate control signal on the floating gate is reduced, and the second transistor is turned off;

In a third reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is turned on, the write bit line is used for receiving the first write bit line control signal, the word line is used for receiving the first word line control signal, and the voltage difference between the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate positive polarization.
The ferroelectric memory of claim 25, wherein,

in a first reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is conducted, the write bit line is used for receiving a second write bit line control signal, the word line is used for receiving a second word line control signal, the voltage difference between the second word line control signal and the second write bit line control signal enables a ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, and the polarization state of the ferroelectric film layer is kept unchanged;

in a second reading stage, the precharge line is used for receiving a second precharge control signal, so that the first transistor is turned off, the read bit line is used for receiving a first read bit line control signal, the word line is used for receiving a word line control signal smaller than the voltage of the second word line control signal, the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line keeps the negative polarity state of the first ferroelectric capacitor unchanged, the voltage of the floating gate control signal on the floating gate is unchanged, and the second transistor is turned on;

In a third reading stage, the precharge line is used for receiving the first precharge control signal so that the first transistor is turned on, the write bit line is used for receiving the first write bit line control signal, the word line is used for receiving the first word line control signal, and the voltage difference between the first word line control signal and the first write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to generate negative polarization.
Ferroelectric memory according to any one of claims 25 to 27, characterized in that,

in the standby stage, the write bit line is used for receiving the first write bit line control signal, the word line is used for receiving the first word line control signal, and the voltage difference between the first word line control signal and the first write bit line control signal enables the polarization state of the ferroelectric film layer of the first ferroelectric capacitor to be kept unchanged.
The ferroelectric memory of claim 28, wherein during the write phase, the first read phase, the third read phase, and the standby phase;

the source line is used for receiving a source line control signal, the read bit line is used for receiving a second read bit line control signal, and the voltage values of the source line control signal and the second read bit line control signal are equal.
An electronic device, comprising:

a processor; and

the ferroelectric memory of any one of claims 1 to 29, the processor and the ferroelectric memory being electrically connected.
A control method of a ferroelectric memory, characterized in that the ferroelectric memory comprises:

precharge line, write bit line, read bit line, source line, and word line; and

a plurality of memory cells, each of the memory cells comprising:

the device comprises a first transistor, a second transistor, a floating gate and a first ferroelectric capacitor, wherein the control end of the first transistor is electrically connected with the pre-charge line, the first end of the first transistor is electrically connected with the floating gate, the second end of the first transistor is electrically connected with the writing bit line, the first end of the first ferroelectric capacitor is electrically connected with the floating gate, the second end of the first ferroelectric capacitor is electrically connected with the word line, the control end of the second transistor is electrically connected with the floating gate, the first end of the second transistor is electrically connected with the source line, and the second end of the second transistor is electrically connected with the reading bit line;

the control method comprises the following steps: in the course of the write phase of the writing,

outputting a first precharge control signal to the precharge line to turn on the first transistor;

Outputting a first write bit line control signal to the write bit line;

and outputting a first word line control signal to the word line, wherein a voltage difference between the first word line control signal and the first write bit line control signal polarizes a ferroelectric film layer of the first ferroelectric capacitor.
The control method of a ferroelectric memory according to claim 31, further comprising:

in the first phase of the reading process,

outputting the first precharge control signal to the precharge line to turn on the first transistor; outputting a second write bit line control signal to the write bit line; outputting a second word line control signal to the word line, wherein the voltage difference between the second word line control signal and the second write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, and the polarization state of the ferroelectric film layer is kept unchanged;

in the second reading phase of the present invention,

outputting a second precharge control signal to the precharge line to turn off the first transistor; outputting a first read bit line control signal to the read bit line; outputting a word line control signal smaller than the voltage of the second word line control signal to the word line, wherein the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line causes the first ferroelectric capacitor to be inverted from positive polarization to negative polarization so as to reduce the voltage of the floating gate control signal on the floating gate, and the second transistor is turned off;

In the third phase of the read-out,

outputting the first precharge control signal to the precharge line to turn on the first transistor; outputting the first write bit line control signal to the write bit line; outputting the first word line control signal to the word line; wherein, the voltage difference between the first word line control signal and the first write bit line control signal causes the ferroelectric film layer of the first ferroelectric capacitor to generate positive polarization.
The control method of a ferroelectric memory according to claim 31, further comprising:

in the first phase of the reading process,

outputting the first precharge control signal to the precharge line to turn on the first transistor; outputting a second write bit line control signal to the write bit line; outputting a second word line control signal to the word line, wherein the voltage difference between the second word line control signal and the second write bit line control signal enables the ferroelectric film layer of the first ferroelectric capacitor to be in a half-selected state, and the polarization state of the ferroelectric film layer is kept unchanged;

in the second reading phase of the present invention,

outputting a second precharge control signal to the precharge line to turn off the first transistor; outputting a first read bit line control signal to the read bit line; outputting a word line control signal smaller than the voltage of the second word line control signal to the word line, wherein the voltage difference between the floating gate control signal on the floating gate and the word line control signal on the word line keeps the negative polarity state of the first ferroelectric capacitor unchanged, the voltage of the floating gate control signal on the floating gate is unchanged, and the second transistor is conducted;

In the third phase of the read-out,

outputting the first precharge control signal to the precharge line to turn on the first transistor; outputting the first write bit line control signal to the write bit line; outputting the first word line control signal to the word line; wherein, the voltage difference between the first word line control signal and the first write bit line control signal causes the ferroelectric film layer of the first ferroelectric capacitor to generate negative polarization.
The control method of a ferroelectric memory according to any one of claims 31 to 33, characterized in that the control method further comprises:

outputting a first word line control signal to the word line in a standby stage; outputting the first write bit line control signal to the write bit line, wherein a voltage difference between the first word line control signal and the first write bit line control signal keeps a polarization state of a ferroelectric film layer of the first ferroelectric capacitor unchanged.
The control method according to claim 34, characterized in that the control method further comprises:

and in the writing stage, the first reading stage, the third reading stage and the standby stage, controlling the source line and the reading bit line so that the voltage values of the source line control signal of the source line and the second reading bit line control signal of the reading bit line are equal.