CN117060942B - Compact gallium nitride receiving and dispatching front-end circuit - Google Patents
Compact gallium nitride receiving and dispatching front-end circuit Download PDFInfo
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- CN117060942B CN117060942B CN202311316801.4A CN202311316801A CN117060942B CN 117060942 B CN117060942 B CN 117060942B CN 202311316801 A CN202311316801 A CN 202311316801A CN 117060942 B CN117060942 B CN 117060942B
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 67
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 61
- 239000003990 capacitor Substances 0.000 claims description 72
- 101710135888 50S ribosomal protein L18 Proteins 0.000 claims description 6
- 101100206915 Arabidopsis thaliana TL17 gene Proteins 0.000 claims description 6
- 101710118659 Thylakoid lumenal 29 kDa protein, chloroplastic Proteins 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 229920006395 saturated elastomer Polymers 0.000 description 4
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- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 101100365516 Mus musculus Psat1 gene Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
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Abstract
The invention discloses a compact gallium nitride transceiving front-end circuit, which belongs to the field of semiconductor integrated circuits and comprises a gallium nitride broadband amplifier core and four gallium nitride high-power single-pole double-throw switches, wherein the four single-pole double-throw switches have solid line transceiving switching functions, and the input and output structures of the switches are transceiving symmetrical, so that the consistency of receiving and transmitting performances is realized, and the problems of weak burning resistance, high noise and low output power in the prior art are solved.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to a compact gallium nitride transceiver front-end circuit.
Background
The miniature, low cost and high integration degree are the development direction of electronic information systems in civil and national defense fields, and the receiving and transmitting front end is used as a radio frequency front end core, so that the method can be widely applied to various receiving and transmitting systems, and the application scene covers the fields of radar, communication, internet of things and the like. Although the transceiver front end is integrated into a single chip, two types of amplifier cores are required to be designed separately, a low noise amplifier at the receiving end requires low noise input and amplitude limiting functions, and a power amplifier at the transmitting end requires high power output; therefore, in terms of circuit structure, the receiving and transmitting links of the traditional GaAs asymmetric transceiver front end adopt different amplifying cores, the matching circuit structure is complex, and a large area is occupied; the appearance of GaN brings new opportunities for the development of a receiving and transmitting front end, the GaN has excellent burning resistance, a limiter is not needed to be introduced into a receiving end, the noise is lower, and the limiting low-noise amplifier can be replaced to be used as the receiving end. The GaN power density is 5-10 times of that of GaAs or even higher, and the requirement of high output power of the transmitting end can be met simultaneously, so that the transmitting and receiving front end is integrated on a single chip based on a GaN technology, the total area of the transmitting and receiving front end is smaller than that of a discrete chip, and the transmitting and receiving front end is more convenient to apply. However, gaN, which is the third generation semiconductor, has a dominant wafer size of 4 inches and GaAs is 6 inches compared to the more mature GaAs process; the cost per unit area of GaN of the actual flow sheet is 5 times that of GaAs. Therefore, it is important to reduce the front end area of the GaN-based process and the cost of the wafer.
Disclosure of Invention
Aiming at the problems of easy burning of the circuit, large interference noise, low output power and large area existing in the prior art, the invention provides a compact gallium nitride transceiver front-end circuit,
the technical scheme adopted by the invention for achieving the purpose is as follows:
the compact gallium nitride transceiver front-end circuit comprises a gallium nitride broadband amplifier core circuit, four single-pole double-throw switch circuits, a first matching circuit, a second matching circuit, a first core matching circuit, a second core matching circuit, a power supply port VG, a power supply port VD, a control interface CA and a control interface CB, wherein the four single-pole double-throw switches are sequentially connected in series, the first matching circuit is connected with the first single-pole double-throw switch circuit, the second matching circuit is connected with the third single-pole double-throw switch circuit, one end of the first core matching circuit is connected with the second single-pole double-throw switch circuit, the other end of the first core matching circuit is connected with the gallium nitride broadband amplifier core circuit, one end of the second core matching circuit is connected with the fourth single-pole double-throw switch circuit, the other end of the second core matching circuit is connected with the gallium nitride broadband amplifier core circuit, the VD VG and the power supply port are connected with the gallium nitride broadband amplifier core circuit, and the control interface CA and the control interface CB are connected between the third single-pole double-throw switch circuit and the fourth single-pole double-throw switch circuit.
Preferably, the first matching circuit comprises a capacitor C1 and an inductor L1, wherein one end of the capacitor C1 is connected with the first port, the other end of the capacitor C1 is connected with the inductor L1, and the other end of the inductor L1 is connected with the first single-pole double-throw switch circuit; the second matching circuit comprises a capacitor C7 and an inductor L5, wherein one end of the capacitor C7 is connected with the second port, the other end of the capacitor C7 is connected with the inductor L5, and the other end of the inductor L5 is connected with the third single-pole double-throw switch circuit; the first core matching circuit comprises a microstrip line TL7 and a capacitor C2, wherein one end of the microstrip line TL7 is connected with a resistor R2, the other end of the microstrip line TL is connected with the capacitor C2, and the other end of the capacitor C2 is connected with the gallium nitride broadband amplifier core circuit; the second core matching circuit comprises a microstrip line TL13 and a capacitor C6, wherein one end of the microstrip line TL13 is connected with a resistor R3, the other end of the microstrip line TL is connected with the capacitor C6, and the other end of the capacitor C6 is connected with the gallium nitride broadband amplifier core circuit.
Preferably, the gallium nitride broadband amplifier core circuit consists of an input matching circuit, a first bias circuit, a transistor T1, an interstage matching circuit, a transistor T2, a second bias circuit, an output matching circuit, a drain bias circuit and a negative feedback circuit; the input matching circuit is connected with the grid electrode of the transistor T1, the source electrode of the transistor T1 is grounded, the drain electrode of the transistor T1 is connected with the inter-stage matching circuit, the other end of the inter-stage matching circuit is connected with the source electrode of the transistor T2, the second biasing circuit is connected with the grid electrode of the transistor T2, one end of the output matching circuit is connected with the drain electrode of the transistor T2, the other end of the output matching circuit is connected between the drain electrode biasing circuit and the negative feedback circuit, and the drain electrode biasing circuit, the negative feedback circuit and the first biasing circuit are sequentially connected in series.
Preferably, the first single-pole double-throw switch circuit structure is as follows: one end of the resistor R1 is grounded, the other end of the resistor R1 is connected with the microstrip line TL1, the switching tube Q1, the microstrip line TL2, the microstrip line TL3, the microstrip line TL4, the microstrip line TL5, the switching tube Q4 and the microstrip line TL6 are sequentially connected in series, the source stage of the switching tube Q3 is connected between the microstrip line TL4 and the microstrip line TL5, the drain electrode is grounded, the grid electrode is connected with the resistor RG3, the resistor RG3 is connected with the resistor RG2, the source stage of the switching tube Q2 is connected between the microstrip line TL2 and the microstrip line TL3, the drain electrode is grounded, the grid electrode is connected with the resistor RG2, one end of the resistor RG1 is connected with the grid electrode of the switching tube Q1, the other end of the resistor RG4 is connected with the grid electrode of the switching tube Q4; the second single-pole double-throw switch circuit structure is as follows: the resistor R2 is grounded at one end, the other end is connected with the microstrip line TL25, the switch tube Q12, the microstrip line TL24, the microstrip line TL23, the microstrip line TL22, the microstrip line TL21, the switch tube Q9 and the microstrip line TL20 are sequentially connected in series, the source stage of the switch tube Q11 is connected between the microstrip line TL24 and the microstrip line TL23, the drain electrode is grounded, the grid electrode is connected with the resistor RG11, the resistor RG11 is connected with the resistor RG10, the source stage of the switch tube Q10 is connected between the microstrip line TL22 and the microstrip line TL21, the drain electrode is grounded, the grid electrode is connected with the resistor RG10, one end of the resistor RG12 is connected with the grid electrode of the switch tube Q12, the other end is connected with the resistor RG9, and the other end of the resistor RG9 is connected with the grid electrode of the switch tube Q9; the third single pole double throw switch circuit structure is: the resistor R4 is grounded at one end, the other end is connected with the microstrip line TL19, the switch tube Q8, the microstrip line TL18, the microstrip line TL17, the microstrip line TL16, the microstrip line TL15, the switch tube Q5 and the microstrip line TL14 are sequentially connected in series, the source stage of the switch tube Q7 is connected between the microstrip line TL18 and the microstrip line TL17, the drain electrode is grounded, the grid electrode is connected with the resistor RG7, the resistor RG7 is connected with the resistor RG6, the source stage of the switch tube Q6 is connected between the microstrip line TL15 and the microstrip line TL16, the drain electrode is grounded, the grid electrode is connected with the resistor RG6, one end of the resistor RG8 is connected with the grid electrode of the switch tube Q8, the other end is connected with the resistor RG5, and the other end of the resistor RG5 is connected with the grid electrode of the switch tube Q5; the fourth single pole double throw switch circuit structure is: the resistor R3 is grounded at one end, the other end is connected with the microstrip line TL26, the switch tube Q13, the microstrip line TL27, the microstrip line TL28, the microstrip line TL29, the microstrip line TL30, the switch tube Q16 and the microstrip line TL31 are sequentially connected in series, the source stage of the switch tube Q14 is connected between the microstrip line TL27 and the microstrip line TL28, the drain electrode is grounded, the grid electrode is connected with the resistor RG14, the resistor RG14 is connected with the resistor RG15, the source stage of the switch tube Q15 is connected between the microstrip line TL29 and the microstrip line TL30, the drain electrode is grounded, the grid electrode is connected with the resistor RG15, one end of the resistor RG16 is connected with the grid electrode of the switch tube Q16, the other end is connected with the resistor RG13, and the other end of the resistor RG13 is connected with the grid electrode of the switch tube Q13.
Preferably, the four single pole double throw switch circuits are connected as follows: there is a circuit connection between resistance RG4, resistance RG1 between resistance RG15, resistance RG14, there is a circuit connection between resistance RG2, resistance RG3 between resistance RG16, resistance RG13, there is a circuit connection between resistance RG15, resistance RG14 between resistance RG5, resistance RG8, there is a circuit connection between resistance RG16, resistance RG13 between resistance RG6, resistance RG7 between resistance RG9, resistance RG12, there is a circuit connection between resistance RG5, resistance RG8 between resistance RG11, resistance RG10, control interface CA between resistance RG14, resistance RG15, control interface CB between resistance RG6 and resistance RG 7.
Preferably, the input matching circuit comprises a microstrip line TL8, a capacitor C3 and a microstrip line TL9, wherein the microstrip line TL8 is used for connecting the capacitor C2 with the microstrip line TL9, one end of the capacitor C3 is grounded, the other end of the capacitor C3 is connected between the microstrip line TL8 and the microstrip line TL9, and the other end of the microstrip line TL9 is connected with the grid electrode of the transistor T1.
Preferably, the first bias circuit includes an inductor L2, where one end of the inductor L2 is connected to the gate of the transistor T1, and the other end is connected to the power supply port VG.
Preferably, the inter-stage matching circuit includes a microstrip line TL10, and the microstrip line TL10 is connected between the drain of the transistor T1 and the source of the transistor T2.
Preferably, the second bias circuit comprises a resistor R7, a resistor R8, a resistor R6 and a capacitor C5, wherein one end of the resistor R7 is connected with the power supply port VD, the other end of the resistor R7 is connected with the resistor R8, the other end of the resistor R8 is grounded, a circuit is arranged between the resistor R7 and the resistor R8 and is connected with the resistor R6, the other end of the resistor R6 is connected with the grid of the transistor T2, and the other end of the capacitor C5 is grounded and connected with the grid of the transistor T2.
Preferably, the output matching circuit comprises an inductor L3, one end of the inductor L3 is connected to the drain electrode of the transistor T2, and the other end is connected between the inductor L4, the microstrip line TL12 and the capacitor C6.
Preferably, the drain bias circuit comprises an inductor L4 and a microstrip line TL11, wherein the inductor L4 and the microstrip line TL11 are connected in series, the other end of the microstrip line TL11 is connected with a power supply port VD, and the other end of the inductor L4 is connected among an inductor L3, the microstrip line TL12 and a capacitor C6; the negative feedback circuit comprises a microstrip line TL12, a capacitor C4 and a resistor R5, wherein one end of the microstrip line TL12 is connected between an inductor L3, the inductor L4 and the capacitor C6, the other end of the microstrip line TL is connected with the capacitor C4, the other end of the capacitor C4 is connected with the resistor R5, and the other end of the resistor R5 is connected with the grid electrode of the transistor T1.
Preferably, the compact gallium nitride transceiving front-end circuit structure uses a single amplifying core, and achieves transceiving functions through switching of a switch.
Preferably, the compact gallium nitride transceiver front-end circuit provided by the invention uses a simple matching circuit structure, the receiving and transmitting modes adopt the same amplifying core, the chip area is reduced, and the cost of the radio frequency front-end gallium nitride MMIC chip is reduced.
Preferably, the noise coefficient of the invention has a typical value of 3.5dB under the condition that the input end is provided with two groups of single-pole double-throw switches, thereby realizing smaller noise interference.
Preferably, the gallium nitride power amplifier core circuit adopts a 'common source and common grid' structure, so that the output power is improved, and the saturated output power is 28dBm;
preferably, the invention adopts four gallium nitride high-power single-pole double-throw switches for improving the burning resistance of the transceiving front end.
Compared with the prior art, the technical scheme of the invention has the following advantages/beneficial effects:
1. the compact gallium nitride transceiving front-end circuit provided by the invention adopts the same amplifying core in the receiving and transmitting modes, and in the transceiving mode switching process, the switching of an amplifier power supply is not needed, and the control is simple.
2. The gallium nitride switch and the gallium nitride amplifying transistor can obviously improve the high-power burnout resistance.
3. The compact gallium nitride transceiving front-end circuit provided by the invention can save the chip area and realize low noise characteristic and high power output.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, and it is to be understood that the following drawings only illustrate some embodiments of the present invention and should not be construed as limiting the scope, and other related drawings can be obtained according to the drawings without inventive effort to those skilled in the art.
Fig. 1 is a schematic diagram of a modular structure of a compact gan transceiver front-end circuit according to the present invention.
Fig. 2 is a schematic diagram of a specific circuit structure of a compact gan transceiver front-end circuit according to the present invention.
Fig. 3 is a graph of a state noise figure of a compact gan transceiver front-end circuit according to the present invention.
Fig. 4 is a graph of saturated output power (Psat) of a transmit-receive state of a compact gan transmit-receive front-end circuit in accordance with the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, are intended to fall within the scope of the present invention. Accordingly, the detailed description of the embodiments of the invention provided below is not intended to limit the scope of the invention as claimed, but is merely representative of selected embodiments of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, it may not be further defined and explained in the following figures.
Examples:
as shown in fig. 1 and 2, a compact gallium nitride transceiver front-end circuit has the following specific circuit structure:
the compact gallium nitride transceiver front-end circuit comprises a gallium nitride broadband amplifier core circuit, four single-pole double-throw switch circuits, a first matching circuit, a second matching circuit, a first core matching circuit, a second core matching circuit, a power supply port VG, a power supply port VD, a control interface CA and a control interface CB, wherein the four single-pole double-throw switches are sequentially connected in series, the first matching circuit is connected with the first single-pole double-throw switch circuit, the second matching circuit is connected with the third single-pole double-throw switch circuit, one end of the first core matching circuit is connected with the second single-pole double-throw switch circuit, the other end of the first core matching circuit is connected with the gallium nitride broadband amplifier core circuit, one end of the second core matching circuit is connected with the fourth single-pole double-throw switch circuit, the other end of the second core matching circuit is connected with the gallium nitride broadband amplifier core circuit, the VD VG and the power supply port are connected with the gallium nitride broadband amplifier core circuit, and the control interface CA and the control interface CB are connected between the third single-pole double-throw switch circuit and the fourth single-pole double-throw switch circuit.
The first matching circuit comprises a capacitor C1 and an inductor L1, wherein one end of the capacitor C1 is connected with the first port, the other end of the capacitor C1 is connected with the inductor L1, and the other end of the inductor L1 is connected with the first single-pole double-throw switch circuit; the second matching circuit comprises a capacitor C7 and an inductor L5, wherein one end of the capacitor C7 is connected with the second port, the other end of the capacitor C7 is connected with the inductor L5, and the other end of the inductor L5 is connected with the third single-pole double-throw switch circuit; the first core matching circuit comprises a microstrip line TL7 and a capacitor C2, wherein one end of the microstrip line TL7 is connected with a resistor R2, the other end of the microstrip line TL is connected with the capacitor C2, and the other end of the capacitor C2 is connected with the gallium nitride broadband amplifier core circuit; the second core matching circuit comprises a microstrip line TL13 and a capacitor C6, wherein one end of the microstrip line TL13 is connected with a resistor R3, the other end of the microstrip line TL is connected with the capacitor C6, and the other end of the capacitor C6 is connected with the gallium nitride broadband amplifier core circuit.
The gallium nitride broadband amplifier core circuit consists of an input matching circuit, a first bias circuit, a transistor T1, an interstage matching circuit, a transistor T2, a second bias circuit, an output matching circuit, a drain bias circuit and a negative feedback circuit; the input matching circuit is connected with the grid electrode of the transistor T1, the source electrode of the transistor T1 is grounded, the drain electrode of the transistor T1 is connected with the inter-stage matching circuit, the other end of the inter-stage matching circuit is connected with the source electrode of the transistor T2, the second biasing circuit is connected with the grid electrode of the transistor T2, one end of the output matching circuit is connected with the drain electrode of the transistor T2, the other end of the output matching circuit is connected between the drain electrode biasing circuit and the negative feedback circuit, and the drain electrode biasing circuit, the negative feedback circuit and the first biasing circuit are sequentially connected in series.
The first single-pole double-throw switch circuit structure is as follows: one end of the resistor R1 is grounded, the other end of the resistor R1 is connected with the microstrip line TL1, the switching tube Q1, the microstrip line TL2, the microstrip line TL3, the microstrip line TL4, the microstrip line TL5, the switching tube Q4 and the microstrip line TL6 are sequentially connected in series, the source stage of the switching tube Q3 is connected between the microstrip line TL4 and the microstrip line TL5, the drain electrode is grounded, the grid electrode is connected with the resistor RG3, the resistor RG3 is connected with the resistor RG2, the source stage of the switching tube Q2 is connected between the microstrip line TL2 and the microstrip line TL3, the drain electrode is grounded, the grid electrode is connected with the resistor RG2, one end of the resistor RG1 is connected with the grid electrode of the switching tube Q1, the other end of the resistor RG4 is connected with the grid electrode of the switching tube Q4; the second single-pole double-throw switch circuit structure is as follows: the resistor R2 is grounded at one end, the other end is connected with the microstrip line TL25, the switch tube Q12, the microstrip line TL24, the microstrip line TL23, the microstrip line TL22, the microstrip line TL21, the switch tube Q9 and the microstrip line TL20 are sequentially connected in series, the source stage of the switch tube Q11 is connected between the microstrip line TL24 and the microstrip line TL23, the drain electrode is grounded, the grid electrode is connected with the resistor RG11, the resistor RG11 is connected with the resistor RG10, the source stage of the switch tube Q10 is connected between the microstrip line TL22 and the microstrip line TL21, the drain electrode is grounded, the grid electrode is connected with the resistor RG10, one end of the resistor RG12 is connected with the grid electrode of the switch tube Q12, the other end is connected with the resistor RG9, and the other end of the resistor RG9 is connected with the grid electrode of the switch tube Q9; the third single pole double throw switch circuit structure is: the resistor R4 is grounded at one end, the other end is connected with the microstrip line TL19, the switch tube Q8, the microstrip line TL18, the microstrip line TL17, the microstrip line TL16, the microstrip line TL15, the switch tube Q5 and the microstrip line TL14 are sequentially connected in series, the source stage of the switch tube Q7 is connected between the microstrip line TL18 and the microstrip line TL17, the drain electrode is grounded, the grid electrode is connected with the resistor RG7, the resistor RG7 is connected with the resistor RG6, the source stage of the switch tube Q6 is connected between the microstrip line TL15 and the microstrip line TL16, the drain electrode is grounded, the grid electrode is connected with the resistor RG6, one end of the resistor RG8 is connected with the grid electrode of the switch tube Q8, the other end is connected with the resistor RG5, and the other end of the resistor RG5 is connected with the grid electrode of the switch tube Q5; the fourth single pole double throw switch circuit structure is: the resistor R3 is grounded at one end, the other end is connected with the microstrip line TL26, the switch tube Q13, the microstrip line TL27, the microstrip line TL28, the microstrip line TL29, the microstrip line TL30, the switch tube Q16 and the microstrip line TL31 are sequentially connected in series, the source stage of the switch tube Q14 is connected between the microstrip line TL27 and the microstrip line TL28, the drain electrode is grounded, the grid electrode is connected with the resistor RG14, the resistor RG14 is connected with the resistor RG15, the source stage of the switch tube Q15 is connected between the microstrip line TL29 and the microstrip line TL30, the drain electrode is grounded, the grid electrode is connected with the resistor RG15, one end of the resistor RG16 is connected with the grid electrode of the switch tube Q16, the other end is connected with the resistor RG13, and the other end of the resistor RG13 is connected with the grid electrode of the switch tube Q13.
The connection relation of the four single-pole double-throw switch circuits is as follows: there is a circuit connection between resistance RG4, resistance RG1 between resistance RG15, resistance RG14, there is a circuit connection between resistance RG2, resistance RG3 between resistance RG16, resistance RG13, there is a circuit connection between resistance RG15, resistance RG14 between resistance RG5, resistance RG8, there is a circuit connection between resistance RG16, resistance RG13 between resistance RG6, resistance RG7 between resistance RG9, resistance RG12, there is a circuit connection between resistance RG5, resistance RG8 between resistance RG11, resistance RG10, control interface CA between resistance RG14, resistance RG15, control interface CB between resistance RG6 and resistance RG 7.
The input matching circuit comprises a microstrip line TL8, a capacitor C3 and a microstrip line TL9, wherein the microstrip line TL8 is used for connecting the capacitor C2 with the microstrip line TL9, one end of the capacitor C3 is grounded, the other end of the capacitor C3 is connected between the microstrip line TL8 and the microstrip line TL9, and the other end of the microstrip line TL9 is connected with the grid electrode of the transistor T1.
The first bias circuit comprises an inductor L2, one end of the inductor L2 is connected to the gate of the transistor T1, and the other end of the inductor L2 is connected to the power supply port VG.
The inter-stage matching circuit includes a microstrip line TL10, the microstrip line TL10 being connected between the drain of the transistor T1 and the source of the transistor T2.
The second bias circuit comprises a resistor R7, a resistor R8, a resistor R6 and a capacitor C5, wherein one end of the resistor R7 is connected with the power supply port VD, the other end of the resistor R7 is connected with the resistor R8, the other end of the resistor R8 is grounded, a circuit is arranged between the resistor R7 and the resistor R8 and is connected with the resistor R6, the other end of the resistor R6 is connected with the grid electrode of the transistor T2, and one end of the capacitor C5 is grounded and the other end of the capacitor C5 is connected with the grid electrode of the transistor T2.
The output matching circuit comprises an inductor L3, one end of the inductor L3 is connected with the drain electrode of the transistor T2, and the other end of the inductor L3 is connected among the inductor L4, the microstrip line TL12 and the capacitor C6.
The drain bias circuit comprises an inductor L4 and a microstrip line TL11, wherein the inductor L4 and the microstrip line TL11 are connected in series, the other end of the microstrip line TL11 is connected with a power supply port VD, and the other end of the inductor L4 is connected among an inductor L3, the microstrip line TL12 and a capacitor C6; the negative feedback circuit comprises a microstrip line TL12, a capacitor C4 and a resistor R5, wherein one end of the microstrip line TL12 is connected between an inductor L3, the inductor L4 and the capacitor C6, the other end of the microstrip line TL is connected with the capacitor C4, the other end of the capacitor C4 is connected with the resistor R5, and the other end of the resistor R5 is connected with the grid electrode of the transistor T1.
The four gallium nitride high-power single-pole double-throw switch circuits are positioned at the radio frequency input and output ends of the receiving and transmitting front end and are used for switching the receiving/transmitting states; when four gallium nitride high-power single-pole double-throw switches are switched into a first port input, a second port output and a second port input, and the first port output, the corresponding two circuits are symmetrical circuits with identical structure and component values.
A gallium nitride broadband amplifier is of a 'common-source common-gate' structure formed by two transistors, and a broadband radio-frequency signal amplification channel is formed.
The gate bias circuit of the gallium nitride broadband amplifier has a supply voltage of-1.5V, namely the voltage at the supply port VG is: -1.5V, the drain bias circuit supply voltage is 28V, i.e. the voltage at the supply port VD is: 28V; when the control voltage of the control port of the gallium nitride high-power single-pole double-throw switch is 0V and-28V, namely the control interface CA=0V and the control interface CB= -28V, a radio frequency signal can be input through the first port and output through the second port; when the control voltage of the control port is-28V and 0V, namely the control port CA= -28V, and the control port CB=0V, the radio frequency signal can be input through the second port, and the first port can be output.
As can be seen from FIG. 3, the noise factor of the invention is typically 3.5dB when the input end is provided with two groups of single-pole double-throw switches, and the noise factor of the invention is smaller than the noise interference of the prior art.
The core circuit of the gallium nitride power amplifier adopts a 'cascode' structure, the working frequency band of the gallium nitride power amplifier is 4 GHz-15 GHz, as can be seen from fig. 4, the saturated output power of the gallium nitride power amplifier is 28dBm, and compared with the prior art, the saturated output power of the gallium nitride power amplifier is improved.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that the above-mentioned preferred embodiment should not be construed as limiting the invention, and the scope of the invention should be defined by the appended claims. It will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the spirit and scope of the invention, and such modifications and adaptations are intended to be comprehended within the scope of the invention.
Claims (10)
1. The compact gallium nitride transceiving front-end circuit is characterized by comprising a gallium nitride broadband amplifier core circuit, four single-pole double-throw switch circuits, a first matching circuit, a second matching circuit, a first core matching circuit, a second core matching circuit, a power supply port VG, a power supply port VD, a control interface CA and a control interface CB, wherein the four single-pole double-throw switches are sequentially connected in series, the first matching circuit is connected with the first single-pole double-throw switch circuit, the second matching circuit is connected with the third single-pole double-throw switch circuit, one end of the first core matching circuit is connected with the second single-pole double-throw switch circuit, the other end of the first core matching circuit is connected with the gallium nitride broadband amplifier core circuit, one end of the second core matching circuit is connected with the fourth single-pole double-throw switch circuit, the other end of the second core matching circuit is connected with the gallium nitride broadband amplifier core circuit, the power supply port VG and the power supply port VD are connected with the gallium nitride broadband amplifier core circuit, and the control interface CA and the control interface CB are connected between the third single-pole double-throw switch circuit and the fourth single-pole double-throw switch circuit; control interface CA is connected between resistance RG14 and resistance RG15, control interface CB is connected between resistance RG6 and resistance RG 7; the four gallium nitride high-power single-pole double-throw switch circuits are positioned at the radio frequency input and output ends of the receiving and transmitting front end and are used for receiving and transmitting switching; when four gallium nitride high-power single-pole double-throw switches are switched into a first port input, a second port output and a second port input, and the first port output, the corresponding two circuits are symmetrical circuits with identical structure and component values.
2. The compact gallium nitride transceiver front-end circuit according to claim 1, wherein the first matching circuit comprises a capacitor C1 and an inductor L1, wherein one end of the capacitor C1 is connected to the first port, the other end of the capacitor C1 is connected to the inductor L1, and the other end of the inductor L1 is connected to the first single-pole double-throw switch circuit; the second matching circuit comprises a capacitor C7 and an inductor L5, wherein one end of the capacitor C7 is connected with the second port, the other end of the capacitor C7 is connected with the inductor L5, and the other end of the inductor L5 is connected with the third single-pole double-throw switch circuit; the first core matching circuit comprises a microstrip line TL7 and a capacitor C2, wherein one end of the microstrip line TL7 is connected with a resistor R2, the other end of the microstrip line TL is connected with the capacitor C2, and the other end of the capacitor C2 is connected with the gallium nitride broadband amplifier core circuit; the second core matching circuit comprises a microstrip line TL13 and a capacitor C6, wherein one end of the microstrip line TL13 is connected with a resistor R3, the other end of the microstrip line TL is connected with the capacitor C6, and the other end of the capacitor C6 is connected with the gallium nitride broadband amplifier core circuit.
3. The compact gallium nitride transceiver front-end circuit of claim 1, wherein the gallium nitride broadband amplifier core circuit is comprised of an input matching circuit, a first bias circuit, a transistor T1, an inter-stage matching circuit, a transistor T2, a second bias circuit, an output matching circuit, a drain bias circuit, and a negative feedback circuit; the input matching circuit is connected with the grid electrode of the transistor T1, the source electrode of the transistor T1 is grounded, the drain electrode of the transistor T1 is connected with the inter-stage matching circuit, the other end of the inter-stage matching circuit is connected with the source electrode of the transistor T2, the second biasing circuit is connected with the grid electrode of the transistor T2, one end of the output matching circuit is connected with the drain electrode of the transistor T2, the other end of the output matching circuit is connected between the drain electrode biasing circuit and the negative feedback circuit, and the drain electrode biasing circuit, the negative feedback circuit and the first biasing circuit are sequentially connected in series.
4. The compact gallium nitride transceiver front-end circuit of claim 1, wherein the first single pole double throw switch circuit structure is: one end of the resistor R1 is grounded, the other end of the resistor R1 is connected with the microstrip line TL1, the switching tube Q1, the microstrip line TL2, the microstrip line TL3, the microstrip line TL4, the microstrip line TL5, the switching tube Q4 and the microstrip line TL6 are sequentially connected in series, the source stage of the switching tube Q3 is connected between the microstrip line TL4 and the microstrip line TL5, the drain electrode is grounded, the grid electrode is connected with the resistor RG3, the resistor RG3 is connected with the resistor RG2, the source stage of the switching tube Q2 is connected between the microstrip line TL2 and the microstrip line TL3, the drain electrode is grounded, the grid electrode is connected with the resistor RG2, one end of the resistor RG1 is connected with the grid electrode of the switching tube Q1, the other end of the resistor RG4 is connected with the grid electrode of the switching tube Q4; the second single-pole double-throw switch circuit structure is as follows: the resistor R2 is grounded at one end, the other end is connected with the microstrip line TL25, the switch tube Q12, the microstrip line TL24, the microstrip line TL23, the microstrip line TL22, the microstrip line TL21, the switch tube Q9 and the microstrip line TL20 are sequentially connected in series, the source stage of the switch tube Q11 is connected between the microstrip line TL24 and the microstrip line TL23, the drain electrode is grounded, the grid electrode is connected with the resistor RG11, the resistor RG11 is connected with the resistor RG10, the source stage of the switch tube Q10 is connected between the microstrip line TL22 and the microstrip line TL21, the drain electrode is grounded, the grid electrode is connected with the resistor RG10, one end of the resistor RG12 is connected with the grid electrode of the switch tube Q12, the other end is connected with the resistor RG9, and the other end of the resistor RG9 is connected with the grid electrode of the switch tube Q9; the third single pole double throw switch circuit structure is: the resistor R4 is grounded at one end, the other end is connected with the microstrip line TL19, the switch tube Q8, the microstrip line TL18, the microstrip line TL17, the microstrip line TL16, the microstrip line TL15, the switch tube Q5 and the microstrip line TL14 are sequentially connected in series, the source stage of the switch tube Q7 is connected between the microstrip line TL18 and the microstrip line TL17, the drain electrode is grounded, the grid electrode is connected with the resistor RG7, the resistor RG7 is connected with the resistor RG6, the source stage of the switch tube Q6 is connected between the microstrip line TL15 and the microstrip line TL16, the drain electrode is grounded, the grid electrode is connected with the resistor RG6, one end of the resistor RG8 is connected with the grid electrode of the switch tube Q8, the other end is connected with the resistor RG5, and the other end of the resistor RG5 is connected with the grid electrode of the switch tube Q5; the fourth single pole double throw switch circuit structure is: the resistor R3 is grounded at one end, the other end is connected with the microstrip line TL26, the switch tube Q13, the microstrip line TL27, the microstrip line TL28, the microstrip line TL29, the microstrip line TL30, the switch tube Q16 and the microstrip line TL31 are sequentially connected in series, the source stage of the switch tube Q14 is connected between the microstrip line TL27 and the microstrip line TL28, the drain electrode is grounded, the grid electrode is connected with the resistor RG14, the resistor RG14 is connected with the resistor RG15, the source stage of the switch tube Q15 is connected between the microstrip line TL29 and the microstrip line TL30, the drain electrode is grounded, the grid electrode is connected with the resistor RG15, one end of the resistor RG16 is connected with the grid electrode of the switch tube Q16, the other end is connected with the resistor RG13, and the other end of the resistor RG13 is connected with the grid electrode of the switch tube Q13; the circuit between the resistor RG4 and the resistor RG1 is connected between the resistor RG15 and the resistor RG14, the circuit between the resistor RG2 and the resistor RG3 is connected between the resistor RG16 and the resistor RG13, the circuit between the resistor RG15 and the resistor RG14 is connected between the resistor RG5 and the resistor RG8, the circuit between the resistor RG16 and the resistor RG13 is connected between the resistor RG6 and the resistor RG7, the circuit between the resistor RG6 and the resistor RG7 is connected between the resistor RG9 and the resistor RG12, and the circuit between the resistor RG5 and the resistor RG8 is connected between the resistor RG11 and the resistor RG 10.
5. A compact gallium nitride transceiving front-end circuit according to claim 3, wherein said input matching circuit comprises a microstrip line TL8, a capacitor C3 and a microstrip line TL9, said microstrip line TL8 is used for connecting a capacitor C2 and the microstrip line TL9, one end of the capacitor C3 is grounded, the other end is connected between the microstrip line TL8 and the microstrip line TL9, and the other end of the microstrip line TL9 is connected to the gate of the transistor T1.
6. A compact gallium nitride transceiver front-end circuit according to claim 3, wherein the first bias circuit comprises an inductor L2, one end of the inductor L2 being connected to the gate of the transistor T1, and the other end being connected to the power supply port VG.
7. A compact gallium nitride transceiving front-end circuit according to claim 3, wherein said interstage matching circuit comprises a microstrip line TL10, said microstrip line TL10 being connected between a transistor T1 drain and a transistor T2 source.
8. A compact gallium nitride transceiving front-end circuit according to claim 3, wherein said second bias circuit comprises a resistor R7, a resistor R8, a resistor R6 and a capacitor C5, wherein one end of said resistor R7 is connected to a power supply port VD, the other end is connected to said resistor R8, the other end of said resistor R8 is grounded, a circuit is provided between said resistor R7 and said resistor R8 and connected to said resistor R6, the other end of said resistor R6 is connected to the gate of said transistor T2, and the other end of said capacitor C5 is grounded and connected to the gate of said transistor T2.
9. A compact gallium nitride transceiver front-end circuit according to claim 3, wherein the output matching circuit comprises an inductor L3, one end of the inductor L3 is connected to the drain of the transistor T2, and the other end is connected between the inductor L4, the microstrip line TL12 and the capacitor C6.
10. A compact gallium nitride transceiving front-end circuit according to claim 3, wherein said drain bias circuit comprises an inductance L4 and a microstrip line TL11, wherein said inductance L4 and microstrip line TL11 are connected in series, the other end of microstrip line TL11 is connected to a power supply port VD, and the other end of inductance L4 is connected between inductance L3, microstrip line TL12 and capacitor C6; the negative feedback circuit comprises a microstrip line TL12, a capacitor C4 and a resistor R5, wherein one end of the microstrip line TL12 is connected between an inductor L3, the inductor L4 and the capacitor C6, the other end of the microstrip line TL is connected with the capacitor C4, the other end of the capacitor C4 is connected with the resistor R5, and the other end of the resistor R5 is connected with the grid electrode of the transistor T1.
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