CN117032386A - Automatic maximum voltage selection circuit - Google Patents

Automatic maximum voltage selection circuit Download PDF

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Publication number
CN117032386A
CN117032386A CN202310762536.6A CN202310762536A CN117032386A CN 117032386 A CN117032386 A CN 117032386A CN 202310762536 A CN202310762536 A CN 202310762536A CN 117032386 A CN117032386 A CN 117032386A
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China
Prior art keywords
tube
circuit
pmos tube
nmos tube
maximum voltage
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Chinese (zh)
Inventor
岳宏卫
韦家锐
许仕海
韦善于
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Guilin University of Electronic Technology
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Guilin University of Electronic Technology
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Priority to CN202310762536.6A priority Critical patent/CN117032386A/en
Publication of CN117032386A publication Critical patent/CN117032386A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a maximum voltage automatic selection circuit, and belongs to the technical field of analog integrated circuits. The invention provides a maximum voltage automatic selection circuit, which comprises a bias circuit, a cascode current mirror circuit, a maximum voltage comparison circuit, a Schmitt trigger and a maximum voltage selection switch, wherein the bias circuit is connected with the cascode current mirror circuit; the bias circuit consists of a reference current generating circuit and a bias voltage generating circuit; the cascode current mirror circuit adopts a cascode structure; the maximum voltage comparison circuit converts input voltage into corresponding current, and then automatically charges and discharges the energy storage capacitor according to the current; the Schmitt trigger reshapes the result of the maximum voltage comparison circuit and then drives the maximum voltage selection switch; the maximum voltage selection switch is turned on and then transmits the maximum voltage to the output terminal. The invention creatively uses the NMOS tube energy storage capacitor to replace the common metal capacitor, thereby greatly reducing the layout area of the circuit; the mode of converting voltage comparison into current comparison and the use of the Schmitt trigger not only increase the speed and precision of voltage comparison, but also improve the stability of the circuit; the current generated by the reference current circuit and the mirror circuit is in the nanoampere level, so the total power consumption of the whole circuit is extremely small.

Description

Automatic maximum voltage selection circuit
Technical Field
The invention belongs to the technical field of analog integrated circuit design, and particularly relates to an automatic maximum voltage selection circuit.
Background
In analog chip applications, such as in analog circuitry, PMIC, EEPROM, SOC, OTP, multiple power supplies are often present. And some circuit modules have minimum requirements for the supply voltage, and cannot work normally below a certain value. Therefore, the maximum voltage automatic selection circuit can track and select among a plurality of power supplies, and the maximum voltage is selected to share the needed circuit module for use. The performance of analog circuitry may be affected if the maximum voltage selection circuit is unable to quickly and accurately select the maximum voltage. The traditional voltage selection circuit generally realizes the output of the selected voltage through one-way conduction switch, has limited speed and low stability, and does not carry out low-power consumption processing on the circuit.
Disclosure of Invention
Aiming at the problems, the invention provides a maximum voltage automatic selection circuit, which uses an NMOS tube energy storage capacitor to replace a common metal capacitor, so that the layout area of the circuit can be greatly reduced; the mode of converting voltage comparison into current comparison and the use of the Schmitt trigger not only increase the speed and precision of voltage comparison, but also improve the stability of the circuit; the current generated by the reference current circuit and the branch current of the mirror circuit are both in nanoampere level, so the total power consumption of the whole circuit is extremely small.
Aiming at the defects in the prior art and the prior art, the invention is realized by the following design scheme:
a maximum voltage automatic selection circuit includes a bias circuit (100), a cascode current mirror circuit (200), a maximum voltage comparison circuit (300), a Schmitt trigger, and a maximum voltage selection switch (400, 500).
The bias circuit (100) includes a reference current generating circuit (101) and a bias voltage generating circuit (102) for generating a reference current and a bias voltage; the cascode current mirror circuit (200) adopts a cascode current mirror structure, and copies the reference current to be used as a current source of the maximum voltage comparison circuit (300); the maximum voltage comparison circuit (300) is composed of a cascode current source, a protection resistor and an energy storage capacitor MNC; the Schmitt trigger reshapes the result of the maximum voltage comparison circuit and then drives the maximum voltage selection switch; the maximum voltage selection switches (400, 500) adopt complementary CMOS structures, and the maximum voltage is transmitted to the output end after being conducted.
Further, the reference current generating circuit (101) is composed of an NMOS tube MN1, a resistor RS, a PMOS tube MP1 and a PMOS tube MP 2. The grid electrode of the NMOS tube MN1 is connected with an ideal voltage bias VREF, the source electrode of the NMOS tube MN1 is connected with a resistor RS to form a source electrode negative feedback, and the drain electrode of the NMOS tube MP1 is connected with the drain electrode of the PMOS tube MP 2; one end of the resistor RS is connected with the source electrode of the NMOS tube MN1, and the other end of the resistor RS is grounded; the source electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP2, and the grid electrode of the PMOS tube MP1 is connected with bias voltage VBP2; the source of the PMOS tube MP2 is connected with the power supply voltage VINA.
Further, the bias generating circuit (102) is composed of a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN2 and an NMOS tube MN 3. The source electrode of the PMOS tube MP3 is connected with the power supply voltage VINA, the grid electrode is connected with the bias voltage VBP1, and the drain electrode is connected with the source electrode of the PMOS tube MP 4; the grid electrode of the PMOS tube MP4 is connected with bias voltage VBP2, and the drain electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MN 2; the PMOS tube MP5 is connected with the drain of the NMOS tube MN3 after the gate and the drain are in short circuit, and the source is connected with the power supply voltage VINA; the NMOS tube MN2 is connected with the drain electrode of the PMOS tube MP4 and the grid electrode of the NMOS tube MN3 after the gate and the drain are in short circuit, and the source electrode is grounded; the source of NMOS transistor MN3 is grounded.
Further, the cascode current mirror circuit (200) is composed of a PMOS transistor MP6, a PMOS transistor MP7, an NMOS transistor MN4, an NMOS transistor MN5, an NMOS transistor MN6, an NMOS transistor MN7, an NMOS transistor MN8, and an NMOS transistor MN 9. The source electrode of the PMOS tube MP6 is connected with the power supply voltage VINA, the grid electrode is connected with the bias voltage VBP1, and the drain electrode is connected with the source electrode of the PMOS tube MP 7; the grid electrode of the PMOS tube MP7 is connected with the bias voltage VBP2, and the drain electrode of the NMOS tube MN4 is connected with the grid electrode of the NMOS tube MN 5; the grid electrode of the NMOS tube MN4 is connected with the bias voltage VBN1, and the source electrode is connected with the drain electrode of the NMOS tube MN 5; the source electrode of the NMOS tube MN5 is grounded; the gates of the NMOS tube MN7 and the NMOS tube MN9 are both connected with the bias voltage VBN2, the sources are both grounded, the drain electrode of the NMOS tube MN7 is connected with the source electrode of the NMOS tube MN6, and the drain electrode of the NMOS tube MN9 is connected with the source electrode of the NMOS tube MN 8; the gates of the NMOS transistor MN6 and the NMOS transistor MN8 are both connected with the bias voltage VBN1, the drain electrode of the NMOS transistor MN6 is connected with the VG node, and the drain electrode of the NMOS transistor MN8 is connected with the VC node.
Further, the maximum voltage comparison circuit (300) is composed of a resistor RN, a resistor RP, a PMOS tube MP8, a PMOS tube MP9, an energy storage capacitor MNC and two paths of cascode current sources. One end of the resistor RN is connected with the input voltage VIN, and the other end of the resistor RN is connected with the source electrode of the PMOS tube MP 8; one end of the resistor RP is connected with the input voltage VIP, and the other end of the resistor RP is connected with the source electrode of the PMOS tube MP 9; the PMOS tube MP8 is connected with the grid electrode of the PMOS tube MP9 after the grid electrode and the drain electrode are short-circuited; the sources of the PMOS tube MP8 and the PMOS tube MP9 are respectively connected with a path of common-source common-gate current source; the energy storage capacitor MNC is a MOS capacitor, and is formed by grounding the source and drain of the NMOS tube and connecting the grid electrode with the VC node.
Further, the schmitt trigger marks the output of the result of the maximum voltage comparison circuit, namely after the voltage at two ends of the energy storage capacitor MNC is shaped, after entering the inverter INV1 as SA; the output of the SA signal after entering the inverter INV2 is recorded as SB; so SA and SB are a pair of logically opposite signals to each other.
Further, the maximum voltage selection switch (400, 500) is a complementary CMOS switch; the VIN branch switch (400) is composed of an NMOS tube MN10 and a PMOS tube MP 10; the VIP branch switch (500) is composed of an NMOS tube MN11 and a PMOS tube MP 11; the grid electrode of the NMOS tube MN10 is connected with an SB signal, the grid electrode of the PMOS tube MP10 is connected with an SA signal, the drain electrode of the NMOS tube MN10 is connected with the source electrode of the PMOS tube MP10 and then is connected with an input signal VIN, and the source electrode of the NMOS tube MN10 is connected with the drain electrode of the PMOS tube MP10 and then is connected with an output signal VOUT; the grid electrode of the NMOS tube MN11 is connected with an SA signal, the grid electrode of the PMOS tube MP11 is connected with an SB signal, the drain electrode of the NMOS tube MN11 is connected with the source electrode of the PMOS tube MP11 and then is connected with an input signal VIP, and the source electrode of the NMOS tube MN11 is connected with the drain electrode of the PMOS tube MP11 and then is connected with an output signal VOUT.
Further, the supply voltages of the schmitt trigger, the inverter INV1 and the inverter INV2 are the output voltage VOUT.
The maximum voltage automatic selection circuit provided by the invention has the following beneficial effects:
(1) The NMOS tube energy storage capacitor is used for replacing a common metal capacitor, so that the layout area of a circuit can be greatly reduced.
(2) The mode of converting voltage comparison into current comparison and the use of the schmitt trigger not only increase the speed and precision of voltage comparison, but also improve the stability of the circuit.
(3) The current generated by the reference current circuit and the mirror circuit is in the nanoampere level, so the total power consumption of the whole circuit is extremely small.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, in which the drawings are only some embodiments recorded in the present invention, and other drawings can be obtained according to these drawings without paying any inventive effort to those skilled in the art.
FIG. 1 is a schematic diagram of the structure of a non-biased circuit detail of a maximum voltage automatic selection circuit of the present invention;
FIG. 2 is a schematic diagram of a full circuit configuration of an automatic maximum voltage selection circuit according to the present invention;
FIG. 3 is a diagram showing the relationship between the MOS capacitor MNC and the gate voltage VG according to the present invention;
FIG. 4 is a schematic diagram showing the final simulation result of a maximum voltage automatic selection circuit according to the present invention;
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings described in accordance with the drawings are merely exemplary and are not limited to these embodiments.
It should be noted that, in order to avoid obscuring the present invention due to unnecessary details, only the structures and/or processing steps closely related to the solution according to the present invention are shown in the accompanying drawings, while other details not greatly related to the present invention are omitted.
And, in the description of the present invention, the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are directions or positional relationships based on the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, an embodiment of the present invention includes: the circuit comprises a circuit (100), a cascode current mirror circuit (200), a maximum voltage comparison circuit (300), a Schmitt trigger and maximum voltage selection switches (400, 500).
The bias circuit (100) includes a reference current generating circuit (101) and a bias voltage generating circuit (102) for generating a reference current and a bias voltage; the cascode current mirror circuit (200) adopts a cascode current mirror structure, and copies the reference current to be used as a current source of the maximum voltage comparison circuit (300); the maximum voltage comparison circuit (300) is composed of a cascode current source, a protection resistor and an energy storage capacitor MNC; the Schmitt trigger reshapes the result of the maximum voltage comparison circuit and then drives the maximum voltage selection switch; the maximum voltage selection switches (400, 500) adopt complementary CMOS structures, and the maximum voltage is transmitted to the output end after being conducted.
Further, the reference current generating circuit (101) is composed of an NMOS tube MN1, a resistor RS, a PMOS tube MP1 and a PMOS tube MP 2. The grid electrode of the NMOS tube MN1 is connected with an ideal voltage bias VREF, the source electrode of the NMOS tube MN1 is connected with a resistor RS to form a source electrode negative feedback, and the drain electrode of the NMOS tube MP1 is connected with the drain electrode of the PMOS tube MP 2; one end of the resistor RS is connected with the source electrode of the NMOS tube MN1, and the other end of the resistor RS is grounded; the source electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP2, and the grid electrode of the PMOS tube MP1 is connected with bias voltage VBP2; the source of the PMOS tube MP2 is connected with the power supply voltage VINA.
Further, the bias generating circuit (102) is composed of a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN2 and an NMOS tube MN 3. The source electrode of the PMOS tube MP3 is connected with the power supply voltage VINA, the grid electrode is connected with the bias voltage VBP1, and the drain electrode is connected with the source electrode of the PMOS tube MP 4; the grid electrode of the PMOS tube MP4 is connected with bias voltage VBP2, and the drain electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MN 2; the PMOS tube MP5 is connected with the drain of the NMOS tube MN3 after the gate and the drain are in short circuit, and the source is connected with the power supply voltage VINA; the NMOS tube MN2 is connected with the drain electrode of the PMOS tube MP4 and the grid electrode of the NMOS tube MN3 after the gate and the drain are in short circuit, and the source electrode is grounded; the source of NMOS transistor MN3 is grounded.
Further, the cascode current mirror circuit (200) is composed of a PMOS transistor MP6, a PMOS transistor MP7, an NMOS transistor MN4, an NMOS transistor MN5, an NMOS transistor MN6, an NMOS transistor MN7, an NMOS transistor MN8, and an NMOS transistor MN 9. The source electrode of the PMOS tube MP6 is connected with the power supply voltage VINA, the grid electrode is connected with the bias voltage VBP1, and the drain electrode is connected with the source electrode of the PMOS tube MP 7; the grid electrode of the PMOS tube MP7 is connected with the bias voltage VBP2, and the drain electrode of the NMOS tube MN4 is connected with the grid electrode of the NMOS tube MN 5; the grid electrode of the NMOS tube MN4 is connected with the bias voltage VBN1, and the source electrode is connected with the drain electrode of the NMOS tube MN 5; the source electrode of the NMOS tube MN5 is grounded; the gates of the NMOS tube MN7 and the NMOS tube MN9 are both connected with the bias voltage VBN2, the sources are both grounded, the drain electrode of the NMOS tube MN7 is connected with the source electrode of the NMOS tube MN6, and the drain electrode of the NMOS tube MN9 is connected with the source electrode of the NMOS tube MN 8; the gates of the NMOS transistor MN6 and the NMOS transistor MN8 are both connected with the bias voltage VBN1, the drain electrode of the NMOS transistor MN6 is connected with the VG node, and the drain electrode of the NMOS transistor MN8 is connected with the VC node.
Further, the maximum voltage comparison circuit (300) is composed of a resistor RN, a resistor RP, a PMOS tube MP8, a PMOS tube MP9, an energy storage capacitor MNC and two paths of cascode current sources. One end of the resistor RN is connected with the input voltage VIN, and the other end of the resistor RN is connected with the source electrode of the PMOS tube MP 8; one end of the resistor RP is connected with the input voltage VIP, and the other end of the resistor RP is connected with the source electrode of the PMOS tube MP 9; the PMOS tube MP8 is connected with the grid electrode of the PMOS tube MP9 after the grid electrode and the drain electrode are short-circuited; the sources of the PMOS tube MP8 and the PMOS tube MP9 are respectively connected with a path of common-source common-gate current source; the energy storage capacitor MNC is a MOS capacitor, and is formed by grounding the source and drain of the NMOS tube and connecting the grid electrode with the VC node.
Further, the schmitt trigger marks the output of the result of the maximum voltage comparison circuit, namely after the voltage at two ends of the energy storage capacitor MNC is shaped, after entering the inverter INV1 as SA; the output of the SA signal after entering the inverter INV2 is recorded as SB; so SA and SB are a pair of logically opposite signals to each other.
Further, the maximum voltage selection switch (400, 500) is a complementary CMOS switch; the VIN branch switch (400) is composed of an NMOS tube MN10 and a PMOS tube MP 10; the VIP branch switch (500) is composed of an NMOS tube MN11 and a PMOS tube MP 11; the grid electrode of the NMOS tube MN10 is connected with an SB signal, the grid electrode of the PMOS tube MP10 is connected with an SA signal, the drain electrode of the NMOS tube MN10 is connected with the source electrode of the PMOS tube MP10 and then is connected with an input signal VIN, and the source electrode of the NMOS tube MN10 is connected with the drain electrode of the PMOS tube MP10 and then is connected with an output signal VOUT; the grid electrode of the NMOS tube MN11 is connected with an SA signal, the grid electrode of the PMOS tube MP11 is connected with an SB signal, the drain electrode of the NMOS tube MN11 is connected with the source electrode of the PMOS tube MP11 and then is connected with an input signal VIP, and the source electrode of the NMOS tube MN11 is connected with the drain electrode of the PMOS tube MP11 and then is connected with an output signal VOUT.
Further, the supply voltages of the schmitt trigger, the inverter INV1 and the inverter INV2 are the output voltage VOUT.
The maximum voltage automatic selection circuit provided by the invention has the following beneficial effects:
(1) The NMOS tube energy storage capacitor is used for replacing a common metal capacitor, so that the layout area of a circuit can be greatly reduced.
(2) The mode of converting voltage comparison into current comparison and the use of the schmitt trigger not only increase the speed and precision of voltage comparison, but also improve the stability of the circuit.
(3) The current generated by the reference current circuit and the mirror circuit is in the nanoampere level, so the total power consumption of the whole circuit is extremely small.
In this embodiment, the purpose of the automatic maximum voltage selection circuit is to accurately and quickly select and transmit the maximum voltage of the two input voltages that continuously change to the output terminal.
As shown in the schematic diagram of the complete circuit structure of fig. 2, the principle of the reference current generating circuit (101) in this embodiment is as follows: an ideal voltage bias VREF is added on the gate of the NMOS tube MN1, and a source voltage VS generated after the MN1 is conducted generates a reference current through a resistor RS; by increasing the resistance of the resistor RS, the value of the reference current can be reduced to the nanoampere level. The voltage-current relationship is shown in the following two formulas:
the principle of the bias voltage generating circuit (102) in this embodiment is as follows: the reference current IREF is copied in equal proportion by a common-source common-gate current mirror formed by the PMOS tube MP3 and the PMOS tube PM4, and then flows through an NMOS tube MN2 with a short circuit of gate and drain to generate bias voltage VBN1; the NMOS transistor MN2 copies the reference current IREF to the NMOS transistor MN3 in equal proportion, and then flows through the PMOS transistor MP5 with its gate and drain shorted to generate the bias voltage VBP2. The voltage-current relationship is shown in the following two formulas:
the principle of the maximum voltage comparison circuit (300) in the present embodiment is: the reference current IREF is copied in equal proportion by a two-time cascode current mirror and then is used as a current source of a maximum voltage comparison circuit (300); the branch current at which the input voltage VIN is maintained at IREF due to the current source; the branch current where the input voltage VIP is located is different, if the input voltage VIP is greater than the input voltage VIN, the source voltage of the PMOS transistor MP9 will be greater than the source voltage of the PMOS transistor MP9, the current on the PMOS transistor MP9 will also be greater than the current of the current source below, and the redundant current will flow to the energy storage capacitor MNC to pull up the voltage of the VC node; if the input voltage VIP is less than the input voltage VIN, the source voltage of the PMOS transistor MP9 will be smaller than the source voltage of the PMOS transistor MP9, the current on the PMOS transistor MP9 will be greater than the current of the current source below, and the energy storage capacitor MNC discharges to the current source branch until the voltage of the VC node is pulled down. Thus, there is the following relationship: when VIP is greater than VIN, VC voltage is high; VIP < VIN the VC voltage is low.
From the above analysis, when the voltage of the VC node is high, the VC node is shaped by the schmitt trigger and then outputs a low level, and the high level SA signal is obtained after passing through the inverter INV1, and the low level SB signal is obtained after passing through the inverter INV 2; when the voltage of the VC node is low, the high level is output after being shaped by the Schmitt trigger, the low level SA signal is output after passing through the inverter INV1, and the high level SB signal is output after passing through the inverter INV 2.
The principle of the maximum voltage selection switch (400, 500) in this embodiment is: when SA is high and SB is low, the voltage selection switch (500) is turned on, the voltage selection switch (400) is turned off, vout=vip; when SA is low and SB is high, the voltage selection switch (400) is turned on, the voltage selection switch (500) is turned off, and vout=vin.
Through the above analysis, the relationship between the voltage signals of each node in the final combing circuit is shown in the following table 1:
input relation VC SA SB Switch 400 Switch 500 VOUT
VIN>VIP Low and low Low and low High height Conduction Closing VIN
VIN<VIP High height High height Low and low Closing Conduction VIP
TABLE 1
Fig. 3 is a schematic diagram showing the relationship between the capacitance MNC of the MOS capacitor and the gate voltage VG of the MOS capacitor according to the present invention. The graph shows the relationship between the capacitance MNC of the MOS capacitor and the voltage applied to the gate, and although the capacitance is not constant during the gate voltage variation, this does not affect the normal function of the automatic maximum voltage selection circuit of the present invention.
FIG. 4 is a schematic diagram showing the final simulation result of a maximum voltage automatic selection circuit according to the present invention. The graph shows that the maximum voltage automatic selection circuit can accurately and quickly select the maximum voltage in the two paths of continuously changing input voltages and transmit the maximum voltage to the output end.
Furthermore, it should be noted that, in this specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to specific embodiments, and that the embodiments may be combined appropriately to form other embodiments that will be understood by those skilled in the art.

Claims (8)

1. A maximum voltage automatic selection circuit is characterized by comprising a bias circuit (100), a cascode current mirror circuit (200), a maximum voltage comparison circuit (300), a Schmitt trigger and maximum voltage selection switches (400, 500). The bias circuit (100) includes a reference current generating circuit (101) and a bias voltage generating circuit (102) for generating a reference current and a bias voltage; the cascode current mirror circuit (200) adopts a cascode current mirror structure, and copies the reference current to be used as a current source of the maximum voltage comparison circuit (300); the maximum voltage comparison circuit (300) is composed of a cascode current source, a protection resistor and an energy storage capacitor MNC; the Schmitt trigger reshapes the result of the maximum voltage comparison circuit and then drives the maximum voltage selection switch; the maximum voltage selection switches (400, 500) adopt complementary CMOS structures, and the maximum voltage is transmitted to the output end after being conducted.
2. The maximum voltage automatic selection circuit according to claim 1, wherein: the reference current generating circuit (101) is composed of an NMOS tube MN1, a resistor RS, a PMOS tube MP1 and a PMOS tube MP 2. The grid electrode of the NMOS tube MN1 is connected with an ideal voltage bias VREF, the source electrode of the NMOS tube MN1 is connected with a resistor RS to form a source electrode negative feedback, and the drain electrode of the NMOS tube MP1 is connected with the drain electrode of the PMOS tube MP 2; one end of the resistor RS is connected with the source electrode of the NMOS tube MN1, and the other end of the resistor RS is grounded; the source electrode of the PMOS tube MP1 is connected with the drain electrode of the PMOS tube MP2, and the grid electrode of the PMOS tube MP1 is connected with bias voltage VBP2; the source of the PMOS tube MP2 is connected with the power supply voltage VINA.
3. The maximum voltage automatic selection circuit according to claim 1, wherein: the bias generating circuit (102) is composed of a PMOS tube MP3, a PMOS tube MP4, a PMOS tube MP5, an NMOS tube MN2 and an NMOS tube MN 3. The source electrode of the PMOS tube MP3 is connected with the power supply voltage VINA, the grid electrode is connected with the bias voltage VBP1, and the drain electrode is connected with the source electrode of the PMOS tube MP 4; the grid electrode of the PMOS tube MP4 is connected with bias voltage VBP2, and the drain electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MN 2; the PMOS tube MP5 is connected with the drain of the NMOS tube MN3 after the gate and the drain are in short circuit, and the source is connected with the power supply voltage VINA; the NMOS tube MN2 is connected with the drain electrode of the PMOS tube MP4 and the grid electrode of the NMOS tube MN3 after the gate and the drain are in short circuit, and the source electrode is grounded; the source of NMOS transistor MN3 is grounded.
4. The maximum voltage automatic selection circuit according to claim 1, wherein: the cascode current mirror circuit (200) is composed of a PMOS tube MP6, a PMOS tube MP7, an NMOS tube MN4, an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8 and an NMOS tube MN 9. The source electrode of the PMOS tube MP6 is connected with the power supply voltage VINA, the grid electrode is connected with the bias voltage VBP1, and the drain electrode is connected with the source electrode of the PMOS tube MP 7; the grid electrode of the PMOS tube MP7 is connected with the bias voltage VBP2, and the drain electrode of the NMOS tube MN4 is connected with the grid electrode of the NMOS tube MN 5; the grid electrode of the NMOS tube MN4 is connected with the bias voltage VBN1, and the source electrode is connected with the drain electrode of the NMOS tube MN 5; the source electrode of the NMOS tube MN5 is grounded; the gates of the NMOS tube MN7 and the NMOS tube MN9 are both connected with the bias voltage VBN2, the sources are both grounded, the drain electrode of the NMOS tube MN7 is connected with the source electrode of the NMOS tube MN6, and the drain electrode of the NMOS tube MN9 is connected with the source electrode of the NMOS tube MN 8; the gates of the NMOS transistor MN6 and the NMOS transistor MN8 are both connected with the bias voltage VBN1, the drain electrode of the NMOS transistor MN6 is connected with the VG node, and the drain electrode of the NMOS transistor MN8 is connected with the VC node.
5. The maximum voltage automatic selection circuit according to claim 1, wherein: the maximum voltage comparison circuit (300) is composed of a resistor RN, a resistor RP, a PMOS tube MP8, a PMOS tube MP9, an energy storage capacitor MNC and two paths of common-source and common-gate current sources. One end of the resistor RN is connected with the input voltage VIN, and the other end of the resistor RN is connected with the source electrode of the PMOS tube MP 8; one end of the resistor RP is connected with the input voltage VIP, and the other end of the resistor RP is connected with the source electrode of the PMOS tube MP 9; the PMOS tube MP8 is connected with the grid electrode of the PMOS tube MP9 after the grid electrode and the drain electrode are short-circuited; the sources of the PMOS tube MP8 and the PMOS tube MP9 are respectively connected with a path of common-source common-gate current source; the energy storage capacitor MNC is a MOS capacitor, and is formed by grounding the source and drain of the NMOS tube and connecting the grid electrode with the VC node.
6. The maximum voltage automatic selection circuit according to claim 1, wherein: the schmitt trigger records the result of the maximum voltage comparison circuit, namely after the voltage at two ends of the energy storage capacitor MNC is shaped, the output of the energy storage capacitor MNC after entering the inverter INV1 as SA; the output of the SA signal after entering the inverter INV2 is recorded as SB; so SA and SB are a pair of logically opposite signals to each other.
7. The maximum voltage automatic selection circuit according to claim 1, wherein: the maximum voltage selection switches (400, 500) are complementary CMOS switches; the VIN branch switch (400) is composed of an NMOS tube MN10 and a PMOS tube MP 10; the VIP branch switch (500) is composed of an NMOS tube MN11 and a PMOS tube MP 11; the grid electrode of the NMOS tube MN10 is connected with an SB signal, the grid electrode of the PMOS tube MP10 is connected with an SA signal, the drain electrode of the NMOS tube MN10 is connected with the source electrode of the PMOS tube MP10 and then is connected with an input signal VIN, and the source electrode of the NMOS tube MN10 is connected with the drain electrode of the PMOS tube MP10 and then is connected with an output signal VOUT; the grid electrode of the NMOS tube MN11 is connected with an SA signal, the grid electrode of the PMOS tube MP11 is connected with an SB signal, the drain electrode of the NMOS tube MN11 is connected with the source electrode of the PMOS tube MP11 and then is connected with an input signal VIP, and the source electrode of the NMOS tube MN11 is connected with the drain electrode of the PMOS tube MP11 and then is connected with an output signal VOUT.
8. The maximum voltage automatic selection circuit according to claim 1, wherein: the power supply voltages of the schmitt trigger, the inverter INV1 and the inverter INV2 are the maximum voltage of the two input voltages, i.e., VOUT.
CN202310762536.6A 2023-06-27 2023-06-27 Automatic maximum voltage selection circuit Pending CN117032386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310762536.6A CN117032386A (en) 2023-06-27 2023-06-27 Automatic maximum voltage selection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310762536.6A CN117032386A (en) 2023-06-27 2023-06-27 Automatic maximum voltage selection circuit

Publications (1)

Publication Number Publication Date
CN117032386A true CN117032386A (en) 2023-11-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310762536.6A Pending CN117032386A (en) 2023-06-27 2023-06-27 Automatic maximum voltage selection circuit

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