CN117012644A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117012644A
CN117012644A CN202210476449.XA CN202210476449A CN117012644A CN 117012644 A CN117012644 A CN 117012644A CN 202210476449 A CN202210476449 A CN 202210476449A CN 117012644 A CN117012644 A CN 117012644A
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CN
China
Prior art keywords
forming
layer
etching
fin
sacrificial
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CN202210476449.XA
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Chinese (zh)
Inventor
张静
陈永强
范义秋
叶南飞
涂武涛
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210476449.XA priority Critical patent/CN117012644A/en
Publication of CN117012644A publication Critical patent/CN117012644A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate; forming a fin structure on the substrate, wherein the fin structure comprises a plurality of layers of sacrificial layers overlapped along the normal direction of the surface of the substrate and a channel layer positioned between two adjacent layers of sacrificial layers; etching the sacrificial layer by adopting a wet etching process, wherein etching liquid for wet etching comprises alkaline solution and oxidizing solution, and the etching liquid has etching property and oxidizing property on the sacrificial layer; under the dual effects, the wet etching process has a larger etching selection ratio on the sacrificial layer, so that damage to the channel layer can be greatly reduced in the process of removing the sacrificial layer, the consistency of the final channel layer is improved, and further, the performance of each finally formed MOS structure is improved, so that the performance of the final semiconductor structure is improved.

Description

Method for forming semiconductor structure
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
Metal-oxide-semiconductor field effect transistors (MOSFETs) are one of the most important elements in modern integrated circuits, the basic structure of a MOSFET comprising: a semiconductor substrate; a gate structure on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; source and drain doped regions in the semiconductor substrate on both sides of the gate structure.
With further development of semiconductor technology, conventional finfet has a limitation in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a MOSFET of a Gate All Around (GAA) structure is proposed, so that the volume for serving as a channel region is increased, further increasing the operating current of the GAA structure MOSFET.
However, the electrical performance of the GAA structure MOSFET in the prior art is still to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a fin structure on the substrate, wherein the fin structure comprises a plurality of layers of sacrificial layers overlapped along the normal direction of the surface of the substrate and a channel layer positioned between two adjacent layers of sacrificial layers; and etching the sacrificial layer by adopting a wet etching process, wherein etching liquid for wet etching comprises alkaline solution and oxidizing solution, and the etching liquid has etching property and oxidizing property on the sacrificial layer.
Optionally, the wet etching is an isotropic wet etching process, and the etching selection ratio of the wet etching process to the sacrificial layer and the channel layer ranges from 4:1 to 150:1.
Optionally, the material of the sacrificial layer is silicon germanium, and the material of the channel layer is monocrystalline silicon.
Optionally, the alkaline solution comprises ammonia; the oxidizing solution comprises hydrogen peroxide.
Optionally, the volume ratio of the alkaline solution to the oxidizing solution is 1:20-20:1.
Optionally, the atomic percentage concentration of germanium atoms in the silicon germanium ranges from 20% to 40%.
Optionally, the etching selectivity of the wet etching process to the sacrificial layer is directly proportional to the atomic percentage concentration of the germanium atoms.
Optionally, the thickness of the sacrificial layer is 2 nm-50 nm, and the thickness of the channel layer is 2 nm-50 nm.
Optionally, the method further comprises: forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the fin structure and covers part of the side wall and the top surface of the fin structure; forming source and drain grooves in fin structures on two sides of the pseudo gate structure; etching part of the sacrificial layer exposed out of the side wall of the source drain groove by adopting the etching liquid, and forming fin part grooves between two adjacent layers of channel layers; and forming a barrier layer in the fin groove.
Optionally, the method for forming the barrier layer includes: forming a first initial barrier layer on the side wall and the bottom surface of the source drain groove and the side wall and the top surface of the pseudo gate structure; etching back the first initial barrier layer until the bottom surface of the source drain groove and the top surface of the pseudo gate structure are exposed, and forming a second initial barrier layer; and etching back the second initial barrier layer until the side wall of the channel layer is exposed, so as to form the barrier layer.
The method of forming a semiconductor structure of claim 9, wherein the material of the barrier layer comprises silicon nitride.
Optionally, after forming the barrier layer, the method further includes: and forming a source-drain doped layer in the source-drain groove, wherein source-drain ions are arranged in the source-drain doped layer.
Optionally, the method for forming the source-drain groove includes: and etching the fin part structure by taking the pseudo gate electrode structure as a mask until the top surface of the substrate is exposed, and forming the source and drain grooves in the fin part structures at two sides of the pseudo gate electrode structure.
Optionally, the dummy gate structure includes a dummy gate layer.
Optionally, the process of forming the first initial barrier layer includes a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
Optionally, the process of etching back the first initial barrier layer and the second initial barrier layer includes a wet etching process or a dry etching process.
Optionally, the forming process of the source-drain doped layer comprises an epitaxial growth process; the process of doping the source-drain ions in the source-drain doping layer comprises an in-situ doping process.
Optionally, after forming the source-drain doped layer, the method further includes: forming a dielectric layer on the substrate, the fin part structure and the side wall surface of the pseudo gate structure, wherein the dielectric layer exposes the top surface of the pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the dielectric layer; etching the gate opening to expose the sacrificial layer by adopting a wet etching process, and forming a gate groove between adjacent channel layers; a gate structure is formed within the gate opening and the gate trench, the gate structure surrounding the channel layer.
Optionally, the material of the dummy gate layer includes polysilicon or amorphous silicon.
Optionally, the forming method of the fin structure includes: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of layers of sacrificial material films overlapped along the normal direction of the surface of the substrate and channel material films positioned in two adjacent layers of sacrificial material films; forming a patterning layer on the fin material film; and etching the fin material film by taking the patterned layer as a mask to form the fin structure, wherein the fin structure comprises a plurality of layers of sacrificial layers overlapped along the normal direction of the surface of the substrate and a channel layer positioned between two adjacent layers of sacrificial layers.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, the sacrificial layer is etched by adopting a wet etching process, the etching liquid for wet etching comprises an alkaline solution and an oxidizing solution, the etching liquid has etching property and oxidizing property on the sacrificial layer, and the etching liquid has etching property and oxidizing property on the sacrificial layer.
Drawings
FIGS. 1-2 are schematic diagrams of a semiconductor structure;
fig. 3 to 13 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background art, the electrical performance of the GAA structure MOSFET in the prior art is still to be improved. The following will make a detailed description with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided; forming a fin structure on the substrate 100, wherein the fin structure comprises a plurality of layers of sacrificial layers 101 overlapped along the normal direction of the surface of the substrate, and a channel layer 102 positioned between two adjacent layers of sacrificial layers 101; a dummy gate structure 103 is formed on the substrate 100 across the fin structure, the dummy gate structure 103 covering a portion of the fin structure sidewall and a portion of the top surface.
Referring to fig. 2, source-drain grooves 104 are formed in fin structures at two sides of the dummy gate structure 103; and removing part of the sacrificial layer 101 exposed from the side wall of the source drain groove 104 to form a fin groove 105.
However, in the above embodiment, in a subsequent process, a barrier layer (not shown) needs to be formed in the fin recess 105; after the barrier layer is formed, the sacrificial layer 101 is removed, and a gate trench (not shown) is formed between adjacent channel layers 102; after the gate trenches are formed, gate structures (not shown) are formed within the gate trenches. Since the removal of the sacrificial layer 101 after the formation of the fin recess 105 may result in a loss of the channel layer 102 to different extents, after the formation of the gate structure, the shape, length, etc. of the channel region formed by the channel layer 102 surrounded by the gate structure may also be different, so that the performance of each MOS structure formed may be different, which may further result in poor performance of the final semiconductor structure.
On the basis, the invention provides a method for forming a semiconductor structure, wherein in the process of removing the sacrificial layer by using etching liquid, the etching rate of the etching liquid on the sacrificial layer is larger than the etching rate of the etching liquid on the channel layer, so that the damage to the channel layer can be greatly reduced in the process of removing the sacrificial layer, the consistency of the final channel layer is improved, and further, the performance of each finally formed MOS structure is improved, thereby improving the performance of the final semiconductor structure.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 13 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided.
The material of the substrate 200 may be monocrystalline silicon or monocrystalline germanium silicon; in this embodiment, the substrate 200 is made of monocrystalline silicon germanium.
Referring to fig. 4, a fin structure is formed on the substrate 200, and the fin structure includes a plurality of sacrificial layers 201 overlapping along a surface normal direction of the substrate 200, and a channel layer 202 between two adjacent sacrificial layers 201.
In this embodiment, the number of layers of the sacrificial layer 201 is three; the number of channel layers 202 is also three.
In this embodiment, the thickness of the sacrificial layer 201 is 2nm to 50nm, and the thickness of the channel layer 202 is 2nm to 50nm.
In this embodiment, the method for forming the fin structure includes: forming a fin material film (not shown) on the substrate 200, wherein the fin material film comprises a plurality of layers of sacrificial material films overlapped along the normal direction of the surface of the substrate 200 and channel material films positioned in two adjacent layers of sacrificial material films; forming a patterned layer (not shown) on the fin material film; and etching the fin material film by taking the patterned layer as a mask to form the fin structure, wherein the fin structure comprises a plurality of layers of sacrificial layers 201 overlapped along the surface normal direction of the substrate 200 and a channel layer 202 positioned between two adjacent layers of sacrificial layers 201.
In this embodiment, the materials of the sacrificial layer 201 and the channel layer 202 are different. The purpose is to remove the sacrificial layer 201 when the gate structure is formed later, so that the damage to the channel layer 202 in the process of removing the sacrificial layer 201 is reduced by adopting different materials to have a larger etching selectivity ratio of the sacrificial layer 201 and the channel layer 202.
In this embodiment, the material of the sacrificial layer 201 is silicon germanium, and the material of the channel layer 202 is monocrystalline silicon.
In this embodiment, the atomic percentage concentration of germanium atoms is in the range of 20% -40%.
In this embodiment, after the fin material film is etched to form the fin structure, the method further includes: etching part of the substrate 200 by taking the fin structure as a mask; an isolation structure 203 is formed on the substrate 200, the top surface of the isolation structure 203 being lower than the top surface of the substrate 200.
The material of the isolation structure 203 includes silicon oxide or silicon nitride. In this embodiment, the isolation structure 203 is made of silicon nitride.
Referring to fig. 5, a dummy gate structure is formed on the substrate 200 across the fin structure, the dummy gate structure covering a portion of the sidewalls and top surface of the fin structure.
In this embodiment, the dummy gate structure includes: the device comprises a gate dielectric layer 204 positioned on the fin structure, a dummy gate layer 205 positioned on the gate dielectric layer 204, a protection layer 206 positioned on the dummy gate layer 205, and a side wall 207 positioned on the side walls of the dummy gate layer 205 and the protection layer 206.
In this embodiment, the material of the dummy gate layer 205 is polysilicon; in other embodiments, amorphous silicon may also be used as the material of the dummy gate layer.
In this embodiment, the material of the protection layer 206 is silicon nitride; in other embodiments, the material of the protective layer may also be silicon oxide.
The method for forming the side wall 207 includes: forming a sidewall material layer (not shown) on the top surface of the gate dielectric layer 204, the sidewall of the dummy gate layer 205, and the sidewall and top surface of the protection layer 206; and etching the side wall material layer until the protection layer 206 and the top surface of the gate dielectric layer 204 are exposed, thereby forming the side wall 207.
The forming process of the side wall material layer is one or a combination of a plurality of chemical vapor deposition processes, physical vapor deposition processes or atomic layer deposition processes.
In this embodiment, the formation process of the sidewall material layer adopts an atomic layer deposition process.
The material of the sidewall 207 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the material of the side wall 207 is silicon nitride.
In this embodiment, the sidewall 207 is used to define the position of the subsequent source-drain doped layer.
Referring to fig. 6, source-drain grooves 208 are formed in the fin structures on both sides of the dummy gate structure.
In this embodiment, the method for forming the source-drain recess 208 includes: and etching the fin structure by taking the pseudo gate structure as a mask until the top surface of the substrate 200 is exposed, and forming the source-drain grooves 208 in the fin structure at two sides of the pseudo gate structure.
In this embodiment, the source-drain recess 208 is used to provide a space for the source-drain doped layer to be formed later.
The process for etching the fin structure comprises the following steps: an anisotropic dry etching process or an anisotropic wet etching process. In this embodiment, the process of etching the fin structure is an anisotropic dry etching process, and parameters of the dry etching process include: the etching gas comprises HBr and Ar, wherein the flow rate of the HBr is 10 sccm-1000 sccm, and the flow rate of the Ar is 10 sccm-1000 sccm.
Referring to fig. 7, a wet etching process is used to etch and remove a portion of the sacrificial layer 201 exposed by the sidewall of the source-drain recess 208, and fin recesses 209 are formed between two adjacent channel layers 202.
In this embodiment, the fin recess 209 is used to provide space for a barrier layer to be formed later.
In this embodiment, the etching solution for wet etching includes an alkaline solution and an oxidizing solution.
In this embodiment, the etching solution has both etching property and oxidizing property on the sacrificial layer 201, and under the dual action, the wet etching process has a larger etching selection ratio on the sacrificial layer, so that damage to the channel layer can be greatly reduced in the process of removing the sacrificial layer, the consistency of the final channel layer is improved, and further, the performance of each finally formed MOS structure is improved, thereby improving the performance of the final semiconductor structure.
In this embodiment, the wet etching is isotropic wet etching, and since the isotropic wet etching is utilized, it is ensured that there is an equal etching amount in all directions, thereby improving the quality of etching the sacrificial layer 201.
In this embodiment, the etching selectivity of the etching solution to the sacrificial layer 201 is greater than the etching selectivity of the etching solution to the channel layer 202, so that damage to the channel layer 202 is reduced in the process of etching to form the fin recess 209, loss of the channel layer 202 is reduced, structural consistency of the channel layer 202 is improved, and preparation is made for forming a semiconductor device with high quality subsequently.
In this embodiment, the ratio of the etching selectivity of the etching solution to the sacrificial layer 201 to the etching selectivity of the etching solution to the channel layer 202 ranges from 4:1 to 150:1, and when the ratio of the etching selectivity of the etching solution to the sacrificial layer 201 to the etching selectivity of the etching solution to the channel layer 202 is less than 4:1, damage is easily caused to the channel layer 202 during the process of etching and removing the sacrificial layer 201, and the damage amount of the channel layer 202 is increased, so that the difference between different channel layers 202 is increased, which is unfavorable for forming a semiconductor structure with stable performance.
In this embodiment, the alkaline solution comprises aqueous ammonia; the oxidizing solution comprises hydrogen peroxide
In this embodiment, the volume ratio of the alkaline solution to the oxidizing solution is 1:20 to 20:1; when the volume ratio of the alkaline solution to the oxidizing solution is less than 1:20, the reaction rate is very slow, and the process requirement is difficult to meet; when the volume ratio of the alkaline solution to the oxidizing solution is greater than 20:1, the reaction is too fast and monocrystalline silicon is at risk of being anisotropically etched by alkali.
In this embodiment, the volume ratio of the alkaline solution to the oxidizing solution is adjusted to adjust the etching selectivity to the sacrificial layer 201 to achieve the final desired etching selectivity.
In this embodiment, the etching selectivity of the etching solution to the sacrificial layer 201 is proportional to the atomic percentage concentration of the germanium atoms.
Referring to fig. 8, a barrier layer 210 is formed in the fin recess 209.
Because the formed side wall of the fin recess 209 has a flat shape, the thickness of the barrier layer 210 formed in the fin recess 209 is uniform, and a source-drain doped layer and a gate structure need to be formed in a subsequent process, and the isolation effect between the source-drain doped layer and the gate structure can be effectively improved through the barrier layer 212 with a uniform thickness.
In this embodiment, the method for forming the barrier layer 210 includes: forming a first initial barrier layer (not shown) on the sidewalls and bottom surfaces of the source drain recess 208 and the sidewalls and top surfaces of the dummy gate structure; etching back the first initial barrier layer until the bottom surfaces of the source-drain grooves 208 and the top surfaces of the dummy gate structures are exposed, and forming a second initial barrier layer (not shown); the second initial barrier layer is etched back until the channel layer 202 sidewalls are exposed, forming the barrier layer 210.
In this embodiment, the material of the blocking layer 210 is silicon nitride.
The process of forming the first initial barrier layer includes a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. In this embodiment, the first initial barrier layer is formed by an atomic layer deposition process.
The process of etching back the first initial barrier layer and the second initial barrier layer includes a wet etching process or a dry etching process. In this embodiment, a dry etching process is used in the process of etching back the first initial barrier layer and the second initial barrier layer, and parameters of the dry etching process include: the etching gas includes CF 4 And CH (CH) 2 F 2 Wherein CF is 4 The flow rate of (C) is 50 sccm-500 sccm, CH 2 F 2 The flow rate of the water is 30sccm to 100sccm.
In this embodiment, the thickness of the barrier layer 210 is 1nm to 5nm, and the thickness direction of the barrier layer 210 is a direction parallel to the top surface of the substrate 200.
Referring to fig. 9, after the barrier layer 210 is formed, a source-drain doped layer 211 is formed in the source-drain recess 208, and source-drain ions are contained in the source-drain doped layer 211.
In this embodiment, the forming process of the source-drain doped layer 211 includes an epitaxial growth process; the process of doping the source drain ions within the source drain doped layer 214 includes an in-situ doping process.
When the semiconductor structure is a P-type device, the material of the source-drain doped layer 211 includes: silicon, germanium or silicon germanium; the source-drain ions are P-type ions, and comprise boron ions and BF 2- Ions or indium ions; when the semiconductor structure is an N-type device, the material of the source-drain doped layer 211 includes: silicon, gallium arsenide or indium gallium arsenide; the source-drain ions are N-type ions, and the source-drain ions comprise phosphorus ions or arsenic ions.
In this embodiment, the semiconductor structure is an N-type device, the material of the source-drain doped layer 211 is silicon, and the source-drain ions are phosphorus ions.
After the source-drain doped layer 211 is formed, forming a dielectric layer on the substrate 200, the fin structure and the side wall surface of the pseudo gate structure, wherein the dielectric layer exposes the top surface of the pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the dielectric layer; removing the gate opening to expose the sacrificial layer 201, and forming a gate trench between adjacent channel layers 202; a gate structure is formed within the gate opening and the gate trench, the gate structure surrounding the channel layer 202. The specific process of forming the gate structure is shown in fig. 10 to 13.
Referring to fig. 10, a dielectric layer 212 is formed on the substrate 200, the fin structure and the side wall surface of the dummy gate structure, and the dielectric layer 212 exposes the top surface of the dummy gate structure.
In this embodiment, the dielectric layer 212 specifically covers the source-drain doped layer 211 and the sidewalls of the dummy gate structure, exposing the top surface of the dummy gate structure.
In this embodiment, the method for forming the dielectric layer 212 includes: forming an initial dielectric layer (not shown) on the source-drain doped layer 211 and the dummy gate structure, the initial dielectric layer covering a top surface and a sidewall surface of the dummy gate structure; the initial dielectric layer is planarized until the surface of the protective layer 206 on top of the dummy gate structure is exposed, forming the dielectric layer 212.
In this embodiment, the material of the dielectric layer 212 is silicon oxide.
Referring to fig. 11, the dummy gate structure is removed, and a gate opening 213 is formed in the dielectric layer 212.
In this embodiment, the protection layer 206 and the dummy gate layer 205 of the dummy gate structure are specifically removed.
Referring to fig. 12, the gate opening 213 is removed to expose the sacrificial layer 201, and a gate trench 214 is formed between adjacent channel layers 202.
In this embodiment, the sacrificial layer 201 is etched by a wet etching process, and the etching solution of the wet etching includes an alkaline solution and an oxidizing solution, and has both etching property and oxidizing property for the sacrificial layer.
In this embodiment, the volume ratio of the alkaline solution to the oxidizing solution is 1:20 to 20:1.
In this embodiment, the ratio of the alkaline solution to the oxidizing solution is adjusted to adjust the etching selectivity of the sacrificial layer 201 to the final desired etching selectivity.
In this embodiment, the etching selectivity of the etching solution to the sacrificial layer 201 is greater than the etching selectivity of the etching solution to the channel layer 202, so that in the process of removing the sacrificial layer to form the gate trench 214, damage to the channel layer 202 can be greatly reduced, uniformity of morphology of the channel layer 202 is ensured, and performance of the semiconductor structure is improved.
In this embodiment, the etching solution has both an oxidizing effect and an etching effect on the sacrificial layer 201, so that the etching solution has a larger etching selectivity ratio on the sacrificial layer 201 than on the channel layer 202 under the dual effects, thereby further reducing damage to the channel layer 202, reducing loss of the channel layer 202, and improving structural consistency of the channel layer 202 finally, so as to ensure performance of the semiconductor structure finally formed.
Referring to fig. 13, a gate structure is formed in the gate opening 213 and the gate trench 214, and surrounds the channel layer 202.
Through the barrier layer 210 with the thickness of 1nm to 5nm, the gate structure and the source-drain doped layer 211 can be effectively isolated, and meanwhile, too much occupied formation space of the gate structure is avoided, so that the length of the channel region formed by the gate structure surrounding the channel layer 202 is reduced, and further, the performance of the finally formed semiconductor structure is influenced.
In this embodiment, the gate structure includes a gate layer 215.
The material of the gate layer 215 is a metal, and the metal material includes one or more of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.
In this embodiment, tungsten is used as the material of the gate layer 215.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a fin structure on the substrate, wherein the fin structure comprises a plurality of layers of sacrificial layers overlapped along the normal direction of the surface of the substrate and a channel layer positioned between two adjacent layers of sacrificial layers;
and etching the sacrificial layer by adopting a wet etching process, wherein etching liquid for wet etching comprises alkaline solution and oxidizing solution, and the etching liquid has etching property and oxidizing property on the sacrificial layer.
2. The method of claim 1, wherein the wet etching is an isotropic wet etching process, and the wet etching process has an etching selectivity to the sacrificial layer and the channel layer in a range of 4:1 to 150:1.
3. The method of claim 1, wherein the material of the sacrificial layer is silicon germanium and the material of the channel layer is monocrystalline silicon.
4. The method of forming a semiconductor structure of claim 3, wherein the alkaline solution comprises aqueous ammonia; the oxidizing solution comprises hydrogen peroxide.
5. The method of forming a semiconductor structure of claim 3, wherein a volume ratio of said alkaline solution to said oxidizing solution is from 1:20 to 20:1.
6. The method of forming a semiconductor structure of claim 3, wherein the concentration of germanium atoms in the silicon germanium ranges from 20% to 40% by atomic percentage.
7. The method of claim 6, wherein an etch selectivity of the wet etch process to the sacrificial layer is proportional to an atomic percent concentration of the germanium atoms.
8. The method of forming a semiconductor structure of claim 1, wherein the sacrificial layer has a thickness of 2nm to 50nm and the channel layer has a thickness of 2nm to 50nm.
9. The method of forming a semiconductor structure of claim 1, further comprising: forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the fin structure and covers part of the side wall and the top surface of the fin structure; forming source and drain grooves in fin structures on two sides of the pseudo gate structure; etching part of the sacrificial layer exposed out of the side wall of the source drain groove by adopting the wet etching process, and forming fin part grooves between two adjacent layers of channel layers; and forming a barrier layer in the fin groove.
10. The method of forming a semiconductor structure of claim 9, wherein the method of forming a barrier layer comprises: forming a first initial barrier layer on the side wall and the bottom surface of the source drain groove and the side wall and the top surface of the pseudo gate structure; etching back the first initial barrier layer until the bottom surface of the source drain groove and the top surface of the pseudo gate structure are exposed, and forming a second initial barrier layer; and etching back the second initial barrier layer until the side wall of the channel layer is exposed, so as to form the barrier layer.
11. The method of forming a semiconductor structure of claim 9, wherein the material of the barrier layer comprises silicon nitride.
12. The method of forming a semiconductor structure of claim 9, further comprising, after forming the barrier layer: and forming a source-drain doped layer in the source-drain groove, wherein source-drain ions are arranged in the source-drain doped layer.
13. The method of forming a semiconductor structure of claim 9, wherein the method of forming a source drain recess comprises: and etching the fin part structure by taking the pseudo gate electrode structure as a mask until the top surface of the substrate is exposed, and forming the source and drain grooves in the fin part structures at two sides of the pseudo gate electrode structure.
14. The method of forming a semiconductor structure of claim 9, wherein the dummy gate structure comprises a dummy gate layer.
15. The method of forming a semiconductor structure of claim 10, wherein the process of forming the first initial barrier layer comprises a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
16. The method of forming a semiconductor structure of claim 10, wherein the process of etching back the first initial barrier layer and the second initial barrier layer comprises a wet etching process or a dry etching process.
17. The method of forming a semiconductor structure of claim 12, wherein the process of forming the source-drain doped layer comprises an epitaxial growth process; the process of doping the source-drain ions in the source-drain doping layer comprises an in-situ doping process.
18. The method of forming a semiconductor structure of claim 12, further comprising, after forming the source-drain doped layer: forming a dielectric layer on the substrate, the fin part structure and the side wall surface of the pseudo gate structure, wherein the dielectric layer exposes the top surface of the pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the dielectric layer; etching the gate opening to expose the sacrificial layer by adopting a wet etching process, and forming a gate groove between adjacent channel layers; a gate structure is formed within the gate opening and the gate trench, the gate structure surrounding the channel layer.
19. The method of forming a semiconductor structure of claim 14, wherein the material of the dummy gate layer comprises polysilicon or amorphous silicon.
20. The method of forming a semiconductor structure of claim 1, wherein the method of forming a fin structure comprises: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of layers of sacrificial material films overlapped along the normal direction of the surface of the substrate and channel material films positioned in two adjacent layers of sacrificial material films; forming a patterning layer on the fin material film; and etching the fin material film by taking the patterned layer as a mask to form the fin structure, wherein the fin structure comprises a plurality of layers of sacrificial layers overlapped along the normal direction of the surface of the substrate and a channel layer positioned between two adjacent layers of sacrificial layers.
CN202210476449.XA 2022-04-29 2022-04-29 Method for forming semiconductor structure Pending CN117012644A (en)

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