CN116994965A - 形成无基板的SiP模块的半导体器件和方法 - Google Patents

形成无基板的SiP模块的半导体器件和方法 Download PDF

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Publication number
CN116994965A
CN116994965A CN202310259611.7A CN202310259611A CN116994965A CN 116994965 A CN116994965 A CN 116994965A CN 202310259611 A CN202310259611 A CN 202310259611A CN 116994965 A CN116994965 A CN 116994965A
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Prior art keywords
substrate
encapsulant
terminals
bumps
semiconductor device
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CN202310259611.7A
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Inventor
权智恩
文智植
李基喆
林保利
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Publication of CN116994965A publication Critical patent/CN116994965A/zh
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Abstract

本公开涉及形成无基板的SiP模块的半导体器件和方法。半导体器件具有牺牲基板和设置在牺牲基板上的电组件。在牺牲基板内形成凸块阻止层。电组件的凸块或端子的至少一部分嵌入到牺牲基板中以接触凸块阻止层。在所述电组件和牺牲基板上沉积密封剂。形成穿过所述密封剂且部分进入所述牺牲基板的通道。去除牺牲基板以使电组件的凸块或端子从密封剂延伸出。半导体元件的厚度由密封剂以及从密封剂延伸出的凸块的厚度确定。可以去除密封剂的一部分以减小半导体器件的厚度。导电膏可以沉积在从密封剂延伸出的凸块或端子上。

Description

形成无基板的SiP模块的半导体器件和方法
技术领域
本发明一般地涉及半导体器件，并且更特别地涉及形成无基板的SiP模块的半导体和方法。
背景技术
半导体器件通常存在于现代电子产品中。半导体器件执行各种各样的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子器件、光电以及为电视显示器创建可视图像。半导体器件存在于通信、功率转换、网络、计算机、娱乐和消费产品的领域中。半导体器件也存在于军事应用、航空、汽车、工业控制器和办公设备中。
多个半导体管芯、分立半导体器件、和集成无源器件(IPD)可以集成到系统级封装(SiP)模块中，以在小空间中实现更高的密度和扩展的电功能。在SiP模块内，半导体管芯和IPD被安装到基板以用于结构支撑和电互连。密封剂沉积在半导体管芯、分立半导体器件、IPD和基板上。SiP模块的总高度由密封剂和基板的组合高度确定。减小SiP模块的高度将是优选的。
附图说明
图1a-1c示出具有由切道分开的多个半导体管芯的半导体晶片；
图2a-2k示出形成没有基板的SiP模块的工艺；
图3a-3c示出形成具有嵌入式凸块阻止层的牺牲基板的工艺；
图4示出具有嵌入在牺牲基板中下至凸块蚀刻阻止层的凸块的电组件；
图5示出从密封剂延伸出的电组件的凸块；
图6a-6d示出形成没有基板的SiP模块的另一工艺；
图7a-7e示出形成没有基板的SiP模块的另一工艺；
图8a-8e示出形成没有基板的SiP模块的另一工艺；
图9a-9c示出形成没有基板的SiP模块的另一工艺；以及图10示出具有安装到PCB表面的不同类型的封装的印刷电路板(PCB)。
具体实施方式
在以下描述中，参考附图以一个或多个实施例来描述本发明，其中，相同的附图标记表示相同或相似的元件。虽然根据用于实现本发明的目的的最佳模式描述本发明，但是本领域技术人员将会理解，本发明旨在覆盖可以包括在由所附权利要求以及它们的由以下公开和附图支持的等同物限定的本发明的精神和范围内的替代、修改和等同物。本文中所使用的术语“半导体管芯”指代单数形式和复数形式的词语两者，且因此可以指代单个半导体器件和多个半导体器件两者。
半导体器件通常是使用两种复杂的制造工艺来制造的：前端制造和后端制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含被电连接以形成功能电路的有源和无源电组件。诸如晶体管和二极管的有源电组件具有控制电流流动的能力。诸如电容器、电感器和电阻器的无源电组件创建执行电路功能所需的、电压和电流之间的关系。
后端制造指代将完成的晶片切割或单片化为个体半导体管芯并且封装该半导体管芯以用于结构支撑、电互连和环境隔离。为了单片化半导体管芯，晶片沿着称为切道或划线的晶片的非功能区来刻划和断开。使用激光切割工具或锯刀将晶片单片化。在单片化之后，将个体半导体管芯安装到封装基板，所述封装基板包括用于与其它系统组件互连的引脚或接触焊盘。然后将形成在半导体管芯上的接触焊盘连接到封装内的接触焊盘。可以用导电层、凸块、柱形凸块、导电膏或接合线来进行电连接。密封剂或其它模制材料沉积在封装上以提供物理支撑和电隔离。然后将完成的封装插入到电系统中，并且使半导体器件的功能可用于其它系统组件。
图1a示出具有基底基板材料102的半导体晶片100，所述基底基板材料102诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或用于结构支撑的其它块体材料。多个半导体管芯或组件104形成在晶片100上，由非有源、管芯间晶片区域或切道106分开。切道106提供切割区域以将半导体晶片100单片化成个体半导体管芯104。在一个实施例中，半导体晶片100具有100-450毫米(mm)的宽度或直径。
图1b示出半导体晶片100的一部分的截面图。每个半导体管芯104具有背面或非有源表面108和有源表面110，所述有源表面110包含：模拟或数字电路，被实现为根据管芯的电设计和功能而形成在管芯内且电互连的有源器件、无源器件、导电层和介电层。例如，电路可以包括一个或多个晶体管、二极管和被形成在有源表面110内以实现模拟电路或数字电路的其它电路元件，诸如数字信号处理器(DSP)、专用集成电路(ASIC)、存储器或其它信号处理电路。半导体管芯104也可以包含用于RF信号处理的IPD，诸如电感器、电容器和电阻器。
使用PVD、CVD、电解电镀、化学电镀工艺或其它合适的金属沉积工艺在有源表面110上形成导电层112。导电层112可以是一层或多层铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)或其它合适的导电材料。导电层112作为电连接到有源表面110上的电路的接触焊盘操作。
使用蒸发、电解电镀、化学电镀、球滴或丝网印刷工艺在导电层112上沉积导电凸块材料。凸块材料可以是具有可选助焊剂溶液的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料可以是共晶Sn/Pb、高铅焊料或无铅焊料。使用合适的附着或接合工艺将凸块材料接合到导电层112。在一个实施例中，通过将凸块材料加热到其熔点以上来使该材料回流以形成球或凸块114。在一个实施例中，凸块114形成在具有润湿层、阻挡层和粘合层的凸块下金属化层(UBM)上。凸块114也可以被压紧接合或热压接合到导电层112。凸块114表示可以在导电层112上形成的一种类型的互连结构。互连结构也可以使用接合线、导电膏、柱形凸块、微凸块或其它电互连。
在图1c中，使用锯刀或激光切割工具118通过切道106将半导体晶片100单片化成个体半导体管芯104。可以检查和电测试个体半导体管芯104，以识别单片化后已知的良好管芯或单元(KGD/KGU)。
图2a-2k示出形成没有基板的SiP模块的工艺。图2a示出包括顶部主表面122和底部主表面124的牺牲基板或载板120的截面图。基板120包含牺牲材料，该牺牲材料提供结构支撑并且可以在随后的步骤中容易地去除。牺牲基底材料可以是塑料、聚合物、氧化铍、玻璃或其它合适的低成本刚性材料。在一个实施例中，基板120由预浸渍的聚四氟乙烯(预浸料坯)、FR-4、FR-1、CEM-1或CEM-3与酚醛棉纸、环氧树脂、编织玻璃、哑光玻璃、聚酯和其它加强纤维或织物的组合的一个或多个层压层制成。凸块阻止层128嵌入在基板120内，在表面122下方。
图3a-3c示出形成凸块阻止层128的进一步细节。图3a示出基板120的一部分。在附图中，具有类似功能的元件被分配相同的附图标记。在图3b中，在基板120上形成凸块阻止层128。凸块阻止层128可以是金属层或能够阻止导电凸块114的穿透的其它刚性材料，如下所述。在图3c中，使用PVD、CVD、印刷、旋涂、喷涂、狭缝涂布、辊涂、层压或烧结在基板120和凸块阻止层128上形成可穿透薄膜层132。在一个实施例中，可穿透薄膜层132是聚合物、环氧树脂、丙烯基的B阶材料或具有可穿透特性的其它类似材料。可穿透薄膜层132具有125微米(μm)的厚度。替选地，可穿透薄膜层132可以为一层或多层二氧化硅(SiO2)、氮化硅(Si3N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、二氧化硅(SiO2)、氮化硅(Si2N4)、氮氧化硅(SiON)、五氧化二钽(Ta2O5)、氧化铝(Al2O3)、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或具有类似绝缘及结构性质的其它材料。可穿透薄膜层132作为用于附着电子组件的临时可穿透基板操作。可穿透薄膜层132被认为是基板120的一部分，并且可穿透薄膜层的顶部表面成为基板120的主表面122。
在图2b中，多个电组件130a-130h被安装到基板120的表面122。使用拾取和放置操作将每个电组件130a-130h定位在基板120上。例如，电组件130a和130e可以是来自图1c的半导体管芯104，其中，有源表面110和凸块114朝向基板120的表面122取向。电组件130b和130f可以是分立的电器件，诸如晶体管、二极管、电阻器、电容器和电感器。电组件130b和130f具有用于电互连的端子134。电组件130c、130d、130g和130h可以被制成类似于半导体管芯104，尽管可能具有不同的形式和功能，其中，凸块114朝向表面122取向。替选地，电组件130a-130h可以包括其它半导体管芯、半导体封装和表面安装器件。
特别地，电组件130a-130h被设置在表面122上，然后用力F压入基板120中，使得凸块114和端子134在基板表面下方延伸以接触凸块阻止层128。作为示例，图4示出具有延伸到基板120中的凸块114的电组件130a的进一步细节。在这种情况下，凸块114被压入基板120中，并且在表面122下方至少部分地延伸到可穿透薄膜层132中并接触凸块阻止层128。
图2c示出设置在表面122上的电组件130a-130h，其中，电组件的凸块114、端子134或其它电互连至少部分地延伸到基板120中以接触凸块阻止层128。特别地，图4示出了具有嵌入到可穿透薄膜层132中以接触凸块阻止层128的凸块114的示例性电组件130a的进一步细节。如图3c中所限定的，电组件130a的凸块114至少部分地延伸到基板120中，以接触凸块阻止层128。
在图2d中，使用膏印刷、压紧模制、转移模制、液体密封剂模制、真空层压、旋涂或其它合适的施加器将密封剂或模制化合物138沉积在组件130a-130h和基板120上和周围。密封剂138可以是聚合物复合材料，诸如具有填充物的环氧树脂、具有填充物的环氧丙烯酸酯、或具有适当填充物的聚合物。密封剂138是不导电的，提供结构支撑，并且在环境上保护半导体器件不受外部元件和污染物的影响。
在图2e中，使用锯刀或激光切割工具142在密封剂138的表面141中切割通道140。通道140完全延伸穿过密封剂138，并且部分但不完全穿过基板120。通道140至少延伸超过凸块阻止层128。基板120的剩余厚度是T1，大约100-100μm。
在图2f中，通过研磨机144将包括凸块阻止层128的牺牲基板120去除，下至电组件130a-130h的凸块114和端子134。研磨机144可以相对于表面146以一定角度倾斜来操作。替选地，通过化学蚀刻、化学机械抛光(CMP)、机械剥离、机械研磨、热烘、紫外(UV)光、激光扫描或湿法剥离来去除基板120，以暴露电组件130a-130h的凸块114和端子134。研磨操作完成了将基板120单片化成SiP模块148a和148b。
在图2g中，通过蚀刻工艺去除研磨后的基板120的剩余部分，使得凸块114和端子134从密封剂138的表面146延伸出。凸块114和端子134的至少一部分从密封剂138延伸出超过表面146。
图2h示出了研磨后的SIP模块148a，其中，电组件130a-130d的凸块114和端子134从密封剂138延伸。电组件130a-130d的凸块114和端子134由于凸块和端子已经至少部分地嵌入在基板120内并且然后去除基板以暴露凸块和端子的性质而从密封剂138的表面146延伸出。图5示出了具有从密封剂138延伸的凸块114的示例性电路组件130a的进一步细节。凸块114由于凸块已经至少部分地嵌入在基板120内的性质(如图4所示)并且然后去除基板以暴露凸块而从密封剂138的表面146延伸出。包含电组件130e-130h的SiP模块148b的情况也是如此。电组件130e-130h的凸块114和端子134由于凸块和端子已经至少部分地嵌入在基板120内并且然后去除基板以暴露凸块和端子的性质而从密封剂138的表面146延伸出。
与具有基板的SiP模块相比，去除基板120并使电组件130a-130h的凸块114和端子134从密封剂138延伸出减小了SiP模块148a和148b的厚度。SiP模块148a和148b的厚度变成密封剂138和暴露的凸块114和端子134的厚度T2。在一个实施例中，SiP模块148a和148b的厚度可以是T2，大约640μm。通过取消基板120，SiP模块148a和148b具有减小的厚度。SiP模块148a和148b没有基板120。
在图2i中，可选地通过研磨机150去除密封剂138的一部分，以进一步减小SiP模块148a的厚度。在图2j的情况下，SiP模块148a和148b的厚度可以是T3，大约340μm。
在图2k中，可以在暴露的凸块114和端子134上沉积焊膏156。
在另一实施例中，从图2d继续，通过研磨机160去除包括凸块阻止层128的基板120，下至电组件130a-130h的凸块114和端子134，如图6a中所示。研磨机160可以相对于表面162以一定角度倾斜来操作。替选地，通过化学蚀刻、CMP、机械剥离、机械研磨、热烘、UV光、激光扫描或湿法剥离来去除基板120，以暴露电组件130a-130h的凸块114和端子134。
研磨后，通过蚀刻工艺去除基板120的剩余部分，使得凸块114和端子134从表面162延伸出。凸块114和端子134的至少一部分从密封剂138延伸出超过表面162。图6b示出了研磨后从密封剂138延伸的电组件130a-130h的凸块114和端子134。焊膏164可以沉积在暴露的凸块114和端子134上。
在图6c中，使用锯刀或激光切割工具166来单片化密封剂138。SiP模块168a包括具有延伸出超过密封剂138的表面162的凸块114和端子134的电组件130a-130d。SiP模块168b包括具有延伸出超过密封剂138的表面162的凸块114和端子134的电组件130e-130h。
图6d示出研磨后的SIP模块168a，其中，电组件130a-130d的凸块114和端子134延伸出超过密封剂138的表面162。电组件130a-130d的凸块114和端子134由于凸块和端子已经至少部分地嵌入在基板120内并且然后去除基板以暴露凸块和端子的性质而从密封剂138的表面162延伸出。图5示出具有从密封剂138延伸的凸块114的示例性电路组件130a的进一步细节。凸块114由于凸块已经至少部分地嵌入在基板120内(如图4所示)并且然后去除基板以暴露凸块的性质而从密封剂138的表面162延伸出。包含电组件130e-130h的SiP模块168b的情况也是如此。电组件130e-130h的凸块114和端子134由于凸块和端子已经至少部分地嵌入在基板120内并且然后去除基板以暴露凸块和端子的性质而从密封剂138的表面162延伸出。
与具有基板的SiP模块相比，去除基板120并使电组件130a-130h的凸块114和端子134延伸出超过密封剂138的表面162减小了SiP模块168a和168b的厚度。SiP模块168a和168b的厚度变成密封剂138和暴露的凸块114和端子134的厚度T4。在一个实施例中，SiP模块168a和168b的厚度可以是T4，大约325μm。通过取消基板120，SiP模块168a和168b具有减小的厚度。SiP模块168a和168b没有基板120。
在另一实施例中，从图2d继续，通过研磨机170去除密封剂138的一部分以减小密封剂的厚度，如图7a中所示。
在图7b中，使用锯刀或激光切割工具176在密封剂138的表面174切割通道172。通道172完全延伸穿过密封剂138，并且部分但不完全穿过基板120。通道172至少延伸超过凸块阻止层128。基板120的剩余厚度是T5，大约200μm。
在图7c中，通过研磨机180去除包括凸块阻止层128的基板120，以暴露电组件130a-130h的凸块114和端子134。研磨机180可以相对于表面182以一定角度倾斜来操作。替选地，通过化学蚀刻、CMP、机械剥离、机械研磨、热烘、UV光、激光扫描或湿法剥离来去除基板120，以暴露电组件130a-130h的凸块114和端子134。研磨操作完成了将基板120单片化成SiP模块188a和188b。
通过蚀刻工艺去除研磨后的基板120的剩余部分，使得凸块114和端子134从表面174延伸出。凸块114和端子134的至少一部分从密封剂138延伸出超过表面174。图7d示出研磨后的SIP模块188a，其中，电组件130a-130d的凸块114和端子134延伸出超过密封剂138的表面174。电组件130a-130d的凸块114和端子134由于凸块和端子已经至少部分地嵌入在基板120内并且然后去除基板以暴露凸块和端子的性质而从密封剂138的表面174延伸出。图5示出了具有从密封剂138延伸的凸块114的示例性电路组件130a的进一步细节。凸块114由于凸块已经至少部分地嵌入在基板120内(如图4所示)并且然后去除基板以暴露凸块的性质而从密封剂138的表面174延伸出。包含电组件130e-130h的SiP模块188b的情况也是如此*电组件130e-130h的凸块114和端子134由于凸块和端子已经至少部分地嵌入在基板120内并且然后去除基板以暴露凸块和端子的性质而从密封剂138的表面174延伸出。
与具有基板的SiP模块相比，去除基板120并使电组件130a-130h的凸块114和端子134从密封剂138延伸出减小了SiP模块188a和188b的厚度。SiP模块188a和188b的厚度变成密封剂138和暴露的凸块114和端子134的厚度T6。在一个实施例中，SiP模块188a和188b的厚度可以是T6，大约340μm。通过取消基板120，SiP模块188a和188b具有减小的厚度。SiP模块188a和188b没有基板120。
在图7e中，可以在暴露的凸块114和端子134上沉积焊膏190。
在另一实施例中，从图2e继续，通过研磨机144将包括凸块阻止层128的牺牲基板120去除，下至密封剂138的表面146，如图8a中所示。研磨机144可以相对于表面146以一定角度倾斜来操作。替选地，通过化学蚀刻、CMP、机械剥离、机械研磨、热烘、UV光、激光扫描或湿法剥离来去除基板120，以暴露电组件130a-130h的凸块114和端子134。研磨操作完成了将基板120单片化成SiP模块148a和148b，如图8b中所示。
图8c示出了研磨后的SIP模块148a，其中，电组件130a-130d的凸块114和端子134与密封剂138的表面146共面并从该表面146暴露。
可以通过研磨机150去除密封剂138的一部分，以进一步减小SiP模块148a的厚度，类似于图2i。在图8d中，可以使用印刷工艺将焊膏200沉积在暴露的凸块114和端子134上。焊膏200回流以重新形成从密封剂138延伸出的凸块114和端子134，如图8e中所示。
在另一实施例中，包括顶部主表面122和底部主表面124的牺牲基板或载板120的截面图，如图9a中所示。凸块阻止层128嵌入在基板120内在表面122下方，参见图3a-3c。通过蚀刻或LDA工艺去除基板120的一部分，以形成延伸下至凸块阻止层128的开口210。开口210的位置对应于凸块114和端子134。
在图9b中，多个电组件130a-130h被安装到基板120，其中，凸块114和端子与开口210对准并且在表面122下方向下延伸以接触凸块阻止层128，以形成SiP模块220，类似于图2b-2c。
图9c示出设置在表面122上的电组件130a-130h，其中，电组件的凸块114、端子134或其它电互连至少部分地在表面122下方延伸以接触凸块阻止层128。SiP模块220的处理类似于图2e-2k来继续。
图10示出了具有芯片载板基板或PCB 302的电子器件300，其中，在PCB 302的表面上安装多个半导体封装，所述多个半导体封装包括SIP模块148a、148b、168a、168b、188a、188b。电子器件300可以具有一种类型的半导体封装，或者多种类型的半导体封装，这取决于应用。
电子器件300可以是使用半导体封装来执行一个或多个电功能的独立系统。替选地，电子器件300可以是较大系统的子组件。例如，电子器件300可以是平板电脑、蜂窝电话、数码相机、通信系统或其它电子器件的一部分。替选地，电子器件300可以是图形卡、网络接口卡或其它可以插入到计算机中的信号处理卡。半导体封装可以包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立器件或其它半导体管芯或电组件。小型化和重量减轻对于产品被市场接受是必要的。可以减小半导体器件之间的距离以实现更高的密度。
在图10中，PCB 302提供一种用于安装在PCB上的半导体封装的结构支撑和电互连的通用基板。使用蒸发、电解电镀、化学电镀、丝网印刷或其它合适的金属沉积工艺在PCB302的表面上或在PCB 302的层内形成导电信号迹线304。信号迹线304在每个半导体封装、安装的组件和其它外部系统组件之间提供电通信。迹线304也向每个半导体封装提供电源和接地连接。
在一些实施例中，半导体器件具有两个封装级。第一级封装是一种用于将半导体管芯机械和电附着到中间基板的技术。第二级封装涉及将中间基板机械和电附着到PCB。在其它实施例中，半导体器件可以仅具有第一级封装，其中，管芯被机械和电直接安装到PCB。为了说明的目的，在PCB 302上示出几种类型的第一级封装，包括接合线封装306和倒装芯片308。另外，示出了安装在PCB 302上的几种类型的第二级封装，包括球栅阵列(BGA)310、凸块芯片载板(BCC)312、焊盘栅阵列(LGA)316、多芯片模块(MCM)或SIP模块318、四方扁平无引线封装(QFN)320、四方扁平封装322、嵌入式晶片级球栅阵列(eWLB)324和晶片级芯片尺度封装(WLCSP)326。在一个实施例中，eWLB 324是扇出晶片级封装(Fo-WLP)，并且WLCSP326是扇入晶片级封装(Fi-WLP)。根据系统要求，配置有第一和第二级封装样式的任何组合的半导体封装以及其它电子组件的任何组合可以连接到PCB 302。在一些实施例中，电子器件300包括单个附着的半导体封装，而其它实施例要求多个互连的封装。通过在单个基板上组合一个或多个半导体封装，制造商可以将预制组件并入到电子器件和系统中。由于半导体封装包括复杂的功能，所以可以使用不太昂贵的组件和流水线制造工艺来制造电子器件。所得到的器件不太可能失效，并且制造不太昂贵，从而导致消费者的更低成本。
尽管已经详细地示出本发明的一个或多个实施例，但是本领域技术人员将会理解：在不偏离所附权利要求中阐述的本发明的范围的情况下，可以进行对那些实施例的修改和适配。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供基板；
将电组件设置在所述基板上，其中，所述电组件的端子至少部分地嵌入在所述基板中；
在所述电组件和基板上沉积密封剂；以及
去除所述基板以使所述电组件的所述端子暴露所述密封剂。
2.根据权利要求1所述的方法，还包括在所述基板内形成阻止层。
3.根据权利要求2所述的方法，其中，形成所述阻止层包括：
在所述基板上形成所述阻止层；以及
在所述阻止层和所述基板上形成可穿透层。
4.根据权利要求1所述的方法，还包括形成穿过所述密封剂并部分进入所述基板的通道。
5.一种制造半导体器件的方法，包括：
提供基板；
在所述基板上设置电组件；
在所述电组件和基板上沉积密封剂；以及
去除所述基板以使所述电组件的端子从所述密封剂延伸出。
6.根据权利要求5所述的方法，还包括在所述基板内形成阻止层。
7.根据权利要求6所述的方法，其中，形成所述阻止层包括：
在所述基板上形成所述阻止层；以及
在所述阻止层和所述基板上形成可穿透层。
8.根据权利要求5所述的方法，还包括形成穿过所述密封剂并部分进入所述基板的通道。
9.根据权利要求5所述的方法，其中，所述半导体器件的厚度由所述密封剂和从所述密封剂延伸出的端子的厚度确定。
10.根据权利要求5所述的方法，还包括去除所述密封剂的一部分。
11.一种半导体器件，包括：
电组件；以及
沉积在所述电组件上的密封剂，其中，所述电组件的端子从所述密封剂延伸出，并且所述半导体器件的厚度由所述密封剂和从所述密封剂暴露的所述端子的厚度确定。
12.根据权利要求11所述的半导体器件，其中，所述密封剂沉积在多个电组件上。
13.根据权利要求11所述的半导体器件，还包括穿过所述密封剂形成的通道。
14.根据权利要求11所述的半导体器件，还包括沉积在所述端子上的导电膏。
15.根据权利要求11所述的半导体器件，其中，所述电组件包括半导体管芯或分立半导体器件。
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