TW202345243A - 半導體裝置及形成沒有基板的系統級封裝模組的方法 - Google Patents

半導體裝置及形成沒有基板的系統級封裝模組的方法 Download PDF

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TW202345243A
TW202345243A TW112106124A TW112106124A TW202345243A TW 202345243 A TW202345243 A TW 202345243A TW 112106124 A TW112106124 A TW 112106124A TW 112106124 A TW112106124 A TW 112106124A TW 202345243 A TW202345243 A TW 202345243A
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Taiwan
Prior art keywords
substrate
encapsulant
bumps
terminals
semiconductor device
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TW112106124A
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English (en)
Inventor
權智恩
文智植
李基喆
林保利
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新加坡商星科金朋私人有限公司
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Publication of TW202345243A publication Critical patent/TW202345243A/zh

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Abstract

本發明提供一種半導體裝置，其具有犧牲基板及設置於該犧牲基板上方之電性組件。凸塊停止層形成於該犧牲基板內。該電性組件之凸塊或端子的至少一部分嵌入於該犧牲基板中以接觸該凸塊停止層。密封劑沉積於該電性組件及該犧牲基板上方。通道形成穿透該密封劑且部分進入該犧牲基板。該犧牲基板經移除以使該電性組件之凸塊或端子從該密封劑延伸出去。該半導體裝置之厚度藉由該密封劑及從該密封劑延伸出去之凸塊的厚度來判定。該密封劑之一部分能經移除以減小該半導體裝置之該厚度。導電膏能沉積於從該密封劑延伸出去之該凸塊或端子上方。

Description

半導體裝置及形成沒有基板的系統級封裝模組的方法
本發明大體上關於半導體裝置，且更特定言之，關於一種半導體及形成沒有基板之系統級封裝模組的方法。
半導體裝置通常見於現代電子產品中。半導體裝置進行廣泛範圍之功能，諸如訊號處理、高速計算、傳輸及接收電磁訊號、控制電子裝置、光電效應及產生電視顯示器之視覺影像。半導體裝置見於通信、功率轉換、網路、電腦、娛樂及消費產品領域。半導體裝置亦見於軍事應用、航空、汽車、工業控制器及辦公設備。
能將多個半導體晶粒、離散半導體裝置及積體被動裝置（integrated passive device；IPD）整合至系統級封裝（system in package；SiP）模組中以實現較小空間中之較大密度及經擴展之電功能性。在SIP模組內，半導體晶粒及IPD安裝至基板用以結構支撐及電互連。將密封劑沉積於半導體晶粒、離散半導體裝置、IPD及基板上方。SiP模組之總高度藉由密封劑及基板之組合高度來判定。減小SiP模組之高度將為較佳的。
根據本發明之一個態樣，其提供一種製造半導體裝置之方法，其包括提供基板；將電性組件設置於該基板上方，其中該電性組件之端子至少部分嵌入於該基板中；將密封劑沉積於該電性組件及該基板上方；及移除該基板以使該電性組件之該端子暴露於該密封劑。
根據本發明之另一個態樣，其提供一種製造半導體裝置之方法，其包括提供基板；將電性組件設置於該基板上方；將密封劑沉積於該電性組件及該基板上方；及移除該基板以使該電性組件之端子從該密封劑延伸出去。
根據本發明之另一個態樣，其提供一種半導體裝置，其包括電性組件；及密封劑，其沉積於該電性組件上方，其中該電性組件之端子從該密封劑延伸出去，且該半導體裝置之厚度係藉由該密封劑及從該密封劑暴露之該端子的厚度來判定。
在以下描述中參考圖式於一或多個實施例中描述本發明，在圖式中，相似編號表示相同或類似元件。儘管本發明係依據用於達成本發明目標之最佳模式來描述，但所屬技術領域中具通常知識者將瞭解的是，其意欲涵蓋如能包含於如由所附申請專利範圍及如由以下揭示內容及圖式支持之其等效物所界定的本發明之精神及範疇內的替代方案、修改及等效物。如本文所使用之術語「半導體晶粒」係指詞之單數形式及複數形式兩者，且因此，能指單個半導體裝置及多個半導體裝置兩者。
通常使用兩個複雜製造製程來製造半導體裝置：前段製造及後段製造。前段製造涉及在半導體晶圓之表面上形成複數個晶粒。晶圓上之各晶粒含有主動及被動電性組件，而電性組件電連接以形成功能性電路。諸如電晶體及二極體之主動電性組件具有控制電流之流動的能力。諸如電容器、電感器及電阻器之被動電性組件在進行電路功能所必需之電壓與電流之間建立關係。
後段製造指將成品晶圓切割或單體化成個別半導體晶粒，且封裝半導體晶粒用以結構支撐、電互連及環境隔離。為了使半導體晶粒單體化，沿著稱作切割道（saw street）或切割線（scribe）的晶圓之非功能性區域刻劃及切（折）斷晶圓。晶圓單體化是使用雷射切割工具或鋸片。在單體化之後，將個別半導體晶粒安裝至封裝基板，而封裝基板包含接針或接觸墊用以與其他系統組件互連。接著將形成於半導體晶粒之上方的接觸墊連接至封裝內之接觸墊。能以導電層、凸塊、短柱凸塊（stud bump）、導電膏或焊線製作電連接。密封劑或其他模製材料沉積於封裝上方以提供實體支撐及電隔離。接著將成品封裝插入至電性系統中，且使半導體裝置之功能性對於其他系統組件而言為可用的。
圖1a展示具有基底基板材料102之半導體晶圓100，該基底基板材料為諸如矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽或用於結構支撐之其他塊材。複數個半導體晶粒104或組件形成於晶圓100上，所述半導體晶粒或構件組件藉由非作用晶粒間晶圓區域或切割道106分離。切割道106提供將半導體晶圓100單體化成個別半導體晶粒104的切割區域。在一個實施例中，半導體晶圓100具有100毫米至450毫米（mm）之寬度或直徑。
圖1b展示半導體晶圓100之一部分的橫截面視圖。各半導體晶粒104具有後或非作用表面108及作用表面110，且該作用表面含有實施為形成於晶粒內且根據晶粒之電性設計及功能而電互連的主動裝置、被動裝置、導電層及介電層之類比或數位電路。舉例而言，電路能包含形成於作用表面110內之一或多個電晶體、二極體及其他電路元件以實施類比電路或數位電路，諸如數位訊號處理器（digital signal processor；DSP）、特殊應用積體電路（application specific integrated circuit；ASIC）、記憶體或其他訊號處理電路。半導體晶粒104亦可含有諸如電感器、電容器及電阻器之整合式被動裝置（Integrated Passive Device；IPD）以進行射頻（Radio frequency；RF）訊號處理。
導電層112使用物理氣相沉積（physical vapor deposition；PVD）、化學氣相沉積（chemical vapor deposition；CVD）、電解電鍍、無電鍍製程或其他適合之金屬沉積製程而形成於作用表面110上方。導電層112能為鋁（aluminum；Al）、銅（copper；Cu）、錫（tin；Sn）、鎳（nickel；Ni）、金（gold；Au）、銀（silver；Ag）或其他合適導電材料之一或多個層。導電層112操作為電連接至作用表面110上之電路的接觸墊。
使用蒸鍍、電解電鍍、無電鍍、落球或網版列印製程將導電凸塊材料沉積於導電層112上方。凸塊材料能為Al、Sn、Ni、Au、Ag、鉛（Pb）、鉍（Bi）、Cu、焊料或此等中之兩者或多於兩者的組合，具有視情況選用之焊劑溶液。舉例而言，凸塊材料能為共晶Sn/Pb、高鉛焊料或無鉛焊料。凸塊材料使用合適附接或接合製程接合至導電層112。在一個實施例中，藉由將材料加熱超過其熔點而回焊凸塊材料以形成球或凸塊114。在一個實施例中，凸塊114形成於具有潤濕層、障壁層及黏著層之凸塊下層金屬（under bump metallization；UBM）上方。凸塊114亦能壓縮接合或熱壓縮接合至導電層112。凸塊114表示能形成於導電層112上方之一種類型之互連結構。互連結構亦能使用接合線、導電膏、短柱凸塊、微型凸塊或其他電互連件。
在圖1c中，使用鋸片或雷射切割工具118透過切割道106將半導體晶圓100單體化成個別半導體晶粒104。能在單體化後檢測及電測試個別半導體晶粒104用以識別良裸晶粒或單元（known good die or unit；KGD/KGU）。
圖2a至圖2k說明形成無基板之SiP模組的過程。圖2a展示包含頂部主表面122及底部主表面124之犧牲基板120或載體之橫截面視圖。基板120含有犧牲材料，其提供結構支撐且能易於在稍後步驟移除。犧牲基底材料能為塑膠、聚合物、氧化鈹、玻璃或其他合適之低成本剛性材料。在一個實施例中，基板120由聚四氟乙烯預浸漬（預浸體）、FR-4、FR-1、CEM-1或CEM-3之一或多個層壓層與酚醛棉紙（phenolic cotton paper）、環氧樹脂、樹脂、玻璃布（woven glass）、毛玻璃（matte glass）、聚酯及其他強化纖維或織物的組合製成。凸塊停止層128嵌入於基板120內，位於表面122下方。
圖3a至圖3c說明形成凸塊停止層128之另外細節。圖3a展示基板120之一部分。在圖式中，向具有類似功能之元件指派相同參考編號。在圖3b中，凸塊停止層128形成於基板120上方。凸塊停止層128能為能夠停止導電凸塊114穿透的金屬層或其他剛性材料，如下文所描述。在圖3c中，使用PVD、CVD、列印、旋轉塗佈、噴塗、狹縫塗佈、滾塗、層壓或燒結而在基板120及凸塊停止層128上方形成可穿透膜層132。在一個實施例中，可穿透膜層132為聚合物、環氧樹脂、丙烯醯基類B-階段材料（acryl-based B-stage material）或具有可穿透屬性之其他類似材料。可穿透膜層132具有125微米（μm）之厚度。替代地，可穿透膜層132能為二氧化矽（silicon dioxide；SiO2）、氮化矽（silicon nitride；Si3N4）、氮氧化矽（silicon oxynitride；SiON）、五氧化二鉭（tantalum pentoxide；Ta2O5）、氧化鋁（aluminum oxide；Al2O3）、四氮化二矽（Si2n4）、、聚醯亞胺、苯環丁烯（benzocyclobutene；BCB）、聚苯並噁唑（polybenzoxazoles；PBO）或具有類似絕緣及結構屬性之其他材料的一或多層。可穿透膜層132操作為用以附接電性組件的臨時可穿透基板。可穿透膜層132視為基板120之部分，且可穿透膜層之頂部表面變成基板120之主表面122。
在圖2b中，將複數個電性組件130a至電性組件130h安裝至基板120之表面122。電性組件130a至電性組件130h使用取放操作而各自定位於基板120上方。舉例而言，電性組件130a及電性組件130e能為來自圖1c以作用表面110及凸塊114定向朝向基板120之表面122的半導體晶粒104。電性組件130b及電性組件130f能為離散電子裝置，諸如電晶體、二極體、電阻器、電容器及電感器。電性組件130b及電性組件130f具有用於電互連之端子134。使電性組件130c、電性組件130d、電性組件130g及電性組件130h能以類似於半導體晶粒104，但可能具有與朝向表面122定向之凸塊114不同的形式及功能而製造。替代地，電性組件130a至電性組件130h能包含其他半導體晶粒、半導體封裝及表面安裝裝置。
特定言之，將電性組件130a至電性組件130h設置於表面122上且接著藉由力F按壓至基板120中，使得凸塊114及端子134延伸至基板之表面下方以接觸凸塊停止層128。作為範例，圖4展示具有延伸至基板120中之凸塊114之電性組件130a的另外細節。在此情況下，凸塊114被按壓至基板120中且延伸至表面122下方，凸塊114至少部分延伸至可穿透膜層132中，且接觸凸塊停止層128。
圖2c展示設置於表面122上方之電性組件130a至電性組件130h，其中凸塊114、端子134或電性組件之其他電互連件至少部分延伸至基板120中以接觸凸塊停止層128。特定言之，圖4展示具有嵌入至可穿透膜層132中以接觸凸塊停止層128之凸塊114的例示性電性組件130a之另外細節。電性組件130a之凸塊114至少部分延伸至基板120中（如圖3c中所定義）以接觸凸塊停止層128。
在圖2d中，使用膏列印、擠壓模製（compressive molding）、轉印模製（transfer molding）、液體密封劑模製、真空層壓、旋轉塗佈或其他合適之塗覆器將密封劑138或模製化合物沉積於電性組件130a至電性組件130h及基板120上方及周圍。密封劑138能為聚合物複合材料，諸如具有填充劑之環氧樹脂、具有填充劑之環氧丙烯酸酯或具有適當填充劑之聚合物。密封劑138為不導電的，提供結構支撐，且環境上保護半導體裝置免受外部元素及污染物影響。
在圖2e中，使用鋸片或雷射切割工具142將通道140切割至密封劑138之表面141中。通道140完全延伸穿透密封劑138且部分但不完全穿透基板120。通道140至少延伸穿透凸塊停止層128。基板120之剩餘厚度為T1，約100 μm。
在圖2f中，藉由研磨機144將包含凸塊停止層128之犧牲基板120向下移除至電性組件130a至電性組件130h之凸塊114及端子134。研研磨機144可相對於表面146以一角度傾斜操作。替代地，藉由化學蝕刻、化學機械研磨（chemical mechanical polishing；CMP）、機械剝離、機械研磨、熱烘烤、紫外線（ultra-violet；UV）光、雷射掃描或濕式剝離來移除基板120以暴露電性組件130a至電性組件130h之凸塊114及端子134。研磨操作完成將基板120單體化成SiP模組148a及SiP模組148b。
在圖2g中，藉由蝕刻製程來移除基板120研磨後之剩餘部分，使得凸塊114及端子134從密封劑138之表面146延伸出去。凸塊114及端子134之至少一部分從密封劑138延伸出去而超出表面146。
圖2h展示研磨後之SIP模組148a，其中電性組件130a至電性組件130d之凸塊114及端子134從密封劑138延伸。在電性組件130a至電性組件130d之凸塊114及端子134已至少部分地嵌入於基板120內且接著移除基板以暴露凸塊及端子之基礎上，凸塊114及端子134從密封劑138之表面146延伸出去。圖5展示具有從密封劑138延伸之凸塊114之例示性電路組件130a的另外細節。在凸塊114已至少部分地嵌入於基板120內（如圖4中所繪示）且接著移除基板以暴露凸塊之基礎上，凸塊114從密封劑138之表面146延伸出去。對於含有電性組件130e至電性組件130h之SiP模組148b亦如此。在電性組件130e至電性組件130h之凸塊114及端子134已至少部分地嵌入於基板120內且接著移除基板以暴露凸塊及端子之基礎上，凸塊114及端子134從密封劑138之表面146延伸出去。
與具有基板之SiP模組相比，移除基板120且使電性組件130a至電性組件130h之凸塊114及端子134從密封劑138延伸，這減小了SiP模組148a及SiP模組148b之厚度。SiP模組148a及SiP模組148b之厚度變為密封劑138與經暴露凸塊114及端子134之厚度T2。在一個實施例中，SiP模組148a及SiP模組148b之厚度可為T2，約640 μm。SiP模組148a及SiP模組148b藉由消除基板120而具有減小之厚度。SiP模組148a及SiP模組148b沒有基板120。
在圖2i中，視情況藉由研磨機150移除密封劑138之一部分以進一步減小SiP模組148a之厚度。在圖2j之情況下，SiP模組148a及SiP模組148b之厚度可為T3，約340 μm。
在圖2k中，能將焊膏156沉積於經暴露凸塊114及端子134上方。
在另一實施例中，從圖2d繼續，藉由研磨機160將包含凸塊停止層128之基板120向下移除至電性組件130a至電性組件130h之凸塊114及端子134，如圖6a中所展示。研磨機160可相對於表面162以一角度傾斜操作。替代地，藉由化學蝕刻、CMP、機械剝離、機械研磨、熱烘烤、UV光、雷射掃描或濕式剝離來移除基板120以暴露電性組件130a至電性組件130h之凸塊114及端子134。
藉由蝕刻製程來移除研磨後之基板120的剩餘部分，使得凸塊114及端子134從表面162延伸出去。凸塊114及端子134之至少一部分從密封劑138延伸出去而超出表面162。圖6b展示電性組件130a至電性組件130h之從研磨後的密封劑138延伸之凸塊114及端子134。能將焊膏164沉積於經暴露凸塊114及端子134上方。
在圖6c中，使用鋸片或雷射切割工具166使密封劑138單體化。SiP模組168a包含具有延伸超出密封劑138之表面162的凸塊114及端子134之電性組件130a至電性組件130d。SiP模組168b包含具有延伸超出密封劑138之表面162的凸塊114及端子134之電性組件130e至電性組件130h。
圖6d展示研磨後之SIP模組168a，其中電性組件130a至電性組件130d之凸塊114及端子134延伸超出密封劑138之表面162。在電性組件130a至電性組件130d之凸塊114及端子134已至少部分地嵌入於基板120內且接著移除基板以暴露凸塊114及端子134之基礎上，凸塊114及端子134從密封劑138之表面162延伸出去。圖5展示具有從密封劑138延伸之凸塊114之例示性電路組件130a的另外細節。在凸塊114已至少部分地嵌入於基板120內（如圖4中所繪示）且接著移除基板以暴露凸塊114之基礎上，凸塊114從密封劑138之表面162延伸出去。對於含有電性組件130e至電性組件130h之SiP模組168b亦如此。在電性組件130e至電性組件130h之凸塊114及端子134已至少部分地嵌入於基板120內且接著移除基板以暴露凸塊114及端子134之基礎上，凸塊114及端子134從密封劑138之表面162延伸出去。
與具有基板之SiP模組相比，移除基板120且使電性組件130a至電性組件130h之凸塊114及端子134延伸超出密封劑138之表面162減小了SiP模組168a及SiP模組168b之厚度。SiP模組168a及SiP模組168b之厚度變為密封劑138與經暴露凸塊114及端子134之厚度T4。在一個實施例中，SiP模組168a及SiP模組168b之厚度可為T4，約325 μm。SiP模組168a及SiP模組168b藉由消除基板120而具有減小之厚度。SiP模組168a及SiP模組168b沒有基板120。
在另一實施例中，從圖2d繼續，藉由研磨機170移除密封劑138之一部分以減小密封劑之厚度，如圖7a中所展示。
在圖7b中，使用鋸片或雷射切割工具176將通道172切割至密封劑138之表面174中。通道172完全延伸穿透密封劑138且部分但不完全穿透基板120。通道172至少延伸穿透凸塊停止層128。基板120之剩餘厚度為T5，約200 μm。
在圖7c中，藉由研磨機180來移除包含凸塊停止層128之基板120以暴露電性組件130a至電性組件130h之凸塊114及端子134。研磨機180可相對於表面182以一角度傾斜操作。替代地，藉由化學蝕刻、CMP、機械剝離、機械研磨、熱烘烤、UV光、雷射掃描或濕式剝離來移除基板120以暴露電性組件130a至電性組件130h之凸塊114及端子134。研磨操作完成將基板120單體化成SiP模組188a及SiP模組188b。
藉由蝕刻製程移除研磨後之基板120的剩餘部分，使得凸塊114及端子134從表面174延伸出去。凸塊114及端子134之至少一部分從密封劑138延伸出去而超出表面174。圖7d展示研磨後之SIP模組188a，其中電性組件130a至電性組件130d之凸塊114及端子134延伸超出密封劑138之表面174。在電性組件130a至電性組件130d之凸塊114及端子134已至少部分地嵌入於基板120內且接著移除基板120以暴露凸塊114及端子134之基礎上，凸塊114及端子134從密封劑138之表面174延伸出去。圖5展示具有從密封劑138延伸之凸塊114之例示性電路組件130a的另外細節。在凸塊114已至少部分地嵌入於基板120內（如圖4中所繪示）且接著移除基板以暴露凸塊114之基礎上，凸塊114從密封劑138之表面174延伸出去。對於含有電性組件130e至電性組件130h之SiP模組188b亦如此。在電性組件130e至電性組件130h之凸塊114及端子134已至少部分地嵌入於基板120內且接著移除基板以暴露凸塊114及端子134之基礎上，凸塊114及端子134從密封劑138之表面174延伸出去。
與具有基板之SiP模組相比，移除基板120且使電性組件130a至電性組件130h之凸塊114及端子134從密封劑138延伸出去減小了SiP模組188a及SiP模組188b之厚度。SiP模組188a及SiP模組188b之厚度變為密封劑138與經暴露凸塊114及端子134之厚度T6。在一個實施例中，SiP模組188a及SiP模組188b之厚度可為T6，約340 μm。SiP模組188a及SiP模組188b藉由消除基板120而具有減小之厚度。SiP模組188a及SiP模組188b沒有基板120。
在圖7e中，能將焊膏190沉積於經暴露凸塊114及端子134上方。
在另一實施例中，從圖2e繼續，藉由研研磨機144將包含凸塊停止層128之犧牲基板120向下移除至密封劑138之表面146，如圖8a中所展示。研研磨機144可相對於表面146以一角度傾斜操作。替代地，藉由化學蝕刻、CMP、機械剝離、機械研磨、熱烘烤、UV光、雷射掃描或濕式剝離來移除基板120以暴露電性組件130a至電性組件130h之凸塊114及端子134。研磨操作完成將基板120單體化成SiP模組148a及SiP模組148b，如圖8b中所展示。
圖8c展示研磨後之SIP模組148a，其中電性組件130a至電性組件130d之凸塊114及端子134與密封劑138之表面146共平面且從該表面146暴露。
類似於圖2i，能藉由研磨機150來移除密封劑138之一部分以進一步減小SiP模組148a之厚度。在圖8d中，能使用列印製程將焊膏200沉積於經暴露凸塊114及端子134上方。將焊膏200回焊以重新形成從密封劑138延伸出去之凸塊114及端子134，如圖8e中所展示。
在另一實施例中，包含頂部主表面122及底部主表面124之犧牲基板120或載體之橫截面視圖，如圖9a中所展示。凸塊停止層128嵌入於基板120內而位於表面122下方，參見圖3a至圖3c。藉由蝕刻或雷射直接燒蝕（Laser Direct Ablation；LDA）製程來移除基板120之一部分以形成向下延伸至凸塊停止層128之開口210。開口210之位置對應於凸塊114及端子134。
在圖9b中，類似於圖2b至圖2c，將複數個電性組件130a至電性組件130h安裝至基板120，其中凸塊114及端子與開口210對準且在表面122下方向下延伸以接觸凸塊停止層128，從而形成SiP模組220。
圖9c展示設置於表面122上方之電性組件130a至電性組件130h，其中凸塊114、端子134或電性組件之其他電互連件至少部分地在表面122下方延伸以接觸凸塊停止層128。SiP模組220之處理類似於圖2e至圖2k而繼續。
圖10說明具有晶片載體基板或印刷電路板302之電子裝置300，其中複數個半導體封裝安裝於印刷電路板302之表面上，該複數個半導體封裝包含SIP模組148a、SIP模組148b、SIP模組168a、SIP模組168b、SIP模組188a及SIP模組188b。取決於應用，電子裝置300能具有一種類型之半導體封裝或多種類型之半導體封裝。
電子裝置300能為使用半導體封裝進行一或多個電功能之獨立系統。替代地，電子裝置300能為較大系統之子組件。舉例而言，電子裝置300能為平板電腦、蜂巢式電話、數位攝像機、通信系統或其他電子裝置之部分。替代地，電子裝置300能為顯示卡、網路介面卡或可插入至電腦中之另一訊號處理卡。半導體封裝能包含微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散裝置或其他半導體晶粒或電性組件。小型化及減重為市場所接受之產品所必需的。可減小半導體裝置之間的距離以達成較高密度。
在圖10中，印刷電路板302提供通用基板以用於安裝於PCB上之半導體封裝的結構支撐及電互連。使用蒸鍍、電解電鍍、無電鍍、網版列印或其他合適之金屬沉積製程在印刷電路板302之表面上方或層內形成導電訊號跡線304。訊號跡線304提供用於半導體封裝、經安裝組件及其他外部系統組件中之各者之間的電連通。跡線304亦向半導體封裝中之各者提供電力及接地連接。
在一些實施例中，半導體裝置具有兩個封裝層級。第一層級封裝為用於將半導體晶粒機械及電附接至中間基板之技術。第二層級封裝涉及將中間基板機械及電附接至PCB。在其他實施例中，半導體裝置可僅具有第一層級封裝，其中晶粒以機械方式及以電氣方式直接安裝至PCB。出於說明之目的，包含接合線封裝306及覆晶308之若干類型的第一層級封裝展示於印刷電路板302上。另外，包含球柵陣列（ball grid array；BGA）310、凸塊晶片載體（bump chip carrier；BCC）312、平台格柵陣列（land grid array；LGA）316、多晶片模組（multi-chip module；MCM）或SIP模組318、方形扁平無導線封裝（quad flat non-leaded package；QFN）320、方形扁平封裝322、嵌入式晶圓級球柵陣列（embedded wafer level ball grid array；eWLB）324及晶圓級晶片尺度封裝（wafer level chip scale package；WLCSP）326之若干類型的第二層級封裝展示為安裝於印刷電路板302上。在一個實施例中，嵌入式晶圓級球柵陣列324為扇出晶圓級封裝（fan-out wafer level package；Fo-WLP）且晶圓級晶片尺度封裝326為扇入晶圓級封裝（fan-in wafer level package；Fi-WLP）。視系統要求而定，組態具有第一及第二層級封裝式樣以及其他電性組件之任何組合的半導體封裝之任何組合能連接至印刷電路板302。在一些實施例中，電子裝置300包含單一附接之半導體封裝，而其他實施例需要多個互連之封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商能將預製組件併入至電子裝置及系統中。由於半導體封裝包含複雜功能性，因此能使用較不昂貴組件及流暢的製造製程來製造電子裝置。所得裝置不大能能發生故障且製造起來不太昂貴，由此降低了消費者成本。
儘管已詳細說明本發明之一或多個實施例，但所屬技術領域中具通常知識者將瞭解，能在不脫離如以下申請專利範圍中所闡述之本發明之範圍的情況下對彼等實施例作出修改及調整。
100:晶圓 102:基底基板材料 104:半導體晶粒 106:切割道 108:非作用表面 110:作用表面 112:導電層 114:凸塊 118:雷射切割工具 120:基板 122:表面 124:底部主表面 128:凸塊停止層 130a:電性組件 130b:電性組件 130c:電性組件 130d:電性組件 130e:電性組件 130f:電性組件 130g:電性組件 130h:電性組件 132:可穿透膜層 134:端子 138:密封劑 140:通道 141:表面 142:雷射切割工具 144:研磨機 146:表面 148a:SiP模組 148b:SiP模組 150:研磨機 156:焊膏 160:研磨機 162:表面 164:焊膏 166:鋸片或雷射切割工具 168a:SiP模組 168b:SiP模組 170:研磨機 172:通道 174:表面 176:鋸片或雷射切割工具 180:研磨機 182:表面 186:表面 188a:SiP模組 188b:SiP模組 190:焊膏 200:焊膏 210:開口 220:SiP模組 300:電子裝置 302:印刷電路板 304:跡線 306:接合線封裝 308:覆晶 310:球柵陣列 312:凸塊晶片載體 316:平台格柵陣列 318:多晶片模組或SIP模組 320:方形扁平無導線封裝 322:方形扁平封裝 324:嵌入式晶圓級球柵陣列 326:晶圓級晶片尺度封裝 F:力 T1:厚度 T2:厚度 T3:厚度 T4:厚度 T5:厚度 T6:厚度
[圖1a]至[圖1c]說明具有藉由切割道分離之複數個半導體晶粒的半導體晶圓； [圖2a]至[圖2k]說明形成沒有基板之SiP模組的過程； [圖3a]至[圖3c]說明形成具有嵌入式凸塊停止層之犧牲基板的過程； [圖4]說明具有嵌入於犧牲基板中向下到達凸塊蝕刻停止層之凸塊的電性組件； [圖5]說明從密封劑延伸出去之電性組件的凸塊； [圖6a]至[圖6d]說明形成沒有基板之SiP模組的另一過程； [圖7a]至[圖7e]說明形成沒有基板之SiP模組的另一過程； [圖8a]至[圖8e]說明形成沒有基板之SiP模組的另一過程； [圖9a]至[圖9c]說明形成沒有基板之SiP模組的另一過程；且 [圖10]說明具有安裝至印刷電路板（printed circuit board；PCB）之表面的不同類型之封裝的印刷電路板。
104:半導體晶粒
108:非作用表面
110:作用表面
112:導電層
114:凸塊
120:基板
122:表面
124:底部主表面
128:凸塊停止層
130a:電性組件
130b:電性組件
130c:電性組件
130d:電性組件
130e:電性組件
130f:電性組件
130g:電性組件
130h:電性組件
134:端子
138:密封劑
160:研磨機
162:表面

Claims (15)

  1. 一種製造半導體裝置之方法，其包括： 提供基板； 將電性組件設置於該基板上方，其中該電性組件之端子至少部分嵌入於該基板中； 將密封劑沉積於該電性組件及該基板上方；及 移除該基板以使該電性組件之該端子暴露於該密封劑。
  2. 如請求項1之方法，其進一步包含在該基板內形成停止層。
  3. 如請求項2之方法，其中形成該停止層包含： 在該基板上方形成該停止層；及 在該停止層及該基板上方形成能穿透層。
  4. 如請求項1之方法，其進一步包含形成穿過該密封劑且部分進入該基板之通道。
  5. 一種製造半導體裝置之方法，其包括： 提供基板； 將電性組件設置於該基板上方； 將密封劑沉積於該電性組件及該基板上方；及 移除該基板以使該電性組件之端子從該密封劑延伸出去。
  6. 如請求項5之方法，其進一步包含在該基板內形成停止層。
  7. 如請求項6之方法，其中形成該停止層包含： 在該基板上方形成該停止層；及 在該停止層及該基板上方形成能穿透層。
  8. 如請求項5之方法，其進一步包含形成穿過該密封劑且部分進入該基板之通道。
  9. 如請求項5之方法，其中該半導體裝置之厚度係藉由該密封劑及從該密封劑延伸出去之端子的厚度來判定。
  10. 如請求項5之方法，其進一步包含移除該密封劑之一部分。
  11. 一種半導體裝置，其包括： 電性組件；及 密封劑，其沉積於該電性組件上方，其中該電性組件之端子從該密封劑延伸出去，且該半導體裝置之厚度係藉由該密封劑及從該密封劑暴露之該端子的厚度來判定。
  12. 如請求項11之半導體裝置，其中該密封劑沉積於複數個電性組件上方。
  13. 如請求項11之半導體裝置，其進一步包含穿過該密封劑所形成之通道。
  14. 如請求項11之半導體裝置，其進一步包含沉積於該端子上方之導電膏。
  15. 如請求項11之半導體裝置，其中該電性組件包含半導體晶粒或離散半導體裝置。
TW112106124A 2022-05-02 2023-02-20 半導體裝置及形成沒有基板的系統級封裝模組的方法 TW202345243A (zh)

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