CN116982155A - Method for packaging semiconductor - Google Patents
Method for packaging semiconductor Download PDFInfo
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- CN116982155A CN116982155A CN202280018577.8A CN202280018577A CN116982155A CN 116982155 A CN116982155 A CN 116982155A CN 202280018577 A CN202280018577 A CN 202280018577A CN 116982155 A CN116982155 A CN 116982155A
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- pattern layer
- packaging
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 30
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- 238000000151 deposition Methods 0.000 claims description 37
- 238000002161 passivation Methods 0.000 claims description 32
- 239000004020 conductor Substances 0.000 claims description 23
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- 238000004519 manufacturing process Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 238000012858 packaging process Methods 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
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- 238000010586 diagram Methods 0.000 description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
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- 229910052721 tungsten Inorganic materials 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
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- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
The present invention relates to a method of packaging a semiconductor, and more particularly, to a method of packaging a semiconductor of a semiconductor device by a wafer level packaging method. A method of packaging a semiconductor according to an embodiment of the present invention includes the steps of: preparing a wafer comprising a plurality of semiconductor devices; forming a conductive pattern layer on the wafer by using a mask member provided independently of the wafer; and dicing the wafer for each of the semiconductor devices.
Description
Technical Field
The present invention relates to a method of packaging semiconductors, and more particularly, to a method of packaging semiconductors that is capable of packaging semiconductor devices in a wafer level packaging (wafer level packaging) method.
Background
The packaging process refers to a process of packaging a semiconductor device to protect the semiconductor device from the external environment. In such a packaging process, a process of forming a conductive pattern to arrange a circuit of a semiconductor to receive a signal from or transmit a signal to an external device is involved.
In the conventional packaging process, a wafer (wafer) including a plurality of semiconductor devices is cut along a dicing line to divide the semiconductor devices into individual semiconductor devices, and then the packaging process is performed for each of the divided individual semiconductor devices. The conventional packaging process needs to be performed in a chip (chip) unit, which takes a very long time to package all semiconductor devices.
In recent years, therefore, a wafer level packaging method for dividing a wafer is being used in which a packaging process is performed for each semiconductor device after the packaging process is performed in a state in which the wafer includes a plurality of semiconductor devices.
In such a wafer level packaging method, a conductive pattern for arranging a wiring of a semiconductor device is generally formed by a photolithography method. However, the photolithography method has a drawback in that it is difficult to effectively reduce the time required for packaging the semiconductor device due to a complicated process in which a photoresist is applied to a wafer to perform exposure, development and etching processes and then the photoresist is removed.
(prior art documents)
(patent document 1) KR10-2001-0061786A
Disclosure of Invention
Technical problem
The present invention provides a method of packaging semiconductors that improves the yield of semiconductor devices.
Technical means
According to an exemplary embodiment, a method of packaging a semiconductor includes: a wafer including a plurality of semiconductor devices is prepared and a conductive pattern layer electrically connected to the semiconductor devices is formed by using a mask member provided independently of the wafer.
Preparing the wafer may include preparing a wafer having a passivation layer formed on the semiconductor device.
Forming the conductive pattern layer may include: the mask is disposed over the wafer and a conductive material is supplied to the wafer to pass through the mask to deposit the conductive material on the wafer.
Providing the mask may include aligning the mask with the chip.
Providing the mask may include providing the mask on the wafer to be separated from the wafer.
Deposition of the conductive material may be performed by a sputtering process.
The placement of the masking members and the deposition of the conductive material may be performed in different chambers.
The placement of the masking members and the deposition of the conductive material may be performed simultaneously on different wafers.
The method may further include dicing the wafer for each semiconductor device after forming the conductive pattern layer.
The masking member may comprise a film coating mask.
Advantageous effects
Based on the semiconductor device packaging method according to the exemplary embodiment, the conductive pattern layer may be formed on the wafer including the plurality of semiconductor devices through a single process using the mask member provided in a wafer-independent manner, thereby minimizing the number of processes for forming the conductive pattern layer.
Therefore, the time taken to manufacture the semiconductor device can be minimized to minimize the material cost used in the process, thereby improving the yield of the semiconductor device.
Drawings
Fig. 1 is a schematic diagram illustrating an apparatus for packaging a substrate according to an exemplary embodiment.
Fig. 2 is a diagram illustrating a deposition apparatus according to an exemplary embodiment.
Fig. 3 is a schematic diagram illustrating a method of packaging a semiconductor according to an exemplary embodiment.
Fig. 4 to 10 are diagrams illustrating states in which semiconductors are packaged in a plurality of stages (stages) according to an exemplary embodiment.
Detailed Description
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions may be exaggerated for clarity of description. Like numbers refer to like elements throughout.
Fig. 1 is a schematic view illustrating an apparatus for packaging a substrate according to an exemplary embodiment, and fig. 2 is a view illustrating a deposition device according to an exemplary embodiment.
Referring to fig. 1 and 2, an apparatus for packaging semiconductors according to an exemplary embodiment may include a cassette 10, an apparatus front end module 20, a transfer module 30 (TM), a mask storage 40, a mask aligner 50, and a vapor deposition apparatus 60.
The apparatuses for packaging semiconductors may be classified into a cluster type (in-line type) and a linear type (in-line type) according to arrangement of devices. Here, the leaf type refers to a structure in which a plurality of other devices are disposed near one device (e.g., the conveyor 30), and the line type refers to a structure in which a plurality of devices are disposed in order. Hereinafter, a case where the apparatus for packaging semiconductors has a blade type will be exemplarily described, but the embodiment may also be applied to an apparatus for packaging semiconductors having a linear structure.
The wafer provided with the plurality of unit circuits is stored in the cassette 10. In this case, a first passivation layer may be further provided on the wafer to shield the unit circuits. Here, the wafer refers to a form in which these unit circuits are arranged on one substrate. In this case, each unit circuit may be referred to as a semiconductor device for performing functions such as information conversion, storage, and operation, and a wiring structure thereof. A plurality of wafers provided with the semiconductor devices and the first passivation layer as described above may be stored in the cassette 10. The number of cassettes 10 may be plural, i.e., include cassettes 10 for providing wafers to the equipment front end module 20 and cassettes 10 for receiving wafers from the equipment front end module 20.
In the apparatus for manufacturing semiconductor chips, wafers are loaded into the cassette 10 and provided to the apparatus front end module 20. Although not shown, the wafer provided to the equipment front end module 20 may be transferred to the transfer module 30 through a load lock chamber (loadlock chamber) L/L, U/L.
Wafers stored in the load lock chamber L/L, U/L may be transferred to each of the mask storage 40, the mask aligner 50, the deposition apparatus 60, and the auxiliary apparatus 70 by a transfer module 30 including a transfer machine for transferring the wafers. Here, the mask storage 40 may include a mask storage cavity storing a mask for forming a conductive pattern layer on the wafer, and the mask aligner 50 may include a mask alignment cavity placing a mask taken out of the mask storage cavity on the wafer and aligning the mask and the wafer. Furthermore, the deposition apparatus 60 may include a deposition chamber for forming a conductive pattern layer on the wafer using a mask, and the auxiliary apparatus 70 may include an auxiliary chamber for performing auxiliary functions such as heating the wafer.
Here, the deposition apparatus 60 may include a deposition chamber 610, a support 620, a support plate 630, and a target 640.
The deposition chamber 610 forms a process space in which a deposition process is performed, and the deposition chamber 610 may be connected to a predetermined vacuum pump (not shown) to maintain a vacuum state therein. The deposition chamber 610 may further include a gate valve (not shown) for disposing the wafer on the support 620 or unloading the wafer to the outside of the deposition chamber 610 and an exhaust port (not shown) for exhausting process gases and byproducts in the process space.
A gas supply pipe (not shown) for supplying an inert gas such as argon (Ar) may be connected to the deposition chamber 610. A gas supply tube may be connected to the deposition chamber 610 to supply an inert gas to a region where plasma discharge (plasma discharge) occurs, i.e., a region between the target 640 and the wafer.
A support 620 is disposed inside the deposition chamber 610 to support wafers loaded into the deposition chamber 610. The support 620 may include a heating element such as a built-in heating coil to heat the wafer disposed on the support 620. At the same time, a support 620 may be mounted in the deposition chamber 610 to allow at least one of lifting, rotating, and moving by means of a lifting device (not shown). For example, the support 620 may be raised so that the wafer gradually approaches or moves away from the target 640 from a starting position during the sputtering process. The support 620 may enable the substrate S to rotate in a clockwise or counterclockwise direction during a sputtering process, or may enable the substrate S to periodically rotate in a clockwise or counterclockwise direction.
The support plate 630 supports the target 640 and applies a voltage to the target 640. For this, the support plate 630 may be electrically connected to an external power source 650 (e.g., a direct current power source, an alternating current power source, or a radio frequency power source) to apply a plasma power supplied from the external power source 650 to the target 640.
A target 640 is installed in the deposition chamber 610 to face the support 620. In this case, the target 640 may be made of a conductive material to form a conductive pattern layer on the wafer and may have an area larger than that of the wafer. The targets 640 may be mounted on the rear surface of the support plate 630 to be separated from the wafer by a predetermined distance and to face each other.
Although not shown, the deposition apparatus 60 may further include a magnetic field forming unit installed inside the deposition chamber 610.
The magnetic field forming unit may vibrate with a specific period (or width) during the sputtering process and also form a magnetic field on the surface of the target 640 while moving in a predetermined direction, so as to uniformly distribute a corrosion (erosion) area of the target 640 over the entire area of the target 640 due to the magnetic field, thereby maximizing the use efficiency of the target 640. In addition, the magnetic field forming unit may form a high density plasma on the surface of the target 640 by the magnetic field to increase the deposition rate of the conductive pattern layer deposited on the wafer. For this purpose, the magnetic field forming unit may include a magnet module and a magnet moving module.
Hereinafter, a semiconductor chip manufacturing method according to an exemplary embodiment will be described in detail with reference to fig. 3 to 9. The semiconductor chip manufacturing method according to an exemplary embodiment may be a semiconductor chip manufacturing method by using the apparatus for manufacturing a semiconductor chip described above, and thus the description related to the apparatus for manufacturing a semiconductor chip described above is applicable thereto, and thus will not be repeated.
Fig. 3 is a schematic diagram illustrating a method of packaging a semiconductor according to an exemplary embodiment.
Referring to fig. 3, the semiconductor chip manufacturing method according to an exemplary embodiment includes a process S100 of preparing a wafer W including a plurality of semiconductor devices D and a process S200 of forming a conductive pattern layer MP1 or a conductive pattern layer MP2 on the wafer by using a mask M1 or a mask M2.
In the process S100 for preparing the wafer W, as shown in fig. 4, the wafer W on which a plurality of semiconductor devices D are formed is prepared. Here, the wafer W refers to a form in which these unit circuits are arranged on one substrate. In this case, as described above, each unit circuit may refer to the semiconductor device D for performing functions such as information conversion, storage, and calculation, and a wiring structure thereof.
In the process of preparing the wafer W, as shown in fig. 5, the wafer W having the first passivation layer P1 formed on the wafer W including the semiconductor devices D is prepared. Each semiconductor device D may have an input/output pad to be electrically connected to an external device. In this case, the first passivation layer P1 is formed on the semiconductor devices D to expose the input/output pads of the respective semiconductor devices D.
The first passivation layer P1 may be formed by first forming a first passivation film on the wafer W and then patterning the formed first passivation film by means of a laser drilling or photolithography process or patterning using a mask. At this time, the first passivation layer may be formed of at least one of Polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide-triazine (BT), phenol resin (phenolic resin), epoxy resin, silicon oxide (silicone), oxide layer (SiOx), and nitride layer (SiNx).
In the process S200 of forming the conductive pattern layer MP1 or the conductive pattern layer MP2, the conductive pattern layer MP1 or the conductive pattern layer MP2 is formed on the wafer W using the mask M1 or the mask M2. Here, the conductive pattern layer MP1 or the conductive pattern layer MP2 may include a metal pattern layer having conductivity. The mask M1 or the mask M2 may be made of a metal material or provided in a film-forming form using a synthetic resin such as polyimide. Such a mask M1 or mask M2 may include a plating mask provided independently of the wafer W.
The process S200 of forming the conductive pattern layer MP1 or the conductive pattern layer MP2 may include a process of forming the first conductive pattern layer MP1 on the first passivation layer P1 and a process of forming the second conductive pattern layer MP2 on the second passivation layer P2. In addition, the process of forming the conductive pattern layer MP1 or the conductive pattern layer MP2 may include a process of disposing the mask M1 or the mask M2 on the wafer W and a process of supplying a conductive material (e.g., a metal material) to the wafer W to pass through the mask M1 or the mask M2, thereby depositing the conductive material on the wafer W in the same shape as the pattern of the mask M1 or the mask M2.
In a wafer level package in which a packaging process is first performed in a state in which a wafer W includes the semiconductor devices D to divide the wafer W into a plurality of semiconductor chips, in the related art, a conductive pattern for arranging the wiring of the semiconductor devices is formed in a photolithography method. However, in the photolithography method, the photolithography method has a defect in that it takes a very long time to package the wafer W due to a complicated process in which a photoresist is applied on the wafer to perform exposure, development and etching processes, and then the photoresist is removed.
Accordingly, in an exemplary embodiment, by using the mask M1 or the mask M2, a conductive pattern layer may be formed on a wafer on which these semiconductor devices are formed, so as to minimize the number of processes for forming the conductive pattern layer.
In the process of forming the first conductive pattern layer MP1, as shown in fig. 6, the first conductive pattern layer MP1 is formed on the exposed area formed on the first passivation layer P1. Here, the first conductive pattern layer MP1 is used to redistribute the electrical paths of the semiconductor device D. That is, the first conductive pattern layer MP1 redistributes the electrical paths of the semiconductor device D to electrically connect the semiconductor chip to the external device regardless of the positions of the input/output pads of the semiconductor device D. The first conductive pattern layer MP1 may be made of a metal material having high conductivity, such as copper, silver, aluminum, nickel, etc., or an alloy material containing other components.
Here, the first mask M1 may be used to form the first conductive pattern layer MP1. That is, the process of forming the first conductive pattern layer MP1 may include a process of disposing the first mask M1 on the wafer W on which the first passivation layer P1 is formed and a process of supplying the first conductive material onto the wafer W to pass through the first mask M1, thereby forming the first conductive pattern layer MP1 on the first passivation layer P1 in the same shape as the pattern of the first mask M1.
In this case, in the process of forming the first conductive pattern layer MP1, the first mask M1 may be disposed on and aligned with the wafer W to be separated from the wafer W, and the first conductive material may be supplied onto the wafer W to pass through the first mask M1, thereby forming the first conductive pattern layer MP1. In this case, the process of disposing the first mask M1 and the process of depositing the first conductive material may be performed in different chambers. That is, as described above, since the apparatus for packaging semiconductors includes the mask aligner and the deposition device, the process of disposing the first mask member M1 and the process of depositing the first conductive material may be performed in different devices (i.e., different chambers).
The process of disposing the first mask M1 and the process of depositing the first conductive material may be performed simultaneously on different wafers. That is, since the mask aligner and the deposition apparatus are provided in a separate manner in the apparatus for packaging semiconductors according to an exemplary embodiment while the mask member is disposed on and aligned with the wafer in the mask aligner, the first conductive material may be deposited on another wafer in the deposition apparatus.
In this case, a chemical vapor deposition process may be performed to form the first conductive pattern layer MP1, but the process of forming the first conductive pattern layer MP1 may be performed by a sputtering process of depositing particles emitted from a metal target on the first passivation layer P1.
Next, as shown in fig. 7, a process of forming the second passivation layer P2 on the first conductive pattern layer MP1 may be performed.
In the process of forming the second passivation layer P2, the second passivation layer may be first formed on the first conductive pattern layer MP1, and then the second passivation layer may be patterned by means of a laser drilling, a photolithography process, or may be directly patterned using a mask to form the second passivation layer P2. At this time, the second passivation layer P2 may be formed of at least one of Polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide-triazine (BT), phenol resin (phenolic resin), epoxy resin, silicon oxide (silicone), oxide layer (SiOx), and nitride layer (SiNx).
The second passivation layer P2 and the first passivation layer P1 may be made of different materials. When the first passivation layer P1 and the second passivation layer P2 are formed of materials different from each other, permeated moisture or the like may move along a boundary between a plurality of layers formed of materials different from each other to increase a moving distance. Therefore, the penetration of moisture and the like can be prevented.
After the second passivation layer P2 is formed, a process of forming the second conductive pattern layer MP2 on the second passivation layer P2 may be performed. In the process of forming the second conductive pattern layer MP2, as shown in fig. 8, the second conductive pattern layer MP2 is formed on the exposed region formed on the second passivation layer P2. Here, the second conductive pattern layer MP2 serves as a seed layer for forming the conductive bump B. As described above, the second conductive pattern layer MP2 may be made of a metal material such as copper, silver, aluminum, nickel, chromium, titanium, or tungsten or an alloy material containing other components. Further, the second conductive pattern layer MP2 may be formed by laminating a plurality of layers, and in this case, a plurality of layers made of chromium, chrome-copper alloy, and copper material, a plurality of layers made of titanium-tungsten alloy, and copper material, or a plurality of layers made of aluminum, nickel, and copper material may be laminated to form the second conductive pattern layer MP2.
Here, the second mask M2 may be used to form the second conductive pattern layer MP2. That is, the process of forming the second conductive pattern layer MP2 may include a process of disposing the second mask M2 on the wafer W on which the second passivation layer P2 is formed and a process of supplying the second conductive material onto the wafer W to pass through the second mask M2, thereby forming the second conductive pattern layer MP2 on the second passivation layer P2 in the same shape as the pattern of the second mask M2.
In this case, in the process of forming the second conductive pattern layer MP2, the second mask M2 may be disposed on and aligned with the wafer W to be separated from the wafer W, and the second conductive material may be supplied onto the wafer W to pass through the second mask M2, thereby forming the second conductive pattern layer MP2. In this case, the process of disposing the second mask M2 and the process of depositing the second conductive material may be performed in different chambers, and the process of disposing the second mask M2 and the process of depositing the second conductive material, like the first conductive pattern layer MP1, may be performed simultaneously in different wafers.
In addition, a chemical vapor deposition process may be performed to form the second conductive pattern layer MP2, but the process of forming the second conductive pattern layer MP2 may be performed by a sputtering process of depositing particles emitted from a metal target on the second passivation layer P2, like the first conductive pattern layer MP1.
Thereafter, as shown in fig. 9, a process of forming the conductive bump B on the second conductive pattern layer MP2 may be performed.
Here, an electrolytic plating process electrolytic plating process may be used as a method for forming the conductive bump B. Further, the conductive bump B may be formed by directly forming conductive solder on the second conductive pattern layer MP2. In this case, the conductive bump B may be formed on the second conductive pattern layer MP2 based on a ball dropping process using a ball dropping plate (ball drop stencil) or screen printing.
In an exemplary embodiment, a structure of redistributing an electrical path of a semiconductor device using the first conductive pattern layer MP1 and the second conductive pattern layer MP2 is exemplarily described, but additional conductive pattern layers may be formed between the first conductive pattern layer MP1 and the second conductive pattern layer MP2 to redistribute an electrical path of the semiconductor device by means of three or more conductive pattern layers.
Thereafter, as shown in fig. 10, a process S300 of dicing wafers for the respective semiconductor devices may be performed. In the dicing process S300, a plurality of semiconductor chips including at least one semiconductor device D are formed by dicing the wafer along dicing lines.
Based on the semiconductor device packaging method according to the exemplary embodiment, the conductive pattern layer may be formed on the wafer including the plurality of semiconductor devices through a single process using the mask member provided in a wafer-independent manner, thereby minimizing the number of processes for forming the conductive pattern layer.
Therefore, the time taken to manufacture the semiconductor device can be minimized to minimize the material cost used in the process, thereby improving the yield of the semiconductor device.
Although the specific embodiments are described and illustrated using specific terms, these terms are merely examples for clearly explaining the exemplary embodiments, and thus it will be apparent to those skilled in the art that the exemplary embodiments and technical terms may be embodied in other specific forms without changing technical ideas or essential features. Therefore, it should be understood that simple modifications according to exemplary embodiments of the present invention may belong to the technical spirit of the present invention.
Claims (10)
1. A method of packaging a semiconductor, the method comprising:
preparing a wafer comprising a plurality of semiconductor devices; and
a conductive pattern layer electrically connected to the plurality of semiconductor devices is formed by using a mask provided independently of the wafer.
2. The method of claim 1, wherein preparing the wafer comprises preparing the wafer with a passivation layer formed on the plurality of semiconductor devices.
3. The method of claim 1, wherein forming the conductive pattern layer comprises:
disposing the mask on the wafer; and
a conductive material is supplied onto the wafer to pass through the mask member to deposit the conductive material on the wafer.
4. The method of claim 3, wherein disposing the mask comprises aligning the mask with the wafer.
5. The method of claim 3, wherein disposing the mask comprises disposing the mask on the wafer to be separated from the wafer.
6. The method of claim 3, wherein the depositing of the conductive material is performed by a sputtering process.
7. The method of claim 3, wherein the disposing of the mask and the depositing of the conductive material are performed in different chambers.
8. The method of claim 7, wherein the disposing of the masking member and the depositing of the conductive material are performed simultaneously on different wafers.
9. The method of claim 1, further comprising dicing the wafer for each of the semiconductor devices after forming the conductive pattern layer.
10. The method of claim 1, wherein the mask comprises a plating mask.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2021-0029614 | 2021-03-05 | ||
| KR1020220021287A KR20220125678A (en) | 2021-03-05 | 2022-02-18 | Method for packaging semiconductor |
| KR10-2022-0021287 | 2022-02-18 | ||
| PCT/KR2022/002742 WO2022186551A1 (en) | 2021-03-05 | 2022-02-24 | Semiconductor packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116982155A true CN116982155A (en) | 2023-10-31 |
Family
ID=88478223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280018577.8A Pending CN116982155A (en) | 2021-03-05 | 2022-02-24 | Method for packaging semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116982155A (en) |
-
2022
- 2022-02-24 CN CN202280018577.8A patent/CN116982155A/en active Pending
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