CN114171407A - Fan-out type packaging method and packaging structure - Google Patents

Fan-out type packaging method and packaging structure Download PDF

Info

Publication number
CN114171407A
CN114171407A CN202111493912.3A CN202111493912A CN114171407A CN 114171407 A CN114171407 A CN 114171407A CN 202111493912 A CN202111493912 A CN 202111493912A CN 114171407 A CN114171407 A CN 114171407A
Authority
CN
China
Prior art keywords
layer
chips
density
forming
groups
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111493912.3A
Other languages
Chinese (zh)
Inventor
杜茂华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tongfu Microelectronics Co Ltd
Original Assignee
Tongfu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tongfu Microelectronics Co Ltd filed Critical Tongfu Microelectronics Co Ltd
Priority to CN202111493912.3A priority Critical patent/CN114171407A/en
Publication of CN114171407A publication Critical patent/CN114171407A/en
Priority to PCT/CN2022/137251 priority patent/WO2023104097A1/en
Priority to US18/680,211 priority patent/US20240321825A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a fan-out type packaging method and a packaging structure, wherein the method comprises the following steps: providing a wafer carrying disc, a panel carrying sheet and a plurality of groups of first chips, wherein a plurality of conductive bumps are arranged on the front surface of each first chip; fixing the back surfaces of the multiple groups of first chips on the surface of the wafer carrying disc in a first array mode, and forming a first plastic packaging layer on the front surfaces of the multiple groups of first chips; separating the multiple groups of first chips from the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the multiple groups of first chips; cutting a plurality of groups of first chips, and fixing one side of the first chips on which the high-density interconnection wiring layer is formed on the surface of a panel carrier in a second array mode; forming a second plastic packaging layer on one side of the plurality of groups of first chips, which is far away from the high-density interconnection wiring layer; and separating the plurality of groups of first chips from the panel carrier to form a low-density interconnection wiring layer on the high-density interconnection wiring layer. The packaging method can well meet the requirement of high-density interconnection, and has low cost and high yield.

Description

Fan-out type packaging method and packaging structure
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out type packaging method and a fan-out type packaging structure.
Background
As semiconductor technology has advanced, packaging technology has advanced toward high density/high integration. Currently, fan-out technology is becoming an important development direction for high density interconnects. The single chip and the multiple chips are connected by using the rewiring layer, so that the flexibility of packaging integration is greatly improved. Fanout technology has been applied in the fields of High Performance Computing (HPC) and cell phone processors.
Currently, there are two main development directions for fan-out technology, one is fan-out wafer level package (FOWLP) based on wafer technology, and the other is fan-out panel level package (FOPLP) based on panel technology. The wiring density of fan-out wafer level packaging can be higher, the mass production of the line width of 2um is realized at present, but the yield is low, and the cost is high. Fan-out formula panel level encapsulation is because the output rate is high, and is with low costs, nevertheless because the panel size is big, and the fine rule width realizes that the degree of difficulty is big, but present volume production linewidth all is more than 5 um.
In view of the above problems, it is necessary to provide a fan-out package method and a package structure that are reasonable in design and can effectively solve the above problems.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art and provides a fan-out type packaging method and a packaging structure.
In one aspect of the invention, a fan-out packaging method is provided, the method comprising:
providing a wafer carrying disc, a panel carrying sheet and a plurality of groups of first chips, wherein a plurality of conductive bumps are arranged on the front surface of each first chip;
fixing the back surfaces of a plurality of groups of first chips on the surface of the wafer carrying disc in a first array mode, and forming a first plastic packaging layer on the front surfaces of the plurality of groups of first chips;
separating the multiple groups of first chips from the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the multiple groups of first chips;
cutting the plurality of groups of first chips, and fixing one side of the panel carrier sheet, on which the high-density interconnection wiring layer is formed, in a second array mode on the surface of the panel carrier sheet;
forming a second plastic packaging layer on one side of the plurality of groups of first chips, which is far away from the high-density interconnection wiring layer;
and separating the plurality of groups of first chips from the panel carrier, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.
Optionally, before forming the high-density interconnection wiring layer on the front side of the first chip, the method further includes:
and separating the plurality of groups of first chips from the wafer carrying disc, and grinding the front surfaces of the first chips to expose the conductive bumps.
Optionally, the forming a high-density interconnection wiring layer on the front surfaces of the plurality of groups of first chips includes:
forming a first dielectric layer on the first plastic packaging layer and the conductive bump, and patterning the first dielectric layer to form a plurality of first openings;
and forming a first metal interconnection layer on the surface of the patterned first dielectric layer, patterning the first metal interconnection layer, and forming the high-density interconnection wiring layer, wherein the first metal interconnection layer is electrically connected with the conductive bump.
Optionally, the forming a low-density interconnect wiring layer on the surface of the high-density interconnect wiring layer includes:
forming a second dielectric layer on the surface of the high-density interconnection wiring layer, and patterning the second dielectric layer to form a plurality of second openings;
and forming a second metal interconnection layer on the surface of the patterned second dielectric layer, and patterning the second metal interconnection layer to form the low-density interconnection wiring layer.
Optionally, the dielectric material of the first dielectric layer and the second dielectric layer is different.
Optionally, after forming the low-density interconnect wiring layer, the method further includes:
forming a third dielectric layer on the surface of the patterned second metal interconnection layer, and patterning the third dielectric layer to form a plurality of third openings;
planting balls at the third openings to form a plurality of solder balls;
and cutting the multiple groups of first chips to form a single group of chip packaging structure.
Optionally, after forming the plurality of solder balls, the method further includes: polishing one side of the second plastic packaging layer, which is far away from the plurality of groups of first chips; or,
after forming a second molding layer on a side of the plurality of groups of first chips facing away from the high-density interconnect wiring layer, the method further comprises:
and polishing one side of the second plastic packaging layer departing from the plurality of groups of first chips.
Optionally, each group of first chips includes one or more first chips.
Another aspect of the present invention provides a fan-out package structure, including: the chip comprises a first chip, a plastic package layer, a high-density interconnection wiring layer and a low-density interconnection wiring layer, wherein the front surface of the first chip is provided with a plurality of conductive bumps;
the plastic packaging layer wraps the first chip, and the high-density interconnection wiring layer is clamped between the plastic packaging layer and the low-density interconnection wiring layer.
Optionally, the high-density interconnect wiring layer includes a first dielectric layer disposed on the conductive bump, and a first metal interconnect layer disposed on the first dielectric layer,
wherein the first metal interconnect layer is electrically connected with the conductive bump;
the low-density interconnect routing layer includes a second dielectric layer disposed on the first metal interconnect layer, and a second metal interconnect layer disposed on the second dielectric layer.
According to the fan-out type packaging method and the packaging structure, after the high-density interconnection layer is completed by adopting a fan-out type wafer level packaging technology, the low-density interconnection layer is completed by adopting a fan-out type panel level packaging technology, compared with the traditional fan-out type wafer level packaging technology, the fan-out type packaging method can provide lower cost and higher yield under the condition of the same interconnection density, and compared with the traditional fan-out type panel level packaging technology, the fan-out type packaging method can provide higher interconnection density and meet the requirements of high-performance devices.
Drawings
FIG. 1 is a flow chart illustrating a fan-out packaging method according to an embodiment of the invention;
FIG. 2 is a schematic view of a chip placement area in a wafer carrier according to another embodiment of the present invention;
FIG. 3 is a schematic view of a second array B on a faceplate slide according to another embodiment of the present invention;
FIG. 4 is a schematic view of a first array A on a wafer carrier in accordance with another embodiment of the present invention;
fig. 5 to 21 are schematic views illustrating a packaging process of a fan-out package structure according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, an aspect of the present invention provides a packaging method S100 for a fan-out package structure, where the packaging method S100 includes:
s110, providing a wafer carrying disc, a panel carrying sheet and a plurality of groups of first chips, wherein a plurality of conductive bumps are arranged on the front surface of each first chip.
Specifically, as shown in fig. 2, 3 and 4, a wafer tray 110, a panel carrier 120 and a plurality of sets of first chips 130 are provided, wherein the front surface of the first chips 130 is provided with a plurality of conductive bumps 131. In this embodiment, the conductive bumps 131 are disposed at two ends of the first chip 130, and the conductive bumps 131 are copper conductive bumps, and other metal materials may also be used, which is not limited in this embodiment.
It should be noted that the main material of the wafer carrier 110 is glass, silicon wafer or metal. The main material of the panel carrier 120 is glass, metal or glass fiber resin. The materials of the wafer carrier plate 110 and the panel carrier 120 are not particularly limited in this embodiment, and may be selected as needed.
And S120, fixing the back surfaces of the multiple groups of first chips on the surface of the wafer carrying disc in a first array mode, and forming a first plastic packaging layer on the front surfaces of the multiple groups of first chips.
Specifically, as shown in fig. 5, the back surfaces of the plurality of groups of first chips 130 are fixed on the surface of the wafer carrier 110 by the first adhesive 111, that is, the first chips 130 are fixed on the surface of the wafer carrier 110 with their front surfaces facing upward. The high-density interconnection requirement can be well realized by using a wafer level packaging technology. As shown in fig. 3, the attached groups of first chips 130 form a first array a, which is a square array. As shown in fig. 6, plastic package is performed on the front surfaces of the plurality of groups of first chips 130 by using a plastic package material to form a first plastic package layer 140, and the first plastic package layer 140 protects the first chips 130. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
It should be noted that each group of the first chips 130 includes one or more first chips 130, and in this embodiment, each group of the first chips includes only one first chip 130.
S130, separating the multiple groups of first chips from the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the multiple groups of first chips.
Specifically, as shown in fig. 7, the back surfaces of the groups of first chips 130 are separated from the wafer carrier 110, and the separation method may adopt thermal separation, laser separation, ultraviolet light separation, mechanical separation, and the like, which are all currently common temporary bonding separation methods, and the separation method is not specifically limited in this embodiment and can be selected according to actual needs.
As shown in fig. 8, after the back surfaces of the plurality of groups of first chips 130 are separated from the wafer carrier 110, the front surfaces of the plurality of groups of first chips 130 are polished to expose the conductive bumps 131 on the front surfaces of the first chips 130. Other processes may be used to expose the conductive bump 131, and the embodiment is not limited in this respect.
Illustratively, forming a high-density interconnect wiring layer on the front side of the plurality of sets of first chips includes:
first, a first dielectric layer is formed on the first plastic package layer and the conductive bump, and the first dielectric layer is patterned to form a plurality of first openings.
Specifically, as shown in fig. 9, the first dielectric layer 150 is coated on the first molding layer 140 and the conductive bump 131, the material of the first dielectric layer 150 is Polyimide (PI), Polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not limited in this embodiment. The first dielectric layer 150 protects the plurality of groups of the first chips 130. The material of the first dielectric layer 150 and the coating process in this embodiment are not particularly limited, and may be selected according to actual requirements.
As shown in fig. 9, the first dielectric layer 150 is patterned through a photolithography process to form a plurality of first openings 151 on the first dielectric layer 150.
Secondly, forming a first metal interconnection layer on the surface of the patterned first dielectric layer, patterning the first metal interconnection layer, and forming the high-density interconnection wiring layer, wherein the first metal interconnection layer is electrically connected with the conductive bump.
Specifically, as shown in fig. 10, a first metal interconnection layer 160 is deposited on the surface of the patterned first dielectric layer 150, wherein the first metal interconnection layer 160 is electrically connected to the conductive bump 131. The deposition method may adopt electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal material of the first metal interconnection layer 160 is usually metal titanium and metal copper, and the deposition method and the metal material are not particularly limited in this embodiment. The first metal interconnection layer 160 is electrically connected to the conductive bump 131.
As shown in fig. 10, the first metal interconnection layer 160 is patterned by a photolithography and etching process to form a high-density interconnection wiring layer. The etching process may be wet etching or dry etching, and this embodiment is not particularly limited.
The fan-out wafer level packaging is adopted to form the high-density interconnection wiring layer, so that higher interconnection density can be provided, and the requirement of a high-performance device is met.
And S140, cutting the plurality of groups of first chips, and fixing the side on which the high-density interconnection wiring layer is formed on the surface of the panel carrier in a second array mode.
Specifically, as shown in fig. 11, a plurality of groups of first chips 130 are cut according to the area of the panel carrier 120 and fixed on the surface of the panel carrier 120 in the form of a second array B shown in fig. 4, and a panel-level packaging technology is used, so that the yield can be improved and the manufacturing cost can be reduced. In this embodiment, as shown in fig. 12, the side on which the high-density interconnection wiring layer is formed is fixed on the panel carrier 120 by the second patch adhesive 121, that is, the first metal interconnection layer 160 is attached to the second patch adhesive 121.
And S150, forming a second plastic package layer on one side of the plurality of groups of first chips, which is far away from the high-density interconnection wiring layer.
Specifically, as shown in fig. 13, the plurality of groups of first chips 130 are fixed on the panel carrier 120 in a second array form B, and then a second plastic package layer 170 is formed on a side of the plurality of groups of first chips 130 away from the high-density interconnection wiring layer, where the plastic package method may be a film vacuum lamination or a conventional plastic package process, and this embodiment is not limited in particular.
And S160, separating the plurality of groups of first chips from the panel slide, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.
Specifically, as shown in fig. 14, the groups of first chips 130 are separated from the panel carrier 120 by thermal separation, laser separation, ultraviolet separation, mechanical separation, and the like, which are all currently used temporary bonding separation methods, and the separation method is not specifically limited in this embodiment and can be selected according to actual needs.
Illustratively, forming a low-density interconnect routing layer on the high-density interconnect routing layer includes:
first, a second dielectric layer is formed on the surface of the high-density interconnection wiring layer, and the second dielectric layer is patterned to form a plurality of second openings.
Specifically, as shown in fig. 15, a second dielectric layer 180 is covered on the surface of the high-density interconnect wiring layer, that is, the surface of the first metal interconnect layer 160, and the second dielectric layer 180 protects the first metal interconnect layer 160. The material of the second dielectric layer 180 is a photo dielectric layer (PID) or an ajinomoto laminated film (ABF), and the embodiment is not limited in detail. The process of covering the surface of the first metal interconnection layer 160 with the second dielectric layer 180 may be a vacuum lamination or a printing process, and the embodiment is not particularly limited. As shown in fig. 15, the second dielectric layer 180 is patterned by a photolithography process to form a plurality of second openings 181.
And secondly, forming a second metal interconnection layer on the surface of the patterned second dielectric layer, and patterning the second metal interconnection layer to form the low-density interconnection wiring layer.
Specifically, as shown in fig. 16, a second metal interconnection layer 190 is deposited on the surface of the patterned second dielectric layer 180, the deposition method may adopt electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal material of the second metal interconnection layer 190 is usually titanium and copper, and the deposition method and the metal material of the second metal interconnection layer 190 are not particularly limited in this embodiment.
As shown in fig. 16, the second metal interconnection layer 190 is patterned by a photolithography and etching process to form a low-density interconnection wiring layer. The etching process may be wet etching or dry etching, and this embodiment is not particularly limited.
Illustratively, as shown in fig. 16, the dielectric materials of the first dielectric layer 150 and the second dielectric layer 180 are different. The first dielectric layer 150 is made of Polyimide (PI), Polybenzoxazole (PBO), or the like, and the second dielectric layer 180 is made of a photo dielectric layer (PID), an ajinomoto laminated film (ABF), or the like. This is because the first dielectric layer 150 is fabricated by wafer level processes and the second dielectric layer 180 is fabricated by panel level processes, and different processes select the preferred dielectric layer and the materials of the two dielectric layers are close to each other without the problems of poor contact or unrealizable process.
The low-density interconnection wiring layer formed by adopting fan-out type panel level packaging can provide lower cost under the condition of equal interconnection density.
Illustratively, after forming the low-density interconnect routing layer, the method further comprises:
firstly, forming a third dielectric layer on the surface of the patterned second metal interconnection layer, and patterning the third dielectric layer to form a plurality of third openings.
Specifically, as shown in fig. 17, a third dielectric layer 200 covers the surface of the patterned second metal interconnection layer 190, and a light-sensitive solder resist (PSR) or the like may be used as a material of the third dielectric layer 200, which is not limited in this embodiment. The process of covering the second metal interconnection layer 190 with the third dielectric layer 200 may be a vacuum lamination or a printing process, and the embodiment is not particularly limited. As shown in fig. 17, a photolithography process is used to pattern the third dielectric layer 200 to form a plurality of third openings 201.
And then, carrying out ball planting at the third openings to form a plurality of solder balls.
Specifically, as shown in fig. 18, ball mounting is performed at the plurality of third openings 201, and a plurality of solder balls 210 are formed.
And finally, cutting the multiple groups of first chips to form a single group of chip packaging structure.
Illustratively, as shown in fig. 19, after forming a plurality of solder balls 210, the plurality of groups of first chips 130 are cut to form a single group of chip package structures.
For example, as shown in fig. 20, after a plurality of solder balls 210 are formed, a side of the second molding compound 170 facing away from the plurality of groups of first chips 130 is polished to reduce the thickness of the package, and finally the package structure shown in fig. 21 is formed.
For example, as shown in fig. 13, after forming the second molding compound layer 170 on the side of the plurality of groups of first chips 130 facing away from the high-density interconnection wiring layer, the side of the second molding compound layer 170 facing away from the plurality of groups of first chips 130 is polished to reduce the package thickness.
It should be noted that, in the given embodiment, the dielectric layer structure is 3 layers or 4 layers, and the invention can be applied to various layers, which can be adjusted according to the actual design requirement. The number of interconnection layers used in the wafer-level and panel-level processes can also be adjusted according to actual design requirements, for example, when the second interconnection layer also needs high-density interconnection (the panel-level process cannot be realized), the two interconnection layers can be manufactured by using the wafer-level process, and then the wafer-level and panel-level processes are carried out.
It should be further noted that, in the present invention, as shown in fig. 2, the middle area of the wafer carrier 110 is a chip arrangement area 112, the chip arrangement areas 112 are distributed in a first array a as shown in fig. 3, and the chip arrangement area 112 is a square structure, and the diagonal length thereof is equivalent to the diameter of the wafer carrier 110. A high density interconnect wiring layer is formed within the intermediate region by temporary attachment and wafer level rewiring. The chip arrangement region 112 where the high-density interconnection is completed is cut and integrally built on the panel chip 120 in the form of a second array B as shown in fig. 4.
As shown in fig. 4, the size of the currently-used panel carrier 120 is 510 × 515 mm, in this case, 4 chip layout areas 112 can be placed at the same time, and the subsequent process is completed by using the panel-level package interconnection technology, so that the production efficiency can reach 4 times that of the wafer-level package technology, and in the future, if the LCD panel technology is used, the production efficiency can be improved by 6-8 times, and the cost is greatly reduced.
As shown in fig. 2, since the area of the chip placement region 112 is smaller than the area of the wafer carrier 110, a certain area loss will occur. Considering that the chips are all rectangular or square in size, the main wear area is a blank area 113 in the figure, with a short side dimension of 28 mm. For samples with package sizes close to or larger than 28 mm, this area is an invalid area, but for samples with package sizes close to or smaller than 28 mm, the blank area 113 can also be used, so the design of the chip layout area 112 does not increase the cost of the wafer level package. The high-density interconnection is mainly applied to the fields of high-performance calculation and the like, and the packaging in the field is developing towards a large-size direction, so that the high-density interconnection has a remarkable cost reduction effect.
In a package design, the density of the interconnection layer close to the chip is high, while the density of the interconnection layer far from the chip is low, and the connection line width tends to expand step by step. By utilizing the characteristics, the packaging method of the fan-out type packaging structure provided by the invention integrates and uses the fan-out type wafer level packaging technology and the fan-out type panel level packaging technology to complete the fan-out type packaging manufacture, the wafer level packaging technology is used for the interconnection layer close to the chip, the high-density interconnection requirement can be well realized, and the panel level packaging technology is used for the interconnection layer far away from the chip, so that the yield can be improved, and the manufacturing cost can be reduced.
As shown in fig. 21, another aspect of the present invention provides a fan-out package structure 100, the package structure comprising 100: the chip comprises a first chip 130, a plastic package layer 140, a high-density interconnection wiring layer (not shown in the figure) and a low-density interconnection wiring layer (not shown in the figure), wherein the front surface of the first chip 130 is provided with a plurality of conductive bumps 131. In this embodiment, the conductive bump 131 is a copper conductive bump, and other metal materials may also be used, which is not limited in this embodiment.
The plastic package layer 140 wraps the first chip 130, the high-density interconnection wiring layer is sandwiched between the plastic package layer 140 and the low-density interconnection wiring layer, and the conductive bumps 131 are electrically connected with the high-density interconnection wiring layer.
Illustratively, as shown in fig. 21, the high-density interconnect wiring layer includes a first dielectric layer 150 disposed on the conductive bump 131, and a first metal interconnect layer 160 disposed on the first dielectric layer 150, wherein the first metal interconnect layer 160 is electrically connected to the conductive bump 131.
The material of the first dielectric layer 150 is Polyimide (PI), Polybenzoxazole (PBO), etc., and the coating method is usually wafer spin coating, which is not limited in this embodiment. The first dielectric layer 150 protects the plurality of groups of the first chips 130. The material of the first dielectric layer 150 and the coating process in this embodiment are not particularly limited, and may be selected according to actual requirements.
It should be further noted that the first metal interconnection layer 160 can be deposited on the first dielectric layer 150 by using electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal material of the first metal interconnection layer 160 is usually titanium and copper, and the deposition method and the embodiment of the metal material of the first metal interconnection layer 160 are not particularly limited.
As shown in fig. 21, the low-density interconnect wiring layer includes a second dielectric layer 180 disposed on the first metal interconnect layer 160, and a second metal interconnect layer 190 disposed on the second dielectric layer 180.
The material of the second dielectric layer 180 is a photosensitive dielectric layer (PID) or an ajinomoto laminated film (ABF), and the embodiment is not particularly limited. The process of covering the surface of the first metal interconnection layer 160 with the second dielectric layer 180 may be a vacuum lamination or a printing process, and the embodiment is not particularly limited.
It should be further noted that the second metal interconnection layer 190 may be deposited on the second dielectric layer 180 by using electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal material of the second metal interconnection layer 190 is usually titanium and copper, and the deposition method of the second metal interconnection layer 190 and the metal material of the second metal interconnection layer 190 are not particularly limited in this embodiment.
The dielectric materials of the first dielectric layer 150 and the second dielectric layer 180 are different. The first dielectric layer 150 is made of Polyimide (PI), Polybenzoxazole (PBO), or the like, and the second dielectric layer 180 is made of a photo dielectric layer (PID), an ajinomoto laminated film (ABF), or the like. This is because the first dielectric layer 150 is fabricated on a wafer level process and the second dielectric layer 180 is fabricated on a panel level process. The optimal dielectric layer is selected according to different processes, and the materials of the two dielectric layers are close to each other, so that the problems of poor contact or incapability of realizing the process and the like can not occur.
Illustratively, as shown in fig. 21, the package structure 100 further includes a third dielectric layer 200 disposed on the second metal interconnection layer 190, and a plurality of solder balls 210 disposed on the third dielectric layer 200.
Note that the material of the third dielectric layer 200 may use a light-sensitive resist (PSR) or the like, and this embodiment is not particularly limited. The process of covering the second metal interconnection layer 190 with the third dielectric layer 200 may be a vacuum lamination or a printing process, and the embodiment is not particularly limited.
The fan-out type packaging structure is low in cost and high in yield, and can well meet the requirement of high-density interconnection.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A fan-out packaging method, the method comprising:
providing a wafer carrying disc, a panel carrying sheet and a plurality of groups of first chips, wherein a plurality of conductive bumps are arranged on the front surface of each first chip;
fixing the back surfaces of a plurality of groups of first chips on the surface of the wafer carrying disc in a first array mode, and forming a first plastic packaging layer on the front surfaces of the plurality of groups of first chips;
separating the multiple groups of first chips from the wafer carrying disc, and forming a high-density interconnection wiring layer on the front surfaces of the multiple groups of first chips;
cutting the plurality of groups of first chips, and fixing one side of the panel carrier sheet, on which the high-density interconnection wiring layer is formed, in a second array mode on the surface of the panel carrier sheet;
forming a second plastic packaging layer on one side of the plurality of groups of first chips, which is far away from the high-density interconnection wiring layer;
and separating the plurality of groups of first chips from the panel carrier, and forming a low-density interconnection wiring layer on the high-density interconnection wiring layer.
2. The method of claim 1, wherein prior to forming a high-density interconnect wiring layer on the front side of the first chip, the method further comprises:
and separating the plurality of groups of first chips from the wafer carrying disc, and grinding the front surfaces of the first chips to expose the conductive bumps.
3. The method of claim 2, wherein forming a high-density interconnect wiring layer on the front side of the plurality of sets of first chips comprises:
forming a first dielectric layer on the first plastic packaging layer and the conductive bump, and patterning the first dielectric layer to form a plurality of first openings;
and forming a first metal interconnection layer on the surface of the patterned first dielectric layer, patterning the first metal interconnection layer, and forming the high-density interconnection wiring layer, wherein the first metal interconnection layer is electrically connected with the conductive bump.
4. The method of claim 3, wherein said forming a low density interconnect routing layer on said high density interconnect routing layer surface comprises:
forming a second dielectric layer on the surface of the high-density interconnection wiring layer, and patterning the second dielectric layer to form a plurality of second openings;
and forming a second metal interconnection layer on the surface of the patterned second dielectric layer, and patterning the second metal interconnection layer to form the low-density interconnection wiring layer.
5. The method of claim 4, wherein the dielectric material of the first dielectric layer and the second dielectric layer are different.
6. The method of claim 3, wherein after forming the low density interconnect routing layer, the method further comprises:
forming a third dielectric layer on the surface of the patterned second metal interconnection layer, and patterning the third dielectric layer to form a plurality of third openings;
planting balls at the third openings to form a plurality of solder balls;
and cutting the multiple groups of first chips to form a single group of chip packaging structure.
7. The method of any of claims 1 to 6, wherein after forming a plurality of solder balls, the method further comprises:
polishing one side of the second plastic packaging layer, which is far away from the plurality of groups of first chips; or,
after forming a second molding layer on a side of the plurality of groups of first chips facing away from the high-density interconnect wiring layer, the method further comprises:
and polishing one side of the second plastic packaging layer departing from the plurality of groups of first chips.
8. The method according to any of claims 1 to 6, wherein each group of first chips comprises one or more first chips.
9. A fan-out package structure, the package structure comprising: the chip comprises a first chip, a plastic package layer, a high-density interconnection wiring layer and a low-density interconnection wiring layer, wherein the front surface of the first chip is provided with a plurality of conductive bumps;
the plastic packaging layer wraps the first chip, and the high-density interconnection wiring layer is clamped between the plastic packaging layer and the low-density interconnection wiring layer.
10. The package structure of claim 9,
the high-density interconnection wiring layer comprises a first dielectric layer arranged on the conductive bump and a first metal interconnection layer arranged on the first dielectric layer, wherein the first metal interconnection layer is electrically connected with the conductive bump;
the low-density interconnect routing layer includes a second dielectric layer disposed on the first metal interconnect layer, and a second metal interconnect layer disposed on the second dielectric layer.
CN202111493912.3A 2021-12-08 2021-12-08 Fan-out type packaging method and packaging structure Pending CN114171407A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202111493912.3A CN114171407A (en) 2021-12-08 2021-12-08 Fan-out type packaging method and packaging structure
PCT/CN2022/137251 WO2023104097A1 (en) 2021-12-08 2022-12-07 Fan-out packaging method and packaging structure thereof
US18/680,211 US20240321825A1 (en) 2021-12-08 2024-05-31 Fan-out packaging method and packaging structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111493912.3A CN114171407A (en) 2021-12-08 2021-12-08 Fan-out type packaging method and packaging structure

Publications (1)

Publication Number Publication Date
CN114171407A true CN114171407A (en) 2022-03-11

Family

ID=80484465

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111493912.3A Pending CN114171407A (en) 2021-12-08 2021-12-08 Fan-out type packaging method and packaging structure

Country Status (1)

Country Link
CN (1) CN114171407A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104097A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure thereof
CN117080352A (en) * 2023-10-16 2023-11-17 之江实验室 System-on-chip packaging structure and preparation method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104097A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Fan-out packaging method and packaging structure thereof
CN117080352A (en) * 2023-10-16 2023-11-17 之江实验室 System-on-chip packaging structure and preparation method thereof
CN117080352B (en) * 2023-10-16 2024-02-13 之江实验室 System-on-chip packaging structure and preparation method thereof

Similar Documents

Publication Publication Date Title
US10957671B2 (en) Method for fabricating a semiconductor and semiconductor package
US6673698B1 (en) Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers
KR20190003293A (en) Semiconductor device with shield for electromagnetic interference
US8383460B1 (en) Method for fabricating through substrate vias in semiconductor substrate
US8987050B1 (en) Method and system for backside dielectric patterning for wafer warpage and stress control
CN114171407A (en) Fan-out type packaging method and packaging structure
US7833835B2 (en) Multi-layer fin wiring interposer fabrication process
CN114171403A (en) Fan-out type packaging method and packaging structure
JP2002512436A (en) Integrated circuit device
KR20040098539A (en) Semiconductor chip production method, semiconductor device production method, semiconductor chip, and semiconductor device
CN114203689A (en) Fan-out type packaging method and packaging structure
CN114914196B (en) Local interposer 2.5D fan-out packaging structure and process based on core-grain concept
CN102593102B (en) Semiconductor chip, stack-type semiconductor package and manufacture method thereof
US20240321825A1 (en) Fan-out packaging method and packaging structure thereof
US11289435B2 (en) Fan-out antenna packaging structure and packaging method
TWI635579B (en) Package structure and manufacturing method thereof
CN114171409A (en) Fan-out type packaging method and packaging structure
US20200058605A1 (en) Fan-Out Antenna Package Structure And Packaging Method
CN114171412A (en) Fan-out type packaging method and packaging structure
CN114171401A (en) Packaging method and packaging structure of fan-out type stacked chip
CN116190323B (en) Wafer-level fan-out type packaging structure using silicon-based supporting structure and preparation method thereof
JP2003318323A (en) Semiconductor device and its manufacturing method
US20090102056A1 (en) Patterned Leads For WLCSP And Method For Fabricating The Same
CN111146099B (en) Semiconductor structure and manufacturing method thereof
US8847377B2 (en) Stacked wafer level package having a reduced size

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination