KR20220125678A - Method for packaging semiconductor - Google Patents

Abstract

The present invention relates to a semiconductor packaging method, and more particularly, to a semiconductor packaging method for packaging a semiconductor device using a wafer level packaging mode. A semiconductor packaging method according to an embodiment of the present invention includes the steps of: preparing a wafer including a plurality of semiconductor devices; forming a conductive pattern layer on the wafer using a mask member provided separately from the wafer; and cutting the wafer for each semiconductor device.

Description

Semiconductor packaging method

The present invention relates to a semiconductor packaging method, and more particularly, to a semiconductor packaging method for packaging a semiconductor device in a wafer level packaging method.

The packaging process refers to a process of packaging a semiconductor device to protect the semiconductor device from an external environment. In such a packaging process, a process of forming a conductive pattern in order to arrange wiring of a semiconductor device to exchange signals with an external device is accompanied.

In the conventional packaging process, a wafer including a plurality of semiconductor devices is cut along a dicing line to be separated into individual semiconductor devices, and then the packaging process is performed for each separated semiconductor device. In the conventional packaging process, since the packaging process must be performed on a chip-by-chip basis, it takes a very long time to package all semiconductor devices.

Accordingly, in recent years, a wafer level packaging method of first performing a packaging process in a state of a wafer including a plurality of semiconductor devices and then dicing the wafer for each semiconductor device has been used.

In such a wafer level packaging method, a conductive pattern for arranging wiring of a semiconductor device is generally formed by a photolithography method. However, in this photolithography method, a photoresist is coated on a wafer, exposure, development, and etching are performed, and then the photoresist is removed through a complicated process. There is a problem in that it is difficult to effectively reduce the time required for packaging the semiconductor device.

US 10-2001-0061786 A

The present invention provides a semiconductor packaging method capable of improving the productivity of a semiconductor device.

A semiconductor packaging method according to an embodiment of the present invention includes: preparing a wafer including a plurality of semiconductor devices; and forming a conductive pattern layer electrically connected to the plurality of semiconductor devices on the wafer by using a mask member provided separately from the wafer.

In the preparing of the wafer, a wafer having a passivation layer formed on the wafer including the plurality of semiconductor devices may be provided.

The forming of the conductive pattern layer may include disposing the mask member on the wafer; and supplying a conductive material to the wafer to pass through the mask member to deposit the conductive material on the wafer.

The disposing of the mask member may include aligning the mask member on the wafer.

The disposing of the mask member may include disposing the mask member on the wafer to be spaced apart from the wafer.

Depositing the conductive material may be performed by a sputtering process.

The disposing of the mask member and the depositing of the conductive material may be performed in different chambers.

The disposing of the mask member and the depositing of the conductive material may be simultaneously performed on different wafers.

The method may further include, after forming the conductive pattern layer, cutting the wafer for each semiconductor device.

The mask member may include a shadow mask.

According to the semiconductor packaging method according to an embodiment of the present invention, the conductive pattern layer is formed on a wafer including a plurality of semiconductor devices by a single process using a mask member provided separately from the wafer, thereby forming the conductive pattern layer. The number of processes can be minimized.

Accordingly, it is possible to minimize the time it takes to manufacture the semiconductor device, and it is possible to improve the productivity of the semiconductor device by minimizing the cost of materials used in the process.

1 is a view schematically showing a semiconductor packaging facility according to an embodiment of the present invention.
2 is a view showing a deposition apparatus according to an embodiment of the present invention.
3 is a diagram schematically illustrating a semiconductor packaging method according to an embodiment of the present invention.
4 to 9 are diagrams illustrating a state of packaging a semiconductor device in stages according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments of the present invention allow the disclosure of the present invention to be complete, and the scope of the invention to those of ordinary skill in the art It is provided to fully inform In order to explain the invention in detail, the drawings may be exaggerated, and like reference numerals refer to like elements in the drawings.

1 is a diagram schematically showing a semiconductor packaging facility according to an embodiment of the present invention, and FIG. 2 is a diagram showing a deposition apparatus according to an embodiment of the present invention.

1 and 2 , a semiconductor packaging facility according to an embodiment of the present invention includes a cassette 10 , an Equipment Front End Module (EFEM) 20 , and a Transfer Module (TM). ) 30 , a mask stocker 40 , a mask aligner 50 , and a vapor deposition (VD) 60 .

The semiconductor packaging equipment may be classified into a cluster type and an inline type according to an arrangement form of the device. Here, the cluster type means a structure in which a plurality of other devices are disposed around any one device, for example, the transfer device 30 , and the inline type means a structure in which a plurality of devices are sequentially disposed. Hereinafter, a case in which a semiconductor packaging facility has a cluster-type structure will be described as an example, but it goes without saying that embodiments of the present invention may also be applied to a semiconductor packaging facility having an in-line type structure.

The cassette 10 stores a wafer on which a plurality of unit circuits are formed. In this case, a first passivation layer may be further formed on the wafer to cover the plurality of unit circuits. Here, the wafer refers to a form in which a plurality of unit circuits are arranged on one substrate. In this case, the unit circuit may mean a semiconductor device and a wiring structure thereof for performing functions such as information conversion, storage, and calculation. A plurality of wafers on which a plurality of semiconductor devices and a first passivation layer are formed as described above may be stored in the cassette 10, and the cassette 10 is a cassette 10 for providing a wafer to a front end module 20 to be described later. and a cassette 10 for receiving a wafer from the front end module 20 may be provided in plurality.

In the semiconductor chip manufacturing facility, the wafer is loaded on the cassette 10 and provided to the front end module 20 . Although not shown, the wafer provided to the front end module 20 may be transferred to the transfer device 30 through the load lock chamber.

The wafers stored in the load lock chamber are transferred to the mask storage device 40 , the mask alignment device 50 , the deposition device 60 and the auxiliary device 70 by the transfer device 30 including a transfer robot for transferring the wafers. Each can be delivered. Here, the mask storage device 40 includes a mask storage chamber for storing a mask for forming a conductive pattern layer on the wafer, and the mask aligning device 50 arranges the mask drawn out from the mask storage chamber on the wafer. and may include a mask alignment chamber for aligning the mask and the wafer. In addition, the deposition apparatus 60 may include a deposition chamber for forming a conductive pattern layer on the wafer using a mask, and the auxiliary device 70 is an auxiliary chamber for performing auxiliary functions such as heating the wafer. may include

Here, the deposition apparatus 60 may include a deposition chamber 610 , a support 620 , a backing plate 630 , and a target 640 .

The deposition chamber 610 forms a process space in which a deposition process is performed, and the deposition chamber 610 may be connected to a predetermined vacuum pump (not shown) to maintain a vacuum therein. The deposition chamber 610 includes a gate valve (not shown) for seating the wafer on the support 620 or discharging the wafer to the outside of the deposition chamber 610 and an exhaust port for exhausting process gases and by-products in the process space ( not shown) may be further included.

A gas supply pipe (not shown) for supplying an inert gas, for example, argon (Ar) gas, etc. may be connected to the deposition chamber 610 . The gas supply pipe may be connected to the deposition chamber 610 to supply an inert gas to a region where plasma discharge occurs, that is, a region between the target 640 and the wafer.

The support 620 is located inside the deposition chamber 610 to support a wafer loaded into the deposition chamber 610 . The support 620 may include a heating member such as a built-in heating coil to heat the mounted wafer. Meanwhile, the support unit 620 may be installed in the deposition chamber 610 to enable at least one of lifting, rotating, and moving by a lifting device (not shown). For example, the support 620 may be lifted so that the wafer gradually approaches or moves away from the target 640 at the initial position during the sputtering process. Meanwhile, the support 620 may rotate the substrate S clockwise or counterclockwise during the sputtering process, or periodically rotate clockwise and counterclockwise.

The backing plate 630 supports the target 640 and allows a voltage to be applied to the target 640 . To this end, the backing plate 630 is electrically connected to an external power source 650 , for example, DC power, AC power, or RF power and applies plasma power supplied from the external power source 650 to the target 640 . can do.

The target 640 is installed in the deposition chamber 640 to face the support 620 . In this case, the target 640 may be formed of a conductive material for forming a conductive pattern layer on the wafer, and may have a larger area than the wafer. The target 640 may be installed on the rear surface of the backing plate 630 to be spaced apart from the wafer by a predetermined distance and to face each other.

Although not shown, it goes without saying that the deposition apparatus 60 may further include a magnetic field forming unit installed inside the deposition chamber 640 .

This magnetic field forming means forms a magnetic field on the surface of the target 640 while vibrating at a certain period (or width) during the sputtering process and moving in a predetermined direction, thereby forming an erosion region of the target 640 by the magnetic field on the target 640. It is possible to maximize the use efficiency of the target 640 by uniformly distributing it over the entire area of the target 640 . In addition, the magnetic field forming means may increase the deposition rate of the conductive pattern layer deposited on the wafer by forming high-density plasma on the surface of the target 640 through the magnetic field. To this end, the magnetic field forming means may include a magnet module and a magnet moving module.

Hereinafter, a method of manufacturing a semiconductor chip according to an embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 9 . The method for manufacturing a semiconductor chip according to an embodiment of the present invention may be a method for manufacturing a semiconductor chip by the above-described semiconductor chip manufacturing facility. Accordingly, since the above-described contents with respect to the semiconductor chip manufacturing facility may be applied as it is, the overlapping contents may be provided. A description will be omitted.

3 is a diagram schematically illustrating a method of manufacturing a semiconductor chip according to an embodiment of the present invention.

Referring to FIG. 3 , in the method of manufacturing a semiconductor chip according to an embodiment of the present invention, a step of preparing a wafer W including a plurality of semiconductor devices D ( S100 ) and a mask member M1 or M2 are used. and forming a conductive pattern layer MP1 or MP2 on the wafer W ( S200 ).

In the step of preparing the wafer W ( S100 ), as shown in FIG. 4 , a wafer W on which a plurality of semiconductor devices D are formed is prepared. Here, the wafer W refers to a form in which a plurality of unit circuits are arranged on one substrate. In this case, as described above, the unit circuit may mean a semiconductor device D and a wiring structure thereof for performing functions such as information conversion, storage, and calculation.

Meanwhile, in the step of preparing the wafer W, the wafer W having the first passivation layer P1 formed on the wafer W including the plurality of semiconductor devices D is prepared as shown in FIG. 5 . can The plurality of semiconductor devices D may each have input/output pads for electrical connection with an external device. In this case, the first passivation layer P1 is formed on the plurality of semiconductor devices D to expose the input/output pads of each semiconductor device D.

The first passivation layer P1 may be formed by first forming a first passivation film on the wafer W, and patterning the formed first passivation film by laser drilling or photolithography, or patterning using a mask. At this time, the first passivation layer is polyimide (PolyImide, PI), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (BismaleimideTriazine), phenolic resin, epoxy (epoxy), silicone (silicone) , an oxide film (SiO _x ) and a nitride film (SiN _x ) may be formed of at least one material.

In the step of forming the conductive pattern layer MP1 or MP2 ( S200 ), the conductive pattern layer MP1 or MP2 is formed on the wafer W using the mask member M1 or M2 . Here, the conductive pattern layer MP1 or MP2 may include a metal pattern layer having conductivity. Meanwhile, the mask member M1 or M2 may be formed of a metal material or may be formed in a film form using a synthetic resin such as polyimide. Such a mask member M1 or M2 may include a shadow mask provided separately from the wafer W. Referring to FIG.

Forming the conductive pattern layer MP1 or MP2 ( S200 ) includes forming the first conductive pattern layer MP1 on the first passivation layer P1 and the second conductive pattern layer on the second passivation layer P2 . Forming the pattern layer MP2 may be included. In addition, the forming of the conductive pattern layer MP1 or MP2 includes disposing a mask member M1 or M2 on the wafer W and the wafer W so as to pass through the mask member M1 or M2. and supplying a conductive material, for example, a metal material, to the substrate to deposit a conductive material on the wafer W in the same shape as the pattern of the mask member M1 or M2 .

In wafer level packaging in which a packaging process is first performed in a state of a wafer W including a plurality of semiconductor devices D, and then dicing into a plurality of semiconductor chips, in the prior art, a photolithography method is used. A conductive pattern for arranging the wiring of the semiconductor element was formed. However, in this photolithography method, a photoresist is coated on the wafer W, and the photoresist is removed after performing exposure, development and etching processes. There was a problem in that it takes a very long time to package the wafer W because it is made through the process.

Accordingly, in the exemplary embodiment of the present invention, the number of processes for forming the conductive pattern layer may be minimized by forming the conductive pattern layer using the mask member M1 or M2 on the wafer on which the plurality of semiconductor devices are formed.

In the forming of the first conductive pattern layer MP1 , as shown in FIG. 6 , the first conductive pattern layer MP1 is formed on the exposed area formed in the first passivation layer P1 . Here, the first conductive pattern layer MP1 serves to redistribute the electrical path of the semiconductor device D. Referring to FIG. That is, the first conductive pattern layer MP1 redistributes the electrical path of the semiconductor device D to electrically connect the semiconductor chip to an external device regardless of the position of the input/output pad of the semiconductor device D. The first conductive pattern layer MP1 may be formed of a metal material having high conductivity, such as copper, silver, aluminum, nickel, or the like, or an alloy material including other components.

Here, the first mask member M1 may be used to form the first conductive pattern layer MP1 . That is, the forming of the first conductive pattern layer MP1 includes disposing the first mask member M1 on the wafer W on which the first passivation layer P1 is formed, and forming the first mask member M1. The first conductive pattern layer MP1 may be formed on the first passivation layer P1 in the same shape as the pattern of the first mask member M1 by supplying the first conductive material on the wafer W to pass therethrough. can

In this case, the forming of the first conductive pattern layer MP1 includes disposing and aligning the first mask member M1 on the wafer W to be spaced apart from the wafer W, and forming the first mask member M1. The first conductive pattern layer MP1 may be formed by supplying a first conductive material on the wafer W to pass therethrough. In this case, the disposing of the first mask member MP1 and the depositing of the first conductive material may be performed in different chambers. That is, as described above, since the semiconductor packaging facility may include a mask alignment device and a deposition device, the step of disposing the first mask member MP1 and the step of depositing the first conductive material are different devices, that is, It can be performed in different chambers.

Meanwhile, disposing the first mask member MP1 and depositing the first conductive material may be simultaneously performed on different wafers. That is, since the mask alignment apparatus and the deposition apparatus are separately provided in the semiconductor packaging facility according to the embodiment of the present invention, while the mask member is disposed and aligned on one wafer in the mask alignment apparatus, in the deposition apparatus, the other wafer A first conductive material may be deposited thereon.

In this case, a chemical vapor deposition process may be performed to form the first conductive pattern layer MP1 , but the forming of the first conductive pattern layer MP1 includes transferring particles emitted from the metal target to the first passivation layer. (P1) may be performed by a sputtering process to deposit on.

Thereafter, as shown in FIG. 7 , a step of forming a second passivation layer P2 on the first conductive pattern layer MP1 may be performed.

In the step of forming the second passivation layer P2, a second passivation layer is first formed on the first conductive pattern layer MP1, and the formed second passivation layer is patterned by a laser drilling or photolithography process, or using a mask. A directly patterned second passivation layer P2 may be formed. At this time, the second passivation layer (P2) is polyimide (PolyImide, PI), BCB (Benzo Cyclo Butene), PBO (Poly Benz Oxazole), BT (BismaleimideTriazine), phenolic resin, epoxy, silicone (silicone), an oxide film (SiO _x ), and a nitride film (SiN _x ) may be formed of at least one material.

Meanwhile, the second passivation layer P2 may be formed of a material different from that of the first passivation layer P1 . When the first passivation layer (P1) and the second passivation layer (P2) are formed of different materials, the penetrating moisture or the like moves along the boundary of the film having different materials, thereby increasing the movement distance, and accordingly, moisture, etc. penetration can be prevented.

After the second passivation layer P2 is formed, a step of forming the second conductive pattern layer MP2 on the second passivation layer P2 may be performed. In the forming of the second conductive pattern layer MP2 , as shown in FIG. 8 , the second conductive pattern layer MP2 is formed on the exposed area formed in the second passivation P2 layer. Here, the second conductive pattern layer MP2 serves as a seed layer for forming the conductive bumps B. Referring to FIG. As such, the second conductive pattern layer MP2 may be made of a metal material such as copper, silver, aluminum, nickel, chromium, titanium, or tungsten, or an alloy material including other components. In addition, the second conductive pattern layer MP2 may be formed by stacking a plurality of layers, and in this case, a plurality of layers made of chromium, a chromium-copper alloy, and a copper material, a plurality of layers made of a titanium-tungsten alloy and a copper material, respectively. It may be formed by stacking two layers or a plurality of layers made of aluminum, nickel, and copper materials.

Here, the second mask member M2 may be used to form the second conductive pattern layer MP2 . That is, the forming of the second conductive pattern layer MP2 includes disposing the second mask member M2 on the wafer W on which the second passivation layer P2 is formed, and forming the second mask member M2. A second conductive pattern layer MP2 may be formed on the second passivation layer P2 in the same shape as the pattern of the second mask member M2 by supplying a second conductive material on the wafer W to pass therethrough. can

In this case, the forming of the second conductive pattern layer MP2 includes disposing and aligning the second mask member M2 on the wafer W to be spaced apart from the wafer W, and forming the second mask member M2. The second conductive pattern layer MP2 may be formed by supplying a second conductive material on the wafer W to pass therethrough. In this case, the disposing of the second mask member MP2 and the depositing of the second conductive material may be performed in different chambers, and the disposing of the second mask member MP2 and the second conductive material may be performed in different chambers. The step of depositing may be simultaneously performed on different wafers, which is the same as in the case of the first conductive pattern layer MP1.

In addition, although a chemical vapor deposition process may be performed to form the second conductive pattern layer MP2 , the forming of the second conductive pattern layer MP2 includes transferring particles emitted from the metal target to the second passivation layer. It may be performed by a sputtering process of depositing on (P2) the same as in the case of the first conductive pattern layer MP1.

Thereafter, as shown in FIG. 9 , a step of forming conductive bumps B on the second conductive pattern layer MP2 may be performed.

Here, an electrolytic plating process may be used as a method of forming the conductive bumps (B). In addition, the conductive bumps B may be formed by directly forming conductive solder on the second conductive pattern layer MP2. In this case, the conductive bumps B may be manufactured based on a ball drop process using a ball drop stencil or a screen printing process. Conductive bumps B may be formed on the second conductive pattern layer MP2 .

In the embodiment of the present invention, a structure in which electrical paths of a semiconductor device are redistributed using the first conductive pattern layer MP1 and the second conductive pattern layer MP2 has been described as an example, but the first conductive pattern layer MP1 It goes without saying that an additional conductive pattern layer may be formed between the second conductive pattern layer MP2 and the electrical path of the semiconductor device by three or more conductive pattern layers.

Thereafter, as shown in FIG. 10 , a step ( S300 ) of cutting the wafer for each semiconductor device may be performed. In the step of cutting the wafer ( S300 ), a plurality of semiconductor chips including at least one semiconductor device D are formed by cutting the wafer along a dicing line.

As described above, according to the semiconductor packaging method according to an embodiment of the present invention, the conductive pattern layer is formed on a wafer including a plurality of semiconductor devices by forming the conductive pattern layer in a single process using a mask member provided separately from the wafer. The number of processes for forming can be minimized.

Accordingly, it is possible to minimize the time it takes to manufacture the semiconductor device, and it is possible to improve the productivity of the semiconductor device by minimizing the cost of materials used in the process.

In the above, preferred embodiments of the present invention have been described and illustrated using specific terms, but such terms are only for clearly explaining the present invention, and the embodiments of the present invention and the described terms are the spirit of the following claims And it is obvious that various changes and changes can be made without departing from the scope. Such modified embodiments should not be individually understood from the spirit and scope of the present invention, but should be said to fall within the scope of the claims of the present invention.

10: Cassette 20: Front-end module
30: transfer device 40: mask storage device
50: mask alignment device 60: deposition device
610: deposition chamber 620: support
630: backing plate 640: target
650: external power 70: auxiliary device

Claims (10)

providing a wafer including a plurality of semiconductor devices; and
and forming a conductive pattern layer electrically connected to the plurality of semiconductor devices on the wafer by using a mask member provided separately from the wafer. The method according to claim 1,
The step of preparing the wafer,
A semiconductor packaging method for providing a wafer in which a passivation layer is formed on a wafer including the plurality of semiconductor devices. The method according to claim 1,
The step of forming the conductive pattern layer,
disposing the mask member on the wafer; and
and depositing a conductive material on the wafer by supplying a conductive material to the wafer to pass through the mask member. 4. The method of claim 3,
The step of disposing the mask member comprises:
A semiconductor packaging method for aligning the mask member on the wafer. 4. The method of claim 3,
Disposing the mask member comprises:
A semiconductor packaging method for disposing the mask member on the wafer to be spaced apart from the wafer. 4. The method of claim 3,
The step of depositing the conductive material is a semiconductor packaging method performed by a sputtering process. 4. The method of claim 3,
The disposing of the mask member and the depositing of the conductive material are performed in different chambers. 8. The method of claim 7,
The disposing of the mask member and the depositing of the conductive material are simultaneously performed on different wafers. The method according to claim 1,
After forming the conductive pattern layer,
The semiconductor packaging method further comprising; cutting the wafer for each semiconductor device. The method according to claim 1,
wherein the mask member includes a shadow mask.

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