TWI622115B - Wafer susceptor device and semiconductor apparatus - Google Patents

Abstract

A wafer carrier device includes a driving mechanism, a wafer base, and an electrical isolation component. The driving mechanism is coupled to a ground voltage. The wafer base is disposed on the driving mechanism and includes a receiving groove for placing a wafer. Electrical isolation elements are disposed on the wafer pedestal to suppress charge flow between the wafer and the ground voltage.

Description

Wafer carrier and semiconductor device

The disclosure relates to a wafer carrier device and a semiconductor device, and more particularly to a wafer carrier device having an electrical isolation component and a semiconductor device having a plasma device.

Semiconductor devices have been used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. The semiconductor device is fabricated substantially by sequentially depositing insulating or dielectric layers, conductive layers, and materials of the semiconductor layer to a wafer, and patterning a plurality of material layers using lithography techniques to form circuit components and components thereon. . Many integrated circuits are typically fabricated on a single wafer, and individual dies on the wafer are cut and separated along a cutting line between the integrated circuits. For example, individual dies are substantially packaged separately in a multi-wafer module or other type of package.

In an Atomic layer deposition process, a first precursor is first deposited on a wafer, and then a second precursor is deposited on the first precursor, and the first precursor and the second precursor are The materials are combined to form a film on the wafer. Since the thickness of the above film can be smaller than the thickness of the film formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD), the atomic layer deposition process has been gradually applied to advanced semiconductor processes.

Although atomic layer deposition devices are currently in line with general purposes, But did not meet the aspects. Therefore, there is a need to provide an improved solution for an atomic layer deposition apparatus.

The present disclosure provides a wafer carrier device including a driving mechanism, a wafer base, and an electrical isolation element. The driving mechanism is coupled to a ground voltage. The wafer base is disposed on the driving mechanism and includes a receiving groove for placing a wafer. Electrical isolation elements are disposed on the wafer pedestal to suppress charge flow between the wafer and the ground voltage.

The present disclosure provides a semiconductor device including a driving mechanism, a wafer base, an electrical isolation element, and a plasma device. The driving mechanism is coupled to a ground voltage. The wafer pedestal is disposed on the driving mechanism. The wafer base includes a plurality of receiving slots for placing a plurality of wafers. Electrical isolation elements are disposed on the wafer pedestal to suppress charge flow between the wafer and the ground voltage.

10‧‧‧ drive mechanism

20‧‧‧ Wafer pedestal

21‧‧‧Axis

22‧‧‧ Carrying tray

221‧‧‧ lower surface

222‧‧‧ upper surface

23‧‧‧ accommodating slots

231‧‧‧ bottom

24‧‧‧ interval bumps

30‧‧‧Electrical isolation components

31‧‧‧ interval projection

A1‧‧‧Semiconductor equipment

A2‧‧‧ wafer carrier

A3‧‧‧Processing device

AX1‧‧‧Rotary axis

B10‧‧‧Deposition device

B11‧‧‧Processing chamber

B12‧‧‧Sediment gas distribution device

B121‧‧‧Distributed ontology

B122‧‧‧ channel

B123‧‧‧air inlet

B124‧‧‧Export

B125‧‧‧ upper surface

B126‧‧‧ lower surface

B13‧‧‧First gas supply device

B14‧‧‧Second gas supply

B20‧‧‧Clearing device

B21‧‧‧Processing chamber

B22‧‧‧Clear gas distribution device

B221‧‧‧Distributed ontology

B222‧‧‧ channel

B223‧‧‧Air inlet

B224‧‧‧Export

B225‧‧‧ upper surface

B226‧‧‧ lower surface

B23‧‧‧Clean gas supply

B30‧‧‧Micro plasma device

B31‧‧‧Processing chamber

B32‧‧‧ Plasma gas distribution device

B321‧‧‧Distributed ontology

B322‧‧‧ channel

B323‧‧ Air intake

B324‧‧‧Export

B325‧‧‧ upper surface

B326‧‧‧ lower surface

B33‧‧‧First electrode plate

B331‧‧‧First Through Hole

B34‧‧‧Second electrode plate

B341‧‧‧Second through hole

B35‧‧‧RF device

B351‧‧‧RF generator

B352‧‧‧ impedance matching components

B36‧‧‧ Plasma gas supply device

VSS‧‧‧ Grounding voltage

W1‧‧‧ wafer

W11‧‧‧ upper surface

W12‧‧‧ lower surface

1 is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

2 is a top plan view of a semiconductor device in accordance with some embodiments of the present disclosure.

3 is a top plan view of a wafer susceptor in accordance with some embodiments of the present disclosure.

4 is a flow diagram of an atomic layer deposition process in accordance with some embodiments of the present disclosure.

FIG. 5 is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

Figure 6 is a schematic illustration of a semiconductor device in accordance with some embodiments of the present disclosure.

Figure 7 is a schematic illustration of a wafer carrier device in accordance with some embodiments of the present disclosure.

Figure 8 is a schematic illustration of a wafer carrier device in accordance with some embodiments of the present disclosure.

Figure 9 is a schematic illustration of a wafer carrier device in accordance with some embodiments of the present disclosure.

Figure 10 is a schematic illustration of a wafer carrier device in accordance with some embodiments of the present disclosure.

The following description provides many different embodiments, or examples, for implementing the various features of the disclosure. The components and arrangements described in the following specific examples are only used to simplify the disclosure, and are merely illustrative and not intended to limit the disclosure. For example, the description of the structure of the first feature on or above a second feature includes direct contact between the first and second features, or another feature disposed between the first and second features such that The first and second features are not in direct contact.

Spatially related terms used herein, such as above or below, are used to simply describe one element or the relationship of one feature to another. In addition to the orientations described in the drawings, the devices are used or operated in different orientations.

This description uses the same reference numerals and/or characters in the different examples. The foregoing use is only for simplification and clarity, and does not mean that it is not There must be an association between the same embodiment and the settings.

The vocabulary of the first and second words of this specification are for the purpose of clarity of explanation and are not intended to be construed as limiting. In addition, the first feature and the second feature are not limited to the same or different features.

The shapes, dimensions, thicknesses, and angles of inclinations in the drawings may not be drawn to scale or simplified for the purpose of clarity of description, and are merely illustrative.

It will be understood that in each of the steps of the following embodiments, additional steps may be added before, after, and between the steps, and some of the steps described above may be replaced, deleted, or moved.

1 is a schematic diagram of a semiconductor device device A1 in accordance with some embodiments of the present disclosure. 2 is a top plan view of a semiconductor device A1 in accordance with some embodiments of the present disclosure. FIG. 3 is a top plan view of wafer base 20 in accordance with some embodiments of the present disclosure.

The semiconductor device A1 may be an atomic layer deposition device, a plasma device, or an etching device. In the present embodiment, the semiconductor device A1 is an atomic layer deposition device. The atomic layer deposition apparatus is used to perform an Atomic layer deposition process to a wafer W1.

The semiconductor device A1 includes a wafer carrier A2 and a plurality of processing devices A3. The wafer carrier device A2 is used to carry a plurality of wafers W1. The processing device A3 is disposed above the wafer carrier A2. Each processing device A3 can be located above a wafer W1. As shown in Fig. 2, the processing device A3 is radially arranged. In some embodiments, processing device A3 is arranged along a circular path.

In some embodiments, processing device A3 can include multiple deposition packages B10, a plurality of cleaning devices B20, and a plurality of plasma devices B30. Each deposition device B10, cleaning device B20, and plasma device B30 are staggered.

In some embodiments, the wafer carrier A2 includes a drive mechanism 10 and a wafer base 20. The driving mechanism 10 is configured to rotate and/or lift the wafer base 20 and is coupled to a ground voltage VSS. The wafer pedestal 20 is disposed on the driving mechanism 10 and is configured to carry a plurality of wafers W1. The wafer pedestal 20 may have a receiving groove 23. The wafer W1 can be placed in the accommodating groove 23. In some embodiments, the driving mechanism 10 provides a vacuum suction to the receiving groove 23 of the wafer base 20, so that the wafer W1 is adsorbed in the receiving groove 23.

By rotating the wafer pedestal 20, the wafer W1 can be sequentially passed under the plurality of processing devices A3, thereby performing a plurality of steps of the atomic layer deposition process onto the wafer W1.

4 is a flow diagram of an atomic layer deposition process in accordance with some embodiments of the present disclosure. In step S101, a wafer W1 is rotated below the deposition apparatus B10 (as shown in FIG. 1), and the deposition apparatus B10 deposits the first material onto the wafer W1. In some embodiments, the first material may be dichlorosilane (DCS, SiH ₂ Cl ₂ ).

In some embodiments, the deposition apparatus B10 includes a processing chamber B11, a deposition gas distribution device B12, a first gas supply device B13, and a second gas supply device B14.

The processing chamber B11 is located above the wafer carrier A2. The cross-sectional area of the processing chamber B11 in the horizontal direction corresponds to the area of the accommodating groove 23 and the area of the wafer W1. In other words, when the process is in progress, the processing chamber B11 is not located above the two or more accommodating grooves 23 at the same time.

The deposition gas distribution device B12 is disposed in the processing chamber B11 and above the wafer carrier A2. In other words, the deposition gas distribution device B12 can be located above one of the accommodating grooves 23, but when the process is in progress, the deposition gas distribution device B12 is not located above the two or more accommodating grooves 23.

The deposition gas distributing device B12 may be a disk-like structure and may be circular. The deposition gas distribution device B12 includes a distribution body B121 and a channel B122. The distributed body B121 has an intake port B123 and a plurality of discharge ports B124. The passage B122 is connected to the intake port B123 and the discharge port B124.

In some embodiments, the air inlet B123 is formed on the upper surface B125 of the distribution body B121. The discharge port B124 is formed on the lower surface B126 of the distribution body B121. The lower surface B126 is oriented toward the wafer carrier A2. In some embodiments, the discharge ports B124 are evenly distributed on the lower surface B126 of the distribution body B121.

The first gas supply device B13 is coupled to the air inlet B123 of the distribution body B121. The first gas supply device B13 is configured to transport the first material to the deposition gas distribution device B12. The first material is input into the deposition gas distribution device B12 via the intake port B123, and is discharged to the deposition gas distribution device B12 via the passage B122 to the discharge port B124.

By depositing the gas distributing means B12, the first material can be uniformly distributed on the upper surface W11 of the wafer W1.

In step S103, a second material is deposited onto the first material. The second material may be ammonia (Ammonia). The chemical formula of ammonia gas can be (NH ₃ ). As shown in FIG. 1, the second gas supply device B14 is coupled to the intake port B123 of the distribution body B121. The second gas supply device B14 is configured to transport the second material to the deposition gas distribution device B12. The second material is input into the deposition gas distribution device B12 via the intake port B123, and is discharged to the deposition gas distribution device B12 via the passage B122 to the discharge port B124.

By depositing the gas distributing means B12, the second material can be uniformly distributed on the upper surface W11 of the wafer W1.

In some embodiments, deposition device B10 may not include second gas supply device B14. The second material is deposited onto the first material on wafer W1 via another deposition device. When the second material is to be deposited onto the first material on the wafer W1, the wafer carrier A2 moves the wafer W1 below the other deposition device.

In some embodiments, after depositing the first material onto the wafer W1, a cleaning process may be performed to remove the first material that is not attached to the wafer W1.

FIG. 5 is a schematic diagram of a semiconductor device A1 in accordance with some embodiments of the present disclosure. In step S105, the wafer W1 is rotated below the cleaning device B20 (as shown in FIG. 5), and the cleaning device B20 removes the excess second material by using a purge gas. In some embodiments, the purge gas described above can be nitrogen (N ₂ ).

In some embodiments, the cleaning device B20 includes a processing chamber B21, a purge gas distribution device B22, and a purge gas supply device B23.

The processing chamber B21 is located above the wafer carrier A2. The cross-sectional area of the processing chamber B21 in the horizontal direction corresponds to the area of the wafer W1 and the area of the accommodating groove 23. In other words, when the process is in progress, the processing chamber B21 is not located above the two or more accommodating grooves 23 at the same time.

The purge gas distribution device B22 is disposed in the processing chamber B21 and above the wafer carrier A2. In other words, the purge gas distribution device B22 can be located above one of the accommodating grooves 23, but the purge gas distribution device B22 is not At the same time, it is located above two or more accommodating grooves 23.

The purge gas distribution device B22 can be a disk-like structure and can be circular. The purge gas distribution device B22 includes a distribution body B221 and a passage B222. The distribution body B221 has an intake port B223 and a plurality of discharge ports B224. The passage B222 is connected to the intake port B223 and the discharge port B224.

In some embodiments, the air inlet B223 is formed on the upper surface B225 of the distribution body B221. The discharge port B224 is formed on the lower surface B226 of the distribution body B221, and the lower surface B226 faces the wafer carrier A2. In some embodiments, the discharge ports B224 are evenly distributed on the lower surface B326 of the distribution body B221.

The purge gas supply device B23 is coupled to the air inlet B223 of the distribution body B221. The purge gas supply device B23 is configured to transport the purge gas to the purge gas distribution device B22. The purge gas is input into the purge gas distribution device B22 via the intake port B223, and is discharged to the purge gas distribution device B22 via the passage B222 to the discharge port B224.

By removing the gas distributing means B22, the scavenging gas can be uniformly blown toward the upper surface W11 of the wafer W1 so that the excess second material which is not reacted with the first material is blown off the upper surface W11 of the wafer W1.

FIG. 6 is a schematic diagram of a semiconductor device A1 in accordance with some embodiments of the present disclosure. In step S107, a wafer W1 is rotated below the plasma device B30, and a plasma is generated onto the wafer W1 to strengthen the combination of the first material and the second material. In some embodiments, the plasma may be argon or nitrogen.

In some embodiments, the plasma device B30 includes a processing chamber B31, a plasma gas distribution device B32, a first electrode plate B33, and a second battery. A plate B34, a radio frequency device B35, and a plasma gas supply device B36.

The processing chamber B31 is located above the wafer carrier A2. The cross-sectional area of the processing chamber B11 in the horizontal direction corresponds to the area of the accommodating groove 23 and the area of the wafer W1. In other words, when the process is in progress, the processing chamber B11 is not located above the two or more accommodating grooves 23 at the same time.

The plasma gas distribution device B32 is disposed in the processing chamber B31 and above the second shock plate. The plasma gas distribution device B32 can be located above the accommodating groove 23, but the plasma gas distributing device B32 is not located above the two or more accommodating grooves 23 at the same time when the process is in progress.

The plasma gas distribution device B32 can be a disk-like structure and can be circular. The plasma gas distribution device B32 includes a distribution body B321 and a passage B322. The distributed body B321 has a plurality of intake ports B323 and a plurality of discharge ports B324. The passage B322 is connected to the intake port B323 and the discharge port B324.

In some embodiments, the air inlet B323 is formed on the upper surface B325 of the distribution body B321. The discharge port B324 is formed on the lower surface B326 of the distribution body B321, and the lower surface B326 faces the wafer carrier A2. In some embodiments, the discharge ports B324 are evenly distributed on the lower surface B326 of the distribution body B321.

The plasma gas supply device B36 is coupled to the air inlet B323 of the distribution body B321. The plasma gas supply device B36 is for transmitting the process gas to the plasma gas distribution device B32. The process gas is input into the plasma gas distribution device B32 via the intake port B323, and is discharged to the plasma gas distribution device B32 via the passage B322 to the discharge port B324. The process gas described above may be argon or nitrogen.

The first electrode plate B33 is disposed above one of the accommodating grooves 23. In other words, when the process is in progress, the processing chamber B31 is not located at the same time. Two or more accommodating grooves 23 are above, and the first electrode plate B33 is spaced apart from the wafer carrier A2. The first electrode plate B33 may be a plate-like structure. The first electrode plate B33 may be parallel to the horizontal plane and may be parallel to the wafer susceptor 20. In some embodiments, the first electrode plate B33 is coupled to a ground voltage. The first electrode plate B33 has a plurality of first through holes B331.

The second electrode plate B34 is disposed above the first electrode plate B33. The second electrode plate B34 and the first electrode plate B33 are spaced apart from each other. The second electrode plate B34 may be a plate-like structure and may be parallel to the first electrode plate B33. The second electrode plate B34 may have a plurality of second through holes B341. The process gas discharged from the plasma gas distribution device B32 passes through the second through hole B341 through the second electrode plate B34 to between the first electrode plate B33 and the second electrode plate B34.

The RF device B35 is coupled to the second electrode plate B34 for generating an electric field between the first electrode plate B33 and the second electrode plate B34. The processing gas between the first electrode plate B33 and the second electrode plate B34 forms a plasma via the electric field described above. In some embodiments, argon or nitrogen between the first electrode plate B33 and the second electrode plate B34 forms positively charged argon ions or nitrogen ions.

In some embodiments, the radio frequency device B35 includes a radio frequency generator B351 and an impedance matching component B352. The RF generator B351 is coupled to the impedance matching component B352, and the impedance matching component B352 is coupled to the second electrode plate B34. In some embodiments, the RF power generated by the radio frequency device B35 is between about 13.56 KHz and 60 kHz.

The plasma between the first electrode plate B33 and the second electrode plate B34 passes through the first through holes B331 of the first electrode plate B33 to the surface of the wafer W1 and the wafer base 20. In this embodiment, the first material on the wafer W1 is reinforced by plasma. The bond between the material and the second material.

In some embodiments, wafer base 20 can be made of a conductive material. In some embodiments, wafer base 20 can be made of a metal material such as iron, iron alloy, copper, or copper alloy. In some embodiments, wafer base 20 can be made of a non-metallic conductive material, such as graphite, or ceramic. The wafer base 20 has a resistivity between about 10 ^-9 ohms and 10 ^-7 ohm meters.

The wafer base 20 includes a shaft portion 21 and a carrier disk 22. The shaft portion 21 is disposed on the drive mechanism 10 and extends along a rotation axis AX1. The drive mechanism 10 drives the shaft portion 21 to rotate, thereby driving the carrier disk 22 to rotate. In some embodiments, one end of the shaft portion 21 is fixed to the center of the wafer base 20, and the other end of the shaft portion 21 is fixed to the drive mechanism 10. In some embodiments, the shaft portion 21 can be secured to the lower surface 221 of the carrier disk 22.

When the drive mechanism 10 drives the shaft portion 21 to rotate, the wafer base 20 rotates about the rotation axis AX1. In some embodiments, wafer base 20 extends along a horizontal plane. In other words, the drive mechanism 10 can drive the carrier tray 22 to rotate along a horizontal plane.

The carrier tray 22 can be a plate-like structure and can be circular. The carrier tray 22 includes a plurality of receiving slots 23 for placing the wafer W1. The accommodating groove 23 is formed on the upper surface 222 of the carrier disk 22. In some embodiments, the upper surface 222 is parallel to the lower surface 221 of the carrier disk 22, and the upper surface 222 and the lower surface 221 of the carrier disk 22 are the major surfaces of the carrier disk 22.

In some embodiments, the area of the bottom surface 231 of the receiving groove 23 is approximately larger than the area of the upper surface 222 or the lower surface 221 of the wafer W1. The area of the bottom surface 231 of the accommodating groove 23 is approximately the surface W11 or the lower surface W12 of the wafer W1. 1 to 2 times the product. The upper surface W11 and the lower surface W12 of the wafer W1 are the main surfaces of the wafer W1. The upper surface W11 of the wafer W1 may be parallel to the lower surface W12 of the wafer W1.

The depth of the accommodating groove 23 may be greater than the thickness of the wafer W1. When the wafer W1 is placed in the accommodating groove 23, the upper surface 411 of the wafer W1 is higher than or lower than the upper surface 222 of the accommodating disk 22 with respect to the bottom surface 231 of the accommodating groove 23. In some embodiments, when the wafer W1 is placed in the accommodating groove 23, the upper surface W11 of the wafer W1 is at the same level as the upper surface 222 of the carrier disk 22.

As shown in FIG. 3, the accommodating grooves 23 are radially arranged on the carrier tray 22. In other words, the accommodating slots 23 are spaced apart along the edge of the carrier tray 22, and the accommodating slots 23 are not located in the central area of the carrier tray 22. In some embodiments, the receiving slots 23 are arranged along a circular path.

In some embodiments, the carrier tray 22 can include a plurality of spacer protrusions 24 disposed on the bottom surface 231 of the receiving slot 23 . When the wafer W1 is placed in the accommodating groove 23, the spacer protrusion 24 supports or contacts the lower surface W12 of the wafer W1 to form a gap between the wafer W1 and the bottom surface 231 of the accommodating groove 23.

As shown in FIG. 1, the height of the spacer bump 24 with respect to the bottom surface 231 of the accommodating groove 23 is approximately equal to the thickness of the wafer W1. In some embodiments, the height of the spacer bumps 24 relative to the bottom surface 231 of the receiving trench 23 is between about 0.5 and 5 times the thickness of the wafer W1.

As shown in FIGS. 1 and 3, the spacer protrusions 24 are evenly distributed on the bottom surface 231 of the accommodating groove 23. In some embodiments, the spacer protrusions 24 may be arranged in an array on the bottom surface 231 of the accommodating groove 23.

The wafer base further includes an electrical isolation element 30 to suppress the wafer The charge flow between W1 and ground voltage 10. In some embodiments, the electrical isolation element 30 is disposed between the shaft portion 21 and the carrier disk 22. Electrical isolation element 30 can be a piece of structure. In some embodiments, the thickness of the electrically isolating element 30 can range between 50 mm and 100 mm.

In some embodiments, the electrical isolation element 30 has a dielectric constant between about 3.5 and 3.7. The electrical isolation element 30 has a resistivity between about 10 ¹⁴ ohms and 10 ¹⁹ ohm meters. In some embodiments, the electrical isolation element 30 has a resistivity greater than 10 ¹⁴ ohm meters. The material of the electrical isolation element 30 may comprise quartz, ceramic or a combination of the above.

As shown in FIG. 6, when a plasma process is performed, the positively charged ions are dropped into the wafer W1, the carrier disk 22, and the receiving groove 23 of the carrier disk 22. Since the driving mechanism 10 is coupled to the ground voltage VSS, a small amount of negative charges will sequentially neutralize the positively charged on the carrier 22 via the driving mechanism 10, the electrical isolation element 30, the shaft portion 21, and the carrier 22 ion. In addition, the negative charge is again conducted to the wafer W1 via the spacer bumps 24 to neutralize the positively charged ions that are dropped onto the wafer W1.

Since the electrical isolation element 30 is disposed on the wafer susceptor 20, the current of negative charge conduction to the wafer W1 can be greatly reduced, the high kinetic energy can be prevented from passing through the wafer, and the electronic components on the wafer can be damaged. And reducing the voltage on the wafer W1 can reduce the damage caused by the excessive voltage of the wafer W1, thereby improving the yield of the wafer W1.

Figure 7 is a schematic illustration of a wafer carrier A2 in accordance with some embodiments of the present disclosure. As shown in FIG. 7, the electrical isolation element 30 is disposed in the shaft portion 21. The electrically isolating element 30 extends in a direction perpendicular to the axis of rotation AX1. In some embodiments, the electrically isolating element 30 is located in a central section of the shaft portion 21. Electrical isolation component The drive mechanism 10 is spaced apart from the drive mechanism 10 and spaced from the carrier disk 22.

Figure 8 is a schematic illustration of a wafer carrier A2 in accordance with some embodiments of the present disclosure. As shown in FIG. 8, the electrical isolation element 30 is disposed within the carrier disk 22. The electrically isolating element 30 extends along the direction in which the carrier disk 22 extends. In some embodiments, the electrically isolating element 30 is located between the upper surface 222 and the lower surface 221 of the carrier disk 22. In some embodiments, the electrically isolating element 30 is located between the receiving groove 23 and the lower surface 221 of the retainer disk. In other words, the electrical isolation element 30 is spaced apart from the shaft portion 21 and spaced apart from the accommodating groove 23.

In another embodiment, the electrical isolation element 30 is disposed in a recess formed in the lower surface 221 of the carrier disk 22 and contacts the shaft portion 21.

Figure 9 is a schematic illustration of a wafer carrier A2 in accordance with some embodiments of the present disclosure. As shown in FIG. 9, the electrical isolation element 30 is disposed in the accommodating groove 23. In some embodiments, the electrical isolation element 30 is coated on the sidewall of the accommodating groove 23 and the bottom surface 231. In some embodiments, the electrical isolation element 30 includes a plurality of spacer protrusions 31 for supporting and contacting the lower surface W12 of the wafer W1. In some embodiments, the spacer protrusions 31 are evenly distributed over the bottom surface 231 of the accommodating groove 23.

In some embodiments, the electrically isolating element 30 may not include the spacer protrusions 31. The lower surface W12 of the wafer W1 is directly attached to the electrical isolation element 30.

Figure 10 is a schematic illustration of a wafer carrier A2 in accordance with some embodiments of the present disclosure. The electrically isolating element 30 is applied to the spacer protrusions 24 in the receiving groove 23. In other words, the electrically isolating element 30 is located between the wafer W1 and the spacer bumps 24. The electrically isolating component 30 is used to space the wafer W1 and the spacer bumps 24.

In summary, the wafer carrier device used in the semiconductor device of the present disclosure utilizes an electrical isolation element to suppress electricity between the wafer and the ground voltage. The flow of the load. Therefore, when a plasma process is performed on the wafer, the current conducted to the wafer through the wafer pedestal can be reduced, and the damage caused by the excessive voltage of the wafer can be reduced, thereby improving the yield of the wafer.

The present disclosure provides a wafer carrier device for use in a semiconductor device. In a plasma process, the wafer carrier device can lower the voltage generated by the wafer, thereby increasing the yield of the wafer.

The present disclosure provides a wafer carrier device including a driving mechanism, a wafer base, and an electrical isolation element. The driving mechanism is coupled to a ground voltage. The wafer base is disposed on the driving mechanism and includes a receiving groove for placing a wafer. Electrical isolation elements are disposed on the wafer pedestal to suppress charge flow between the wafer and the ground voltage.

In some embodiments, the electrical isolation element is disposed within the receiving slot. The electrically isolating element includes a plurality of spaced apart protrusions for contacting the underlying surface of the wafer.

In some embodiments, the wafer pedestal includes a plurality of spacer protrusions disposed on a bottom surface of the accommodating groove, and the electrical isolation element is disposed on the spacer protrusion.

In some embodiments, the wafer base further includes a shaft portion and a carrier tray. The shaft portion is disposed on the drive mechanism. The carrier disk is disposed on the shaft portion and includes a receiving groove.

In some embodiments, the electrically isolating element is disposed between the shaft portion and the carrier disk. In some embodiments, the electrically isolating element is disposed within the shaft portion and/or within the carrier disk.

The present disclosure provides a semiconductor device including a driving mechanism, a wafer base, an electrical isolation element, and a plasma device. Drive machine The coupling is connected to a ground voltage. The wafer pedestal is disposed on the driving mechanism. The wafer base includes a plurality of receiving slots for placing a plurality of wafers. Electrical isolation elements are disposed on the wafer pedestal to suppress charge flow between the wafer and the ground voltage.

In some embodiments, the plasma device includes a first electrode plate, a second electrode plate, and a radio frequency device. The first electrode plate is disposed above one of the accommodating grooves. The second electrode plate is disposed above the first electrode plate. The RF device is coupled to the second electrode plate for generating an electric field between the first electrode plate and the second electrode plate.

In some embodiments, the plasma device further includes a plasma gas distribution device and a plasma gas supply device. The plasma gas distribution device is disposed on the second electrode plate. The gas supply device provides a process gas to the plasma gas distribution device. The process gas flows between the first electrode plate and the second electrode plate via the plasma gas distribution device, and forms a plasma between the first electrode plate and the second electrode plate.

The above-disclosed features can be combined, modified, substituted or diverted with one or more of the disclosed embodiments in any suitable manner and are not limited to the specific embodiments.

The present invention has been described above with reference to various embodiments, which are intended to be illustrative only and not to limit the scope of the invention, and those skilled in the art can make a few changes without departing from the spirit and scope of the invention. With retouching. The above-described embodiments are not intended to limit the scope of the invention, and the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A wafer carrying device includes: a driving mechanism coupled to a ground voltage; a wafer base disposed on the driving mechanism, and including a receiving groove for placing a wafer; and an electrical An isolation component is disposed in the accommodating groove to suppress a charge flow between the wafer and the ground voltage, wherein the electrical isolation component includes a plurality of spacer protrusions for contacting the lower surface of the wafer. The wafer carrier device of claim 1, wherein the wafer base further comprises: a shaft portion disposed on the driving mechanism; and a carrier tray disposed on the shaft portion and including the receiving portion groove. A semiconductor device includes: a driving mechanism coupled to a ground voltage; a wafer base disposed on the driving mechanism, wherein the wafer base includes a plurality of receiving slots for placing a plurality of wafers An electrical isolation element disposed on the wafer base to suppress charge flow between the wafers and the ground voltage; and a plasma device disposed above the wafer carrier and comprising: a first electrode plate is disposed above one of the accommodating grooves; a second electrode plate is disposed above the first electrode plate; and a radio frequency device coupled to the second electrode plate And an electric field is generated between the first electrode plate and the second electrode plate. The semiconductor device of claim 3, wherein the plasma device further comprises: a plasma gas distribution device disposed on the second electrode plate; and a plasma gas supply device providing a process gas to The plasma gas distribution device; wherein the processing gas flows between the first electrode plate and the second electrode plate via the plasma gas distribution device, and forms between the first electrode plate and the second electrode plate Plasma. The semiconductor device of claim 3, wherein the electrical isolation component is disposed in the accommodating slots, and the electrical isolation component includes a plurality of spacer protrusions for contacting the wafers surface. The semiconductor device of claim 3, wherein the wafer pedestal comprises a plurality of spacer protrusions disposed on a bottom surface of the accommodating grooves, and the electrical isolation element is disposed on the spacer protrusions . The semiconductor device of claim 3, wherein the wafer base further comprises: a shaft portion disposed on the driving mechanism; and a carrier disk disposed on the shaft portion and including the receiving groove The electrical isolation element is disposed between the shaft portion and the carrier, within the shaft portion, and/or within the carrier tray. A wafer carrier device includes: a driving mechanism coupled to a ground voltage; a wafer base disposed on the driving mechanism and including a receiving groove for placing a wafer; An electrical isolation device is disposed on the wafer base to suppress a charge flow between the wafer and the ground voltage, wherein the wafer base includes a plurality of spacer protrusions disposed in the receiving groove On the bottom surface, the electrical isolation element is disposed on the equally spaced protrusions. A wafer carrier device includes: a driving mechanism coupled to a ground voltage; a wafer base disposed on the driving mechanism, and comprising: a shaft portion disposed on the driving mechanism; and a carrier tray Provided on the shaft portion, and including a receiving groove for placing a wafer; and an electrical isolation member disposed on the wafer base to suppress charge flow between the wafer and the ground voltage The electrical isolation element is disposed between the shaft portion and the carrier. A wafer carrier device includes: a driving mechanism coupled to a ground voltage; a wafer base disposed on the driving mechanism, and comprising: a shaft portion disposed on the driving mechanism; and a carrier tray Provided on the shaft portion, and including a receiving groove for placing a wafer; and an electrical isolation member disposed on the wafer base to suppress charge flow between the wafer and the ground voltage The electrically isolating component is disposed in the shaft portion and/or in the carrier.