CN108206153B - Wafer bearing device and semiconductor equipment - Google Patents
Wafer bearing device and semiconductor equipment Download PDFInfo
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- CN108206153B CN108206153B CN201611169532.3A CN201611169532A CN108206153B CN 108206153 B CN108206153 B CN 108206153B CN 201611169532 A CN201611169532 A CN 201611169532A CN 108206153 B CN108206153 B CN 108206153B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
Abstract
A wafer carrying device and a semiconductor device are provided, the wafer carrying device includes a driving mechanism, a wafer base and an electrical isolation element. The driving mechanism is coupled to a ground voltage. The wafer base is arranged on the driving mechanism and comprises a containing groove for placing a wafer. The electrically isolated element is arranged on the wafer pedestal to inhibit the charge flow between the wafer and the grounding voltage.
Description
Technical Field
The present disclosure relates generally to a wafer carrier and a semiconductor apparatus, and more particularly, to a wafer carrier with an electrical isolation device and a semiconductor apparatus with a plasma device.
Background
Semiconductor devices have been used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are generally manufactured by sequentially depositing materials for insulating or dielectric layers, conductive layers, and semiconductor layers onto a wafer and patterning the various material layers using lithographic techniques to form circuit elements and devices thereon. Many integrated circuits are typically fabricated on a single wafer, and individual dies on the wafer are singulated between the integrated circuits along a dicing line. For example, the individual dies are typically packaged separately in a multi-chip module or other type of package.
In an Atomic layer deposition (Atomic layer deposition) process, a first precursor is deposited on a wafer, a second precursor is deposited on the first precursor, and the first precursor and the second precursor are combined to form a thin film on the wafer. Since the thickness of the thin film may be smaller than that of a thin film formed by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), the ald process has been gradually applied to advanced semiconductor processes.
While current atomic layer deposition apparatus have met with general objectives, they have not met all aspects. Accordingly, there is a need to provide an improved arrangement of atomic layer deposition apparatus.
Disclosure of Invention
The present disclosure provides a wafer carrying device, which includes a driving mechanism, a wafer pedestal and an electrically isolated element. The driving mechanism is coupled to a ground voltage. The wafer base is arranged on the driving mechanism and comprises a containing groove for placing a wafer. The electrically isolated element is arranged on the wafer pedestal to inhibit the charge flow between the wafer and the grounding voltage.
The present disclosure provides a semiconductor apparatus including a driving mechanism, a wafer pedestal, an electrically isolating device, and a plasma device. The driving mechanism is coupled to a ground voltage. The wafer base is arranged on the driving mechanism. The wafer base comprises a plurality of accommodating grooves for accommodating a plurality of wafers. The electrically isolated element is arranged on the wafer pedestal to inhibit the charge flow between the wafer and the grounding voltage.
Drawings
Fig. 1 is a schematic diagram of a semiconductor apparatus according to some embodiments of the present disclosure.
Fig. 2 is a top view of a semiconductor apparatus according to some embodiments of the present disclosure.
Fig. 3 is a top view of a wafer pedestal according to some embodiments of the present disclosure.
Figure 4 is a flow diagram of an atomic layer deposition process in accordance with some embodiments of the present disclosure.
Fig. 5 is a schematic diagram of a semiconductor apparatus according to some embodiments of the present disclosure.
Fig. 6 is a schematic diagram of a semiconductor apparatus according to some embodiments of the present disclosure.
Fig. 7 is a schematic view of a wafer carrier apparatus according to some embodiments of the present disclosure.
Fig. 8 is a schematic view of a wafer carrier apparatus according to some embodiments of the present disclosure.
Fig. 9 is a schematic view of a wafer carrier apparatus according to some embodiments of the present disclosure.
Figure 10 is a schematic view of a wafer carrier apparatus according to some embodiments of the present disclosure.
Wherein the reference numerals are as follows:
Shaft part 21
Carrier tray 22
Semiconductor device a1
Wafer carrier A2
Processing apparatus A3
Rotation axis AX1
Deposition apparatus B10
Processing chamber B11
Deposition gas distribution apparatus B12
Distribution body B121
Channel B122
Air inlet B123
Discharge port B124
Upper surface B125
Lower surface B126
First gas supply device B13
Second gas supply device B14
Clearing device B20
Processing chamber B21
Purge gas distribution apparatus B22
Distribution body B221
Channel B222
Air inlet B223
Discharge port B224
Upper surface B225
Lower surface B226
Purge gas supply apparatus B23
Plasma apparatus B30
Processing chamber B31
Plasma gas distribution apparatus B32
Distribution body B321
Channel B322
Gas inlet B323
Discharge port B324
Upper surface B325
Lower surface B326
First electrode plate B33
First through hole B331
Second electrode plate B34
Second through hole B341
Radio frequency device B35
Radio frequency generator B351
Impedance matching element B352
Plasma gas supply device B36
Ground voltage VSS
Wafer W1
Upper surface W11
Lower surface W12
Detailed Description
The following description provides many different embodiments, or examples, for implementing different features of the disclosure. The following specific examples are intended to be illustrative only and are not intended to be limiting. For example, the description of a structure having a first feature over or on a second feature may include direct contact between the first and second features, or another feature disposed between the first and second features, such that the first and second features are not in direct contact.
Spatially relative terms, such as above or below, are used herein for ease of description of one element or feature relative to another element or feature. Devices that are used or operated in different orientations than those illustrated or described in the figures are intended to be encompassed.
The present description uses the same reference numbers and/or letters in the various examples. The foregoing is used for simplicity and clarity and does not necessarily indicate a relationship between the various embodiments and configurations.
The terms first and second, etc. in this specification are used for clarity of explanation only and do not correspond to and limit the scope of the claims. The terms first feature, second feature, and the like are not intended to be limited to the same or different features.
The shapes of the figures, dimensions, thicknesses, and angles of inclination may not be drawn to scale or simplified for clarity of illustration only and are provided for illustrative purposes.
It is understood that in the steps of the methods of the following embodiments, additional steps may be added before, after, and between the steps, and some of the steps may be replaced, deleted, or moved.
Fig. 1 is a schematic diagram of a semiconductor apparatus a1 according to some embodiments of the present disclosure. Fig. 2 is a top view of a semiconductor device a1, according to some embodiments of the present disclosure. Fig. 3 is a top view of a wafer pedestal 20 according to some embodiments of the present disclosure.
The semiconductor apparatus a1 may be an atomic layer deposition apparatus, a plasma apparatus, or an etching apparatus. In the present embodiment, the semiconductor apparatus a1 is an atomic layer deposition apparatus. The Atomic layer deposition apparatus is used to perform an Atomic layer deposition (Atomic layer deposition) process on a wafer W1.
The semiconductor apparatus a1 includes a wafer carrier a2 and a plurality of processing devices A3. The wafer carrier a2 is used for carrying a plurality of wafers W1. The processing apparatus A3 is disposed above the wafer carrier apparatus a 2. Each processing apparatus a3 may be located above a wafer W1. As shown in fig. 2, the processing devices a3 may be arranged radially. In some embodiments, processing device a3 is arranged along a circular path.
In some embodiments, the processing apparatus a3 may include a plurality of deposition apparatuses B10, a plurality of cleaning apparatuses B20, and a plurality of plasma apparatuses B30. Each of the deposition apparatus B10, the cleaning apparatus B20 and the plasma apparatus B30 was staggered.
In some embodiments, the wafer carrier a2 includes a drive mechanism 10 and a wafer pedestal 20. The driving mechanism 10 is used for rotating and/or lifting the wafer pedestal 20 and is coupled to a ground voltage VSS. The wafer susceptor 20 is disposed on the driving mechanism 10 and is used for carrying a plurality of wafers W1. The wafer base 20 may have a receiving slot 23. The wafer W1 may be placed in the receiving slot 23. In some embodiments, the driving mechanism 10 provides a vacuum force to the receiving cavity 23 of the wafer susceptor 20, so that the wafer W1 is sucked into the receiving cavity 23.
By rotating the wafer pedestal 20, the wafer W1 may be sequentially passed under a plurality of processing apparatuses A3, thereby performing a plurality of steps of the ald process onto the wafer W1.
Figure 4 is a flow diagram of an atomic layer deposition process in accordance with some embodiments of the present disclosure. In step S101, a wafer W1 is rotated below deposition apparatus B10 (shown in fig. 1), and deposition apparatus B10 deposits a first material on wafer W1. In some embodiments, the first material may be Dichlorosilane (DCS, SiH)2Cl2)。
In some embodiments, the deposition apparatus B10 includes a process chamber B11, a deposition gas distribution apparatus B12, a first gas supply apparatus B13, and a second gas supply apparatus B14.
Process chamber B11 is located above wafer carrier a 2. The cross-sectional area of the processing chamber B11 in the horizontal direction corresponds to the area of the receiving groove 23 and the area of the wafer W1. In other words, the processing chamber B11 is not simultaneously located above two or more receiving grooves 23 during the process.
Deposition gas distribution apparatus B12 is disposed within processing chamber B11 and above wafer carrier a 2. In other words, the deposition gas distribution apparatus B12 may be located above one receiving groove 23, but the deposition gas distribution apparatus B12 is not located above more than two receiving grooves 23 simultaneously during the process.
The deposition gas distribution apparatus B12 may have a disk-like structure and may be circular. The deposition gas distribution apparatus B12 includes a distribution body B121 and a passage B122. The distribution body B121 has an intake port B123 and a plurality of discharge ports B124. The passage B122 is connected to an intake port B123 and an exhaust port B124.
In some embodiments, the air inlet B123 is formed on the upper surface B125 of the distribution body B121. The discharge port B124 is formed in the lower surface B126 of the distributing body B121. The lower surface B126 faces the wafer carrier a 2. In some embodiments, the discharge openings B124 are evenly distributed on the lower surface B126 of the distribution body B121.
The first gas supply device B13 is coupled to the gas inlet B123 of the distribution body B121. The first gas supply apparatus B13 is used to deliver the first material to the deposition gas distribution apparatus B12. The first material is input into the deposition gas distribution apparatus B12 through the gas inlet B123 and discharged from the deposition gas distribution apparatus B12 through the passage B122 to the discharge port B124.
The deposition gas distribution apparatus B12 allows the first material to be uniformly distributed on the upper surface W11 of the wafer W1.
In step S103, a second material is deposited on the first material. The second material may be Ammonia (Ammonia). The ammonia gas may have the formula (NH)3). As shown in fig. 1, the second gas supply device B14 is coupled to the gas inlet B123 of the distribution body B121. The second gas supply device B14 is used to deliver the second material to the deposition gas distribution device B12. The second material is input into the deposition gas distribution apparatus B12 through the gas inlet B123 and discharged from the deposition gas distribution apparatus B12 through the passage B122 to the discharge port B124.
The second material is uniformly distributed on the upper surface W11 of the wafer W1 by the deposition gas distribution apparatus B12.
In some embodiments, the deposition apparatus B10 may not include the second gas supply apparatus B14. A second material is deposited via another deposition device onto the first material on the wafer W1. When a second material is to be deposited onto the first material on the wafer W1, the wafer carrier a2 moves the wafer W1 to below the other deposition apparatus.
In some embodiments, after depositing the first material on the wafer W1, a cleaning process may be performed to clean the first material not adhered to the wafer W1.
Fig. 5 is a schematic diagram of a semiconductor device a1, according to some embodiments of the present disclosure. In step S105, the wafer W1 is rotated to a position below the purge apparatus B20 (shown in FIG. 5), and the purge apparatus B20 uses a purge gas to purge excess second material. In some embodiments, the purge gas may be nitrogen (N)2)。
In some embodiments, the purge apparatus B20 includes a process chamber B21, a purge gas distribution apparatus B22, and a purge gas supply apparatus B23.
Process chamber B21 is located above wafer carrier a 2. The cross-sectional area of the processing chamber B21 in the horizontal direction corresponds to the area of the wafer W1 and the area of the receiving groove 23. In other words, the processing chamber B21 is not simultaneously located above two or more receiving grooves 23 during the process.
A purge gas distribution apparatus B22 is disposed within the processing chamber B21 above the wafer carrier a 2. In other words, the purge gas distributor B22 may be located above one receiving groove 23, but the purge gas distributor B22 is not located above more than two receiving grooves 23 at the same time.
The purge gas distributor B22 may be a disk-like structure and may be circular. The purge gas distribution means B22 includes a distribution body B221 and a channel B222. The distribution body B221 has an intake port B223 and a plurality of discharge ports B224. The passage B222 is connected to an intake port B223 and an exhaust port B224.
In some embodiments, the gas inlet B223 is formed on the upper surface B225 of the distribution body B221. The discharge port B224 is formed in the lower surface B326 of the distribution body B221, and the lower surface B226 faces the wafer carrier a 2. In some embodiments, the discharge openings B224 are evenly distributed on the lower surface B326 of the distribution body B221.
The purge gas supply device B23 is coupled to the gas inlet B223 of the distribution body B221. The purge gas supply B23 is used to deliver purge gas to the purge gas distribution device B22. The purge gas is input into the purge gas distributor B22 through the gas inlet B223 and discharged from the purge gas distributor B22 through the passage B222 to the discharge outlet B224.
By means of the purge gas distributor B22, the purge gas can be uniformly blown toward the upper surface W11 of the wafer W1, so that the excess second material that has not reacted with the first material is blown off the upper surface W11 of the wafer W1.
Fig. 6 is a schematic diagram of a semiconductor device a1, according to some embodiments of the present disclosure. In step S107, a wafer W1 is rotated below the plasma device B30 and a plasma is generated on the wafer W1 to enhance the bonding of the first material and the second material. In some embodiments, the plasma may be argon ions or nitrogen ions.
In some embodiments, the plasma device B30 includes a processing chamber B31, a plasma gas distribution device B32, a first electrode plate B33, a second electrode plate B34, a radio frequency device B35, and a plasma gas supply device B36.
Process chamber B31 is located above wafer carrier a 2. The cross-sectional area of the processing chamber B11 in the horizontal direction corresponds to the area of the receiving groove 23 and the area of the wafer W1. In other words, the processing chamber B11 is not simultaneously located above two or more receiving grooves 23 during the process.
A plasma gas distribution device B32 is disposed within the process chamber B31 above the second striking plate. The plasma gas distribution device B32 may be located above the receiving slots 23, but during the process, the plasma gas distribution device B32 is not located above more than two receiving slots 23 at the same time.
The plasma gas distribution apparatus B32 may have a disk-like structure and may be circular. The plasma gas distribution device B32 includes a distribution body B321 and a passage B322. The distribution body B321 has a plurality of intake ports B323 and a plurality of discharge ports B324. The passage B322 is connected to the intake port B323 and the discharge port B324.
In some embodiments, the gas inlets B323 are formed on the upper surface B325 of the distribution body B321. The discharge port B324 is formed on a lower surface B326 of the distribution body B321, and the lower surface B326 faces the wafer carrier a 2. In some embodiments, the discharge ports B324 are evenly distributed on the lower surface B326 of the distribution body B321.
The plasma gas supply device B36 is coupled to the gas inlet B323 of the distribution body B321. The plasma gas supply device B36 is used to deliver the process gas to the plasma gas distribution device B32. The process gas is input into the plasma gas distribution apparatus B32 through the gas inlet B323, and is exhausted out of the plasma gas distribution apparatus B32 through the passage B322 to the exhaust port B324. The processing gas may be argon or nitrogen.
The first electrode plate B33 is disposed above one of the receiving slots 23. In other words, the processing chamber B31 is not located above two or more receiving slots 23 simultaneously during the process, and the first electrode plate B33 and the wafer carrier a2 are spaced apart from each other. The first electrode plate B33 may be a plate-like structure. The first electrode plate B33 may be parallel to the horizontal plane and may be parallel to the wafer pedestal 20. In some embodiments, the first electrode plate B33 is coupled to a ground voltage. The first electrode plate B33 has a plurality of first through holes B331.
The second electrode plate B34 is disposed above the first electrode plate B33. The second electrode plate B34 is spaced apart from the first electrode plate B33. The second electrode plate B34 may be a plate-shaped structure, and may be parallel to the first electrode plate B33. The second electrode plate B34 may have a plurality of second through holes B341. The processing gas ejected from the plasma gas distribution device B32 passes through the second electrode plate B34 to between the first electrode plate B33 and the second electrode plate B34 via the second through holes B341.
The rf device B35 is coupled to the second electrode plate B34, and is used for generating an electric field between the first electrode plate B33 and the second electrode plate B34. The process gas between the first electrode plate B33 and the second electrode plate B34 forms plasma via the electric field described above. In some embodiments, the argon or nitrogen gas between the first electrode plate B33 and the second electrode plate B34 forms positively charged argon ions or nitrogen ions.
In some embodiments, the rf device B35 includes an rf generator B351 and an impedance matching element B352. The rf generator B351 is coupled to the impedance matching element B352, and the impedance matching element B352 is coupled to the second electrode plate B34. In some embodiments, the RF power generated by the RF device B35 is in the range of approximately 13.56kHz to 60 kHz.
The plasma between the first electrode plate B33 and the second electrode plate B34 flows through the first through hole B331 of the first electrode plate B33 to the wafer W1 and the surface of the wafer susceptor 20. In the present embodiment, the bonding between the first material and the second material on the wafer W1 is enhanced by plasma.
In some embodiments, the wafer pedestal 20 may be made of a conductive material. In some embodiments, the wafer pedestal 20 may be made of a metal material, such as iron, an iron alloy, copper, or a copper alloy. In some embodiments, the wafer pedestal 20 may be made of a non-metallic conductive material, such as graphite or ceramic. The wafer pedestal 20 has a resistivity of about 10-9Ohm's meter to 10-7Between the range of ohm meters.
The wafer pedestal 20 includes a shaft 21 and a susceptor 22. The shaft 21 is provided on the drive mechanism 10 and extends along a rotation axis AX 1. The driving mechanism 10 drives the shaft 21 to rotate, so as to drive the carrier tray 22 to rotate. In some embodiments, one end of the shaft 21 is fixed to the center of the wafer pedestal 20, and the other end of the shaft 21 is fixed to the driving mechanism 10. In some embodiments, shaft 21 may be fixed to lower surface 221 of carrier tray 22.
When the drive mechanism 10 rotates the drive shaft 21, the wafer susceptor 20 rotates about the rotation axis AX 1. In some embodiments, the wafer pedestal 20 extends along a horizontal plane. In other words, the driving mechanism 10 can drive the carrier tray 22 to rotate along a horizontal plane.
The carrier tray 22 may have a plate-like structure and may be circular. The susceptor 22 includes a plurality of receiving slots 23 for receiving the wafers W1. The receiving grooves 23 are formed on the upper surface 222 of the carrier tray 22. In some embodiments, the upper surface 222 is parallel to the lower surface 221 of the susceptor 22, and the upper surface 222 and the lower surface 221 of the susceptor 22 are major surfaces of the susceptor 22.
In some embodiments, the area of the bottom 231 of the receiving cavity 23 is substantially larger than the area of the top surface 222 or the bottom surface 221 of the wafer W1. The area of the bottom 231 of the receiving cavity 23 is about 1 to 2 times the area of the upper surface W11 or the lower surface W12 of the wafer W1. The upper surface W11 and the lower surface W12 of the wafer W1 are the main surfaces of the wafer W1. The upper surface W11 of the wafer W1 may be parallel to the lower surface W12 of the wafer W1.
The depth of the receiving groove 23 may be greater than the thickness of the wafer W1. When the wafer W1 is placed in the receiving cavity 23, the top surface W11 of the wafer W1 is higher or lower than the top surface 222 of the susceptor 22 relative to the bottom 231 of the receiving cavity 23. In some embodiments, when the wafer W1 is placed in the receiving cavity 23, the top surface W11 of the wafer W1 is at the same level as the top surface 222 of the susceptor 22.
As shown in fig. 3, the receiving grooves 23 may be radially arranged on the tray 22. In other words, the receiving grooves 23 may be arranged at intervals along the edge of the carrier tray 22, and the receiving grooves 23 are not located in the central region of the carrier tray 22. In some embodiments, the accommodating grooves 23 are arranged along a circular path.
In some embodiments, the tray 22 may include a plurality of spacing protrusions 24 disposed on the bottom 231 of the accommodating groove 23. When the wafer W1 is placed in the receiving cavity 23, the spacer bumps 24 support or contact the lower surface W12 of the wafer W1, so that a gap is formed between the wafer W1 and the bottom 231 of the receiving cavity 23.
As shown in fig. 1, the height of the spacer bumps 24 relative to the bottom 231 of the receiving cavity 23 is approximately equal to the thickness of the wafer W1. In some embodiments, the height of the spacer bumps 24 relative to the bottom 231 of the receiving cavity 23 is in a range of about 0.5 to 5 times the thickness of the wafer W1.
As shown in fig. 1 and 3, the spacing protrusions 24 may be evenly distributed on the bottom surface 231 of the receiving groove 23. In some embodiments, the spacing protrusions 24 may be arranged on the bottom surface 231 of the receiving cavity 23 in an array manner.
The wafer pedestal further includes an electrically isolated device 30 to inhibit the flow of charge between the wafer W1 and the ground voltage 10. In some embodiments, the electrically isolating element 30 is disposed between the shaft 21 and the carrier tray 22. The electrically isolating element 30 may be a sheet structure. In some embodiments, the thickness of the electrical isolation element 30 may be in a range of 50mm to 100 mm.
In some embodiments, the dielectric constant of the electrically isolated elements 30 is in a range of about 3.5 to about 3.7. Electrical insulationThe resistivity of the discrete element 30 is about 1014Ohm's meter to 1019Between the range of ohm meters. In some embodiments, the electrical resistivity of the electrically isolated components 30 is greater than 1014Ohm-rice. The electrically isolating elements 30 may be made of quartz, ceramic, or a combination thereof.
As shown in fig. 6, when a plasma process is performed, the positively charged ions fall into the wafer W1, the susceptor 22 and the receiving cavity 23 of the susceptor 22. Since the driving mechanism 10 is coupled to the ground voltage VSS, a small amount of negative charges sequentially pass through the driving mechanism 10, the electrically isolating element 30, the shaft 21 and the susceptor 22 to neutralize the positively charged ions on the susceptor 22. In addition, the negative charges are conducted to the wafer W1 through the spacer bumps 24 to neutralize the positively charged ions falling onto the wafer W1.
Since the electrically isolating elements 30 are disposed on the wafer pedestal 20, the current conducted by the negative charge to the wafer W1 is greatly reduced, preventing the high kinetic energy charges from penetrating the wafer and damaging the electronic components on the wafer. And the voltage on the wafer W1 is reduced, so that the damage of the wafer W1 caused by an excessively high voltage can be reduced, and the yield of the wafer W1 can be improved.
Fig. 7 is a schematic view of a wafer carrier apparatus a2 according to some embodiments of the present disclosure. As shown in fig. 7, the electrically isolating element 30 is disposed in the shaft 21. The electrically isolating member 30 extends in a direction perpendicular to the rotation axis AX 1. In some embodiments, the electrically isolating element 30 is located in a central section of the shaft 21. The electrically isolating element 30 is spaced apart from the driving mechanism 10 and from the carrier tray 22.
Fig. 8 is a schematic view of a wafer carrier apparatus a2 according to some embodiments of the present disclosure. As shown in fig. 8, the electrically isolating elements 30 are disposed in the carrier tray 22. The electrically isolating elements 30 extend along the extension direction of the carrier tray 22. In some embodiments, the electrically isolating elements 30 are located between the upper surface 222 and the lower surface 221 of the susceptor 22. In some embodiments, the electrically isolating element 30 is located between the receiving groove 23 and the lower surface 221 of the tray. In other words, the electrically isolating element 30 is spaced apart from the shaft 21 and spaced apart from the receiving groove 23.
In another embodiment, the electrically isolating element 30 is disposed in a groove formed on the lower surface 221 of the carrier 22 and contacts the shaft 21.
Fig. 9 is a schematic view of a wafer carrier apparatus a2 according to some embodiments of the present disclosure. As shown in fig. 9, the electrically isolating element 30 is disposed in the receiving groove 23. In some embodiments, the electrical isolation element 30 is coated on the sidewall and the bottom 231 of the receiving groove 23. In some embodiments, the electrically isolating element 30 includes a plurality of spaced apart bumps 31 for supporting and contacting the lower surface W12 of the wafer W1. In some embodiments, the spacing protrusions 31 may be evenly distributed on the bottom surface 231 of the receiving groove 23.
In some embodiments, the electrically isolating element 30 may not include the spacer bump 31. The lower surface W12 of the wafer W1 directly adheres to the electrically isolated components 30.
Fig. 10 is a schematic view of a wafer carrier apparatus a2 according to some embodiments of the present disclosure. The electrically isolating element 30 is coated on the spacing protrusions 24 in the receiving groove 23. In other words, the electrically isolating elements 30 are located between the wafer W1 and the spacer bumps 24. The electrically isolating elements 30 are used to space the wafer W1 from the spacer bumps 24.
In summary, the wafer carrier device for semiconductor equipment of the present disclosure utilizes the electrically isolating element to suppress the charge flow between the wafer and the ground voltage. Therefore, when a plasma process is performed on the wafer, the current conducted to the wafer through the wafer pedestal can be reduced, damage to the wafer due to an excessive voltage can be reduced, and the yield of the wafer can be improved.
The present disclosure provides a wafer carrier device for a semiconductor device, which can reduce a voltage generated to a wafer during a plasma process, thereby increasing a yield of the wafer.
The present disclosure provides a wafer carrying device, which includes a driving mechanism, a wafer pedestal and an electrically isolated element. The driving mechanism is coupled to a ground voltage. The wafer base is arranged on the driving mechanism and comprises a containing groove for placing a wafer. The electrically isolated element is arranged on the wafer pedestal to inhibit the charge flow between the wafer and the grounding voltage.
In some embodiments, the electrically isolating element is disposed in the receiving groove. The electrically isolated element comprises a plurality of spacing lugs for contacting the lower surface of the wafer.
In some embodiments, the wafer pedestal includes a plurality of spaced bumps disposed on the bottom surface of the receiving cavity, and the electrically isolating elements are disposed on the spaced bumps.
In some embodiments, the wafer pedestal further includes a shaft and a susceptor. The shaft portion is disposed on the driving mechanism. The bearing disc is arranged on the shaft part and comprises a containing groove.
In some embodiments, the electrically isolating element is disposed between the shaft and the carrier plate. In some embodiments, the electrically isolating element is disposed within the shaft and/or within the carrier platter.
The present disclosure provides a semiconductor apparatus including a driving mechanism, a wafer pedestal, an electrically isolating device, and a plasma device. The driving mechanism is coupled to a ground voltage. The wafer base is arranged on the driving mechanism. The wafer base comprises a plurality of accommodating grooves for accommodating a plurality of wafers. The electrically isolated element is arranged on the wafer pedestal to inhibit the charge flow between the wafer and the grounding voltage.
In some embodiments, the plasma device includes a first electrode plate, a second electrode plate, and a radio frequency device. The first electrode plate is arranged above one of the accommodating grooves. The second electrode plate is arranged above the first electrode plate. The radio frequency device is coupled to the second electrode plate and used for generating an electric field between the first electrode plate and the second electrode plate.
In some embodiments, the plasma apparatus further comprises a plasma gas distribution device and a plasma gas supply device. The plasma gas distribution device is arranged on the second electrode plate. The gas supply device provides a processing gas to the plasma gas distribution device. The processing gas flows between the first electrode plate and the second electrode plate through the plasma gas distribution device, and plasma is formed between the first electrode plate and the second electrode plate.
The above-disclosed features may be combined, modified, replaced, or interchanged with one or more of the disclosed embodiments in any suitable manner and are not limited to a particular embodiment.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. Therefore, the above embodiments are not intended to limit the scope of the present invention, which is defined by the appended claims.
Claims (9)
1. A wafer carrier comprising:
a driving mechanism coupled to a ground voltage;
a wafer base, which is arranged on the driving mechanism and comprises a containing groove for placing a wafer; and
and the plurality of spacing lugs are arranged on the surface of the electrically isolating element far away from the bottom surface of the accommodating groove and are used for contacting the lower surface of the wafer.
2. The wafer carrier of claim 1, wherein the wafer pedestal further comprises:
a shaft part arranged on the driving mechanism; and
the bearing disc is arranged on the shaft part and comprises the accommodating groove.
3. A wafer carrier comprising:
a driving mechanism coupled to a ground voltage;
a wafer base, which is arranged on the driving mechanism and comprises a containing groove for placing a wafer; and
and the electrical isolation element is arranged on the wafer base to inhibit the charge flow between the wafer and the grounding voltage, wherein the wafer base comprises a plurality of interval lugs which are arranged on the bottom surface of the containing groove, and the electrical isolation element is arranged on the plurality of interval lugs.
4. The wafer carrier of claim 3, wherein the wafer pedestal further comprises:
a shaft part arranged on the driving mechanism; and
the bearing disc is arranged on the shaft part and comprises the accommodating groove.
5. The wafer carrier of claim 4, wherein the electrically isolating element is disposed between the shaft and the susceptor.
6. The wafer carrier of claim 4, wherein the electrically isolated elements are disposed within the shaft and/or within the susceptor.
7. A semiconductor device, comprising:
a driving mechanism coupled to a ground voltage;
the wafer base is arranged on the driving mechanism and comprises a plurality of accommodating grooves and a plurality of spaced lugs, the accommodating grooves are used for accommodating a plurality of wafers, and the spaced lugs are arranged on the bottom surfaces of the accommodating grooves;
an electrically isolated element disposed on the plurality of spaced bumps of the wafer pedestal to inhibit charge flow between the wafer and the ground voltage; and
and the plasma device is arranged above the driving mechanism or the wafer base.
8. The semiconductor apparatus of claim 7, wherein the plasma device comprises:
the first electrode plate is arranged above one of the accommodating grooves;
the second electrode plate is arranged above the first electrode plate; and
and the radio frequency device is coupled with the second electrode plate and used for generating an electric field between the first electrode plate and the second electrode plate.
9. The semiconductor apparatus of claim 8, wherein the plasma device further comprises:
a plasma gas distribution device arranged on the second electrode plate; and
a plasma gas supply device for supplying a process gas to the plasma gas distribution device,
wherein the processing gas flows between the first electrode plate and the second electrode plate through the plasma gas distribution device, and forms plasma between the first electrode plate and the second electrode plate.
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