CN116960187A - N-type diamond transverse MOSFET device and preparation process thereof - Google Patents
N-type diamond transverse MOSFET device and preparation process thereof Download PDFInfo
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- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 79
- 239000010432 diamond Substances 0.000 title claims abstract description 79
- 238000002360 preparation method Methods 0.000 title abstract description 18
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 56
- 230000004888 barrier function Effects 0.000 claims description 45
- 238000000151 deposition Methods 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 8
- 230000003197 catalytic effect Effects 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910001020 Au alloy Inorganic materials 0.000 claims description 5
- 239000003353 gold alloy Substances 0.000 claims description 5
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 2
- 239000012212 insulator Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 16
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 abstract description 12
- 238000006555 catalytic reaction Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention discloses an N-type diamond transverse MOSFET device and a preparation process thereof, and relates to the technical field of semiconductor power devices, wherein the device comprises three layers of regions from top to bottom, and the three layers of regions specifically comprise the following parts: a source metal layer, a high-K gate insulating layer and a gate metal layer and a drain metal layer above the source metal layer and the high-K gate insulating layer in the upper layer region; a source graphene layer, a channel region and a drain graphene layer in the middle layer region; a diamond insulating substrate in the underlying region. According to the N-type diamond transverse MOSFET device and the preparation process thereof, the graphene layer of the device is manufactured through catalysis, means such as ion implantation are not needed, material damage is reduced, and the N-type diamond transverse MOSFET device is compatible with diamond materials, so that the electron mobility is high, and the resistance is small; the high-K dielectric hafnium dioxide is adopted as the gate insulating medium of the device, the thickness of the gate insulating medium is increased, the gate leakage is reduced, the probability of the leakage is extremely low due to the diamond insulating substrate, the device characteristics are only affected by the structure, and the non-ideal effect is small.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to an N-type diamond transverse MOSFET device and a preparation process thereof.
Background
Diamond is widely focused and studied as an ultra-wide band gap semiconductor, and has excellent electrical performance, voltage withstanding property and heat conducting property. Diamond devices are now mainly focused on the area of longitudinal power device research, but there is not much research and development in the area of lateral power device research.
Based on the discussion above, we can exploit the excellent physical properties of diamond to develop lateral power devices that are compatible with the properties of diamond materials.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides an N-type diamond transverse MOSFET device and a preparation process thereof, so as to solve the problems in the prior art.
In order to achieve the above purpose, the present invention provides the following technical solutions: the N-type diamond transverse MOSFET device comprises three layers of regions from top to bottom, wherein the three layers of regions specifically comprise the following components:
a source metal layer, a high-K gate insulating layer and a gate metal layer and a drain metal layer above the source metal layer and the high-K gate insulating layer in the upper layer region;
a source graphene layer, a channel region and a drain graphene layer in the middle layer region;
a diamond insulating substrate in the underlying region.
Further optimizing the technical scheme, the N-type diamond transverse MOSFET device is a transverse power device, and the source electrode and the drain electrode of the device are completely symmetrical and are used for device position change.
According to the technical scheme, an active area of the N-type diamond transverse MOSFET device is a graphene layer, and the preparation process of the graphene layer is compatible with diamond materials and is used for guaranteeing the characteristics of high electron mobility and small resistance of the device.
The preparation process of the N-type diamond transverse MOSFET device is based on the preparation of the N-type diamond transverse MOSFET device and comprises the following specific operation steps:
s1, a first barrier layer is deposited above a diamond insulating substrate through chemical vapor deposition, photoresist is smeared on the first barrier layer, the photoresist at the exposed position is removed through a photoresist solution by exposing a first through hole part of the photoresist, and then the first barrier layer is etched, so that a first through hole is formed;
s2, removing the first barrier layer and the photoresist, depositing a second barrier layer on the diamond insulating substrate through chemical vapor deposition, smearing the photoresist on the second barrier layer, exposing the second through hole part of the photoresist, and removing the photoresist at the exposed part by using a photoresist solution to etch the second barrier layer so as to form a second through hole;
s3, depositing a source electrode metal region and a drain electrode metal region above the graphene layer, wherein the ratio of nickel to gold is 2:8-4:6;
s4, removing the second barrier layer and the photoresist, depositing a third barrier layer on the diamond insulating substrate through chemical vapor deposition, smearing the photoresist on the third barrier layer, exposing the third through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution, and then etching the third barrier layer to form a third through hole;
s5, removing the third barrier layer and the photoresist, depositing a fourth barrier layer on the diamond insulating substrate through chemical vapor deposition, smearing the photoresist on the fourth barrier layer, exposing the fourth through hole part of the photoresist, and removing the photoresist at the exposed part by using a photoresist solution to etch the fourth barrier layer so as to form a fourth through hole.
Further optimizing the technical scheme, in the step S1, the method further comprises the step of carrying out boron or aluminum ion implantation on the diamond insulating substrate through the region of the first through hole to form a p-type doped channel region, wherein the doping concentration range of the channel region is 2 multiplied by 10 16 cm -3 -6×10 16 cm -3 。
Further optimizing the technical scheme, in the step S2, a graphene catalytic layer is deposited above the second through hole, wherein the graphene catalytic layer can be nickel or copper;
and annealing at high temperature for 2-5 min at 1000-1200 deg.C for catalyzing source and drain active regions to form graphene and completing activation of p-type impurity doped in channel region.
In the step S3, the metal is nickel-gold alloy, and the proportion of nickel and gold in the nickel-gold alloy is 2:8-4:6.
Further optimizing the technical scheme, in the step S4, the method further comprises the step of depositing a hafnium dioxide high-K gate insulating layer above the third through hole, wherein the hafnium dioxide high-K gate insulating layer is used for increasing the thickness of a gate insulating medium and reducing gate leakage.
Further optimizing the technical scheme, in the step S5, the method further comprises depositing a gate metal over the fourth through hole, wherein the gate metal is copper, so as to reduce the cost of the device.
Compared with the prior art, the invention provides an N-type diamond transverse MOSFET device and a preparation process thereof, and the N-type diamond transverse MOSFET device has the following beneficial effects:
1. according to the N-type diamond transverse MOSFET device and the preparation process thereof, the graphene layer of the device is manufactured through catalysis, means such as ion implantation are not needed, material damage is reduced, and the N-type diamond transverse MOSFET device is compatible with diamond materials, so that electron mobility is high, and resistance is small.
2. According to the N-type diamond transverse MOSFET device and the preparation process thereof, the high-K dielectric hafnium dioxide is adopted as the gate insulating medium of the device, so that the thickness of the gate insulating medium can be increased, the gate leakage is reduced, meanwhile, the diamond insulating substrate enables the leakage probability to be extremely small, the device characteristics are only influenced by the structure, and the non-ideal effect is small.
Drawings
Fig. 1 is a schematic cross-sectional view of an N-type diamond lateral MOSFET device according to the present invention;
fig. 2 is a schematic cross-sectional view of a device for a first through-hole operation in a process for fabricating an N-type diamond lateral MOSFET device according to the present invention;
fig. 3 is a schematic cross-sectional view of a device for a second via operation in a process for fabricating an N-type diamond lateral MOSFET device according to the present invention;
fig. 4 is a schematic cross-sectional view of a device for a third via operation in a process for fabricating an N-type diamond lateral MOSFET device according to the present invention;
fig. 5 is a schematic cross-sectional view of a device for a fourth hole through operation in a process for fabricating an N-type diamond lateral MOSFET device according to the present invention.
In the figure: 1. a gate metal; 2. a source metal layer; 3. a drain metal layer; 4. a high-K gate insulating layer; 5. a channel region; 6. a graphene layer; 7. a diamond insulating substrate; 8. and a graphene catalytic layer.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Examples:
referring to fig. 1, an N-type diamond lateral MOSFET device is a lateral power device, and the source and the drain of the device are completely symmetrical, so that the device is used for changing the position, and the application convenience of the device is improved.
The device comprises three areas from top to bottom, wherein the three areas specifically comprise the following components:
a source metal layer 2, a high-K gate insulating layer 4, and a gate metal 1 and a drain metal layer 3 above the upper layer region.
By adopting the high-K dielectric hafnium oxide as the gate insulating medium of the device, the thickness of the gate insulating medium can be increased, and the gate leakage can be reduced. Replacement of conventional SiO with high K dielectric materials 2 The method is applied to the CMOS device, and can effectively reduce the leakage current of the gate.
A source graphene layer in the middle layer region, a channel region 5 and a drain graphene layer.
A diamond insulating substrate 7 in the lower region.
In this embodiment, the diamond insulating substrate 7 makes the leakage probability extremely small, the device characteristics are affected only by the structure, and the non-ideal effect is small. Meanwhile, the diamond material is adopted, so that the heat conduction property is good, and the heat dissipation property of the device is good.
In this embodiment, the active area of the N-type diamond lateral MOSFET device is a graphene layer 6, and the preparation process of the graphene layer 6 is compatible with diamond materials, so as to ensure the characteristics of high electron mobility and small resistance of the device.
The graphene layer 6 of the device is manufactured through catalysis, means such as ion implantation are not needed, material damage is reduced, and the graphene layer is compatible with diamond materials, so that electron mobility is high, and resistance is small.
The preparation process of the N-type diamond transverse MOSFET device is based on the preparation of the N-type diamond transverse MOSFET device and comprises the following specific operation steps:
s1, as shown in FIG. 2, a first barrier layer is deposited on the diamond insulating substrate 7 through chemical vapor deposition, photoresist is smeared on the first barrier layer, the photoresist at the exposed position is removed through exposure of a first through hole part of the photoresist, and then the first barrier layer is etched through a photoetching solution, so that a first through hole is formed.
In the present embodiment, the diamond insulating substrate 7 is subjected to boron or aluminum ion implantation through the region of the first via hole to form the p-type doped channel region 5, and the doping concentration of the channel region 5 is in the range of 2×10 16 cm -3 -6×10 16 cm -3 。
S2, as shown in FIG. 3, removing the first barrier layer and the photoresist, depositing a second barrier layer on the diamond insulating substrate 7 by chemical vapor deposition, smearing the photoresist on the second barrier layer, exposing the second through hole part of the photoresist, and removing the photoresist at the exposed part by using a photoresist solution to etch the second barrier layer, thereby forming a second through hole.
In this embodiment, a graphene catalytic layer 8 is deposited over the second through hole, where the graphene catalytic layer 8 may be nickel or copper.
And annealing at high temperature for 2-5 min at 1000-1200 deg.c to catalyze the source and drain active regions to form graphene and complete the activation of p-type impurity doped in the channel region 5.
And S3, depositing a source electrode metal region and a drain electrode metal region above the graphene layer 6, wherein the metal is nickel-gold alloy, and the proportion of nickel to gold is 2:8-4:6.
And S4, removing the second barrier layer and the photoresist, depositing a third barrier layer on the diamond insulating substrate 7 through chemical vapor deposition, smearing the photoresist on the third barrier layer, exposing the third through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution, and then etching the third barrier layer to form a third through hole.
In this embodiment, a hafnium oxide high-K gate insulating layer 4 is deposited over the third via hole to increase the gate dielectric thickness and reduce gate leakage.
And S5, removing the third barrier layer and the photoresist, depositing a fourth barrier layer on the diamond insulating substrate 7 through chemical vapor deposition, smearing the photoresist on the fourth barrier layer, exposing the fourth through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution, and then etching the fourth barrier layer to form a fourth through hole.
In this embodiment, a gate metal 1 is deposited over the fourth via, where the gate metal 1 is copper for reducing device cost.
In conclusion, according to the N-type diamond transverse MOSFET device and the preparation process thereof, the graphene layer 6 of the device is manufactured through catalysis, means such as ion implantation are not needed, material damage is reduced, and the N-type diamond transverse MOSFET device is compatible with diamond materials, so that the electron mobility is high, and the resistance is small; by adopting the high-K dielectric hafnium dioxide as the gate insulating medium of the device, the thickness of the gate insulating medium can be increased, the gate leakage is reduced, meanwhile, the diamond insulating substrate 7 enables the leakage probability to be extremely small, the device characteristics are only affected by the structure, and the non-ideal effect is small.
The beneficial effects of the invention are as follows:
1. according to the N-type diamond transverse MOSFET device and the preparation process thereof, the graphene layer of the device is manufactured through catalysis, means such as ion implantation are not needed, material damage is reduced, and the N-type diamond transverse MOSFET device is compatible with diamond materials, so that electron mobility is high, and resistance is small.
2. According to the N-type diamond transverse MOSFET device and the preparation process thereof, the high-K dielectric hafnium dioxide is adopted as the gate insulating medium of the device, so that the thickness of the gate insulating medium can be increased, the gate leakage is reduced, meanwhile, the diamond insulating substrate enables the leakage probability to be extremely small, the device characteristics are only influenced by the structure, and the non-ideal effect is small.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. The N-type diamond transverse MOSFET device is characterized by comprising three layers of regions from top to bottom, wherein the three layers of regions specifically comprise the following components:
a source metal layer, a high-K gate insulating layer and a gate metal layer and a drain metal layer above the source metal layer and the high-K gate insulating layer in the upper layer region;
a source graphene layer, a channel region and a drain graphene layer in the middle layer region;
a diamond insulating substrate in the underlying region.
2. An N-type diamond lateral MOSFET device according to claim 1, wherein the N-type diamond lateral MOSFET device is a lateral power device, the source and drain of the device being fully symmetrical for device repositioning.
3. The N-type diamond lateral MOSFET device of claim 1, wherein an active area of the N-type diamond lateral MOSFET device is a graphene layer.
4. A process for preparing an N-type diamond lateral MOSFET device, based on the N-type diamond lateral MOSFET device of any one of claims 1-3, comprising the following specific operation steps:
s1, a first barrier layer is deposited above a diamond insulating substrate through chemical vapor deposition, photoresist is smeared on the first barrier layer, the photoresist at the exposed position is removed through a photoresist solution by exposing a first through hole part of the photoresist, and then the first barrier layer is etched, so that a first through hole is formed;
s2, removing the first barrier layer and the photoresist, depositing a second barrier layer on the diamond insulating substrate through chemical vapor deposition, smearing the photoresist on the second barrier layer, exposing the second through hole part of the photoresist, and removing the photoresist at the exposed part by using a photoresist solution to etch the second barrier layer so as to form a second through hole;
s3, depositing a source electrode metal region and a drain electrode metal region above the graphene layer;
s4, removing the second barrier layer and the photoresist, depositing a third barrier layer on the diamond insulating substrate through chemical vapor deposition, smearing the photoresist on the third barrier layer, exposing the third through hole part of the photoresist, removing the photoresist at the exposed part by using a photoresist solution, and then etching the third barrier layer to form a third through hole;
s5, removing the third barrier layer and the photoresist, depositing a fourth barrier layer on the diamond insulating substrate through chemical vapor deposition, smearing the photoresist on the fourth barrier layer, exposing the fourth through hole part of the photoresist, and removing the photoresist at the exposed part by using a photoresist solution to etch the fourth barrier layer so as to form a fourth through hole.
5. According to claimThe process for preparing an N-type diamond lateral MOSFET device as described in 4, wherein in the step S1, boron or aluminum ion implantation is performed on the diamond insulating substrate through the region of the first through hole to form a p-type doped channel region, and the doping concentration range of the channel region is 2×10 16 cm -3 -6×10 16 cm -3 。
6. The process for fabricating an N-type diamond lateral MOSFET device according to claim 5, wherein in step S2, a graphene catalytic layer is deposited over the second through hole, and the graphene catalytic layer is nickel or copper;
and annealing at high temperature for 2-5 min at 1000-1200 deg.C for catalyzing source and drain active regions to form graphene and completing activation of p-type impurity doped in channel region.
7. The process for fabricating an N-type diamond lateral MOSFET device according to claim 4, wherein in step S3, the metal is a nickel-gold alloy, and the ratio of nickel to gold in the nickel-gold alloy is in the range of 2:8-4:6.
8. The process for fabricating an N-type diamond lateral MOSFET device of claim 4, further comprising depositing a hafnium oxide high K gate insulator layer over the third via in step S4.
9. The process of claim 4, wherein in step S5, a gate metal is deposited over the fourth via, and the gate metal is copper.
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| CN102479819A (en) * | 2010-11-30 | 2012-05-30 | 中国科学院微电子研究所 | Field effect transistor and preparation method thereof |
| CN103000669A (en) * | 2011-09-09 | 2013-03-27 | 中国科学院微电子研究所 | Source-drain buried graphene transistor device on diamond-like carbon substrate and manufacturing method |
| WO2013038130A1 (en) * | 2011-09-14 | 2013-03-21 | Aberystwyth University | Method for producing graphene |
| CN103915338A (en) * | 2014-03-21 | 2014-07-09 | 中国电子科技集团公司第十三研究所 | Method for manufacturing diamond device |
| CN106783558A (en) * | 2016-12-16 | 2017-05-31 | 中国电子科技集团公司第五十五研究所 | A kind of low on-resistance hydrogen terminal diamond field effect transistor and preparation method thereof |
| CN110071044A (en) * | 2018-01-23 | 2019-07-30 | 清华大学 | The preparation method and field-effect tube of field-effect tube |
| CN109273354A (en) * | 2018-09-07 | 2019-01-25 | 中国电子科技集团公司第十三研究所 | Diamond device and preparation method thereof |
| CN113013246A (en) * | 2019-12-19 | 2021-06-22 | 台湾积体电路制造股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| US20220123134A1 (en) * | 2020-10-21 | 2022-04-21 | IceMos Technology Limited | Semiconductor Device and Method of Forming Low Voltage Power Mosfets Using Graphene for Metal Layers and Graphene Nanoribbons for Channel and Drain Enhancement Regions of Power Vertical and Lateral Mosfets on substrates of Silicon, GAN, SIC, or Diamond to Integrate Narrow Band Gap Engineering with Wide Band Gap Engineering and Achieve Energy Saving Devices and Environmental Progress in the Power Semiconductor Industry |
| JP2022115197A (en) * | 2021-01-28 | 2022-08-09 | 富士通株式会社 | Electronic device, manufacturing method thereof, and electronic equipment |
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