CN116959975A - Preparation method of silicon mesa deep groove structure - Google Patents
Preparation method of silicon mesa deep groove structure Download PDFInfo
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- CN116959975A CN116959975A CN202310784539.XA CN202310784539A CN116959975A CN 116959975 A CN116959975 A CN 116959975A CN 202310784539 A CN202310784539 A CN 202310784539A CN 116959975 A CN116959975 A CN 116959975A
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- silicon
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- etching
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 94
- 239000010703 silicon Substances 0.000 title claims abstract description 94
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 92
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 69
- 230000007797 corrosion Effects 0.000 claims abstract description 43
- 238000005260 corrosion Methods 0.000 claims abstract description 43
- 230000000873 masking effect Effects 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000001259 photo etching Methods 0.000 claims abstract description 14
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- 229910017604 nitric acid Inorganic materials 0.000 claims description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001035 drying Methods 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 101000580353 Rhea americana Rheacalcin-1 Proteins 0.000 description 1
- 101000580354 Rhea americana Rheacalcin-2 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
The invention discloses a preparation method of a silicon mesa deep groove structure, which comprises the following steps: sequentially forming a silicon oxide film and a silicon nitride film on the surface of the cleaned silicon wafer, wherein the silicon oxide film and the silicon nitride film form a deep groove corrosion masking film; carrying out a photoetching process on the silicon wafer with the deep groove corrosion masking film to define a deep groove structure area; removing the deep groove corrosion masking film of the deep groove structure region through an etching process; baking the silicon wafer from which the deep groove corrosion masking film of the deep groove structure area is removed; etching the silicon groove of the baked silicon wafer; and etching the deep groove corrosion masking film outside the deep groove structure area of the silicon wafer after the silicon groove corrosion to obtain a silicon mesa deep groove structure. The invention ensures that the silicon groove has complete structure and no peak burr phenomenon.
Description
Technical Field
The invention belongs to the technical field of silicon corrosion, and particularly relates to a preparation method of a silicon mesa deep groove structure.
Background
The silicon corrosion technology is widely applied to the manufacturing process of discrete devices, and the mature and reliable silicon mesa groove forming process is a guarantee that a semiconductor discrete device chip has excellent high-temperature and high-voltage performance and high reliability. Chinese patent publication No. CN 106783576a, publication date is 2017, 5 and 31, and the name of the process for secondary etching of a high voltage semiconductor discrete device chip is "a method for etching a silicon trench by using an oxide layer as a masking layer. The method has the characteristics that a physical buffer area is formed at the joint of the V-shaped groove table surfaces, so that the high temperature, the high pressure and the high reliability of discrete devices are ensured, but the method has the following defects: the process is complex, the silicon is realized through multiple photoetching processes, in addition, because the silicon groove etching liquid has the etching property on the silicon oxide layer, the silicon groove depth which can be realized by using the silicon oxide as the silicon etching masking layer is limited and is generally not more than 100um deep, otherwise, the silicon mesa structure is incomplete and is accompanied with a peak burr phenomenon, so that the high pressure resistance of the device is affected.
Disclosure of Invention
The invention solves the technical problems that: overcomes the defects of the prior art, and provides a preparation method of a silicon mesa deep groove structure, so that the silicon groove structure is complete and has no peak burr phenomenon.
The invention aims at realizing the following technical scheme: a preparation method of a silicon mesa deep groove structure comprises the following steps: sequentially forming a silicon oxide film and a silicon nitride film on the surface of the cleaned silicon wafer, wherein the silicon oxide film and the silicon nitride film form a deep groove corrosion masking film; carrying out a photoetching process on the silicon wafer with the deep groove corrosion masking film to define a deep groove structure area; removing the deep groove corrosion masking film of the deep groove structure region through an etching process; baking the silicon wafer from which the deep groove corrosion masking film of the deep groove structure area is removed; etching the silicon groove of the baked silicon wafer; and etching the deep groove corrosion masking film outside the deep groove structure area of the silicon wafer after the silicon groove corrosion to obtain a silicon mesa deep groove structure.
In the preparation method of the silicon mesa deep groove structure, the cleaned silicon wafer is put into an oxidation furnace for silicon oxide growth, and the thickness of a silicon oxide film is 50+/-5 nm.
In the preparation method of the silicon mesa deep groove structure, a silicon wafer with a silicon oxide film is placed into low-pressure chemical vapor deposition equipment to deposit a silicon nitride film, and the thickness of the silicon nitride film is 100+/-10 nm.
In the preparation method of the silicon mesa deep groove structure, ultraviolet negative photoresist is adopted in the photoetching process, and the line width of the deep groove structure region of the photoetching process is more than or equal to 10um.
In the preparation method of the silicon mesa deep groove structure, CF4 is adopted as process gas in the etching process, and the etching rate of the deep groove corrosion masking film is 200+/-20 nm/min.
In the preparation method of the silicon mesa deep groove structure, a baking process is carried out in an oven, and the baking temperature is 120 ℃ and the time is 20min.
In the preparation method of the silicon mesa deep groove structure, in the silicon groove corrosion, the corrosive liquid comprises HNO3, HF and HAC; wherein, the volume ratio of HNO3, HF and HAC is 15:9:5.
in the preparation method of the silicon mesa deep groove structure, the concentration of HNO3 is 70%, the concentration of HF is 40%, and the concentration of HAC is not less than 99.7%.
In the preparation method of the silicon mesa deep groove structure, the process temperature is-10-0 ℃ in the silicon groove corrosion.
In the preparation method of the silicon mesa deep groove structure, the BOE corrosive liquid is adopted to corrode the deep groove corrosion masking film at normal temperature.
Compared with the prior art, the invention has the following beneficial effects:
(1) The masking layer adopts a silicon oxide and silicon nitride double-layer process, so that the corrosion resistance of the masking layer in silicon corrosion is improved, and compared with the single-layer silicon oxide serving as the masking layer, the masking layer has obvious advantages;
(2) The invention only needs to carry out one-time photoetching process, the process flow steps are simpler and easy to realize, and the cost is reduced;
(3) The influence of the stress of the masking layer on the corrosion effect is released by adopting a baking process before the silicon groove is corroded, and the silicon groove has the advantages of good corrosion depth consistency, stable process and no peak burrs;
(4) The depth of the silicon groove can reach 150um, and the deeper groove has obvious effect on improving the high pressure resistance of the mesa discrete device.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
fig. 1 is a flowchart of a method for manufacturing a deep trench structure of a silicon mesa according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
Fig. 1 is a flowchart of a method for manufacturing a deep trench structure of a silicon mesa according to an embodiment of the present invention. As shown in fig. 1, the method comprises the steps of:
sequentially forming a silicon oxide film and a silicon nitride film on the surface of the cleaned silicon wafer, wherein the silicon oxide film and the silicon nitride film form a deep groove corrosion masking film;
carrying out a photoetching process on the silicon wafer with the deep groove corrosion masking film to define a deep groove structure area;
removing the deep groove corrosion masking film of the deep groove structure region through an etching process;
baking the silicon wafer from which the deep groove corrosion masking film of the deep groove structure area is removed;
etching the silicon groove of the baked silicon wafer;
and etching the deep groove corrosion masking film outside the deep groove structure area of the silicon wafer after the silicon groove corrosion to obtain a silicon mesa deep groove structure.
Specifically, the embodiment performs 6 main process steps, effectively forms a deep groove structure larger than 150um on a silicon material, has complete silicon groove structure and no peak burr phenomenon, and is applied to a high-voltage-resistant silicon mesa diode manufacturing process in the technical field of semiconductor process production.
(1) Cleaning the silicon wafer by using RCA-1, 1% HF and RCA-2 in sequence; loading the cleaned silicon wafer into an oxidation furnace for silicon oxide growth, wherein the thickness of the silicon oxide film is 50+/-5 nm; and (3) loading the silicon nitride film into low-pressure chemical vapor deposition equipment for deposition, wherein the thickness of the silicon nitride film is 100+/-10 nm.
(2) And (3) adopting ultraviolet negative photoresist, and using a contact type exposure machine to define a deep groove structure region by using a photoetching process on the silicon wafer, wherein the line width of the deep groove structure region of the photoetching process is more than or equal to 10um.
(3) And (3) carrying out an etching process on the wafer by using a plasma dry etching machine to remove the masking film of the deep groove structure region, wherein CF4 is adopted as process gas in the etching process, and the etching rate of the silicon nitride film and the silicon oxide film is 200+/-20 nm/min.
(4) And (3) baking in an oven at 120 ℃ for 20min.
(5) The wafer is subjected to a silicon groove etching process by adopting a wet silicon etching process, and the etching solution adopts HNO3 (70%) +HF (40%) +HAC (more than or equal to 99.7%) =15: 9:5 (volume ratio) and the process temperature is-10-0 ℃.
(6) Placing the wafer into negative photoresist stripping liquid, removing photoresist, taking out the wafer after the photoresist is removed, and spin-drying the wafer after pure water is flushed; placing the wafer into a room temperature BOE corrosive liquid to corrode the silicon nitride film and the silicon oxide film; and (5) rinsing with pure water and spin-drying.
The embodiment effectively forms a deep groove structure larger than 150um on the silicon material by only one photoetching process, has complete silicon groove structure and no peak burr phenomenon, and overcomes the defect that a corrosion area in the deep groove corrosion technology larger than 150um is easy to form peak burrs.
The masking layer of the embodiment adopts a double-layer process of silicon oxide and silicon nitride, so that the corrosion resistance of the masking layer in silicon corrosion is improved, and the masking layer has obvious advantages compared with a single-layer silicon oxide serving as the masking layer; the embodiment only needs to carry out one-time photoetching process, the process flow steps are simpler and easy to realize, and the cost is reduced; the influence of the stress of the masking layer on the corrosion effect is released by adopting a baking process before the silicon groove is corroded, and the silicon groove has the advantages of good corrosion depth consistency, stable process and no peak burrs; the depth of the silicon groove of the embodiment can reach 150um, and the deeper groove has obvious effect on improving the high pressure resistance of the mesa discrete device.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
Claims (10)
1. The preparation method of the silicon mesa deep groove structure is characterized by comprising the following steps:
sequentially forming a silicon oxide film and a silicon nitride film on the surface of the cleaned silicon wafer, wherein the silicon oxide film and the silicon nitride film form a deep groove corrosion masking film;
carrying out a photoetching process on the silicon wafer with the deep groove corrosion masking film to define a deep groove structure area;
removing the deep groove corrosion masking film of the deep groove structure region through an etching process;
baking the silicon wafer from which the deep groove corrosion masking film of the deep groove structure area is removed;
etching the silicon groove of the baked silicon wafer;
and etching the deep groove corrosion masking film outside the deep groove structure area of the silicon wafer after the silicon groove corrosion to obtain a silicon mesa deep groove structure.
2. The method for preparing the deep trench structure of the silicon mesa according to claim 1, wherein the method comprises the following steps: and loading the cleaned silicon wafer into an oxidation furnace for silicon oxide growth, wherein the thickness of a silicon oxide film is 50+/-5 nm.
3. The method for preparing the deep trench structure of the silicon mesa according to claim 2, wherein the method comprises the following steps: and (3) loading the silicon wafer with the silicon oxide film into low-pressure chemical vapor deposition equipment for depositing a silicon nitride film, wherein the thickness of the silicon nitride film is 100+/-10 nm.
4. The method for preparing the deep trench structure of the silicon mesa according to claim 1, wherein the method comprises the following steps: in the photoetching process, ultraviolet negative photoresist is adopted, and the line width of the deep groove structure region of the photoetching process is more than or equal to 10um.
5. The method for preparing the deep trench structure of the silicon mesa according to claim 1, wherein the method comprises the following steps: in the etching process, CF4 is used as process gas, and the etching rate of the deep groove corrosion masking film is 200+/-20 nm/min.
6. The method for preparing the deep trench structure of the silicon mesa according to claim 1, wherein the method comprises the following steps: and (3) baking in an oven at 120 ℃ for 20min.
7. The method for preparing the deep trench structure of the silicon mesa according to claim 1, wherein the method comprises the following steps: in silicon trench etching, etching liquid includes HNO3, HF, and HAC; wherein, the volume ratio of HNO3, HF and HAC is 15:9:5.
8. the method for preparing the deep trench structure of the silicon mesa of claim 7, wherein the method comprises the following steps: the HNO3 concentration is 70%, the HF concentration is 40%, and the HAC concentration is not less than 99.7%.
9. The method for preparing the deep trench structure of the silicon mesa of claim 7, wherein the method comprises the following steps: in the silicon groove corrosion, the process temperature is-10-0 ℃.
10. The method for preparing the deep trench structure of the silicon mesa according to claim 1, wherein the method comprises the following steps: and (3) adopting BOE corrosive liquid to corrode the deep groove corrosion masking film at normal temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310784539.XA CN116959975A (en) | 2023-06-29 | 2023-06-29 | Preparation method of silicon mesa deep groove structure |
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| CN202310784539.XA CN116959975A (en) | 2023-06-29 | 2023-06-29 | Preparation method of silicon mesa deep groove structure |
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| Publication Number | Publication Date |
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| CN116959975A true CN116959975A (en) | 2023-10-27 |
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| CN202310784539.XA Pending CN116959975A (en) | 2023-06-29 | 2023-06-29 | Preparation method of silicon mesa deep groove structure |
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