CN116941034A

CN116941034A - Lead frame and method for manufacturing the same

Info

Publication number: CN116941034A
Application number: CN202280017475.4A
Authority: CN
Inventors: 永田昌博; 篠崎和广; 山田雅宏; 奥山大辅; 初田千秋; 关谦太朗; 松井秀人; 大内一范
Original assignee: Dai Nippon Printing Co Ltd
Current assignee: Dai Nippon Printing Co Ltd
Priority date: 2021-09-03
Filing date: 2022-09-01
Publication date: 2023-10-24
Also published as: CN117766503A

Abstract

Lead frame (100)) Comprises a plurality of lead parts (110), at least a part of the upper surface of the lead parts (110) and the side wall surfaces of the lead parts (110) are roughened surfaces, the roughened surfaces are a in CIELab color space ^* A value in the range of 12 to 19, b ^* The value is in the range of 12 to 17.

Description

Lead frame and method for manufacturing the same

Technical Field

The present disclosure relates to a lead frame and a method of manufacturing the same.

Background

In recent years, miniaturization and thinning of semiconductor devices mounted on a substrate have been demanded. In order to cope with such a demand, various semiconductor devices of the so-called QFN (Quad Flat Non-leaded package) type have been proposed. The QFN type semiconductor device is configured such that a semiconductor element mounted on a mounting surface of a lead frame is sealed with a sealing resin, and a part of a lead is exposed on a back surface side.

Conventionally, a flip-chip semiconductor device is known (see patent document 1). In the flip-chip type semiconductor device, when a semiconductor element is mounted on a mounting substrate, the semiconductor element and the mounting substrate are connected to each other by bumps.

Prior art literature

Patent literature

Patent document 1: japanese patent laid-open No. 2002-110849

Patent document 2: japanese patent application laid-open No. 2019-40994

In general, in a flip-chip semiconductor device, a distance from an outer periphery of the semiconductor device to an electrode of a semiconductor element, that is, a path through which moisture contained in external air (air) can enter is easily shortened. Therefore, moisture in the air may be immersed in the electrode of the semiconductor element from the outer periphery of the semiconductor device.

In addition, conventionally, in the case of manufacturing a semiconductor package for mounting on a vehicle or requiring high reliability, a semiconductor element is mounted on a die pad using a die attach film. In recent years, in such a semiconductor package, a cheaper die attach paste has been used also when mounting a semiconductor element on a die pad.

However, conventionally, when a die attach paste is applied to a die pad and a semiconductor device is mounted thereon and then cured by heating, a phenomenon (bleeding) of an epoxy resin component in the die attach paste occurs due to capillary phenomenon (see patent document 2).

The present embodiment provides a lead frame and a method for manufacturing the same, which can manufacture a semiconductor device as follows: the semiconductor device can inhibit moisture in air from penetrating into the electrode of the semiconductor element.

The present embodiment provides a lead frame and a method for manufacturing the same: the bump and the lead frame can be connected well, and intrusion of moisture from the outer periphery of the semiconductor device toward the electrode of the semiconductor element can be suppressed.

The present embodiment provides a lead frame and a method for manufacturing the same: the lead frame formed with the roughened surface can be manufactured at low cost.

The present embodiment provides a lead frame capable of suppressing intrusion of moisture from an outer periphery of a semiconductor device toward an electrode of a semiconductor element, and a method for manufacturing the lead frame.

The present embodiment provides a lead frame and a method for manufacturing the same, which can suppress the penetration of moisture from the outer periphery of a semiconductor device toward an electrode of a semiconductor element while suppressing the penetration of moisture.

Disclosure of Invention

Embodiments of the present disclosure relate to [1] to [51] below.

[1]A lead frame, wherein the lead frame is provided with a plurality of lead parts, at least a part of the upper surfaces of the lead parts and the side wall surfaces of the lead parts are roughened surfaces, and the roughened surfaces are a in a CIELab color space ^* A value in the range of 12 to 19, b ^* The value is in the range of 12 to 17.

[2]A lead frame comprising a plurality of lead portions, wherein at least a part of the upper surface of the lead portions and the side wall surfaces of the lead portions are roughened surfaces, and the arithmetic average curvature Spc of the peak peaks of the roughened surfaces is 700mm ^-1 The above.

[3] The lead frame according to [2], wherein an arithmetic average height Sa of the roughened surface is 0.12 μm or more.

[4] The lead frame according to any one of [1] to [3], wherein a part of an upper surface of the lead portion and a side wall surface of the lead portion are the roughened surfaces, and a metal plating layer is provided on a surface other than the roughened surface of the upper surface of the lead portion.

[5] The lead frame according to [4], wherein the metal plating layer includes at least one of Ag plating layer, ni plating layer, pd plating layer, and Au plating layer.

[6] The lead frame according to any one of [1] to [5], wherein the lead portion includes an inner lead portion thinned from a lower surface side of the lead portion, and a lower surface of the inner lead portion is the roughened surface.

[7] The lead frame according to any one of [1] to [5], wherein the lead frame further comprises a die pad on which a semiconductor element is mounted, the plurality of lead portions are arranged around the die pad, and an upper surface of the die pad and a side wall surface of the die pad are the roughened surfaces.

[8] The lead frame according to any one of [1] to [7], wherein the lead frame is used for manufacturing a semiconductor device, the semiconductor device includes a sealing portion that seals at least the plurality of lead portions, and an upper surface of the lead portion and a side wall surface of the lead portion that are in contact with the sealing portion are roughened surfaces.

[9]A method of manufacturing a lead frame, wherein the method of manufacturing a lead frame comprises: a metal substrate preparation step of preparing a metal substrate having a 1 st surface and a 2 nd surface facing the 1 st surface; a metal substrate processing step of forming a plurality of lead portions by processing the metal substrate; and a rough surface forming step of roughening at least a part of an upper surface of the lead portion and a side wall surface of the lead portion to form a rough surface, wherein in the rough surface forming step, a in a CIELab color space is defined as the rough surface ^* A value of 12 to 19, b ^* The roughening is performed so that the value falls within the range of 12 to 17.

[10]A method of manufacturing a lead frame, wherein the method of manufacturing a lead frame comprises: a metal substrate preparation step of preparing a metal substrate having a 1 st surface and a 2 nd surface facing the 1 st surface; a metal substrate processing step of forming a plurality of lead portions by processing the metal substrate; and a rough surface forming step of forming a rough surface by roughening at least a part of an upper surface of the lead portion and a side wall surface of the lead portion, wherein in the rough surface forming step, an arithmetic average curvature Spc of a peak-to-peak point of the rough surface is 700mm ^-1 Roughening is performed in the above manner.

[11] The method of manufacturing a lead frame according to [10], wherein in the rough surface forming step, roughening is performed so that the arithmetic average height Sa of the rough surface becomes 0.12 μm or more.

[12] The method for manufacturing a lead frame according to any one of [9] to [11], wherein the lead portion is subjected to alkali treatment after the rough surface forming step.

[13] The method for manufacturing a lead frame according to any one of [9] to [12], wherein a metal plating layer is provided on a part of the upper surface of the lead portion, and the upper surface and the side wall surface of the lead portion where the metal plating layer is not provided are roughened in the roughened surface forming step.

[14] The method of manufacturing a lead frame according to [13], wherein the metal plating layer comprises at least one of an Ag plating layer, a Ni plating layer, a Pd plating layer, and an Au plating layer.

[15] The method for manufacturing a lead frame according to any one of [9] to [14], wherein in the metal substrate processing step, the lead portion including an inner lead portion thinned from a lower surface side of the lead portion is formed, and in the roughened surface forming step, the roughened surface is formed on a lower surface of the inner lead portion.

[16] The method for manufacturing a lead frame according to any one of [9] to [15], wherein in the metal substrate processing step, a die pad portion on which a semiconductor element is mounted is formed so that the plurality of lead portions are arranged around the die pad portion, and the rough surface forming step includes the steps of: the roughened surface is formed by roughening the upper surface of the chip carrier part, the side wall surface of the chip carrier part, at least a part of the upper surface of the lead part, and the side wall surface of the lead part.

[17] A lead frame, wherein the lead frame comprises: a chip holder for mounting the semiconductor element; and a lead portion located around the die pad, wherein a region having a smooth surface is formed on a front surface of the die pad or a front surface of the lead portion, and a region having a rough surface is formed so as to surround the entire periphery of the region having the smooth surface.

[18] The lead frame according to [17], wherein the roughened area is formed along the entire peripheral area of the die pad or the entire peripheral area of the lead portion in a plan view.

[19] The lead frame according to [17] or [18], wherein the lead portion has an inner lead thinned from a back surface side, an inner lead front surface is formed on a front surface side of the inner lead, an inner lead back surface is formed on a back surface side of the inner lead, an inner lead end surface is formed on a surface facing the die pad of the inner lead, an external terminal is formed at a portion of the back surface of the lead portion which is not thinned, the inner lead back surface and the inner lead end surface are roughened surfaces, and the external terminal is a smooth surface.

[20] The lead frame according to any one of [17] to [19], wherein a back surface of the die pad is a smooth surface, and a side surface of the die pad is a rough surface.

[21] The lead frame according to any one of [17] to [20], wherein the area of the smooth surface is circular, elliptical or oblong in plan view.

[22] The lead frame according to any one of [17] to [20], wherein the area of the smooth surface is square or rectangular in plan view.

[23] The lead frame according to any one of [17] to [20], wherein the region of the smooth surface is a closed pattern including a curve and a line segment in a plan view.

[24] The lead frame according to any one of [17] to [23], wherein a shortest distance between the region of the smooth surface and the peripheral edge of the die pad or the lead portion is 0.025mm or more and 1.0mm or less.

[25] The lead frame according to any one of [17] to [24], wherein the S-ratio of the roughened surface is 1.30 or more, and the S-ratio of the smooth surface is less than 1.30.

[26] A method for manufacturing a lead frame, wherein the method for manufacturing a lead frame comprises the steps of: preparing a metal substrate; a step of forming a die pad and a lead portion located around the die pad by etching the metal substrate; a step of forming a plating layer on a part of the metal substrate; a step of forming a roughened surface on a portion of the metal substrate that is not covered with the plating layer; and removing the plating layer, wherein a smooth surface area is formed on the front surface of the die pad or the front surface of the lead portion, and the rough surface area is present so as to surround the entire circumference of the smooth surface area.

[27] A method for manufacturing a lead frame, wherein the method for manufacturing a lead frame comprises the steps of: a step of preparing a metal substrate having a die pad and a lead portion located around the die pad; forming a plating layer on the outer periphery of the metal substrate except at least a part of the front surface; a step of leaving a plating layer present on at least the back surface of the metal substrate and removing the other plating layer; a step of forming a roughened surface on a portion of the metal substrate that is not covered with the plating layer; and removing the plating layer.

[28] The method of manufacturing a lead frame according to [27], wherein in the step of forming the plating layer, the plating layer is not formed over the entire area of the front surface of the metal substrate.

[29] The method of manufacturing a lead frame according to [27], wherein in the step of forming the plating layer, the plating layer is formed on a part of the front surface of the lead portion, and in the step of removing the other plating layer, the plating layer existing on the part of the front surface of the lead portion is left.

[30] The method of manufacturing a lead frame according to [29], wherein the method further comprises a step of forming a metal layer on a part of the front surface of the metal substrate after the step of removing the plating layer.

[31] The method for manufacturing a lead frame according to any one of [27] to [30], wherein the S-ratio of the roughened surface is 1.30 or more.

[32] A lead frame, wherein the lead frame comprises: a chip holder for mounting the semiconductor element; and a lead portion located around the die pad, the lead portion having an inner lead thinned from a back surface side, an inner lead front surface formed on a front surface side of the inner lead, an inner lead back surface formed on a back surface side of the inner lead, an inner lead end surface formed on a surface of the inner lead facing the die pad, an external terminal formed on a portion of the back surface of the lead portion which is not thinned, at least a portion of the inner lead front surface, the inner lead back surface, and the inner lead end surface being roughened, the external terminal being a smooth surface.

[33] The lead frame according to [32], wherein the entirety of the inner lead front surface is roughened.

[34] The lead frame according to [32], wherein a metal layer is formed on the inner lead front surface, and a portion of the inner lead front surface where the metal layer is formed becomes a smooth surface.

[35] A lead frame, wherein the lead frame comprises: a chip holder for mounting the semiconductor element; and a lead portion located around the die pad, wherein a portion of the lead portion is thinned from a back surface side, and a portion of the back surface of the lead portion, which is thinned, is roughened, and a portion of the back surface, which is not thinned, is smoothed.

[36] The lead frame according to [35], wherein a metal layer is provided on a front surface of the lead portion, a 1 st front surface portion adjacent to an outer side of the metal layer among the front surfaces of the lead portion is a smooth surface, and a 2 nd front surface portion adjacent to the outer side of the 1 st front surface portion is a rough surface.

[37] The lead frame according to [35], wherein a metal layer is provided on the front surface of the lead portion, a recess is formed on the outer side of the metal layer in the front surface of the lead portion, a 3 rd front surface portion adjacent to the outer side of the recess is roughened, and an inner surface of the recess is a smooth surface.

[38] The lead frame according to [35], wherein a metal layer is provided on the front surface of the lead portion, a recess is formed on the outer side of the metal layer in the front surface of the lead portion, a 3 rd front surface portion adjacent to the outer side of the recess is roughened, and an inner surface of the recess is roughened.

[39] The lead frame according to any one of [35] to [38], wherein the front surface and the back surface of the die pad are smooth surfaces, and the side surfaces of the die pad are rough surfaces, respectively.

[40] The lead frame according to any one of [35] to [39], wherein the lead portion has an inner lead thinned from a back surface side, an inner lead end surface is formed on a surface of the inner lead facing the die pad, and the inner lead end surface is roughened.

[41] The lead frame according to any one of [35] to [40], wherein the S-ratio of the roughened surface is 1.30 or more and the S-ratio of the smooth surface is less than 1.30.

[42] A method for manufacturing a lead frame, wherein the method for manufacturing a lead frame comprises the steps of: preparing a metal substrate; a step of forming a die pad and a lead portion located around the die pad by etching the metal substrate, wherein a part of the lead portion is thinned from a back surface side; forming a plating layer around the metal substrate; a step of removing a part of the plating layer existing in the rough surface forming region; a step of forming a roughened surface on a portion of the metal substrate that is not covered with the plating layer; and removing the plating layer, wherein the thinned portion of the back surface of the lead portion is roughened and the portion not thinned is smoothed.

[43] A lead frame, wherein the lead frame comprises: a chip holder for mounting the semiconductor element; and a lead portion located around the die pad, a 1 st rough surface being formed on at least a portion of a front surface of the die pad, a 2 nd rough surface being formed on at least a portion of a front surface of the lead portion, the 2 nd rough surface of the lead portion having a roughness greater than that of the 1 st rough surface of the die pad.

[44] The lead frame according to [43], wherein a 3 rd rough surface is formed on a side surface of the chip carrier, and a roughness of the 3 rd rough surface of the chip carrier is larger than a roughness of the 1 st rough surface of the chip carrier.

[45] The lead frame according to [43] or [44], wherein the lead portion has an inner lead thinned from a back surface side, an inner lead back surface is formed on the back surface side of the inner lead, a 4 th roughened surface is formed on the inner lead back surface, and a roughness of the 4 th roughened surface of the lead portion is larger than a roughness of the 1 st roughened surface of the die pad.

[46] The lead frame according to any one of [43] to [45], wherein the lead portion has an inner lead thinned from a back surface side, an inner lead end surface is formed on a surface facing the die pad of the inner lead, a 5 th roughened surface is formed on the inner lead end surface, and a roughness of the 5 th roughened surface of the lead portion is larger than a roughness of the 1 st roughened surface of the die pad.

[47] The lead frame according to any one of [43] to [46], wherein a region of a smooth surface is formed on a front surface of the lead portion.

[48] The lead frame according to [47], wherein a metal layer is formed in a region of the smooth surface.

[49] The lead frame according to [47], wherein an area of the smooth surface is exposed to the outside.

[50] The lead frame according to any one of [43] to [49], wherein the S-ratio of the 1 st roughened surface is 1.10 or more and less than 1.30, and the S-ratio of the 2 nd roughened surface is 1.30 or more and 2.30 or less.

[51] A method for manufacturing a lead frame, wherein the method for manufacturing a lead frame comprises the steps of: preparing a metal substrate; a step of forming a die pad and a lead portion located around the die pad by etching the metal substrate; forming a cover layer on the chip holder and the lead portion; a step of removing the cover layer existing on at least a part of the front surface of the chip carrier; forming a 1 st rough surface on a portion of the die pad not covered with the cover layer; a step of removing the cover layer existing on at least a part of the front surface of the lead portion; and forming a 2 nd rough surface on a portion of the lead portion not covered by the cover layer, the 2 nd rough surface of the lead portion having a roughness greater than a roughness of the 1 st rough surface of the die pad.

According to the present embodiment, such a semiconductor device can be manufactured: which can suppress the penetration of moisture in the air into the electrode of the semiconductor element.

According to the present embodiment, the bump and the lead frame can be connected well, and intrusion of moisture from the outer periphery of the semiconductor device toward the electrode of the semiconductor element can be suppressed.

According to the present embodiment, a lead frame having a roughened surface can be manufactured at low cost.

According to the present embodiment, intrusion of moisture from the outer periphery of the semiconductor device toward the electrode of the semiconductor element can be suppressed.

According to the present embodiment, the penetration of moisture from the outer periphery of the semiconductor device toward the electrode of the semiconductor element can be suppressed.

Drawings

Fig. 1 is a plan view showing a lead frame according to embodiment 1.

Fig. 2 is a partially cut end view of the lead frame of embodiment 1.

Fig. 3 is a plan view showing the semiconductor device of embodiment 1.

Fig. 4 is a partial cut end view of the semiconductor device of embodiment 1.

Fig. 5 is a partial cut end view of a semiconductor device according to a modification of embodiment 1.

Fig. 6A is a process diagram for explaining a method for manufacturing a lead frame according to embodiment 1.

Fig. 6B is a process diagram next to fig. 6A for explaining the method of manufacturing the lead frame according to embodiment 1.

Fig. 6C is a process diagram next to fig. 6B for explaining the method of manufacturing the lead frame according to embodiment 1.

Fig. 6D is a process diagram next to fig. 6C for explaining the method of manufacturing the lead frame according to embodiment 1.

Fig. 6E is a process diagram next to fig. 6D for explaining the method of manufacturing the lead frame according to embodiment 1.

Fig. 6F is a process diagram next to fig. 6E for explaining the method of manufacturing the lead frame according to embodiment 1.

Fig. 6G is a process diagram next to fig. 6F for explaining the method of manufacturing the lead frame according to embodiment 1.

Fig. 6H is a process diagram next to fig. 6G for explaining the method of manufacturing the lead frame according to embodiment 1.

Fig. 7A is a process diagram for explaining a method for manufacturing the semiconductor device according to embodiment 1.

Fig. 7B is a process flow diagram subsequent to fig. 7A for explaining a method of manufacturing the semiconductor device according to embodiment 1.

Fig. 7C is a process flow diagram subsequent to fig. 7B for explaining the method of manufacturing the semiconductor device according to embodiment 1.

Fig. 7D is a process flow diagram subsequent to fig. 7C for explaining the method of manufacturing the semiconductor device according to embodiment 1.

Fig. 8 is a plan view showing a lead frame according to embodiment 2.

Fig. 9 is a cross-sectional view (cross-sectional view along line IX-IX in fig. 8) showing a lead frame of embodiment 2.

Fig. 10 (a) and (b) are enlarged plan views showing the surface of the die pad and the surface of the lead portion, respectively.

Fig. 11 is a plan view showing the semiconductor device of embodiment 2.

Fig. 12 is a cross-sectional view (cross-sectional view along line XII-XII in fig. 11) showing the semiconductor device of embodiment 2.

Fig. 13 (a) and (b) are enlarged cross-sectional views showing the bump as the connecting portion, respectively.

Fig. 14 (a) - (i) are cross-sectional views showing a method of manufacturing a lead frame according to embodiment 2.

Fig. 15 (a) - (d) are cross-sectional views showing a method for manufacturing the semiconductor device of embodiment 2.

Fig. 16 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 2.

Fig. 17 (a) to (d) are enlarged plan views showing the surface of the chip carrier and the surface of the lead portion according to the modification of embodiment 2, respectively.

Fig. 18 is a plan view showing a lead frame according to embodiment 3.

Fig. 19 is a cross-sectional view (cross-sectional view along line XIX-XIX in fig. 18) showing the lead frame of embodiment 3.

Fig. 20 is a plan view showing the semiconductor device of embodiment 3.

Fig. 21 is a cross-sectional view showing the semiconductor device of embodiment 3 (a cross-sectional view taken along line XXI-XXI in fig. 20).

Fig. 22 is an enlarged cross-sectional view showing a bump as a connecting portion.

Fig. 23 (a) - (i) are cross-sectional views showing a method for manufacturing a lead frame according to embodiment 3.

Fig. 24 (a) - (d) are cross-sectional views showing a method for manufacturing the semiconductor device of embodiment 3.

Fig. 25 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 3.

Fig. 26 is a cross-sectional view showing a lead frame of embodiment 4.

Fig. 27 is a cross-sectional view showing the semiconductor device of embodiment 4.

Fig. 28 (a) - (j) are cross-sectional views showing a method of manufacturing a lead frame according to embodiment 4.

Fig. 29 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 4.

Fig. 30 is a plan view showing a lead frame according to embodiment 5.

Fig. 31 is a cross-sectional view showing the lead frame of embodiment 5 (cross-sectional view taken along line XXXI-XXXI in fig. 30).

Fig. 32 is a plan view showing the semiconductor device of embodiment 5.

Fig. 33 is a cross-sectional view showing the semiconductor device of embodiment 5 (a cross-sectional view taken along line XXXIII-XXXIII in fig. 32).

Fig. 34 is an enlarged cross-sectional view showing a bump as a connecting portion.

Fig. 35 (a) - (j) are cross-sectional views showing a method of manufacturing a lead frame according to embodiment 5.

Fig. 36 (a) - (d) are cross-sectional views showing a method for manufacturing the semiconductor device of embodiment 5.

Fig. 37 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 5.

Fig. 38 is a cross-sectional view showing a lead frame of embodiment 6.

Fig. 39 is a cross-sectional view showing the semiconductor device of embodiment 6.

Fig. 40 (a) - (j) are cross-sectional views showing a method of manufacturing a lead frame according to embodiment 6.

Fig. 41 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 6.

Fig. 42 is a cross-sectional view showing a lead frame of embodiment 7.

Fig. 43 is a cross-sectional view showing the semiconductor device of embodiment 7.

Fig. 44 (a) - (j) are cross-sectional views showing a method of manufacturing a lead frame according to embodiment 7.

Fig. 45 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 7.

Fig. 46 is a cross-sectional view showing a lead frame of embodiment 8.

Fig. 47 is a cross-sectional view showing the semiconductor device of embodiment 8.

Fig. 48 (a) - (j) are cross-sectional views showing a method for manufacturing a lead frame according to embodiment 8.

Fig. 49 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 8.

Fig. 50 is a plan view showing a lead frame according to embodiment 9.

Fig. 51 is a cross-sectional view (cross-sectional view along line LI-LI in fig. 50) showing a lead frame of embodiment 9.

Fig. 52 is a plan view showing the semiconductor device of embodiment 9.

Fig. 53 is a cross-sectional view showing the semiconductor device of embodiment 9 (a cross-sectional view taken along line LIII-LIII in fig. 52).

Fig. 54 (a) - (e) are cross-sectional views showing a method of manufacturing a lead frame according to embodiment 9.

Fig. 55 (a) - (h) are cross-sectional views showing a method of manufacturing a lead frame according to embodiment 9.

Fig. 56 (a) - (e) are cross-sectional views showing a method for manufacturing the semiconductor device of embodiment 9.

Fig. 57 is an enlarged partial cross-sectional view showing the semiconductor device of embodiment 9.

Fig. 58 is a cross-sectional view of a lead frame according to a modification of embodiment 9.

Detailed Description

(embodiment 1)

Embodiment 1 will be described below with reference to fig. 1 to 7D. Embodiments of the present disclosure will be described below with reference to the drawings. The drawings are schematic or conceptual, and the dimensions of the respective components, the ratio of the sizes of the components, and the like are not necessarily the same as in the actual case. In addition, even when the same components are shown, the sizes and ratios of the components may be different from each other according to the drawings. In the drawings attached to the present specification, the shape, scale, aspect ratio, and the like of each portion may be changed or exaggerated with respect to the actual object for easy understanding.

In the present specification and the like, the numerical range indicated by the term "to" refers to a range including the numerical values described before and after the term "to" as the lower limit value and the upper limit value. In the present specification and the like, terms such as "film", "sheet", "plate" and the like are not distinguished from each other by differences in terms of designation. For example, "plate" is a concept that also includes components that may be commonly referred to as "sheet", "film".

[ lead frame ]

Embodiments of the lead frame of the present disclosure are described. The lead frame 100 of the present embodiment is used for manufacturing a semiconductor device 200 (see fig. 3 and 4). The lead frame 100 includes a plurality of package regions 100A. The plurality of package regions 100A are arranged in a plurality of rows and a plurality of segments (in a matrix). In fig. 1, only a part of the lead frame 100 centering on one package region 100A is shown.

The package region 100A corresponds to a semiconductor device 200 described later, and is a region surrounded by a rectangular virtual line (a broken line shown in fig. 1) (see fig. 1). In the present embodiment, the lead frame 100 including a plurality of package regions 100A is illustrated, but the present invention is not limited to this, and the lead frame 100 may be constituted by only one package region 100A.

In the present specification and the like, "inner" and "inner" refer to a side toward the center of each package region 100A, and "outer" refer to a side (connection bar 130 side) away from the center of each package region 100A. The "upper surface" refers to a surface on which the semiconductor element 210 is mounted, the "lower surface" refers to a surface on the opposite side of the "upper surface" and refers to a surface connected to an external mounting board (not shown), and the "sidewall surface" refers to a surface located between the "upper surface" and the "lower surface" and refers to a surface constituting the thickness of the lead frame 100 (metal substrate 310).

In the present specification and the like, half etching means etching a material to be etched halfway along the thickness direction thereof. The thickness of the material to be etched after half etching is 30% to 70%, preferably 40% to 60%, of the thickness of the material to be etched before half etching.

As shown in fig. 1 and 2, each package region 100A of the lead frame 100 includes a plurality of lead portions 110, a chip carrier 120, and connection bars 130 connecting the lead portions 110. The lead portion 110 may include an inner lead portion 111 and a terminal portion 113. The inner lead portion 111 is a portion thinned from the lower surface side, and is located inside (on the chip carrier 120 side) each package region 100A. The terminal portions 113 are located outside (on the connection bar 130 side) of the respective package regions 100A. The inner lead portion 111 extends from the terminal portion 113 toward the chip pad portion 120. An internal terminal is formed on the upper surface side of the inner lead portion 111. As will be described later, the internal terminal is a region electrically connected to the semiconductor element 210 via the connection member 220. The inner terminal is provided with a metal plating layer 112 for improving the adhesion with the connection member 220.

Each of the lead portions 110 is connected to the semiconductor element 210 via a connecting member 220 as will be described later, and is disposed with a space between the semiconductor element and the chip carrier 120 (see fig. 4 and 5). The plurality of lead portions 110 are arranged at intervals along the longitudinal direction of the connecting bar 130. Each of the lead portions 110 extends from the connection bar 130.

The lead portion 110 is disposed along the periphery of the chip pad portion 120. The lead portion 110 is partially thinned from the lower surface side. The portion thinned from the lower surface side is an inner lead portion 111. The portion of the lead portion 110 that is not thinned from the lower surface side is a terminal portion 113, and an external terminal 150 is formed on the lower surface of the terminal portion 113. The external terminal 150 is a portion electrically connected to an external mounting board (not shown). The external terminal 150 is exposed outside the semiconductor device 200 described later.

The inner lead portion 111 is thinned from the lower surface side by half etching, for example. The inner lead portion 111 has an inner lead portion upper surface 111A, an inner lead portion lower surface 111B opposed to the inner lead portion upper surface 111A, and an inner lead portion side wall surface. The inner lead portion upper surface 111A is a portion of the upper surface of the lead portion 110. The inner lead portion side wall surface includes: a chip-seat-portion facing surface 111C facing the chip seat portion 120 side; and a surface facing the adjacent lead portion 110. The inner lead portion lower surface 111B is located on the lower side of the lead portion 110.

The terminal portion 113 is located on the connection bar 130 side. The terminal portion 113 is connected to the connection bar 130. The lower surface of the terminal portion 113 constitutes the external terminal 150 described above. The terminal portion 113 is not half-etched, and has the same thickness as the chip pad portion 120. In addition, the lower surface side of a portion of the terminal portion 113 located on the connection bar 130 side may be thinned, and a connection portion connected to the connection bar 130 may be formed.

At least a part of the upper surface and the side wall surface of the lead portion 110 are roughened surfaces, and the lower surface of the lead portion 110 (terminal portion 113) is a non-roughened surface that is not roughened. The inner lead lower surface 111B is a roughened surface. In fig. 1, a rough surface roughened is indicated by a thick dotted line.

In the present embodiment, when simply referred to as "roughened surface", the roughened surface is a roughened surface, and preferably a roughened surface roughened by microetching or the like.

The thinned portion of the lower surface of the lead portion 110 becomes a roughened surface. Specifically, the entire area of the inner lead lower surface 111B is a roughened surface. On the other hand, the portion of the lower surface of the lead portion 110 that is not thinned is a non-roughened surface. Specifically, the terminal portion 113 is not thinned from the lower surface side, and the entire area of the external terminal 150 located on the lower surface side of the terminal portion 113 is a non-roughened surface. The inner lead portion side wall surface including the chip seat portion facing surface 111C becomes a roughened surface whose entire area is roughened.

The metal plating layer 112 may be provided on the non-roughened surface of the upper surface of the lead portion 110 (the inner lead portion 111) as long as a part of the region on the chip carrier portion 120 side is the non-roughened surface. The metal plating layer 112 may be formed by, for example, an electroplating method. The thickness of the metal plating layer 112 may be in the range of 1 μm to 10 μm. The metal plating layer 112 may be, for example, an Ag plating layer, an Ag alloy plating layer, an Au alloy plating layer, a Pt plating layer, a Cu alloy plating layer, a Pd plating layer, a Ni plating layer, or the like, and may include one or more of them. The metal plating layer 112 preferably includes at least one of Ag plating layer, ni plating layer, pd plating layer, au plating layer. In addition, if a base plating layer is required depending on the case of constituting the metal plating layer 112, a known base plating layer may be used as the base plating layer. For example, a Ni plating layer, a Cu plating layer, or the like may be used as the base plating layer.

A semiconductor element 210 is mounted on the upper surface of the chip carrier 120 as will be described later. Further, a plurality of lead portions 110 may be disposed around the chip carrier portion 120. The upper surface and the side wall surface of the chip carrier 120 are roughened surfaces, and the lower surface of the chip carrier 120 may be a non-roughened surface that is not roughened (see fig. 2).

The upper surface of the chip carrier 120 is a region (internal terminal) bonded to the semiconductor element 210 via an adhesive 240 such as a die attach paste as will be described later. The lower surface of the chip carrier 120 is not thinned by half etching, for example, and is a non-roughened surface that is not roughened as in the case of the metal substrate 310 before processing described later. The lower surface of the chip carrier 120 is exposed to the outside in the semiconductor device 200 described later.

The package regions 100A are connected to each other by the connection bars 130, and the connection bars 130 extend in the X-direction and the Y-direction, respectively. The X direction and the Y direction are two directions parallel to each side of the package region 100A in the plane of the lead frame 100, and are orthogonal to each other.

The connection bars 130 are disposed around the package region 100A and outside the package region 100A. Each of the connection bars 130 has an elongated bar shape in a plan view. The width W of each connecting bar 130 (the distance in the direction perpendicular to the longitudinal direction of the connecting bar 130) is not particularly limited, and may be appropriately set in the range of 95 μm to 250 μm, for example. The plurality of lead portions 110 are connected to the connection bar 130 at predetermined intervals along the longitudinal direction of the connection bar 130, and the chip carrier 120 is supported by the connection bar 130 via the suspension leads 140. The connecting bar 130 in the present embodiment is not thinned, but is not limited to this embodiment. For example, the connection bar 130 may be thinned from the lower surface side thereof by half etching. The thickness of the connection bar 130 in this case can be set in consideration of the structure of the semiconductor device 200 and the like. The thickness of the connection bar 130 may be appropriately set in the range of 80 μm to 200 μm, for example.

The lead frame 100 of the present embodiment is used for manufacturing the semiconductor device 200 including the sealing portion 230 described later, and the upper surface of the lead portion 110 and the side wall surface of the lead portion 110 that are in contact with the sealing portion 230 may be roughened surfaces. The upper surface of the lead portion 110 and the side wall surface of the lead portion 110 located outside the package region 100A, and the connection bar 130 may be roughened or non-roughened. In addition, when the semiconductor device 200 is manufactured using the lead frame 100, dicing is performed along the connection bars 130. At this time, if the package regions 100A are molded and cut, if the upper surface of the connection bar 130 is roughened, foreign matter may be generated when cutting the lead frame 100. Therefore, by setting the upper surface of the connection bar 130 to be a non-roughened surface that is not roughened, the generation of foreign matter can be suppressed when manufacturing the semiconductor device 200.

In the roughened surface of the lead frame 100 of the present embodiment, a in the CIELab color space ^* A value in the range of 12 to 19, b ^* A value in the range of 12 to 17, preferably，a ^* A value in the range of 13 to 18, b ^* The values are in the range of 12 to 16. As will be seen from examples described later, when a in the coarse-surface CIELab color space in the lead frame 100 of the present embodiment ^* Value and b ^* When the value is within the predetermined range, the surface area ratio becomes high. Therefore, in the semiconductor device which can be manufactured using the lead frame 100, the adhesion strength to the molding resin is improved. This can prevent moisture in the air from entering the electrode of the semiconductor element. That is, by making a in the CIELab color space of the roughened surface of the lead frame 100 of the present embodiment ^* Value sum b ^* When the value is within the above range, a semiconductor device in which the penetration of moisture in the air into the electrode of the semiconductor element can be suppressed can be manufactured. In addition, in the present embodiment, a for the CIELab color space ^* Value sum b ^* The value was measured using a spectrodensitometer eXact (manufactured by X-rite Co.).

Here, a CIELab color space (l×a×b×color space) will be described. The color space L x a x b x is the CIE recommended chromaticity diagram called CIELab. L (L) ^* Represents brightness, a ^* Indicating the extent of red/magenta or green, b ^* Indicating the degree of yellow or blue. a, a ^* The value of (2) is closer to green as it goes to the negative side and closer to red as it goes to the positive side. In addition, b ^* The value of (2) is closer to blue as it goes to the negative side and closer to yellow as it goes to the positive side. At L ^* At a value of 100, shows white color (total reflection), at L ^* Black (total absorption) is shown at a value of 0. The center of these 3 values is a neutral color (gray). Namely, L ^* The movement in the axial direction indicates a change in brightness, a ^* b ^* The movement in the plane represents a change in hue. The distance in the l×a×b space corresponds to the proximity of the color, and it can be said that the closer the distance is, the closer the color is. In the roughened surface of the lead frame 100 of the present embodiment, a in the CIELab color space ^* The value can be in the range between red, magenta and green, b ^* The value can be in the range between yellow and blue, which corresponds to the above-specified range.

In addition, in the lead frame 100 of the present embodiment, the roughness is roughThe arithmetic mean curvature Spc of the peak apex of the face was 700mm ^-1 Above, preferably 1000mm ^-1 ～5000mm ^-1 More preferably 2000mm ^-1 ～4000mm ^-1 . As will be apparent from examples described later, when the arithmetic average curvature Spc of the peak and the apex of the roughened surface in the lead frame 100 of the present embodiment is within a predetermined range, the point of contact with the object to be contacted is sharp. In this case, in the semiconductor device manufactured using the lead frame 100, the adhesion strength to the mold resin is improved, and the penetration of moisture in the air into the electrode of the semiconductor element can be suppressed. That is, by setting the arithmetic average curvature Spc of the peak and the peak point of the roughened surface in the lead frame 100 of the present embodiment to the above range, a semiconductor device in which the penetration of moisture in the air into the electrode of the semiconductor element can be suppressed can be manufactured. Further, the arithmetic mean height Sa of the roughened surface is preferably 0.12 μm or more, more preferably in the range of 0.12 μm to 0.34 μm. By making the arithmetic average curvature Spc of the peak apex of the rough surface 700mm ^-1 As described above, by setting the arithmetic average height Sa of the roughened surface to a predetermined range, it is possible to manufacture a semiconductor device in which the penetration of moisture in the air into the electrode of the semiconductor element can be effectively suppressed. The arithmetic average curvature Spc of the peak apex represents an average of principal curvatures of the peak apex existing on the object, and the more the peak apex is pointed, the larger the value of the arithmetic average curvature Spc of the peak apex is. The arithmetic average height Sa is a parameter obtained by expanding the arithmetic average height Ra of a line to three dimensions, that is, to a plane, and is a numerical value representing the average of absolute values of differences between the heights of points and the average plane of the surface. In the present embodiment, the arithmetic mean curvature Spc and the arithmetic mean height Sa of the peak apex are measured using a laser microscope VK-X260 (manufactured by KEYENCE corporation, measuring unit) and a laser microscope VK-X250 (manufactured by KEYENCE corporation, controller unit).

Conventionally, in recent years, miniaturization and thinning of a semiconductor device have been demanded with respect to a lead frame used in a Quad Flat Non-leaded package (QFN) type semiconductor device. In such a semiconductor device, a distance from the outer periphery to the electrode of the semiconductor element, that is, a path through which moisture contained in the outside air (air) can enter is easily shortened, and there is a concern that: moisture in the air is immersed in the electrode of the semiconductor element, and the semiconductor device malfunctions.

Therefore, the present inventors have noted that in a lead frame for a semiconductor device, the state of the roughened surface of the lead frame is important. In addition, from the viewpoint of reliability required for the semiconductor device, it is noted that: as an index indicating the state of the rough surface, attention should be paid to the arithmetic average curvature Spc and the arithmetic average height Sa of the CIELab color space or peak apex. Also, a in the CIELab color space ^* A value in the range of 12 to 19, b ^* In the case where the value is in the range of 12 to 17, or in the case where the arithmetic average curvature Spc of the peak top point of the roughened surface is 700mm ^-1 In the above, it was found that a highly reliable lead frame required for a semiconductor device can be obtained when the arithmetic average height Sa of the roughened surface is 0.12 μm or more, and the present invention has been completed.

The roughened surface of the present embodiment can be formed by roughening a metal substrate 310 described later with a microetching solution, for example. The microetching solution usable in the present embodiment includes a microetching solution containing sulfuric acid or hydrochloric acid as a main component, a microetching solution containing hydrogen peroxide and sulfuric acid as main components, and the like.

Regarding the rough surface in the present embodiment, a in the CIELab color space ^* A value in the range of 12 to 19, b ^* The value is in the range of 12 to 17. In addition, the arithmetic mean curvature Spc of the peak apex of the rough surface was 700mm ^-1 The arithmetic mean height Sa of the roughened surface is 0.12 μm or more. By providing the roughened surface in such a predetermined range, it is possible to manufacture a semiconductor device in which the penetration of moisture in the air into the electrode of the semiconductor element can be suppressed.

The lead frame 100 described above is made of a metal such as copper, copper alloy, or Ni alloy. The thickness of the lead frame 100 can be set in consideration of the structure of the semiconductor device 200, for example, but the thickness of the lead frame 100 can be set appropriately in the range of 80 μm to 300 μm, for example.

The lead portions 110 in the present embodiment are all arranged along the four sides of the package region 100A, but the present invention is not limited thereto, and may be arranged along only two opposite sides of the package region 100A, for example.

The lead frame 100 shown in fig. 1 and 2 is described as having the chip carrier 120, but the lead frame is not limited to this, and the chip carrier 120 may not be provided, and each lead 110 may be connected to the semiconductor element 210 via a bump as a connecting member 220 (see fig. 5), for example, as will be described later.

[ semiconductor device ]

Embodiments of the semiconductor device of the present disclosure will be described. As shown in fig. 3 and 4, the semiconductor device 200 includes a plurality of lead portions 110, a die pad 120, a semiconductor element 210, a connection member 220, and a sealing portion 230.

The semiconductor device 200 in the present embodiment is a semiconductor device manufactured using the lead frame 100. Accordingly, the lead portion 110 and the chip pad portion 120 in the semiconductor device 200 are provided in the above-described lead frame 100. Therefore, the upper surface of the lead portion 110 outside (the side away from the chip carrier portion 120) the metal plating layer 112 and the side wall surface of the lead portion 110 are roughened surfaces. The upper surface of the chip carrier 120 and the side wall surface of the chip carrier 120 are roughened surfaces. As shown in fig. 4, the lead portion 110 includes an inner lead portion 111 thinned from the lower surface side of the lead portion 110, and the inner lead portion lower surface 111B is a roughened surface. The sealing portion 230 is closely adhered to the inner lead lower surface 111B. The terminal portion 113 of the lead portion 110 is not thinned from the lower surface side. The external terminal 150 located on the lower surface of the terminal portion 113 is a non-roughened surface. The external terminal 150 is exposed from the sealing part 230.

A in the CIELab color space of the rough surface ^* A value in the range of 12 to 19, b ^* The value is in the range of 12 to 17. By making a in the CIELab color space of the roughened surface ^* Value sum b ^* The value is in the above range, and thus the penetration of moisture in the air into the electrode of the semiconductor element 210 can be suppressed.

In addition, the peaks of the rough surfaceThe arithmetic mean curvature Spc of the points was 700mm ^-1 The above. By making the arithmetic average curvature Spc of the peak apex 700mm ^-1 As described above, the penetration of moisture in the air into the electrode of the semiconductor element 210 can be suppressed. The arithmetic mean height Sa of the roughened surface is preferably 0.12 μm or more, more preferably in the range of 0.12 μm to 0.34 μm. The arithmetic average curvature Spc of the peak apex of the roughened surface was 700mm ^-1 As described above, the arithmetic average height Sa of the roughened surface is within a predetermined range, and thus penetration of moisture in the air into the electrode of the semiconductor element 210 can be more effectively suppressed.

The semiconductor element 210 may be any of various semiconductor elements commonly used in the past, and is not particularly limited, and for example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like may be used. The semiconductor element 210 has a plurality of electrodes 210A each of which mounts a connection member 220.

Each of the connection members 220 is made of a metal material having good electrical conductivity, such as copper or gold, for example, and one end of each of the connection members 220 is electrically connected to the electrode 210A of the semiconductor element 210 and the other end is electrically connected to the metal plating layer 112 located on each of the lead portions 110. As the member used as the connection member 220, a connection wire, a conductor such as a bump, or the like can be exemplified.

The sealing portion 230 seals at least the lead portion 110, the chip carrier portion 120, the semiconductor element 210, and the connection member 220. The sealing portion 230 may be made of a resin such as a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as PPS resin. The thickness of the entire sealing portion 230 is not particularly limited, and may be appropriately set in a range of about 300 μm to 1500 μm, for example. The length of one side of the sealing portion 230 (one side of the semiconductor device 200) in the planar view of the semiconductor device 200 is not particularly limited, and may be appropriately set in a range of about 0.2mm to 20mm, for example.

The semiconductor device 200 shown in fig. 3 and 4 is described as having the chip carrier 120, but the present invention is not limited thereto, and the chip carrier 120 may not be provided, and for example, each lead 110 may be connected to the electrode 210A of the semiconductor element 210 via a bump as the connection member 220 (see fig. 5).

[ method for manufacturing lead frame ]

A method of manufacturing the lead frame 100 shown in fig. 1 and 2 will be described as an example. Fig. 6A to 6H are process drawings for explaining a method of manufacturing a lead frame according to the present embodiment.

< Metal substrate preparation Process >

As shown in fig. 6A and 6B, a metal substrate 310 having a 1 st surface 310A and a 2 nd surface 310B opposed to the 1 st surface 310A is prepared (see fig. 6A). The metal substrate 310 that can be used in the present embodiment includes a pure copper substrate, a copper alloy substrate, a 42 alloy (Fe alloy with 42% Ni), and the like, but is preferably a pure copper substrate or a copper alloy substrate. As the metal substrate 310, a substrate obtained by degreasing the 1 st surface 310A and the 2 nd surface 310B and performing a cleaning process may be used.

< Metal substrate processing Process >

Next, photosensitive resist 320 is coated on each of the 1 st surface 310A and the 2 nd surface 310B of the metal substrate 310, and dried (see fig. 6B). As the photosensitive resist 320 that can be used in the present embodiment, a conventionally known photosensitive resist can be used.

Next, the metal substrate 310 is exposed to light through a photomask and developed, whereby a resist layer 340 having a desired opening 330 is formed (see fig. 6C).

Next, the metal substrate 310 is etched with an etchant using the resist layer 340 as an etching resist (see fig. 6D). The etching liquid may be appropriately selected according to the material of the metal substrate 310 to be used. For example, in the case of using a pure copper substrate as the metal substrate 310, it is generally possible to spray-etch both the 1 st surface 310A and the 2 nd surface 310B of the metal substrate 310 using an aqueous solution of ferric chloride as an etching solution. Thereby, the outer shapes of the lead portion 110, the chip carrier portion 120, and the connection bar 130 are formed. At this time, the inner lead portion 111 and the terminal portion 113 may be formed by thinning a lower surface of a part of the lead portion 110 by half etching.

Next, the resist layer 340 is peeled off and removed, and a cover layer 350 is formed on the surface of the etched metal substrate 310 (see fig. 6E). Thereby, the cover layer 350 is formed over the entire circumferences of the lead portion 110, the chip carrier portion 120, and the connection bar 130. The thickness of the cover layer 350 is not particularly limited as long as it exceeds 0 μm and is 2 μm or less, for example. The metal forming the cover layer 350 is not particularly limited, and silver may be used, for example. When the cover layer 350 is formed of a silver plating layer, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as a plating solution for plating. It is preferable that the cover 350 is not formed on the external terminals 150 on the lower surfaces of the lead portions 110 (the terminal portions 113) and the lower surface of the chip carrier 120. In order to prevent the cover 350 from being formed on the lower surfaces of the external terminals 150 of the lead portions 110 (the terminal portions 113) and the lower surfaces of the chip carrier portions 120, for example, the resist 400 may be formed on the lower surfaces of the external terminals 150 of the lead portions 110 (the terminal portions 113) and the lower surfaces of the chip carrier portions 120, thereby avoiding the cover 350 (see fig. 6E).

Next, the cover layer 350 existing in the region where the roughened surface is formed is removed. Specifically, the cover layer 350 formed on the upper surface of the lead portion 110, the side wall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the chip carrier 120, and the side wall surface of the chip carrier 120 except for the region where the metal plating layer 112 is provided is removed (see fig. 6F). During this time, as shown in fig. 6F, elastic members 410 such as rubber gaskets are disposed on the 1 st surface 310A and the 2 nd surface 310B of the metal substrate 310, respectively, and the metal substrate 310 is held by the jig 420 with the elastic members 410 interposed therebetween. Then, the cover layer 350 is peeled off and removed from the portion not covered by the elastic member 410. Thus, the upper surface of the lead portion 110, the side wall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the chip carrier 120, and the side wall surface of the chip carrier 120 are exposed except for the region where the metal plating layer 112 is provided. On the other hand, the upper surface of the region where the metal plating layer 112 is formed in the upper surface of the lead portion 110 covered by the elastic member 410 and the cover layer 350 on the connection bar 130 remain.

< rough surface Forming Process >

Next, a support layer 360 for supporting the metal substrate is provided on the lower surface side of the metal substrate 310 (see fig. 6G). The support layer 360 may be, for example, a resist layer. After the support layer 360 is provided, a roughened surface is formed by roughening a portion of the metal substrate 310 that is not covered with the cover layer 350 (see fig. 6G). Specifically, the upper surface of the lead portion 110, the side wall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the chip carrier portion 120, and the side wall surface of the chip carrier portion 120 are roughened on the outer side (the side away from the chip carrier portion 120) than the region where the metal plating layer 112 is formed. To form the roughened surface, for example, a microetching solution is supplied to the metal substrate 310. Thus, a rough surface can be formed on the entire metal substrate 310 except for the portion covered with the cover layer 350. The microetching solution is a surface treatment agent capable of slightly dissolving the metal surface to form a roughened surface having fine irregularities. As the microetching solution usable in the present embodiment, there can be mentioned a microetching solution containing sulfuric acid or hydrochloric acid as a main component, a microetching solution containing hydrogen peroxide and sulfuric acid as main components, and the like.

In the step of forming the roughened surface, a in the CIELab color space of the roughened surface is used ^* A value of 12 to 19, b ^* The roughening is performed so that the value falls within the range of 12 to 17. In the step of forming the roughened surface, the arithmetic mean curvature Spc of the peak-to-peak points of the roughened surface was set to 700mm ^-1 Roughening is performed in the above manner. Further, the arithmetic mean height Sa of the roughened surface is preferably 0.12 μm or more, and more preferably, the roughened surface is roughened so as to be in the range of 0.12 μm to 0.34 μm. By forming the roughened surface so as to be within the predetermined range, the lead frame 100 can be obtained as described above: it is possible to manufacture a semiconductor device in which the penetration of moisture in the air into the electrode of the semiconductor element can be suppressed.

Thereafter, the support layer 360 and the cover layer 350 are sequentially peeled off and removed, and the metal plating layer 112 is provided at the inner end portion (chip seat portion 120 side) of the inner lead portion upper surface 111A, thereby obtaining the lead frame 100 shown in fig. 1 and 2 (see fig. 6H). The metal plating layer 112 may be formed by, for example, photolithography to form a plating resist layer having a predetermined pattern, and electroplating is performed on the portion not covered with the plating resist layer to form the metal plating layer 112. The lead frame 100 manufactured by the above manufacturing method may be subjected to alkali treatment. Specifically, the lead frame 100 is immersed in an aqueous alkali solution. By performing the alkali treatment, the acid contained in the surface treatment agent used in the rough surface forming step is neutralized, and thus corrosion of the lead frame 100 can be suppressed. The alkali used in the alkali treatment is not particularly limited, and examples thereof include sodium hydroxide, potassium hydroxide, and the like, and 1 kind of them may be used alone or 2 or more kinds may be used in combination.

[ method for manufacturing semiconductor device ]

A method for manufacturing the semiconductor device 200 shown in fig. 3 and 4 will be described as an example. Fig. 7A to 7D are process charts for explaining a method of manufacturing the semiconductor device according to the present embodiment.

First, a lead frame 100 manufactured by the manufacturing method shown in fig. 6A to 6H is prepared (see fig. 7A). Next, the semiconductor element 210 is mounted on the chip carrier 120 of the lead frame 100. In this case, the semiconductor element 210 is mounted and fixed on the die pad 120 using an adhesive 240 such as a die attach paste (see fig. 7B). The adhesive 240 may be an epoxy resin adhesive containing components such as silver paste and epoxy resin. At this time, the semiconductor element 210 is disposed on the roughened surface of the upper surface of the chip carrier 120 via the adhesive 240.

Next, the electrodes 210A of the semiconductor element 210 and the metal plating layers 112 formed on the lead portions 110 are electrically connected to each other by the connection members 220 (see fig. 7C).

Next, the sealing portion 230 is formed by injection molding or transfer molding a thermosetting resin or a thermoplastic resin to the lead frame 100 (see fig. 7D). Thereby, the lead portion 110, the chip carrier portion 120, the semiconductor element 210, and the connection member 220 can be sealed with resin.

Thereafter, the lead frame 100 is cut for each package region 100A. At this time, since the upper surface of the cut connection bar 130 is a non-roughened surface that is not roughened, generation of foreign matter at the time of cutting can be suppressed. Thus, the semiconductor devices 200 shown in fig. 3 and 4 are obtained by singulating the semiconductor devices 200.

In addition, if the semiconductor device 200 is used for a long period of time, moisture or the like in the air may be immersed from the side surface or the lower surface side of the semiconductor device 200. For example, moisture in the air may enter through the interface between the sealing portion 230 and the lead portion 110 or the chip carrier portion 120.

In response to this problem, in the present embodiment, roughened surfaces are formed on the upper surface of the lead portion 110 where the metallization 112 is not provided, the side wall surface of the lead portion 110, the upper surface of the chip carrier portion 120, and the side wall surface of the chip carrier portion 120. The roughened surface is roughened in the following manner: a in the coarse-surface CIELab color space ^* A value in the range of 12 to 19, b ^* A value of 12 to 17, or an arithmetic mean curvature Spc of the peak top point of the roughened surface of 700mm ^-1 The arithmetic mean height Sa of the roughened surface is 0.12 μm or more. Accordingly, the distance of the penetration path of the moisture from the interface between the sealing portion 230 and the lead portion 110 or the chip carrier portion 120 to the semiconductor element 210 side becomes relatively longer. Therefore, the penetration of moisture into the electrode 210A of the semiconductor element 210 can be suppressed. Further, having the roughened surface within the above-described predetermined range can improve the adhesion strength between the chip carrier 120, the lead portion 110, and the sealing portion 230, and can prevent the chip carrier 120, the lead portion 110, and the sealing portion 230 from peeling off from each other.

The lead portion 110 in the present embodiment includes an inner lead portion 111 thinned from the lower surface side of the lead portion 110. The lower surface of the inner lead portion 111 is roughened, and thus the distance of the moisture penetration path at the interface between the sealing portion 230 and the lead portion 110 becomes longer on the lower surface side of the semiconductor device 200. This can prevent moisture from entering the electrode 210A of the semiconductor element 210 from the interface between the sealing portion 230 and the lead portion 110. Further, by providing the roughened surface within the above-described predetermined range on the lower surface of the inner lead portion 111, the adhesion strength between the lead portion 110 and the sealing portion 230 can be improved, and the lead portion 110 and the sealing portion 230 can be prevented from being peeled off from each other.

The embodiments described above are described for easy understanding of the present invention, and are not described for limiting the present invention. Therefore, the gist of the present invention is that each element disclosed in the above embodiment also includes all design changes and equivalents that fall within the technical scope of the present invention.

Examples (example)

Hereinafter, the present disclosure will be described in more detail with reference to examples and comparative examples, but the present disclosure is not limited to the following examples and the like.

[ example 1 ]

Has the structure shown in fig. 1 and 2. The lead frame 100 is prepared. In the lead frame 100, the upper surface and the side wall surface of the lead portion 110, and the upper surface and the side wall surface of the chip pad portion 120 are defined by a in the CIELab color space ^* A value of 17.53, b ^* An arithmetic mean curvature Spc of 14.80 and peak apex of 2431.46mm ^-1 And a roughened surface having an arithmetic average height Sa of 0.14 μm. A is that ^* Value and b ^* The values were measured using a spectrodensitometer eXact (manufactured by X-rite corporation), and the arithmetic mean curvature Spc and the arithmetic mean height Sa of the peak peaks were measured using a laser microscope VK-X260 (manufactured by KEYENCE corporation, measuring unit) and a laser microscope VK-X250 (manufactured by KEYENCE corporation, controller unit).

[ example 2 ]

Such a lead frame 100 is prepared: the upper surface and sidewall surface of the lead portion 110, and the upper surface and sidewall surface of the chip pad portion 120 are defined by a in the CIELab color space ^* A value of 16.03, b ^* An arithmetic mean curvature Spc of 13.84 and peak apex of 2952.08mm ^-1 The structure was the same as that of example 1 except that the rough surface having an arithmetic average height Sa of 0.17 μm was formed.

[ example 3 ]

Such a lead frame 100 is prepared: the upper surface and sidewall surface of the lead portion 110, and the upper surface and sidewall surface of the chip pad portion 120 are defined by a in the CIELab color space ^* A value of 15.39, b ^* An arithmetic mean curvature Spc of the peak apex of 3523.76mm with a value of 13.16 ^-1 The structure was the same as that of example 1 except that the rough surface having an arithmetic average height Sa of 0.22 μm was formed.

[ example 4 ]

Such a lead frame 100 is prepared: the upper surface and sidewall surface of the lead portion 110, and the upper surface and sidewall surface of the chip pad portion 120 are defined by a in the CIELab color space ^* A value of 14.65, b ^* An arithmetic mean curvature Spc of the peak apex of 12.86 and 3378.00mm ^-1 The structure was the same as that of example 1 except that the rough surface having an arithmetic average height Sa of 0.21 μm was formed.

Comparative example 1

Preparing such a lead frame: the upper surface and sidewall surface of the lead portion 110, and the upper surface and sidewall surface of the chip pad portion 120 are defined by a in the CIELab color space ^* A value of 18.59, b ^* An arithmetic mean curvature Spc of 17.29 at the peak apex of 629.05mm ^-1 The structure was the same as that of example 1 except that the rough surface having an arithmetic average height Sa of 0.11 μm was formed.

Comparative example 2

Preparing such a lead frame: the upper surface and sidewall surface of the lead portion 110, and the upper surface and sidewall surface of the chip pad portion 120 are defined by a in the CIELab color space ^* A value of 10.06, b ^* An arithmetic mean curvature Spc of 7.18 at the peak apex of 986.96mm ^-1 The structure was the same as in example 1, except that the non-roughened surface having an arithmetic average height Sa of 0.09 μm was not roughened.

Test example evaluation test of rough surface State

The rough surface state of each of the lead frames of examples 1 to 4 and comparative examples 1 to 2 was observed by SEM and laser microscope, and the shear strength of each of the lead frames of examples 1 to 4 and comparative examples 1 to 2 was measured. The results are shown in Table 1. The shear strength was measured as follows: as a molding resin close-fitting strength test (puddle cup test), a molding resin was molded on a lead frame, and a shearing direction was imparted. For the molding resin, EME-631 (manufactured by Sumitomo electric Co., ltd.) was used, molding resin was carried out under the conditions of a molding time of 120 seconds, a molding temperature of 175.+ -. 5 ℃ and a molding pressure of 10MPa, and then curing treatment was carried out at 175 ℃ for 6 hours. The molded resin was molded to have a height of 4mm, a bottom diameter of 4mm, and an upper surface diameter of 3mm, and the bottom side was molded into a lead frame. Then, the lead frame was fixed to a bonding strength tester DAGE 4000 (Nordson Co.) and a load of 1kg and 0.1 mm/sec was applied to the molded resin from the lateral direction on the lead frame, thereby measuring the shear strength.

TABLE 1

As shown in table 1, it was confirmed that: if the lead frame 100 has a rough surface of a in the CIELab color space ^* A value in the range of 12 to 19, b ^* A value in the range of 12 to 17, and a ^* Value sum b ^* When the value is outside the above range, the shear strength is increased. Thus, it is inferred that: by making a ^* Value sum b ^* In the semiconductor device manufactured using the lead frame 100, the strength of the adhesion to the molding resin is improved, and the penetration of moisture in the air into the electrode 210A of the semiconductor element 210 can be suppressed.

In addition, it was confirmed that: if the arithmetic average curvature Spc of the peak apex of the roughened surface of the lead frame 100 is 700mm ^-1 The arithmetic mean curvature Spc with the peak top point is less than 700mm ^-1 The shear strength is higher than that in the case of the conventional method. Further, the arithmetic average height Sa of the roughened surface of each of the lead frames 100 of examples 1 to 4 was 0.12 μm or more. From this result, it is inferred that: by making the arithmetic average curvature Spc of the peak apex of the rough surface 700mm ^-1 As described above, the arithmetic average height Sa of the roughened surface is set to 0.12 μm or more, so that the adhesion strength to the molding resin is improved in the semiconductor device manufactured using the lead frame 100, and the penetration of moisture in the air into the electrode 210A of the semiconductor element 210 can be suppressed. The non-roughened material of comparative example 2 The arithmetic average curvature Spc of the peak apex of the roughened surface was 700mm ^-1 The above. This is presumably because, when the lead frame of comparative example 2 was manufactured by rolling a metal substrate, there was a sharp peak of the rolling mark, and therefore the value of the arithmetic mean curvature Spc at the peak apex was 700mm ^-1 The above. In addition, the arithmetic average curvature Spc of the peak peaks of the roughened surface of the lead frame of comparative example 1 is smaller than the arithmetic average curvature Spc of the peak peaks of the non-roughened surface of comparative example 2. This is presumably because, when the rough surface is formed, the rough surface is formed by roughening to such an extent that the peak top points of the sharp peaks of the rolling marks are shaved off, and therefore the value of the arithmetic average curvature Spc becomes small. The roughened surface of the lead frame 100 of examples 1 to 4 is roughened further than that of the lead frame of comparative example 1. Thus, it is inferred that: the etching is deepened, and the value of the arithmetic mean curvature Spc of the peak apex becomes large.

(embodiment 2)

Next, embodiment 2 will be described with reference to fig. 8 to 17. In the drawings, the same reference numerals are given to the same parts, and a part of detailed description may be omitted.

(Structure of lead frame)

First, a outline of the lead frame according to the present embodiment will be described with reference to fig. 8 to 10. Fig. 8 to 10 are diagrams showing the lead frame of the present embodiment.

The lead frame 10 shown in fig. 8 and 9 is used in manufacturing the semiconductor device 20 (fig. 11 and 12). Such a lead frame 10 includes a plurality of package regions 10a. The plurality of package regions 10a are arranged in a plurality of rows and a plurality of segments (in a matrix). In fig. 8, only a part of the lead frame 10 centering on one package region 10a is shown.

In the present specification, "inner" and "inner" refer to the sides facing the center direction of each package region 10a. "outer" and "outer" refer to the side (the connection bar 13 side) away from the center of each package region 10a. The "front surface" refers to the surface on the side on which the semiconductor element 21 is mounted. The "back surface" refers to a surface opposite to the "front surface" and refers to a surface on the side connected to an external mounting board, not shown. The "side face" is a face located between the "front face" and the "back face", and is a face constituting the thickness of the lead frame 10 (metal substrate).

In the present specification, half etching means etching a material to be etched halfway along the thickness direction thereof. The thickness of the material to be etched after half etching is, for example, 30% to 70%, preferably 40% to 60% of the thickness of the material to be etched before half etching.

As shown in fig. 8 and 9, each package region 10a of the lead frame 10 includes a die pad 11 and a lead portion 12 located around the die pad 11. A portion of the lead portion 12 is thinned from the back surface side. The thinned portion of the back surface of the lead portion 12 is roughened. The portion of the back surface of the lead portion 12 that is not thinned becomes a smooth surface.

The package region 10a corresponds to a semiconductor device 20 (described later). The package region 10a is a region surrounded by a rectangular imaginary line (two-dot chain line) in fig. 8. In the present embodiment, the lead frame 10 includes a plurality of package regions 10a. However, the present invention is not limited thereto, and only 1 package region 10a may be formed on 1 lead frame 10.

The package regions 10a are connected to each other by connecting bars (supporting members) 13. The connection bar 13 supports the chip carrier 11 and the lead portion 12. The connection bars 13 extend in the X-direction or the Y-direction, respectively. Here, the X-direction and the Y-direction refer to two directions parallel to each side of the package region 10a in the plane of the lead frame 10. The X direction and the Y direction are mutually orthogonal. The Z direction is a direction perpendicular to both the X direction and the Y direction.

Each connection bar 13 is disposed around the package region 10a and outside the package region 10a. Each connecting bar 13 has an elongated bar shape in plan view. The width of each connecting bar 13 (the distance in the direction orthogonal to the longitudinal direction of the connecting bar 13) may be 95 μm or more and 250 μm or less. The plurality of lead portions 12 are connected to the respective connection bars 13 at intervals along the longitudinal direction of the connection bars 13. The chip carrier 11 is supported by the connection bars 13 via suspension leads 14. The connecting bar 13 is not thinned, but may be thinned from the back side by half etching, for example. The thickness of the connection bar 13 is also dependent on the structure of the semiconductor device 20, but may be 80 μm or more and 200 μm or less.

As shown in fig. 9, the die pad 11 has a die pad front surface 11a on the front surface side and a die pad back surface 11b on the back surface side. The semiconductor element 21 is mounted on the front surface 11a of the die pad as will be described later. The chip-holder rear surface 11b is exposed outward from the semiconductor device 20 (described later). In addition, a 1 st chip-carrier side surface 11c and a 2 nd chip-carrier side surface 11d are formed on the side of the chip carrier 11 facing the lead portion 12. The 1 st chip carrier side 11c is located on the chip carrier front 11a side. The 2 nd die pad side 11d is located on the die pad back 11b side. In this case, the 1 st chip carrier side surface 11c and the 2 nd chip carrier side surface 11d of the chip carrier 11 are roughened surfaces, respectively. On the other hand, as described later, a smooth surface (die pad smooth surface region 11 e) and a rough surface (die pad rough surface region 11 f) are formed on the die pad front surface 11 a. The back surface 11b of the chip holder becomes a smooth surface.

In the present embodiment, the "rough surface" means a surface having an S-ratio of 1.30 or more. "smooth surface" refers to a surface having an S-ratio of less than 1.30. The rough surface is a surface that is rougher than the smooth surface. The S-ratio of the "rough surface" is preferably 1.30 or more and 2.30 or less. The S-ratio of the "smooth surface" is preferably 1.00 or more and 1.20 or less. Here, "S-ratio" refers to a value obtained by dividing a surface to be measured into a plurality of pixels by an optical interferometer and measuring the divided surface area by an observation area. Specifically, using a VertScan manufactured by Hitachi High-Tech Science, the surface to be measured is divided into a plurality of pixels, and the obtained surface area is divided by the observation area.

The roughened surface may also be formed by: for example, the outer surface of the metal substrate 31 described later is roughened with a microetching solution containing hydrogen peroxide and sulfuric acid as main components. The smooth surface may be an unprocessed surface which is not subjected to such roughening treatment on the metal substrate 31 described later. In fig. 9, the roughened portion is indicated by a thick dotted line (the same applies to other cross-sectional views).

The chip carrier front surface 11a of the chip carrier 11 is a region (internal terminal) electrically connected to the semiconductor element 21 via the bump 26 as will be described later. The front surface 11a of the die pad may be a region which is not thinned by half etching or the like. A chip-holder smooth surface region 11e as a smooth surface region and a chip-holder rough surface region 11f as a rough surface region are formed on the chip-holder front surface 11 a.

A plurality of chip-holder smooth surface regions 11e may be formed on the chip-holder front surface 11 a. The chip-holder smooth surface regions 11e are connected to the corresponding bumps 26 (see fig. 12). The number of die pad smooth surface areas 11e on die pad 11 and the number of bumps 26 connected to die pad 11 may be the same. Alternatively, a plurality of bumps 26 may be arranged in 1 chip-carrier smooth surface region 11e. In this case, the number of the chip-holder smooth surface regions 11e on the chip holder 11 may be smaller than the number of the bumps 26 connected to the chip holder 11.

The chip carrier roughened surface area 11f is roughened (S-ratio greater) than the chip carrier smooth surface area 11 e. As shown in fig. 10 (a), the chip-holder roughened surface region 11f is formed so as to surround the entire periphery of each chip-holder smooth surface region 11e in plan view. That is, the chip carrier smooth surface region 11e is not directly contacted with the peripheral edge 11g of the chip carrier 11. The chip carrier roughened surface region 11f is formed along the entire peripheral edge 11g of the chip carrier 11 in a plan view. Here, as shown in fig. 8, the peripheral edge 11g of the chip carrier 11 refers to an area surrounded by a plurality of (four) sides of the chip carrier 11. In addition, the entire area of the chip-carrier front surface 11a other than the chip-carrier smooth surface area 11e may be the chip-carrier rough surface area 11f. That is, the die pad front surface 11a may be constituted only by the plurality of die pad smooth surface regions 11e and the other die pad rough surface regions 11f.

As shown in fig. 10 (a), the chip-holder smooth surface region 11e may be circular in plan view. The chip carrier smooth surface area 11e is preferably larger than the bump 26 (virtual line) in a plan view. The width (diameter) D1 of the chip holder smooth surface region 11e may be 0.030mm or more, or 0.035mm or more. The width (diameter) D1 may be 0.070mm or less, or 0.065mm or less. When the bump 26 is disposed at the center of the chip-holder smooth surface region 11e, the shortest distance d1 between the peripheral edge of the bump 26 and the peripheral edge of the chip-holder smooth surface region 11e may be 0.005mm or more, or 0.010mm or more. The shortest distance d1 may be 0.020mm or less or 0.015mm or less. The shortest distance L1 between the die pad smooth surface region 11e and the peripheral edge 11g of the die pad 11 may be 0.025mm or more, or 0.030mm or more. The shortest distance L1 may be 1.0mm or less or 0.50mm or less. By making the chip-holder smooth surface area 11e circular in a plan view, it is easy to position the circular bump 26 with respect to the chip-holder smooth surface area 11 e. In fig. 10 (a) and (b), the smooth surface is indicated by white, and the rough surface is indicated by hatching (fig. 17 (a) to (d) are also the same).

In fig. 10 (a), when a plurality of chip-holder smooth surface regions 11e are present on the chip-holder front surface 11a, the shortest distance M1 between adjacent chip-holder smooth surface regions 11e may be 0.030mm or more, or 0.040mm or more. The shortest distance M1 may be 1.0mm or less, or may be 0.50mm or less. The pitch P1 between the centers of the chip-holder smooth surface regions 11e adjacent to each other may be 0.045mm or more, or may be 0.057mm or more. The pitch P1 may be 1.2mm or less or 0.60mm or less. The pitch P1 corresponds to the pitch between the centers of the adjacent bumps 26.

Referring to fig. 9, external terminals may be formed on the back surface 11b of the chip carrier 11. The external terminal may be electrically connected to a mounting board not shown. The back surface 11b of the die pad is not thinned by half etching, for example, but is a smooth surface similar to a metal substrate before processing (metal substrate 31 described later). The die pad rear surface 11b is exposed outward from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

Each of the lead portions 12 is connected to the semiconductor element 21 through a bump 26 as will be described later, and is disposed with a space between the semiconductor element and the die pad 11. The plurality of lead portions 12 are arranged at intervals along the longitudinal direction of the connecting bar 13. Each of the lead portions 12 extends from the connecting bar 13.

The lead portion 12 is disposed along the periphery of the die pad 11. A part of the lead portion 12 is thinned from the back surface side. In this case, the back surface of an inner lead 51, which will be described later, in the lead portion 12 is thinned. In addition, an external terminal 17 is formed at a portion of the rear surface of the lead portion 12 that is not thinned. The external terminal 17 is electrically connected to an external mounting board (not shown). The external terminals 17 are exposed outward from the semiconductor device 20 after the manufacture of the semiconductor device 20 (described later).

As shown in fig. 9, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner leads 51 are located on the inner side (chip carrier 11 side). The terminal portion 53 is located outside (the connection bar 13 side). The inner leads 51 extend from the terminal portions 53 toward the chip carrier 11. An internal terminal is formed on the front side of the inner lead 51. The internal terminal is a region (lead smooth surface region 12 e) electrically connected to the semiconductor element 21 via the bump 26 as will be described later.

The inner lead 51 is thinned from the back side by half etching, for example. The inner lead 51 has an inner lead front face 51a and an inner lead back face 51b. The inner lead front face 51a is located on the front face side. Further, an inner lead distal end surface 51c is formed on a surface of the inner lead 51 facing the chip carrier 11. The inner lead back surface 51b is located on the back surface side.

The terminal portion 53 is located on the connection bar 13 side. The base end portion of the terminal portion 53 is connected to the connecting bar 13. The terminal portion 53 has a terminal portion front face 53a. The external terminal 17 is formed on the back surface of the terminal portion 53. The terminal portion 53 is not half-etched and has the same thickness as the chip carrier 11. In addition, the back surface of the portion of the lead portion 12 on the connection bar 13 side with respect to the terminal portion 53 may be thinned, and a connection portion to be connected to the connection bar 13 may be formed.

In the present embodiment, the thinned portion of the back surface of the lead portion 12 is roughened. Specifically, the inner lead 51 of the lead portion 12 is thinned from the back surface side. The entire area of the inner lead back surface 51b located on the back surface side of the inner lead 51 is a roughened surface. On the other hand, the portion of the back surface of the lead portion 12 that is not thinned becomes a smooth surface. Specifically, the terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The entire area of the external terminal 17 located on the back surface side of the terminal portion 53 is a smooth surface.

Further, the entire area of the inner lead distal end face 51c of the lead portion 12 is roughened. Although not shown, both side surfaces of the lead portion 12 in the longitudinal direction may be roughened. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the front surface side. In addition, the terminal portion 53 of the lead portion 12 is not thinned from the front surface side.

The lead front face 12a is constituted by the inner lead front face 51a of the inner lead 51 and the terminal portion front face 53a of the terminal portion 53. The lead front surface 12a is a region which is not thinned from the surface side by half etching or the like. A lead smoothing surface region 12e as a smoothing surface region and a lead roughened surface region 12f as a roughened surface region are formed on the lead front surface 12a.

One lead smoothing surface region 12e is formed on the lead front surface 12a of each lead portion 12. A plurality of lead smoothing surface areas 12e may be formed on the lead front surface 12a of each lead portion 12. The lead smooth surface regions 12e are connected to the corresponding bumps 26 (see fig. 12). In addition, a plurality of bumps 26 may be arranged in 1 lead smoothing surface area 12e. In this case, the number of the lead smoothing surface areas 12e on each lead portion 12 may be smaller than the number of the bumps 26 connected to the lead portion 12.

Around the lead smoothing surface region 12e, a lead roughened surface region 12f is present. The lead roughened surface area 12f is roughened (S-ratio greater) than the lead smooth surface area 12e. As shown in fig. 10 (b), the lead roughened surface region 12f is formed so as to surround the entire periphery of each lead smooth surface region 12e in a plan view. That is, the lead smooth surface region 12e is not directly in contact with the peripheral edge 12g of the lead portion 12. The lead roughened surface area 12f is formed along the entire peripheral edge 12g of the lead portion 12 in a plan view. Here, as shown in fig. 8, the peripheral edge 12g of the lead portion 12 refers to an area surrounded by a plurality (three) of sides of the lead portion 12 and the connecting bar 13. In addition, the entire area of the lead front surface 12a other than the lead smooth surface area 12e may be the lead rough surface area 12f. That is, the lead front surface 12a may be constituted only by the lead smooth surface region 12e and the other lead rough surface region 12f.

As shown in fig. 10 (b), the lead smoothing surface area 12e may be circular in plan view. The shape of the lead smoothing surface region 12e may be the same as or different from the chip carrier smoothing surface region 11e described above. The lead smoothing surface area 12e is preferably larger than the bump 26 (virtual line) in a plan view. The width (diameter) D2 of the lead smooth surface region 12e may be 0.030mm or more, or 0.035mm or more. The width (diameter) D2 may be 0.070mm or less, or 0.065mm or less. When the bump 26 is disposed at the center of the lead smoothing surface area 12e, the shortest distance d2 between the peripheral edge of the bump 26 and the peripheral edge of the lead smoothing surface area 12e may be 0.005mm or more, or 0.010mm or more. The shortest distance d2 may be 0.020mm or less or 0.015mm or less. The shortest distance L2 between the lead smooth surface region 12e and the peripheral edge 12g of the lead portion 12 may be 0.025mm or more, or 0.030mm or more. The shortest distance L2 may be 1.0mm or less, or may be 0.50mm or less. By making the lead smoothing surface region 12e circular in a plan view, the circular bump 26 is easily positioned with respect to the chip carrier smoothing surface region 11 e.

The entire lead frame 10 described above is made of a metal such as copper, a copper alloy, or a 42 alloy (an Fe alloy having 42% Ni). The thickness of the portion of the lead frame 10 that is not thinned is also dependent on the structure of the semiconductor device 20 to be manufactured, but may be 80 μm or more and 300 μm or less.

In the present embodiment, the lead portions 12 are arranged along all 4 sides of the package region 10a, but the present invention is not limited thereto, and may be arranged along only 2 sides of the package region 10a that face each other, for example.

(Structure of semiconductor device)

Next, a semiconductor device according to this embodiment will be described with reference to fig. 11 to 13. Fig. 11 to 13 are diagrams showing the semiconductor device (flip chip type) of the present embodiment.

As shown in fig. 11 and 12, a semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of bumps 26, and a sealing resin 23.

The semiconductor element 21 is mounted on the die pad 11 and the lead portion 12. The plurality of bumps 26 electrically connect the semiconductor element 21 with the die pad 11 or the lead portion 12, respectively. In this case, the bump 26 constitutes a connection portion. In addition, the bump 26 may be a post. The sealing resin 23 resin-seals the die pad 11, the lead portion 12, the semiconductor element 21, and the bump 26.

The chip carrier 11 and the lead portion 12 are made of the above-described lead frame 10. In this case, the inner lead 51 of the lead portion 12 is thinned from the back surface side. The inner lead back surface 51b of the inner lead 51 is roughened. The sealing resin 23 is closely adhered to the inner lead back surface 51 b. The terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The external terminal 17 located on the rear surface of the terminal portion 53 becomes a smooth surface. The external terminal 17 is exposed outward from the sealing resin 23.

Bumps 26 are provided on the die pad 11 and the lead portion 12, respectively. Bumps 26 on the die pad 11 are disposed in the die pad smooth surface area 11e. The bump 26 is set apart from the chip-holder roughened surface area 11f by the shortest distance d 1. The bump 26 on the lead portion 12 is provided in the lead smooth surface region 12e. The bump 26 is set apart from the lead roughened surface area 12f by the shortest distance d 2. The semiconductor element 21, the die pad 11 and the lead portion 12 are electrically connected to each other via the bump 26.

The semiconductor element 21 is not particularly limited, and various semiconductor elements commonly used in the past can be used, and for example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like can be used. The semiconductor element 21 has a plurality of electrodes 21a each having a bump 26 mounted thereon.

As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as PPS resin can be used. The thickness of the entire sealing resin 23 may be 300 μm or more and 1500 μm or less. One side of the sealing resin 23 (one side of the semiconductor device 20) may be, for example, 0.2mm or more and 20mm or less, or may be 0.2mm or more and 16mm or less. In fig. 11, the portion of the sealing resin 23 on the front side of the lead portion 12 and the semiconductor element 21 is not shown.

The bump (connection portion) 26 may be made of a metal material having good conductivity, such as copper, for example, or may have a solid substantially cylindrical shape or a substantially spherical shape. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, respectively, and the lower ends of the bumps 26 are connected to the die pad smoothing surface region 11e or the lead smoothing surface region 12e, respectively. The width (diameter) of the bump 26 may be 0.01mm or more and 0.070mm or less. In addition, the bump 26 may not be provided on the chip carrier 11. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other with an adhesive such as a die bonding paste.

Fig. 13 (a) and (b) are enlarged cross-sectional views showing the periphery of the bump 26. As shown in fig. 13 (a), the bump 26 may be composed of a single layer. In this case, the bump 26 may include, for example, a metal layer such as copper. The bump 26 may be made of the same metal as the main metal (e.g., copper) included in the chip carrier 11 and the lead portion 12. The height of the bump 26 may be set to 30 μm or more and 110 μm or less.

Alternatively, as shown in fig. 13 (b), the bump 26 may include a plurality of layers. For example, the bump 26 includes: layer 1 26a located on the chip carrier 11 side or the lead portion 12 side; and a 2 nd layer 26b located on the semiconductor element 21 side. The 1 st layer 26a may contain a metal such as tin, for example. The height of the 1 st layer 26a may be 1 μm or more and 10 μm or less. The 2 nd layer 26b may contain a metal such as copper, for example. The height of the 2 nd layer 26b may be 30 μm or more and 100 μm or less.

The structures of the die pad 11 and the lead portion 12 are the same as those shown in fig. 8 to 10 described above except that they are not included in the region of the semiconductor device 20, and therefore, a detailed description thereof will be omitted here.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10 shown in fig. 8 and 9 will be described with reference to (a) to (i) of fig. 14. Fig. 14 (a) - (i) are cross-sectional views (corresponding to fig. 9) showing a manufacturing method of the lead frame 10.

First, as shown in fig. 14 (a), a flat metal substrate 31 is prepared. As the metal substrate 31, a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Fe alloy having 42% Ni) can be used. In addition, it is preferable to use a substrate which is subjected to a cleaning treatment such as degreasing on both surfaces of the metal substrate 31.

Next, photosensitive resists 32a and 33a are applied to the entire front and rear surfaces of the metal substrate 31, respectively, and dried (fig. 14 (b)). As the photosensitive resists 32a and 33a, conventionally known photosensitive resists can be used.

Next, the metal substrate 31 is exposed to light through a photomask and developed, whereby etching resist layers 32 and 33 having desired openings 32b and 33b are formed (fig. 14 (c)).

Next, the metal substrate 31 is etched with an etchant using the etching resist layer 32 and the etching resist layer 33 as the corrosion-resistant film ((d) of fig. 14). The etching liquid may be appropriately selected according to the material of the metal substrate 31 to be used. For example, in the case of using copper as the metal substrate 31, spray etching may be performed from both sides of the metal substrate 31, usually using an aqueous solution of ferric chloride as an etching solution. Thus, the outer shapes of the chip carrier 11, the lead portions 12, and the connection bars 13 are formed. At this time, a part of the lead portion 12 is thinned from the back side by half etching. Specifically, the back surface of the inner lead 51 of the lead portion 12 is thinned.

Next, the etching resist layers 32 and 33 are peeled off and removed ((e) of fig. 14). Thus, a metal substrate 31 having the die pad 11 and the lead portions 12 located around the die pad 11 is obtained.

Next, a plating layer 36 is formed on a part of the metal substrate 31 (fig. 14 (f)). At this time, first, an elastic member 46 such as a rubber gasket having openings with a predetermined pattern is disposed on the front surface of the metal substrate 31. The opening of the elastic member 46 has a shape corresponding to the chip-holder smooth surface region 11e and the lead smooth surface region 12 e. Then, the tool 47 presses the front surface of the metal substrate 31 through the elastic member 46. The tool 47 has openings in the same pattern as the elastic member 46. Next, the plating layer 36 is formed at a portion of the front surface of the metal substrate 31 not covered with the elastic member 46 and the tool 47. Thus, the plating layer 36 is formed on the portion of the die pad 11 corresponding to the die pad smooth surface region 11e and the portion of the lead portion 12 corresponding to the lead smooth surface region 12 e. The thickness of the plating layer 36 may also exceed 0 μm and be less than 2 μm. As the metal constituting the plating layer 36, silver, for example, can be used. When the plating layer 36 is a silver plating layer, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as the plating solution for plating.

Next, the elastic member 46 and the tool 47 are removed. Further, a support layer 37 for supporting the metal substrate 31 is provided on the back surface side of the metal substrate 31 (fig. 14 (g)). The support layer 37 may be, for example, a resist layer.

Next, as shown in fig. 14 (h), a roughened surface is formed at a portion of the metal substrate 31 that is not covered with the plating layer 36 and the support layer 37 by roughening the portion. Specifically, the die pad roughened surface region 11f and the lead roughened surface region 12f are formed on the metal substrate 31, respectively. The 1 st die pad side surface 11c, the 2 nd die pad side surface 11d, the inner lead end surface 51c, and the inner lead back surface 51b are roughened surfaces. During this period, by supplying the microetching solution to the metal substrate 31, a roughened surface is formed on the entire metal substrate 31 except for the portion covered with the plating layer 36 and the supporting layer 37. The microetching solution is a surface treatment agent that slightly dissolves the metal surface to form a roughened surface having fine irregularities. For example, when roughening the metal substrate 31 made of copper or copper alloy, a microetching solution containing hydrogen peroxide water and sulfuric acid as main components may be used.

Next, as shown in fig. 14 (i), the support layer 37 and the plating layer 36 are sequentially peeled off and removed, thereby obtaining the lead frame 10 shown in fig. 8 and 9.

(method for manufacturing semiconductor device)

Next, a method for manufacturing the semiconductor device 20 shown in fig. 11 and 12 will be described with reference to (a) to (d) of fig. 15. Fig. 15 (a) - (d) are cross-sectional views (corresponding to fig. 12) showing a method of manufacturing the semiconductor device 20.

First, the lead frame 10 is manufactured by, for example, the methods shown in fig. 14 (a) - (i) (fig. 15 (a)).

Next, the semiconductor element 21 is mounted on the die pad 11 and the lead portion 12 of the lead frame 10. In this case, bumps 26 are formed on the electrodes 21a of the semiconductor element 21, respectively, in advance. Next, the bumps 26 are connected and fixed to the chip carrier 11 and the lead portions 12, respectively (fig. 15 b). At this time, the electrodes 21a of the semiconductor element 21 and the chip carrier 11 and the lead portion 12 are electrically connected to each other via the bump 26. Bumps 26 on the die pad 11 are connected to the die pad smooth surface area 11 e. At this time, the bump 26 is provided separately from the chip-holder roughened surface area 11 f. The bump 26 on the lead portion 12 is connected to the lead smooth surface region 12 e. At this time, the bump 26 is provided separately from the lead roughened surface area 12 f.

Next, the sealing resin 23 is formed by injection molding or transfer molding a thermosetting resin or a thermoplastic resin to the lead frame 10 (fig. 15 (c)). Thereby, the die pad 11, the lead portion 12, the semiconductor element 21, and the bump 26 are resin-sealed.

Then, the lead frame 10 and the sealing resin 23 are cut for each package region 10 a. Thus, the lead frame 10 is separated for each semiconductor device 20, and the semiconductor device 20 shown in fig. 11 and 12 is obtained ((d) of fig. 15).

However, it is conceivable that: during long-term use of the semiconductor device 20 thus manufactured, moisture and the like in the air intrude from the side surface side or the back surface side of the semiconductor device 20 through the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12.

In contrast, according to the present embodiment, the chip-holder roughened surface region 11f is present so as to surround the entire circumference of the chip-holder smooth surface region 11 e. Similarly, the lead roughened surface region 12f is present so as to surround the entire circumference of the lead smooth surface region 12 e. Therefore, the distance of the moisture penetration path at the interface of the die pad front surface 11a or the lead front surface 12a and the sealing resin 23 becomes longer outside the bump 26. This can suppress intrusion of moisture from the interface between the die pad front surface 11a or the lead front surface 12a and the sealing resin 23 toward the semiconductor element 21 (see arrow F in fig. 16) _A ). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

In addition, according to the present embodiment, the chip-holder smooth surface region 11e adjacent to the outer side of the bump 26 in the chip-holder front surface 11a becomes a smooth surface. In addition, the lead smoothing surface region 12e adjacent to the outer side of the bump 26 in the lead front surface 12a becomes a smoothing surface.

In this way, when the bump 26 is formed of a single metal layer such as copper (see fig. 13 (a)), the following effects can be obtained. That is, when the semiconductor element 21 is mounted on the die pad 11 and the lead portion 12, the close adhesion between the bump 26 and the die pad 11 and the lead portion 12 can be improved. On the other hand, if the surfaces of the die pad 11 and the lead portion 12 to which the bump 26 is connected are roughened surfaces, the contact area between the bump 26 and the roughened surfaces becomes small due to the influence of an oxide film (for example, copper oxide) formed on the roughened surfaces. In this case, the bonding strength between the bump 26 and the chip carrier 11 and the lead portion 12 may be weakened.

In addition, when the bump 26 contains a metal such as tin (see fig. 13 (b)), the following effects can be obtained. That is, when the semiconductor element 21 is mounted on the die pad 11 and the lead portion 12, the outflow of tin or the like contained in the bump 26 along the rough surface can be suppressed. On the other hand, if the portion adjacent to the outer side of the bump 26 is a rough surface, there is a possibility that tin or the like contained in the bump 26 flows out along the rough surface due to surface tension.

In addition, according to the present embodiment, the chip-holder roughened surface area 11f is formed along the entire area of the peripheral edge 11g of the chip holder 11 in a plan view. The lead roughened surface area 12f is formed along the entire peripheral edge 12g of the lead portion 12 in a plan view. This can more effectively suppress the intrusion of moisture from the interface between the die pad front surface 11a or the lead front surface 12a and the sealing resin 23 toward the semiconductor element 21.

In addition, according to the present embodiment, the inner lead back surface 51b and the inner lead distal end surface 51c of the lead portion 12 are roughened. The 1 st die pad side surface 11c and the 2 nd die pad side surface 11d of the die pad 11 are roughened surfaces, respectively. Therefore, the distance between the sealing resin 23 and the moisture penetration path at the interface between the chip carrier 11 and the lead portion 12 becomes longer. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 16) _B ). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

In particular, in the flip-chip type semiconductor device 20, the electrode 21a of the semiconductor element 21 faces the back surface side. Therefore, in the flip-chip type semiconductor device 20, the distance from the back surface of the semiconductor device 20 to the electrode 21a of the semiconductor element 21 is easily shortened. In contrast, according to the present embodiment, the thinned portion of the back surface of the lead portion 12 is roughened. This can more effectively suppress the intrusion of moisture from the interface between the sealing resin 23 and the lead portion 12 toward the semiconductor element 21.

In addition, according to the present embodiment, the inner lead back surface 51b and the inner lead distal end surface 51c of the lead portion 12 are roughened. The 1 st die pad side surface 11c and the 2 nd die pad side surface 11d of the die pad 11 are roughened surfaces, respectively. This can improve the adhesion strength between the die pad 11 and the lead portion 12 and the sealing resin 23, and can prevent the die pad 11 and the lead portion 12 from being peeled off from the sealing resin 23.

(modification)

Next, a modified example of the die pad smoothing surface region 11e and the lead smoothing surface region 12e will be described with reference to fig. 17 (a) to (d). Fig. 17 (a) - (d) are enlarged plan views showing the chip-holder smooth surface region 11e and the lead smooth surface region 12e (hereinafter, also simply referred to as smooth surface regions 11e, 12 e), and the chip-holder rough surface region 11f and the lead rough surface region 12f (hereinafter, also simply referred to as rough surface regions 11f, 12 f), respectively.

As shown in fig. 17 (a), the smooth surface areas 11e, 12e may be square or rectangular in plan view. The width (length of each side) D3 of the smooth surface regions 11e, 12e may be 0.030mm or more, or 0.035mm or more. The width D3 may be 0.070mm or less, or 0.065mm or less. When the bump 26 is disposed at the center of the smooth surface areas 11e, 12e, the shortest distance d3 between the peripheral edge of the bump 26 and the peripheral edge of the smooth surface areas 11e, 12e may be 0.005mm or more, or 0.010mm or more. The shortest distance d3 may be 0.020mm or less or 0.015mm or less. The shortest distance L3 between the smooth surface areas 11e, 12e and the peripheral edge 11g of the die pad 11 or the peripheral edge 12g of the lead portion 12 may be 0.025mm or more, or 0.030mm or more. The shortest distance L3 may be 1.0mm or less or 0.50mm or less. By forming the smooth surface regions 11e and 12e to have a square or rectangular shape in a plan view, the shortest distance (interval) d3 between the peripheral edge of the bump 26 and the peripheral edge of the smooth surface regions 11e and 12e can be sufficiently ensured.

As shown in fig. 17 (b), the smooth surface regions 11e and 12e may be square or rectangular in plan view, and a plurality of bumps 26 may be arranged in 1 smooth surface region 11e and 12 e. The length D4a of the long sides of the smooth surface regions 11e, 12e may be 0.045mm or more, or 0.065mm or more. The length D4a may be 0.12mm or less, or 0.10mm or less. The length D4b of the short sides of the smooth surface regions 11e, 12e may be 0.030mm or more, or 0.035mm or more. The length D4b may be 0.070mm or less, or 0.065mm or less. When the bumps 26 are arranged at the centers of the smooth surface areas 11e and 12e in the short side direction, the shortest distance d4 between the peripheral edge of the bump 26 and the peripheral edge of the smooth surface areas 11e and 12e in the short side direction may be 0.005mm or more, or 0.010mm or more. The shortest distance d4 may be 0.020mm or less or 0.015mm or less. The shortest distance L4 between the smooth surface regions 11e and 12e and the peripheral edge 11g of the die pad 11 or the peripheral edge 12g of the lead portion 12 may be 0.025mm or more, or 0.030mm or more. The shortest distance L4 may be 1.0mm or less or 0.50mm or less. By forming the smooth surface regions 11e and 12e to have a square or rectangular shape in a plan view, the shortest distance (interval) d4 between the peripheral edge of the bump 26 and the peripheral edge of the smooth surface regions 11e and 12e can be sufficiently ensured. Further, two or more bumps 26 adjacent to each other may be provided in each of the smooth surface areas 11e and 12 e.

As shown in fig. 17 (c), the smooth surface regions 11e and 12e may be elliptical or oblong in plan view, and a plurality of bumps 26 may be arranged in 1 smooth surface region 11e and 12 e. The length D5a of the smooth surface regions 11e, 12e in the longitudinal direction may be 0.045mm or more, or may be 0.065mm or more. The length D5a may be 0.12mm or less, or 0.10mm or less. The length D5b of the smooth surface regions 11e, 12e in the short side direction may be 0.030mm or more, or 0.035mm or more. The length D5b may be 0.070mm or less, or 0.065mm or less. When the bumps 26 are arranged at the centers of the smooth surface areas 11e, 12e in the short-side direction, the shortest distance d5 between the peripheral edges of the bumps 26 and the peripheral edges of the smooth surface areas 11e, 12e may be 0.005mm or more, or 0.010mm or more. The shortest distance d5 may be 0.020mm or less or 0.015mm or less. The shortest distance L5 between the smooth surface regions 11e and 12e and the peripheral edge 11g of the die pad 11 or the peripheral edge 12g of the lead portion 12 may be 0.025mm or more, or 0.030mm or more. The shortest distance L5 may be 1.0mm or less or 0.50mm or less. By making the smooth surface regions 11e and 12e elliptical or oblong in plan view, two or more projections 26 adjacent to each other can be provided in each smooth surface region 11e and 12 e.

As shown in fig. 17 (d), the peripheral edges of the smooth surface regions 11e and 12e may be closed patterns including the curve Cv and the line Ls in a plan view. The smooth surface regions 11e and 12e may be formed by removing a part of a circle or an ellipse, for example, a semicircle or a semi-ellipse. The line segment Ls constituting the peripheral edge of the smooth surface areas 11e, 12e may be parallel to the peripheral edge 11g of the chip carrier 11 or the peripheral edge 12g of the lead portion 12. The length D6a of the smooth surface regions 11e, 12e in the direction perpendicular to the line segment Ls may be 0.030mm or more, or 0.050mm or more. The length D6a may be 0.12mm or less, or 0.10mm or less. The length D6b of the smooth surface regions 11e, 12e in the direction parallel to the line segment Ls may be 0.030mm or more, or 0.035mm or more. The length D6b may be 0.070mm or less, or 0.065mm or less. When the bumps 26 are arranged at the centers of the directions parallel to the line segment Ls and the directions orthogonal to the line segment Ls in the smooth surface areas 11e and 12e, the shortest distance d6 between the peripheral edge of the bump 26 and the peripheral edge of the smooth surface areas 11e and 12e may be 0.005mm or more, or 0.010mm or more. The shortest distance d6 may be 0.020mm or less or 0.015mm or less. The shortest distance L6 between the smooth surface regions 11e and 12e and the peripheral edge 11g of the die pad 11 or the peripheral edge 12g of the lead portion 12 may be 0.025mm or more, or 0.030mm or more. The shortest distance L6 may be 1.0mm or less or 0.50mm or less. By forming the smooth surface regions 11e and 12e as a closed pattern including the curve Cv and the line Ls in a plan view, the shortest distance L6 between the smooth surface regions 11e and 12e and the peripheral edge 11g of the chip carrier 11 or the peripheral edge 12g of the lead portion 12 can be ensured to be equal to or longer than a predetermined distance.

(embodiment 3)

Next, embodiment 3 will be described with reference to fig. 18 to 25. Fig. 18 to 25 are diagrams showing embodiment 3. In fig. 18 to 25, the same reference numerals are given to the same portions as those in the manner shown in fig. 8 to 17, and detailed description thereof is omitted.

(Structure of lead frame)

First, an outline of the lead frame of the present embodiment will be described with reference to fig. 18 and 19. Fig. 18 and 19 are diagrams showing the lead frame according to the present embodiment.

In the present specification, the "outer periphery" refers to a portion of the lead frame 10 (metal substrate) exposed to the outside, and is a region including the "front face", "side face", and "back face".

As shown in fig. 18 and 19, each package region 10a of the lead frame 10 includes a die pad 11 and a lead portion 12 located around the die pad 11. A portion of the lead portion 12 is thinned from the back surface side. The thinned portion of the back surface of the lead portion 12 is roughened. The portion of the back surface of the lead portion 12 that is not thinned becomes a smooth surface.

As shown in fig. 19, the die pad 11 has a die pad front surface 11a on the front surface side and a die pad back surface 11b on the back surface side. In this case, the chip-holder front surface 11a, the 1 st chip-holder side surface 11c, and the 2 nd chip-holder side surface 11d in the chip-holder 11 are roughened surfaces, respectively. On the other hand, the chip-holder back surface 11b of the chip-holder 11 is a smooth surface.

As shown in fig. 19, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner leads 51 are located on the inner side (chip carrier 11 side). The terminal portion 53 is located outside (the connection bar 13 side). The inner leads 51 extend from the terminal portions 53 toward the chip carrier 11. An internal terminal is formed at the front end of the inner lead 51. As will be described later, the internal terminals are regions electrically connected to the semiconductor element 21 via the bumps 26.

The inner lead 51 is thinned from the back side by, for example, half etching. The inner lead 51 has an inner lead front face 51a and an inner lead back face 51b. The inner lead front face 51a is located on the front face side. An internal terminal is formed on a part of the inner lead front surface 51 a. Further, an inner lead distal end surface 51c is formed on a surface of the inner lead 51 facing the chip carrier 11. The inner lead back surface 51b is located on the back surface side.

The entire area of the inner lead distal end face 51c of the lead portion 12 is a roughened surface. Although not shown, both side surfaces of the lead portion 12 in the longitudinal direction may be roughened. On the other hand, the inner leads 51 of the lead portion 12 are not thinned from the front side. The entire area of the inner lead front face 51a of the inner lead 51 on the front face side is a roughened surface. The terminal portion 53 of the lead portion 12 is not thinned from the front side. The entire area of the terminal portion front surface 53a of the terminal portion 53 on the front side is a roughened surface.

The structure of the lead frame 10 of the present embodiment may be the same as that of the lead frame 10 of embodiment 2.

In this embodiment, the definition of "rough surface" and "smooth surface" and the measurement method are the same as those in embodiment 2.

(Structure of semiconductor device)

Next, a semiconductor device according to this embodiment will be described with reference to fig. 20 to 22. Fig. 20 to 22 are diagrams showing the semiconductor device (flip chip type) of the present embodiment.

As shown in fig. 20 and 21, a semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of bumps 26, and a sealing resin 23.

The semiconductor element 21 is mounted on the die pad 11. In addition, a plurality of lead portions 12 are arranged around the chip carrier 11. The plurality of bumps 26 electrically connect the semiconductor element 21 with the die pad 11 or the lead portion 12, respectively. In this case, the bump 26 constitutes a connection portion. In addition, the bump 26 may be a post. The sealing resin 23 resin-seals the die pad 11, the lead portion 12, the semiconductor element 21, and the bump 26.

Bumps 26 are provided on the die pad 11 and the lead portion 12. The semiconductor element 21 is electrically connected to the die pad 11 and the lead portion 12 via the bump 26.

The bump (connection portion) 26 is made of a metal material having good conductivity, such as copper, and may have a solid substantially cylindrical shape or a substantially spherical shape. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, respectively, and the lower ends of the bumps 26 are connected to the chip carrier 11 and the lead portions 12, respectively. In addition, the bump 26 may not be provided on the chip carrier 11. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other with an adhesive such as a die bonding paste.

Fig. 22 is an enlarged cross-sectional view showing the periphery of the bump 26. As shown in fig. 22, the bump 26 may also comprise multiple layers. For example, the bump 26 includes a 1 st layer 26a located on the chip carrier 11 or the lead portion 12 side, and a 2 nd layer 26b located on the semiconductor element 21 side. The 1 st layer 26a may contain a metal such as tin, for example. The height of the 1 st layer 26a may be 1 μm or more and 10 μm or less. The 2 nd layer 26b may contain a metal such as copper, for example. The height of the 2 nd layer 26b may be 30 μm or more and 100 μm or less.

The semiconductor device 20 is not limited to the flip-chip type. For example, the connection portion may be constituted by a connection wire instead of the bump 26. In this case, the connection line may electrically connect the semiconductor element 21 and the lead portion 12 to each other.

The structure of the semiconductor device 20 of the present embodiment may be the same as that of the semiconductor device 20 of embodiment 2.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10 shown in fig. 18 and 19 will be described with reference to (a) to (i) of fig. 23. Fig. 23 (a) - (i) are cross-sectional views (corresponding to fig. 19) showing a manufacturing method of the lead frame 10.

First, as in the case of embodiment 2 (fig. 14 (a) - (e)), a metal substrate 31 having a chip carrier 11 and a lead portion 12 located around the chip carrier 11 is produced (fig. 23 (a) - (e)).

Next, a plating layer 36 is formed on a part of the outer periphery of the metal substrate 31 (fig. 23 (f)). At this time, the plating layer 36 is formed in the outer peripheral region of the metal substrate 31 except the entire front surface region. That is, the plating layer 36 is not formed over the entire front surface of the metal substrate 31, but over the entire rear surface and the entire side surface of the metal substrate 31. More specifically, the plating layer 36 is not formed on the chip carrier front face 11a of the chip carrier 11, the inner lead front face 51a of the lead portion 12, and the terminal portion front face 53a. On the other hand, the plating layer 36 is formed on the die pad back surface 11b, the 1 st die pad side surface 11c, and the 2 nd die pad side surface 11d of the die pad 11. The plating layer 36 is formed on the external terminal 17, the inner lead back surface 51b, and the inner lead distal end surface 51c of the lead portion 12. The plating layer 36 may not be formed on the front surface of the connection bar 13. The plating layer 36 may be formed on the back surface of the connection bar 13.

At this time, as shown in fig. 23 (f), the entire front surface of the metal substrate 31 is covered with the 1 st clamp 45 via an elastic member 44 such as a rubber gasket. By performing electroplating on the metal substrate 31 in this state, the plating layer 36 is formed in the metal substrate 31 except for the entire front surface area. The thickness of the plating layer 36 may also exceed 0 μm and be less than 2 μm. As the metal constituting the plating layer 36, silver, for example, may be used. When the plating layer 36 is a silver plating layer, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as a plating solution for plating. In this way, the plating layer 36 is not formed over the entire front surface of the metal substrate 31, and thus the amount of metal such as silver that constitutes the plating layer 36 can be reduced. This can reduce the manufacturing cost of the lead frame 10.

Next, a part of the plating layer 36 existing in the region where the roughened surface is formed is removed. Specifically, the plating layer 36 existing on at least the rear surface of the metal substrate 31 is left, and the other plating layer 36 is removed ((g) of fig. 23). Specifically, the portion of the plating layer 36 existing on the side surface of the metal substrate 31 is removed. Thereby, the plating 36 on the 1 st chip carrier side 11c and the 2 nd chip carrier side 11d of the chip carrier 11 is removed. The plating 36 on the inner lead distal end surface 51c and the inner lead back surface 51b of the lead portion 12 is removed.

During this time, as shown in fig. 23 (g), first, an elastic member 46 such as a rubber gasket is disposed on the rear surface of the metal substrate 31, and a 2 nd jig 47A is disposed on the rear surface side of the metal substrate 31 via the elastic member 46. Then, the plating layer 36 of the portion not covered with the elastic member 46 is peeled off and removed. Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the inner lead end surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plating 36 on the chip carrier back surface 11b and the external terminals 17 covered by the elastic member 46 remains.

Next, as shown in fig. 23 (h), a support layer 37 for supporting the metal substrate 31 is provided on the back surface side of the metal substrate 31. The support layer 37 may be, for example, a resist layer. Next, as shown in fig. 23 (h), the portion of the metal substrate 31 not covered with the plating layer 36 is roughened, whereby a roughened surface is formed at the portion not covered with the plating layer 36. Specifically, the die pad front surface 11a, the 1 st die pad side surface 11c, the 2 nd die pad side surface 11d, the inner lead front surface 51a, the terminal portion front surface 53a, the inner lead distal end surface 51c, and the inner lead back surface 51b are roughened surfaces, respectively. During this period, the microetching solution is supplied to the metal substrate 31, whereby a roughened surface is formed on the entire metal substrate 31 except for the portion covered with the plating layer 36. The microetching solution is a surface treatment agent that slightly dissolves the metal surface to form a roughened surface having fine irregularities. For example, when roughening the metal substrate 31 made of copper or copper alloy, a microetching solution containing hydrogen peroxide water and sulfuric acid as main components may be used.

Next, as shown in fig. 23 (i), the support layer 37 and the plating layer 36 are sequentially peeled off and removed, thereby obtaining the lead frame 10 shown in fig. 18 and 19.

(method for manufacturing semiconductor device)

As shown in fig. 24 (a) to (d), the method for manufacturing the semiconductor device 20 according to the present embodiment can be performed substantially in the same manner as the method for manufacturing the semiconductor device 20 according to embodiment 2. In this case, each electrode 21a of the semiconductor element 21 is electrically connected to the chip carrier 11 and the lead portion 12 via the bump 26.

As described above, according to the present embodiment, the plating layer 36 is formed in the region other than the front surface in the metal substrate 31 ((f) of fig. 24). Next, the plating layer 36 existing on the rear surface of the metal substrate 31 is left, and the other plating layer 36 is removed (fig. 24 g). Thereafter, a roughened surface is formed at a portion of the metal substrate 31 not covered with the plating layer 36 (fig. 24 (h)). In this way, the plating layer 36 for forming the roughened surface is not provided on the entire surface of the metal substrate 31, but is provided in a region other than the front surface in the metal substrate 31. This can reduce the amount of metal such as silver used for the plating layer 36. As a result, the manufacturing cost of the lead frame 10 can be reduced.

However, it is conceivable that: during long-term use of the semiconductor device 20 thus manufactured, moisture and the like in the air intrude from the back surface side of the semiconductor device 20 through the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12. In contrast, according to the present embodiment, the inner lead back surface 51b and the inner lead distal end surface 51c of the lead portion 12 are roughened. The 1 st die pad side surface 11c and the 2 nd die pad side surface 11d of the die pad 11 are roughened surfaces, respectively. Therefore, the distance between the sealing resin 23 and the moisture penetration path at the interface between the chip carrier 11 and the lead portion 12 becomes longer. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 25) _A ). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

(embodiment 4)

Next, embodiment 4 will be described with reference to fig. 26 to 29. Fig. 26 to 29 are diagrams showing embodiment 4. The difference between embodiment 4 shown in fig. 26 to 29 is mainly that: the metal layer 25 is provided on the front surface of the die pad 11 and the lead portion 12, and the other structures are substantially the same as those of embodiment 3 described above. In fig. 26 to 29, the same reference numerals are given to the same parts as those of embodiment 2 shown in fig. 8 to 17 and embodiment 3 shown in fig. 18 to 25, and detailed description thereof is omitted.

(Structure of lead frame and semiconductor device)

Fig. 26 is a cross-sectional view showing the lead frame 10A of the present embodiment, and fig. 27 is a cross-sectional view showing the semiconductor device 20A of the present embodiment.

In the lead frame 10A shown in fig. 26 and the semiconductor device 20A shown in fig. 27, the metal layer 25 is located on a part of the die pad 11 and a part of the lead portion 12. Specifically, a plurality of metal layers 25 for improving the adhesion with the bumps 26 are provided on the chip-holder front surface 11a of the chip holder 11. Further, a metal layer 25 for improving the adhesion with the bump 26 is provided on the inner terminal of the lead portion 12 formed on the inner lead 51.

The metal layer 25 is used to make the bump 26 well connected to the chip carrier 11 and the lead portion 12. The metal layer 25 may be, for example, a plating layer formed by an electroplating method. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. As a metal constituting such a plating layer, silver alloy, gold alloy, platinum group, copper alloy, palladium, or the like can be used. When the base plating is required, a known material such as nickel or copper may be used depending on the metal constituting the metal layer 25.

As shown in fig. 26 and 27, the front surface of the lead portion 12 has a 1 st front surface portion 56a as a smooth surface and a 2 nd front surface portion 56b as a rough surface. The 1 st front surface portion 56a is located at an inner side (chip carrier 11 side) end of the lead portion 12. A metal layer 25 is formed on the 1 st front surface portion 56 a. The entirety of the 1 st front portion 56a is a smooth surface. In addition, the 1 st front surface portion 56a is located at a part of the inner lead front surface 51 a.

The 2 nd front portion 56b is adjacent to the 1 st front portion 56a and the outside of the metal layer 25 (opposite side of the die pad 11). The 2 nd front portion 56b is directly connected to the 1 st front portion 56a and the metal layer 25. The entirety of the 2 nd front portion 56b is a roughened surface. In addition, in the lead frame 10A, the 2 nd front portion 56b preferably extends continuously to the connection portion of the lead portion 12 and the connection bar 13. The front face of the connecting strip 13 may be roughened. In addition, the 2 nd front surface portion 56b is located at a part of the inner lead front surface 51a and a part of the terminal portion front surface 53 a.

As shown in fig. 27, in the semiconductor device 20A, bumps 26 are provided on the metal layer 25. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, respectively, and the lower ends of the bumps 26 are connected to the chip carrier 11 and the lead portions 12, respectively, via the metal layer 25. In addition, the metal layer 25 and the bump 26 may not be provided on the chip carrier 11.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10A shown in fig. 26 will be described with reference to (a) to (j) of fig. 28. In fig. 28 (a) - (j), the same reference numerals are given to the same parts as those of the structures shown in fig. 23 (a) - (i), and detailed description thereof is omitted.

First, as in the case of embodiment 2 (fig. 14 (a) - (e)), a metal substrate 31 having a chip carrier 11 and a lead portion 12 located around the chip carrier 11 is produced (fig. 28 (a) - (e)).

Next, a plating layer 36 is formed in a region of the metal substrate 31 except for a part of the front surface (fig. 28 (f)). At this time, the plating layer 36 is formed on a part of the front surface, the entire rear surface, and the entire side surface of the metal substrate 31. In addition, the plating layer 36 is formed on a part of the front surface of the chip carrier 11 and a part of the front surface of the lead portion 12. More specifically, the plating layer 36 is formed in the region of the die pad front surface 11a of the die pad 11 where the metal layer 25 is formed, and is not formed in regions other than the region where the metal layer 25 is formed. The plating layer 36 is formed on the die pad back surface 11b, the 1 st die pad side surface 11c, and the 2 nd die pad side surface 11d of the die pad 11. The plating layer 36 is formed on the 1 st front surface portion 56a of the lead portion 12, the external terminal 17, the inner lead back surface 51b, and the inner lead end surface 51c. On the other hand, the plating layer 36 is not formed on the 2 nd front portion 56b of the lead portion 12. The plating layer 36 may not be formed on the front surface of the connecting bar 13, but may be formed on the back surface of the connecting bar 13.

At this time, as shown in fig. 28 (f), a part of the front surface of the metal substrate 31 is covered with the 1 st clamp 45A via an elastic member 44A such as a rubber gasket. By performing electroplating on the metal substrate 31 in this state, the plating layer 36 is formed in the metal substrate 31 except for a part of the front surface. In this way, by not forming the plating layer 36 on a part of the front surface of the metal substrate 31, the amount of metal such as silver constituting the plating layer 36 can be reduced. This can reduce the manufacturing cost of the lead frame 10A. In addition, the material and thickness of the plating layer 36 can be the same as those in the case of embodiment 3.

Next, a part of the plating layer 36 existing in the region where the roughened surface is formed is removed ((g) of fig. 28). At this time, the plating layer 36 existing on a part of the front surface and the back surface of the metal substrate 31 is removed, and the other plating layer 36 is removed. Specifically, portions of the plating layer 36 corresponding to the 1 st die pad side surface 11c, the 2 nd die pad side surface 11d, the inner lead end surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed.

During this time, as shown in fig. 28 (g), first, the elastic members 46 are disposed on the front and rear surfaces of the metal substrate 31, respectively, and the metal substrate 31 is held by the 2 nd jig 47B via the elastic members 46 such as rubber gaskets. Further, the elastic member 46 on the front side of the metal substrate 31 covers the entire area on the front side of the metal substrate 31. Then, the plating layer 36 of the portion not covered with the elastic member 46 is peeled off and removed. Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the inner lead end surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plated layer 36 on the chip carrier front surface 11a, the chip carrier back surface 11b, the 1 st front surface portion 56a, and the external terminals 17 covered by the elastic member 46 remains.

Next, a support layer 37 is provided on the back surface side of the metal substrate 31 in substantially the same manner as in the step (h) of fig. 23 described above. Next, by roughening the portion of the metal substrate 31 not covered with the plating layer 36, a roughened surface is formed at the portion not covered with the plating layer 36 ((h) of fig. 28). Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the 2 nd front portion 56b, the inner lead end face 51c, and the inner lead back face 51b are roughened.

Next, the supporting layer 37 and the plating layer 36 are peeled off and removed in this order substantially as in the step shown in fig. 23 (i) (fig. 28 (i)).

Then, as shown in fig. 28 (j), a metal layer 25 is formed on a part of the front surface of the metal substrate 31. Specifically, the metal layer 25 is formed on a part of the chip carrier 11 and a part of the lead portion 12. In this case, first, a plating resist layer of a predetermined pattern, not shown, is formed on the chip carrier 11 and the lead portion 12 by, for example, photolithography. Next, a metal layer 25 made of a plating layer is formed at a portion not covered with the plating resist layer, for example, by a plating method. Then, the plating resist layer is removed, whereby the lead frame 10A shown in fig. 26 is obtained.

(method for manufacturing semiconductor device)

The method for manufacturing the semiconductor device 20A according to the present embodiment can be performed substantially in the same manner as the method for manufacturing the semiconductor device 20 shown in (a) to (d) of fig. 24. In this case, each electrode 21a of the semiconductor element 21 is electrically connected to the chip carrier 11 and the lead portion 12 via the bump 26 and the metal layer 25, respectively.

As described above, according to the present embodiment, the plating layer 36 is formed in the metal substrate 31 except for a part of the front surface ((f) of fig. 28). Next, a plating layer 36 existing on a part of the front surface and the back surface of the metal substrate 31 is left, and the other plating layer 36 is removed ((g) of fig. 28). Then, a roughened surface is formed at a portion of the metal substrate 31 not covered with the plating layer 36 ((h) of fig. 28). In this way, the plating layer 36 for forming the roughened surface is not provided on the entire surface of the metal substrate 31, but is provided in a region of the metal substrate 31 other than a part of the front surface. This can reduce the amount of metal such as silver used for the plating layer 36. As a result, the manufacturing cost of the lead frame 10 can be reduced.

In addition, according to the present embodiment, the 2 nd front surface portion 56b adjacent to the outside of the metal layer 25 becomes a rough surface. Therefore, the distance between the surface of the lead portion 12 and the moisture penetration path at the interface of the sealing resin 23 becomes longer. This can suppress intrusion of moisture from the interface between the surface of the lead portion 12 and the sealing resin 23 toward the semiconductor element 21 (see arrow F in fig. 29) _B ). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

In addition, according to the present embodiment, the 2 nd front surface portion 56b of the lead portion 12 is roughened. This can improve the adhesion strength between the 2 nd front surface portion 56b and the sealing resin 23, and can prevent the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

In addition, according to the present embodiment, the distance of the moisture penetration path at the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 becomes longer on the back surface side of the semiconductor device 20A. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 29) _A ). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

(embodiment 5)

Embodiment 5 will be described with reference to fig. 30 to 37. Fig. 30 to 37 are diagrams showing embodiment 5. In fig. 30 to 37, the same reference numerals are given to the same parts as those of the embodiment shown in fig. 8 to 29, and detailed description thereof is omitted.

(Structure of lead frame)

First, an outline of the lead frame of the present embodiment will be described with reference to fig. 30 and 31. Fig. 30 and 31 are diagrams showing the lead frame according to the present embodiment.

As shown in fig. 30 and 31, each package region 10a of the lead frame 10 includes a die pad 11 and a lead portion 12 located around the die pad 11. A portion of the lead portion 12 is thinned from the back surface side. The thinned portion of the back surface of the lead portion 12 is roughened. The portion of the back surface of the lead portion 12 that is not thinned becomes a smooth surface.

As shown in fig. 31, the die pad 11 has a die pad front surface 11a on the front surface side and a die pad back surface 11b on the back surface side. The semiconductor element 21 is mounted on the front surface 11a of the die pad as will be described later. The chip-holder rear surface 11b is exposed outward from the semiconductor device 20 (described later). In addition, a 1 st chip-carrier side surface 11c and a 2 nd chip-carrier side surface 11d are formed on the side of the chip carrier 11 facing the lead portion 12. The 1 st chip carrier side 11c is located on the chip carrier front 11a side. The 2 nd die pad side 11d is located on the die pad back 11b side. In this case, the 1 st chip carrier side surface 11c and the 2 nd chip carrier side surface 11d of the chip carrier 11 are roughened surfaces, respectively. On the other hand, the chip-holder front surface 11a and the chip-holder back surface 11b of the chip-holder 11 are respectively smooth surfaces.

The roughened surface may be formed by roughening the outer surface of the metal substrate 31 described later with a microetching solution containing hydrogen peroxide and sulfuric acid as main components. The smooth surface may be an unprocessed surface which is not subjected to such roughening treatment on the metal substrate 31 described later. In fig. 31, the roughened portion is indicated by a thick dotted line (the same applies to other cross-sectional views).

As shown in fig. 31, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner leads 51 are located on the inner side (chip carrier 11 side). The terminal portion 53 is located outside (the connection bar 13 side). The inner leads 51 extend from the terminal portions 53 toward the chip carrier 11. An internal terminal is formed at the front end of the inner lead 51. As will be described later, the internal terminals are regions electrically connected to the semiconductor element 21 via the bumps 26. A metal layer 25 for improving the close adhesion with the bump 26 is provided on the internal terminal.

Further, the entire area of the inner lead distal end face 51c of the lead portion 12 is roughened. Although not shown, both side surfaces of the lead portion 12 in the longitudinal direction may be roughened. On the other hand, the inner leads 51 of the lead portion 12 are not thinned from the front side. The entire area of the inner lead front face 51a of the inner lead 51 on the front face side is a smooth face. The terminal portion 53 of the lead portion 12 is not thinned from the front side. The entire area of the terminal portion front surface 53a of the terminal portion 53 on the front surface side is a smooth surface.

As shown in fig. 31, the metal layer 25 is located on the die pad 11 and the lead portion 12. The metal layer 25 is formed on a portion of the die pad 11 and a portion of the lead portion 12. The metal layer 25 is used to make the bump 26 well connected to the chip carrier 11 and the lead portion 12. The metal layer 25 may be, for example, a plating layer formed by an electroplating method. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. As a metal constituting such a plating layer, silver alloy, gold alloy, platinum group, copper alloy, palladium, or the like can be used. When the base plating is required, a known material such as nickel or copper may be used as the metal constituting the metal layer 25.

(Structure of semiconductor device)

Next, a semiconductor device according to this embodiment will be described with reference to fig. 32 to 34. Fig. 32 to 34 are diagrams showing the semiconductor device (flip chip type) of the present embodiment.

As shown in fig. 32 and 33, the semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of bumps 26, and a sealing resin 23.

The semiconductor element 21 is mounted on the die pad 11. In addition, a plurality of lead portions 12 are arranged around the chip carrier 11. Further, metal layers 25 are formed on the die pad 11 and the lead portion 12, respectively. Bumps 26 are provided on the metal layer 25. The semiconductor element 21, the die pad 11 and the lead portion 12 are electrically connected to each other via the bump 26.

One side of the sealing resin 23 (one side of the semiconductor device 20) may be, for example, 0.2mm or more and 16mm or less.

The bump (connection portion) 26 may be made of a metal material having good conductivity, such as copper, for example, or may have a solid substantially cylindrical shape or a substantially spherical shape. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, respectively, and the lower ends of the bumps 26 are connected to the chip carrier 11 and the lead portions 12, respectively, via the metal layer 25. In addition, the metal layer 25 and the bump 26 may not be provided on the chip carrier 11. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other with an adhesive such as a die bonding paste.

Fig. 34 is an enlarged cross-sectional view showing the periphery of the bump 26. As shown in fig. 34, bump 26 may also comprise multiple layers. For example, the bump 26 includes a 1 st layer 26a on the metal layer 25 side and a 2 nd layer 26b on the semiconductor element 21 side. The 1 st layer 26a may contain a metal such as tin, for example. The height of the 1 st layer 26a may be 1 μm or more and 10 μm or less. The 2 nd layer 26b may contain a metal such as copper, for example. The height of the 2 nd layer 26b may be 30 μm or more and 100 μm or less.

The structures of the chip carrier 11 and the lead portion 12 are the same as those shown in fig. 30 and 31 described above except that they are not included in the region of the semiconductor device 20, and therefore, a detailed description thereof is omitted here.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10 shown in fig. 30 and 31 will be described with reference to (a) to (j) of fig. 35. Fig. 35 (a) - (j) are cross-sectional views (corresponding to fig. 31) showing a manufacturing method of the lead frame 10.

First, as in the case of embodiment 2 (fig. 14 (a) - (e)), a metal substrate 31 having a chip carrier 11 and a lead portion 12 located around the chip carrier 11 is produced (fig. 35 (a) - (e)).

Next, a plating layer 36 is formed around the metal substrate 31 (fig. 35 (f)). At this time, the plating layer 36 is formed on the entire circumference of the chip carrier 11, the lead portion 12, and the connection bar 13. The thickness of the plating layer 36 may also exceed 0 μm and be less than 2 μm. As the metal constituting the plating layer 36, silver, for example, may be used. When the plating layer 36 is a silver plating layer, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as the plating solution for plating.

Next, a part of the plating layer 36 existing in the region where the roughened surface is formed is removed. Specifically, portions of the plating layer 36 other than the front and rear surfaces of the metal substrate 31 are removed ((g) of fig. 35). Thereby, the plating 36 on the 1 st die pad side 11c of the die pad 11, the 2 nd die pad side 11d of the die pad 11, the inner lead end face 51c of the lead portion 12, and the inner lead back face 51b of the lead portion 12 is removed.

In this period, as shown in fig. 35 (g), first, elastic members 46 such as rubber gaskets are disposed on the front and rear surfaces of the metal substrate 31, respectively, and the metal substrate 31 is held by a jig 47C with the elastic members 46 interposed therebetween. Then, the plating layer 36 of the portion not covered with the elastic member 46 is peeled off and removed. Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the inner lead end surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plating 36 on the chip carrier front surface 11a, the terminal portion front surface 53a, the chip carrier back surface 11b, the inner lead front surface 51a, and the external terminals 17 covered by the elastic member 46 remains.

Next, as shown in fig. 35 (h), a support layer 37 for supporting the metal substrate 31 is provided on the back surface side of the metal substrate 31. The support layer 37 may be, for example, a resist layer. Next, as shown in fig. 35 (h), the portion of the metal substrate 31 not covered with the plating layer 36 is roughened, whereby a roughened surface is formed at the portion not covered with the plating layer 36. Specifically, the 1 st die pad side surface 11c, the 2 nd die pad side surface 11d, the inner lead end surface 51c, and the inner lead back surface 51b are roughened surfaces. During this period, the microetching solution is supplied to the metal substrate 31, whereby a roughened surface is formed on the entire metal substrate 31 except for the portion covered with the plating layer 36. The microetching solution is a surface treatment agent that slightly dissolves the metal surface to form a roughened surface having fine irregularities. For example, when roughening the metal substrate 31 made of copper or copper alloy, a microetching solution containing hydrogen peroxide water and sulfuric acid as main components may be used.

Subsequently, as shown in fig. 35 (i), the support layer 37 and the plating layer 36 are sequentially peeled off and removed.

Then, as shown in fig. 35 (j), a metal layer 25 is formed on the die pad 11 and the lead portion 12. In this case, first, a plating resist layer of a predetermined pattern, not shown, is formed on the chip carrier 11 and the lead portion 12 by, for example, photolithography. Next, a metal layer 25 made of a plating layer is formed at a portion not covered with the plating resist layer, for example, by a plating method. Then, the plating resist layer is removed, whereby the lead frame 10 shown in fig. 30 and 31 is obtained.

(method for manufacturing semiconductor device)

As shown in fig. 36 (a) to (d), the method for manufacturing the semiconductor device 20 according to the present embodiment can be performed substantially in the same manner as the method for manufacturing the semiconductor device 20 according to embodiment 2. In this case, each electrode 21a of the semiconductor element 21 is electrically connected to the chip carrier 11 and the lead portion 12 via the bump 26 and the metal layer 25, respectively.

However, it is conceivable that: during long-term use of the semiconductor device 20 thus manufactured, moisture and the like in the air intrude from the back surface side of the semiconductor device 20 through the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12. In contrast, according to the present embodiment, the inner lead back surface 51b and the inner lead distal end surface 51c of the lead portion 12 are roughened. The 1 st die pad side surface 11c and the 2 nd die pad side surface 11d of the die pad 11 are roughened surfaces, respectively. Therefore, the distance between the sealing resin 23 and the moisture penetration path at the interface between the chip carrier 11 and the lead portion 12 becomes longer. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 37) _A ). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

(embodiment 6)

Next, embodiment 6 will be described with reference to fig. 38 to 41. Fig. 38 to 41 are diagrams showing embodiment 6. The main difference between embodiment 6 shown in fig. 38 to 41 is that: a roughened surface is formed on the front surface of the lead portion 12, and the other configuration is substantially the same as that of embodiment 5 described above. In fig. 38 to 41, the same reference numerals are given to the same parts as those in the embodiment shown in fig. 8 to 37, and detailed description thereof is omitted.

(Structure of lead frame and semiconductor device)

Fig. 38 is a cross-sectional view showing the lead frame 10A of the present embodiment, and fig. 39 is a cross-sectional view showing the semiconductor device 20A of the present embodiment.

In the lead frame 10A shown in fig. 38 and the semiconductor device 20A shown in fig. 39, the front surface of the lead portion 12 has a 1 st front surface portion 54a as a smooth surface and a 2 nd front surface portion 54b as a rough surface.

The 1 st front portion 54a is adjacent to the outside of the metal layer 25 (the opposite side of the chip carrier 11). The 1 st front portion 54a is directly connected to the metal layer 25. The entirety of the 1 st front portion 54a is a smooth surface. Length (length in the X direction) L of the 1 st front portion 54a along the long side direction of the lead portion 12 _A May be 25 μm or more and 200 μm or less, and preferably 50 μm or more and 100 μm or less. Further, the 1 st front surface portion 54a is located at a part of the inner lead front surface 51a, but is not limited thereto. The 1 st front surface portion 54a may be located, for example, at a part of the inner lead front surface 51a and a part of the terminal portion front surface 53 a.

The 2 nd front portion 54b is adjacent to the outside of the 1 st front portion 54 a. That is, the 2 nd front portion 54b directly meets the 1 st front portion 54 a. The entirety of the 2 nd front portion 54b is a roughened surface. In addition, in the lead frame 10A, the 2 nd front portion 54b preferably extends continuously to the connection portion of the lead portion 12 and the connection bar 13. The front face of the connecting strip 13 may be roughened. In addition, the 2 nd front surface portion 54b is located at a part of the inner lead front surface 51a and a part of the terminal portion front surface 53a, but is not limited thereto. The 2 nd front portion 54b may also be located at a part of the terminal portion front surface 53 a.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10A shown in fig. 38 will be described with reference to (a) to (j) of fig. 40. In fig. 40 (a) - (j), the same reference numerals are given to the same parts as those of the structures shown in fig. 35 (a) - (j), and detailed description thereof is omitted.

First, as in the case of embodiment 2 (fig. 14 (a) - (e)), a metal substrate 31 having a chip carrier 11 and a lead portion 12 located around the chip carrier 11 is produced (fig. 40 (a) - (e)).

Next, a plating layer 36 is formed on the entire periphery of the metal substrate 31 substantially in the same manner as in the step shown in fig. 35 (f) (fig. 40 (f)).

Next, portions of the plating layer 36 corresponding to the 1 st die pad side surface 11c, the 2 nd die pad side surface 11d, the 2 nd front surface portion 54b, the inner lead end surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed ((g) of fig. 40).

In this period, as shown in fig. 40 (g), first, elastic members 46 such as rubber gaskets are disposed on the front and rear surfaces of the metal substrate 31, respectively, and the metal substrate 31 is held by a jig 47D with the elastic members 46 interposed therebetween. The front-side elastic member 46 of the metal substrate 31 covers the die pad front surface 11a, the region corresponding to the 1 st front surface portion 54a, and the region of the lead portion 12 where the metal layer 25 is provided. Then, the plating layer 36 of the portion not covered with the elastic member 46 is peeled off and removed. Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the 2 nd front portion 54b, the inner lead end face 51c, and the inner lead back face 51b are exposed. On the other hand, the plating 36 on the chip carrier front surface 11a, the chip carrier back surface 11b, the 1 st front surface portion 54a, and the external terminals 17 covered by the elastic member 46 remain.

Next, a support layer 37 is provided on the back surface side of the metal substrate 31 in substantially the same manner as in the step (h) of fig. 35. Next, by roughening the portion of the metal substrate 31 not covered with the plating layer 36, a roughened surface is formed at the portion not covered with the plating layer 36 ((h) of fig. 40). Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the 2 nd front portion 54b, the inner lead end face 51c, and the inner lead back face 51b are roughened.

Next, the supporting layer 37 and the plating layer 36 are peeled off and removed in this order substantially as in the step shown in fig. 35 (i) (fig. 40 (i)).

Then, the metal layer 25 is formed on the die pad 11 and the lead portion 12 substantially in the same manner as in the step (j) shown in fig. 35. Thus, the lead frame 10A shown in fig. 38 can be obtained ((j) of fig. 40).

(method for manufacturing semiconductor device)

The method for manufacturing the semiconductor device 20A according to the present embodiment can be performed substantially in the same manner as the method for manufacturing the semiconductor device 20 shown in (a) to (d) of fig. 36.

According to the present embodiment, the 1 st front surface portion 54a adjacent to the outside of the metal layer 25 among the front surfaces of the lead portions 12 becomes a smooth surface. Thus, when the semiconductor element 21 is mounted on the die pad 11, the tin or the like contained in the bump 26 can be prevented from flowing out along the 1 st front surface portion 54a (see arrow F in fig. 41) _C ). On the other hand, if the 1 st front surface portion 54a is roughened, there is a possibility that tin or the like contained in the bump 26 flows out along the 1 st front surface portion 54a due to surface tension.

In addition, according to the present embodiment, the 2 nd front portion 54b adjacent to the outside of the 1 st front portion 54a is a rough surface. Therefore, the distance between the surface of the lead portion 12 and the moisture penetration path at the interface of the sealing resin 23 becomes longer. This can suppress moisture from flowing from the interface between the surface of the lead portion 12 and the sealing resin 23 to the semiconductor element 21 side intrusion (see arrow F of FIG. 41) _B ). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

In addition, according to the present embodiment, the 2 nd front surface portion 54b of the lead portion 12 is roughened. This can improve the adhesion strength between the 2 nd front surface portion 54b and the sealing resin 23, and can prevent the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

In addition, according to the present embodiment, the distance of the moisture penetration path at the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 becomes longer on the back surface side of the semiconductor device 20A. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 41) _A ). As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

(embodiment 7)

Next, embodiment 7 will be described with reference to fig. 42 to 45. Fig. 42 to 45 are diagrams showing embodiment 7. The main difference points of embodiment 7 shown in fig. 42 to 45 are that: a recess 18 is formed in the front surface of the lead portion 12, and the other configuration is substantially the same as that of embodiment 5 described above. In fig. 42 to 45, the same portions as those of the embodiment shown in fig. 8 to 41 are denoted by the same reference numerals, and detailed description thereof is omitted.

(Structure of lead frame and semiconductor device)

Fig. 42 is a cross-sectional view showing the lead frame 10B of the present embodiment, and fig. 43 is a cross-sectional view showing the semiconductor device 20B of the present embodiment.

In the lead frame 10B shown in fig. 42 and the semiconductor device 20B shown in fig. 43, the recess 18 is formed on the outer side (opposite side to the die pad 11) of the metal layer 25 in the front surface of the lead portion 12. In addition, a portion adjacent to the outside of the concave portion 18 (3 rd front portion 54 c) becomes a rough surface. The inner surface of the recess 18 is a smooth surface. The portion between the recess 18 and the metal layer 25 (4 th front portion 54 d) becomes a smooth surface.

The 4 th front portion 54d is opposite to the outer side of the metal layer 25 (opposite side of the chip carrier 11) Adjacent. The 4 th front portion 54d is directly connected to the metal layer 25. The 4 th front portion 54d is a smooth surface as a whole. Length (length in the X direction) L of 4 th front surface portion 54d along the long side direction of lead portion 12 _B May be 25 μm or more and 200 μm or less, and preferably 50 μm or more and 100 μm or less.

The recess 18 is adjacent to the outside of the 4 th front portion 54d (opposite side of the chip carrier 11). The recess 18 directly meets the 4 th front portion 54 d. The entire inner surface of the recess 18 is a smooth surface. Length (length in the X direction) L of the recess 18 along the longitudinal direction of the lead portion 12 _c May be 50 μm or more and 150 μm or less, and preferably may be 75 μm or more and 100 μm or less. The depth of the recess 18 may be 25 μm or more and 125 μm or less, and preferably 50 μm or more and 100 μm or less. The planar shape of the concave portion 18 may be, for example, a polygon such as a circle or a quadrangle. The recess 18 is provided in a part of the lead portion 12 in the width direction. However, the concave portion 18 is not limited to this, and may be provided over the entire width direction of the lead portion 12.

The 3 rd front portion 54c is adjacent to the outside of the recess 18 (opposite side of the chip carrier 11). The 3 rd front portion 54c directly meets the recess 18. The 3 rd front portion 54c is roughened overall. In addition, in the lead frame 10B, the 3 rd front portion 54c preferably extends continuously to the connection portion of the lead portion 12 and the connection bar 13. The front face of the connecting strip 13 may be roughened.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10B shown in fig. 42 will be described with reference to (a) to (j) of fig. 44. In fig. 44 (a) - (j), the same reference numerals are given to the same parts as those of the structures shown in fig. 35 (a) - (j), and detailed description thereof is omitted.

First, a metal substrate 31 is prepared substantially in the same manner as in the steps shown in fig. 35 (a) and (b), and photosensitive resists 32a and 33a are formed on the front and rear surfaces of the metal substrate 31, respectively (b) of fig. 44.

Next, etching resist layers 32 and 33 having openings 32b and 33b are formed substantially in the same manner as in the step (c) of fig. 35 (fig. 44). In this case, the opening 32b is also formed in the region corresponding to the recess 18.

Next, the metal substrate 31 is etched to form the outer shapes of the die pad 11, the lead portion 12, and the connection bar 13 (fig. 44 (d)) in substantially the same manner as in the step shown in fig. 35 (d). In this case, a recess 18 is formed in the front surface of the lead portion 12. Next, the etching resist layers 32 and 33 are peeled off and removed in substantially the same manner as in the step shown in fig. 35 (e) (fig. 44 (e)).

Next, a plating layer 36 is formed on the entire periphery of the metal substrate 31 substantially in the same manner as in the step shown in fig. 35 (f) (fig. 44 (f)). In this case, a plating layer 36 is also formed in the recess 18.

Next, portions of the plating layer 36 corresponding to the 1 st die pad side surface 11c, the 2 nd die pad side surface 11d, the 3 rd front surface portion 54c, the inner lead end surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed ((g) of fig. 44).

In this period, as shown in fig. 44 (g), first, elastic members 46 such as rubber gaskets are disposed on the front and rear surfaces of the metal substrate 31, respectively, and the metal substrate 31 is held by a jig 47E with the elastic members 46 interposed therebetween. The front-side elastic member 46 of the metal substrate 31 covers the die pad front surface 11a, the recess 18, the region corresponding to the 4 th front surface portion 54d, and the region of the lead portion 12 where the metal layer 25 is provided. Then, the plating layer 36 of the portion not covered with the elastic member 46 is peeled off and removed. Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the 3 rd front surface portion 54c, the inner lead end surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plating 36 on the chip carrier front surface 11a, the chip carrier back surface 11b, the inner surface of the recess 18, the 4 th front surface portion 54d, and the external terminals 17 covered by the elastic member 46 remain.

Next, a support layer 37 is provided on the back surface side of the metal substrate 31 in substantially the same manner as in the step (h) of fig. 35. Next, by roughening the portion of the metal substrate 31 not covered with the plating layer 36, a roughened surface is formed at the portion not covered with the plating layer 36 ((h) of fig. 44). Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the 3 rd front surface portion 54c, the inner lead end surface 51c, and the inner lead back surface 51b are roughened.

Next, the supporting layer 37 and the plating layer 36 are peeled off and removed in this order substantially as in the step shown in fig. 35 (i) (fig. 44 (i)).

Then, the metal layer 25 is formed on the die pad 11 and the lead portion 12 substantially in the same manner as in the step (j) shown in fig. 35. Thus, the lead frame 10B shown in fig. 42 can be obtained ((j) of fig. 44).

(method for manufacturing semiconductor device)

The method for manufacturing the semiconductor device 20B according to the present embodiment can be performed substantially in the same manner as the method for manufacturing the semiconductor device 20 shown in (a) to (d) of fig. 36.

According to the present embodiment, the 4 th front surface portion 54d adjacent to the outside of the metal layer 25 among the front surfaces of the lead portions 12 becomes a smooth surface. Thus, when the semiconductor element 21 is mounted on the die pad 11, the tin or the like contained in the bump 26 can be prevented from flowing out along the 4 th front surface portion 54d (see arrow F in fig. 45) _C ). On the other hand, if the 4 th front surface portion 54d is roughened, there is a possibility that tin or the like contained in the bump 26 flows out along the 4 th front surface portion 54d due to surface tension.

In addition, according to the present embodiment, the concave portion 18 is formed on the outer side of the metal layer 25 in the front surface of the lead portion 12. Thus, even when tin or the like contained in the bump 26 flows out along the 4 th front surface portion 54d, the flowing-out tin or the like can be received by the concave portion 18. This can prevent tin and the like flowing out from reaching the 3 rd front portion 54c side.

In addition, according to the present embodiment, the 3 rd front surface portion 54c adjacent to the outside of the concave portion 18 is a rough surface. Therefore, the distance between the surface of the lead portion 12 and the moisture penetration path at the interface of the sealing resin 23 becomes longer. This can suppress intrusion of moisture from the interface between the surface of the lead portion 12 and the sealing resin 23 toward the semiconductor element 21 (see arrow F in fig. 45) _B ). As a result, the reliability of the semiconductor device 20B after long-term use can be improved.

In addition, according to the present embodiment, the 3 rd front portion 54c of the lead portion 12 is roughened. This can improve the adhesion strength between the 3 rd front surface portion 54c and the sealing resin 23, and can prevent the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

In addition, according to the present embodiment, the distance of the moisture penetration path at the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 becomes longer on the back surface side of the semiconductor device 20B. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 45) _A ). As a result, the reliability of the semiconductor device 20B after long-term use can be improved.

(embodiment 8)

Next, embodiment 8 will be described with reference to fig. 46 to 49. Fig. 46 to 49 are diagrams showing embodiment 8. The main difference points of embodiment 8 shown in fig. 46 to 49 are that: the inner surface of the recess 18 is roughened, and the other configuration is substantially the same as that of embodiment 7 described above. In fig. 46 to 49, the same reference numerals are given to the same portions as those of the embodiment shown in fig. 8 to 45, and detailed description thereof is omitted.

(Structure of lead frame and semiconductor device)

Fig. 46 is a cross-sectional view showing the lead frame 10C of the present embodiment, and fig. 47 is a cross-sectional view showing the semiconductor device 20C of the present embodiment.

In the lead frame 10C shown in fig. 46 and the semiconductor device 20C shown in fig. 47, the recess 18 is formed on the outer side (opposite side to the die pad 11) of the metal layer 25 in the front surface of the lead portion 12. In addition, a portion adjacent to the outside of the concave portion 18 (3 rd front portion 54 c) becomes a rough surface. The entire inner surface of the recess 18 is roughened. The portion between the recess 18 and the metal layer 25 (4 th front portion 54 d) becomes a smooth surface.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10C shown in fig. 46 will be described with reference to (a) to (j) of fig. 48. In fig. 48 (a) - (j), the same reference numerals are given to the same parts as those of the structures shown in fig. 35 (a) - (j), and detailed description thereof is omitted.

First, a metal substrate 31 is prepared in substantially the same manner as in the steps shown in fig. 35 (a) and (b), and photosensitive resists 32a and 33a are formed on the front and rear surfaces of the metal substrate 31, respectively (b) of fig. 48.

Next, etching resist layers 32 and 33 having openings 32b and 33b are formed substantially in the same manner as in the step (c) of fig. 35. In this case, the opening 32b is also formed in the region corresponding to the recess 18.

Next, the metal substrate 31 is etched to form the outer shapes of the die pad 11, the lead portion 12, and the connection bar 13 (fig. 48 (d)) in substantially the same manner as in the step shown in fig. 35 (d). In this case, a recess 18 is formed in the front surface of the lead portion 12. Next, the etching resist layers 32 and 33 are peeled off and removed in substantially the same manner as in the step shown in fig. 35 (e) (fig. 48 (e)).

Next, a plating layer 36 is formed on the entire periphery of the metal substrate 31 substantially in the same manner as in the step shown in fig. 35 (f) (fig. 48 (f)). In this case, a plating layer 36 is also formed in the recess 18.

Next, portions of the plating layer 36 corresponding to the 1 st die pad side surface 11c, the 2 nd die pad side surface 11d, the 3 rd front surface portion 54c, the recess 18, the inner lead end surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed ((g) of fig. 48).

In this period, as shown in fig. 48 (g), first, elastic members 46 such as rubber gaskets are disposed on the front and rear surfaces of the metal substrate 31, respectively, and the metal substrate 31 is held by a jig 47F with the elastic members 46 interposed therebetween. The front-side elastic member 46 of the metal substrate 31 covers the die pad front surface 11a, the region corresponding to the 4 th front surface portion 54d, and the region of the lead portion 12 where the metal layer 25 is provided. Then, the plating layer 36 of the portion not covered with the elastic member 46 is peeled off and removed. Thus, the 1 st chip carrier side 11c, the 2 nd chip carrier side 11d, the 3 rd front surface portion 54c, the recess 18, the inner lead end surface 51c, and the inner lead back surface 51b are exposed. On the other hand, the plating 36 on the chip carrier front surface 11a, the chip carrier back surface 11b, the 4 th front surface portion 54d, and the external terminals 17 covered by the elastic member 46 remain.

Next, a support layer 37 is provided on the back surface side of the metal substrate 31 in substantially the same manner as in the step (h) of fig. 35. Next, the portion of the metal substrate 31 not covered with the plating layer 36 is roughened, whereby a roughened surface is formed at the portion not covered with the plating layer 36 (fig. 48 (h)). Thus, the 1 st chip carrier side surface 11c, the 2 nd chip carrier side surface 11d, the 3 rd front surface portion 54c, the inner surface of the recess 18, the inner lead end surface 51c, and the inner lead back surface 51b are roughened.

Next, the supporting layer 37 and the plating layer 36 are peeled off and removed in this order substantially as in the step shown in fig. 35 (i)).

Then, the metal layer 25 is formed on the die pad 11 and the lead portion 12 substantially in the same manner as in the step (j) shown in fig. 35. Thus, the lead frame 10C shown in fig. 46 can be obtained ((j) of fig. 48).

(method for manufacturing semiconductor device)

The method for manufacturing the semiconductor device 20C according to the present embodiment can be performed substantially in the same manner as the method for manufacturing the semiconductor device 20 shown in (a) to (d) of fig. 36.

According to the present embodiment, the 4 th front surface portion 54d adjacent to the outside of the metal layer 25 among the front surfaces of the lead portions 12 becomes a smooth surface. Thus, when the semiconductor element 21 is mounted on the die pad 11, the tin or the like contained in the bump 26 can be prevented from flowing out along the 4 th front surface portion 54d (see arrow F in fig. 49) _C ). On the other hand, if the 4 th front surface portion 54d is roughened, there is a possibility that tin or the like contained in the bump 26 flows out along the 4 th front surface portion 54d due to surface tension.

In addition, according to the present embodiment, the inner surface of the concave portion 18 and the 3 rd front surface portion 54c become roughened surfaces. Therefore, the distance between the surface of the lead portion 12 and the moisture penetration path at the interface of the sealing resin 23 becomes longer. This can suppress intrusion of moisture from the interface between the surface of the lead portion 12 and the sealing resin 23 toward the semiconductor element 21 (see arrow F in fig. 49) _B ). As a result, the reliability of the semiconductor device 20C after long-term use can be improved.

In addition, according to the present embodiment, the inner surface of the concave portion 18 and the 3 rd front surface portion 54c become roughened surfaces. This can improve the adhesion strength between the recess 18 and the 3 rd front portion 54c and the sealing resin 23, and can prevent the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

In addition, according to the present embodiment, the distance of the moisture penetration path at the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 becomes longer on the back surface side of the semiconductor device 20C. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 49) _A ). As a result, the reliability of the semiconductor device 20C after long-term use can be improved.

(embodiment 9)

Embodiment 9 will be described with reference to fig. 50 to 57. Fig. 50 to 57 are diagrams showing embodiment 9. In fig. 50 to 57, the same reference numerals are given to the same parts as those of the embodiment shown in fig. 8 to 49, and detailed description thereof is omitted.

(Structure of lead frame)

First, an outline of the lead frame of the present embodiment will be described with reference to fig. 50 and 51. Fig. 50 and 51 are diagrams showing the lead frame according to the present embodiment.

As shown in fig. 50 and 51, each package region 10a of the lead frame 10 includes a die pad 11 and a lead portion 12 located around the die pad 11. A portion of the lead portion 12 is thinned from the back surface side. The thinned portion of the back surface of the lead portion 12 is roughened. The portion of the back surface of the lead portion 12 that is not thinned becomes a smooth surface.

As shown in fig. 51, the die pad 11 has a die pad front surface 11a on the front surface side and a die pad back surface 11b on the back surface side. The semiconductor element 21 is mounted on the front surface 11a of the die pad as will be described later. The chip-holder rear surface 11b is exposed outward from the semiconductor device 20 (described later). In addition, a chip-holder side surface 11h is formed on the side of the chip holder 11 facing the lead portion 12. The chip-holder side surface 11h extends from the chip-holder front surface 11a side to the chip-holder back surface 11b side in the thickness direction (Z direction). In this case, the die pad side surface 11h becomes a rough surface. That is, the 3 rd roughness surface R3 is formed on the die pad side surface 11h. On the other hand, the back surface 11b of the chip holder is a smooth surface.

In the present embodiment, the "rough surface" means a surface having an S-ratio of 1.10 or more. "smooth surface" refers to a surface having an S-ratio of less than 1.10. The rough surface is a surface that is rougher than the smooth surface. The S-ratio of the "rough surface" is preferably 1.10 or more and 2.30 or less. The S-ratio of the "smooth surface" is preferably 1.00 or more and less than 1.10. Here, "S-ratio" means a surface area ratio obtained by dividing a surface to be measured into a plurality of pixels by an optical interferometer and measuring the divided surface. Specifically, using a VertScan manufactured by Hitachi High-Tech Science, the surface to be measured is divided into a plurality of pixels, and the obtained surface area is divided by the observation area.

The roughened surface may be formed by roughening the outer surface of the metal substrate 31 described later with, for example, a microetching solution. As such a microetching solution, a microetching solution containing sulfuric acid or hydrochloric acid as a main component (for example, a 1 st microetching solution described later) is exemplified. Alternatively, as the microetching solution, a microetching solution containing hydrogen peroxide and sulfuric acid as main components (for example, a 2 nd microetching solution described later) may be used. The smooth surface may be an unprocessed surface which is not subjected to such roughening treatment on the metal substrate 31 described later. In fig. 51, a rough surface having a relatively smooth roughness (for example, a 1 st rough surface R1 described later) is indicated by a thin broken line. In fig. 51, rough surfaces having relatively rough roughness (for example, a 2 nd rough surface R2, a 3 rd rough surface R3, a 4 th rough surface R4, and a 5 th rough surface R5 described later) are indicated by thick broken lines (the same applies to other cross-sectional views).

The die pad front surface 11a of the die pad 11 is a region (internal terminal) bonded to the semiconductor element 21 via an adhesive 24 such as a die attach paste as will be described later. The front surface 11a of the die pad may be a region thinned by half etching or the like. Further, the 1 st roughened surface R1 is formed on the chip-holder front surface 11 a. Here, the 1 st roughened surface R1 has a smoother (non-roughened) roughness than the 2 nd roughened surface R2 of the lead portion 12, which will be described later. Specifically, the S-ratio of the 1 st roughened surface R1 may be 1.10 or more and less than 1.30.

In the present embodiment, the 1 st roughness R1 is formed over the entire area of the front surface 11a of the die pad. However, the 1 st roughened surface R1 is not limited thereto, and may be formed on a part of the front surface 11a of the die pad. Particularly preferably, the 1 st roughened surface R1 is formed on the outer peripheral edge of the mounting region of the semiconductor element 21 in the front surface 11a of the die pad. As a result, as will be described later, the component such as epoxy resin in the adhesive 24 can be prevented from bleeding (bleeding) due to capillary phenomenon of the front surface 11a of the chip carrier. The 1 st roughened surface R1 may be formed along the entire peripheral edge of the die pad 11. In the case where the 1 st rough surface R1 is formed on a part of the front surface 11a of the chip carrier, a part other than the 1 st rough surface R1 may be a smooth surface. Alternatively, the portion of the front surface 11a of the die pad other than the 1 st roughened surface R1 may be a roughened surface having a roughness larger than that of the 1 st roughened surface R1. For example, the S-ratio of the portion of the front surface 11a of the chip carrier other than the 1 st roughened surface R1 may be 1.30 or more and 2.30 or less.

Referring to fig. 51, the back surface 11b of the die pad is thinned by half etching, for example, and is a smooth surface similar to the metal substrate before processing (metal substrate 31 described later). The die pad rear surface 11b is exposed outward from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

Each of the lead portions 12 is connected to the semiconductor element 21 via a connection line 22 as will be described later, and is disposed with a space between the semiconductor element and the die pad 11. The plurality of lead portions 12 are arranged at intervals along the longitudinal direction of the connecting bar 13. Each of the lead portions 12 extends from the connection bar 13.

As shown in fig. 51, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner leads 51 are located on the inner side (chip carrier 11 side). The terminal portion 53 is located outside (the connection bar 13 side). The inner leads 51 extend from the terminal portions 53 toward the chip carrier 11. An internal terminal is formed on the front side of the inner lead 51. The internal terminal is a region electrically connected to the semiconductor element 21 via a connection line 22 as will be described later. A metal layer 25 for improving the close adhesion with the connection wire 22 is provided on the internal terminal.

In the present embodiment, the thinned portion of the back surface of the lead portion 12 is roughened. Specifically, the inner lead 51 of the lead portion 12 is thinned from the back surface side. The entire area of the inner lead back surface 51b located on the back surface side of the inner lead 51 is a roughened surface. That is, the 4 th roughened surface R4 is formed on the inner lead back surface 51 b. On the other hand, the portion of the back surface of the lead portion 12 that is not thinned becomes a smooth surface. Specifically, the terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The entire area of the external terminal 17 located on the back surface side of the terminal portion 53 is a smooth surface.

Further, the entire area of the inner lead distal end face 51c of the lead portion 12 is roughened. That is, the 5 th roughened surface R5 is formed on the inner lead distal end surface 51 c. Although not shown, both side surfaces of the lead portion 12 in the longitudinal direction may be roughened. On the other hand, the inner leads 51 of the lead portion 12 are not thinned from the front side. The terminal portion 53 of the lead portion 12 is not thinned from the front side.

The lead front face 12a is constituted by the inner lead front face 51a of the inner lead 51 and the terminal portion front face 53a of the terminal portion 53. The lead front surface 12a is a region which is not thinned from the front surface side by half etching or the like. A smooth surface region S as a region of the smooth surface and a 2 nd rough surface R2 as a region of the rough surface are formed on the lead front surface 12a.

The smooth surface region S is located at the inner end (chip carrier 11 side) of the lead portion 12. A metal layer 25 is formed on the smooth surface region S. In this case, the metal layer 25 covers the entire smooth surface area S in a plan view. The metal layer 25 may be, for example, a plating layer formed by an electroplating method. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. As a metal constituting such a plating layer, silver alloy, gold alloy, platinum group, copper alloy, palladium, or the like can be used. When the base plating is required, a known material such as nickel or copper may be used depending on the metal constituting the metal layer 25.

In this case, one smooth surface region S is formed on each lead front surface 12a of each lead portion 12. However, the present invention is not limited thereto, and a plurality of smooth surface regions S may be formed on the lead front surface 12a of each lead portion 12. The lead front surface 12a of each lead portion 12 may not have the smooth surface region S. That is, the entire lead front surface 12a of each lead portion 12 may be the 2 nd roughened surface R2.

The 2 nd rough surface R2 is located outside (the tie bar 13 side) the smooth surface region S and the metal layer 25. In this case, the 2 nd rough surface R2 is provided only on the outer side (the connecting bar 13 side) of the smooth surface region S. However, the 2 nd rough surface R2 is not limited to this, and may be provided so as to surround the smooth surface region S in a plan view. The lead front surface 12a may be constituted only by the smooth surface region S and the 2 nd rough surface R2.

In the present embodiment, the roughness of the 2 nd roughness surface R2 is larger than the roughness of the 1 st roughness surface R1 of the die pad 11. Specifically, the S-ratio of the 2 nd roughened surface R2 may be 1.30 or more and 2.30 or less. On the other hand, as described above, the S-ratio of the 1 st roughened surface R1 may be 1.10 or more and less than 1.30.

The roughness of the 3 rd roughness surface R3 of the die pad 11 may be larger than the roughness of the 1 st roughness surface R1. The S-ratio of the 3 rd roughness R3 may be 1.30 or more and 2.30 or less. The roughness of the 4 th roughened surface R4 of the lead portion 12 may be larger than the roughness of the 1 st roughened surface R1 described above. The S-ratio of the 4 th roughened surface R4 may be 1.30 or more and 2.30 or less. The roughness of the 5 th roughened surface R5 of the lead portion 12 may be larger than the roughness of the 1 st roughened surface R1 described above. The S-ratio of the 5 th roughened surface R5 may be 1.30 or more and 2.30 or less.

The magnitude of the roughness of the 2 nd rough surface R2, the 3 rd rough surface R3, the 4 th rough surface R4 and the 5 th rough surface R5 is not limited. The roughness of the 2 nd roughened surface R2, the 3 rd roughened surface R3, the 4 th roughened surface R4 and the 5 th roughened surface R5 may be different from each other or the same as each other.

(Structure of semiconductor device)

Next, a semiconductor device according to this embodiment will be described with reference to fig. 52 and 53. Fig. 52 and 53 are diagrams showing the semiconductor device (QFN type) of the present embodiment.

As shown in fig. 52 and 53, the semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of lead portions 12, a plurality of connection lines 22, and a sealing resin 23.

The semiconductor element 21 is mounted on the die pad 11. The plurality of connection lines 22 electrically connect the semiconductor element 21 and the metal layer 25 of the lead portion 12, respectively. In this case, the connection line 22 is configured as a connection member. The sealing resin 23 seals the die pad 11, the lead portion 12, the semiconductor element 21, and the connection line 22 with resin.

The chip carrier 11 and the lead portion 12 are made of the above-described lead frame 10. In this case, the 1 st roughened surface R1 is formed on the chip-holder front surface 11a of the chip holder 11. The 2 nd roughened surface R2 is formed on the outer side (the side away from the die pad 11) of the lead front surface 12a of the lead portion 12 than the metal layer 25. The roughness of the 2 nd roughened surface R2 of the lead portion 12 is greater than the roughness of the 1 st roughened surface R1 of the die pad 11.

In addition, a 3 rd roughened surface R3 is formed on the die pad side surface 11h of the die pad 11. The roughness of the 3 rd rough surface R3 is larger than that of the 1 st rough surface R1. A sealing resin 23 is closely adhered to the side surface 11h of the die pad. The inner lead 51 of the lead portion 12 is thinned from the back surface side. The inner lead back surface 51b of the inner lead 51 becomes the 4 th roughened surface R4. The roughness of the 4 th rough surface R4 is greater than that of the 1 st rough surface R1. The sealing resin 23 is closely adhered to the inner lead back surface 51 b. Further, a 5 th roughened surface R5 is formed on the inner lead distal end surface 51c of the inner lead 51. The roughness of the 5 th rough surface R5 is greater than that of the 1 st rough surface R1. The sealing resin 23 is closely adhered to the inner lead distal end face 51 c. The terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The external terminal 17 located on the back surface of the terminal portion 53 is a smooth surface. The external terminal 17 is exposed outward from the sealing resin 23.

The semiconductor element 21 is not particularly limited, and various semiconductor elements commonly used in the past can be used, and for example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like can be used. The semiconductor element 21 has a plurality of electrodes 21a each having a connection line 22 mounted thereon. The semiconductor element 21 is fixed to the front surface of the die pad 11 with an adhesive 24 such as a die attach paste. The adhesive 24 may be an epoxy resin adhesive containing components such as silver paste and epoxy resin.

Each of the connection lines 22 is made of a material having good conductivity, such as gold or copper. One end of each of the connection lines 22 is connected to the electrode 21a of the semiconductor element 21, and the other end thereof is connected to the metal layer 25 on each of the lead portions 12. Instead of the connection line 22, a conductive body such as a bump may be used as the connection member. In this case, the semiconductor element 21 can be connected to the lead portion 12 by flip-chip bonding agent.

As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as PPS resin can be used. The thickness of the entire sealing resin 23 may be 300 μm or more and 1500 μm or less. One side of the sealing resin 23 (one side of the semiconductor device 20) may be, for example, 0.2mm or more and 20mm or less. In fig. 52, the portion of the sealing resin 23 located on the front side of the lead portion 12 and the semiconductor element 21 is not shown.

The structures of the die pad 11 and the lead portion 12 are the same as those shown in fig. 50 and 51 described above except that they are not included in the region of the semiconductor device 20, and therefore, a detailed description thereof is omitted here.

(method for manufacturing lead frame)

Next, a method for manufacturing the lead frame 10 shown in fig. 50 and 51 will be described with reference to (a) to (e) of fig. 54 and (a) to (h) of fig. 55. Fig. 54 (a) - (e) and 55 (a) - (h) are cross-sectional views (corresponding to fig. 51) showing a manufacturing method of the lead frame 10.

First, as in the case of embodiment 2 (fig. 14 (a) - (e)), a metal substrate 31 having a chip carrier 11 and a lead portion 12 located around the chip carrier 11 is produced (fig. 54 (a) - (e)).

Next, a plating layer (cover layer) 36 is formed around the metal substrate 31 (fig. 55 a). At this time, the plating layer 36 may be formed on the entirety of the chip carrier 11, the lead portion 12, and the portion of the connection bar 13 exposed to the outside. The thickness of the plating layer 36 may also exceed 0 μm and be less than 2 μm. As the metal constituting the plating layer 36, silver, for example, may be used. When the plating layer 36 is a silver plating layer, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as the plating solution for plating.

Next, the plating layer 36 existing in the region where the 1 st rough surface R1 is formed in the metal substrate 31 is removed. Specifically, the plating layer 36 located in the entire area of the chip-holder front surface 11a of the chip holder 11 is removed ((b) of fig. 55). In this case, for example, the front surface and the back surface of the metal substrate 31 other than the chip carrier front surface 11a are held by a jig via elastic members. Then, the plating layer 36 of the portion not covered with the elastic member and the jig may be peeled off and removed. Thereby, the plating 36 on the chip carrier front surface 11a is removed.

Next, the 1 st roughened surface R1 is formed at the portion of the metal substrate 31 that is not covered with the plating layer 36 by roughening the portion (fig. 55 (c)). Specifically, the 1 st micro etching liquid is supplied to the metal substrate 31, whereby the 1 st roughened surface R1 is formed on the entire front surface 11a of the chip carrier which is not covered with the plating layer 36. The 1 st microetching solution is a surface treatment agent for forming a 1 st rough surface R1 having fine irregularities by slightly dissolving the metal surface. For example, in the case of roughening the metal substrate 31 made of copper or copper alloy, a 1 st microetching solution containing sulfuric acid or hydrochloric acid as a main component may be used.

Next, the plating layer 36 existing in the metal substrate 31 except for the smooth surface region S (region where the metal layer 25 is formed) of the lead front surface 12a is removed. In this case, for example, the front surface and the rear surface of the metal substrate 31 other than the smooth surface region S are held by a jig with an elastic member interposed therebetween. Then, the plating layer 36 may be peeled off and removed from the portion not covered with the elastic member and the jig. Thereby, the plating 36 on the die pad backside 11b and the die pad side 11h of the die pad 11 is removed. In the lead portion 12, the plating 36 located at the portion of the lead front surface 12a other than the smooth surface region S, the inner lead back surface 51b, the inner lead distal end surface 51c, and the external terminal 17 is removed.

Next, protective layers 37A are provided on the front and rear surfaces of the metal substrate 31, respectively (fig. 55 (e)). The protective layer 37A may be, for example, a resist layer. The front-side protective layer 37A covers the die pad front surface 11a of the die pad 11 and the plating layer 36 on the smooth surface area S of the lead portion 12. At this time, the protective layer 37A on the front side covers the entire area of the 1 st roughened surface R1 of the die pad 11. The front-side protective layer 37A may cover a part or the whole of the plating layer 36 on the smooth surface region S. The back-side protective layer 37A covers the die pad back surface 11b of the die pad 11 and the external terminals 17 of the lead portions 12.

Next, by roughening the portion of the metal substrate 31 that is not covered with the plating layer 36 and the protective layer 37A, a roughened surface is formed at the portion that is not covered with the plating layer 36 and the protective layer 37A ((f) of fig. 55). Specifically, the 2 nd roughened surface R2 is formed on a part of the lead front surface 12a of the lead portion 12. The 3 rd roughened surface R3 is formed on the die pad side 11h of the die pad 11. The 4 th roughened surface R4 is formed on the inner lead back surface 51b of the lead portion 12. Further, the 5 th roughened surface R5 is formed on the inner lead distal end surface 51c of the lead portion 12.

During this period, the 2 nd microetching liquid is supplied to the metal substrate 31. Thus, a rough surface is formed on the entire metal substrate 31 except for the portion covered with the plating layer 36 and the protective layer 37A. The 2 nd microetching solution is a surface treatment agent for slightly dissolving the metal surface to form a rough surface having fine irregularities. For example, in the case of roughening the metal substrate 31 made of copper or copper alloy, a microetching solution containing hydrogen peroxide water and sulfuric acid as main components may be used as the 2 nd microetching solution. The 2 nd microetching solution may contain a different component from the 1 st microetching solution. The 2 nd microetching solution roughens the metal compared to the 1 st microetching solution. Therefore, the 2 nd rough surface R2, the 3 rd rough surface R3, the 4 th rough surface R4 and the 5 th rough surface R5 are respectively rougher than the 1 st rough surface R1.

Next, the protective layer 37A and the plating layer 36 on the front side of the metal substrate 31 are peeled off and removed, respectively (fig. 55 (g)). At this time, the plating layer 36 covering the lead front face 12a is removed, and the smooth face region S is exposed. The protective layer 37A on the rear surface side remains on the metal substrate 31.

Then, the metal layer 25 is formed on the smooth surface region S of the lead portion 12 ((h) of fig. 55). In this case, first, a resist layer for plating of a predetermined pattern, not shown, is formed on the chip carrier 11 and the lead portion 12 except the smooth surface region S, for example, by photolithography. Next, the metal layer 25 formed of a plating layer is formed in the smooth surface region S not covered with the resist layer for plating, for example, by electroplating. Then, the resist layer for plating is removed, thereby obtaining the lead frame 10 shown in fig. 50 and 51.

(method for manufacturing semiconductor device)

Next, a method for manufacturing the semiconductor device 20 shown in fig. 52 and 53 will be described with reference to (a) to (e) of fig. 56. Fig. 56 (a) - (e) are cross-sectional views (corresponding to fig. 53) showing a method of manufacturing the semiconductor device 20.

First, the lead frame 10 is manufactured by, for example, the methods shown in fig. 54 (a) - (e) and fig. 55 (a) - (h) (fig. 56 (a)).

Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, the semiconductor element 21 is mounted and fixed on the die pad 11 using an adhesive 24 such as a die attach paste, for example (fig. 56 (b)). The adhesive 24 may be an epoxy resin adhesive containing components such as silver paste and epoxy resin. At this time, the semiconductor element 21 is disposed on the 1 st roughened surface R1 of the chip carrier front surface 11a via the adhesive 24. The 1 st rough surface R1 is provided along the outer periphery of the semiconductor element 21 and the adhesive 24.

Next, each electrode 21a of the semiconductor element 21 and the metal layer 25 formed on each lead portion 12 are electrically connected to each other by a connection line (connection member) 22 (fig. 56 c).

Next, the sealing resin 23 is formed by injection molding or transfer molding a thermosetting resin or a thermoplastic resin to the lead frame 10 (fig. 56 (d)). Thereby, the die pad 11, the lead portion 12, the semiconductor element 21, and the connection wire 22 are resin-sealed.

Then, the lead frame 10 and the sealing resin 23 are cut for each package region 10 a. Thus, the lead frame 10 is separated for each semiconductor device 20, and the semiconductor device 20 shown in fig. 52 and 53 is obtained ((e) of fig. 56).

In addition, during the production of the semiconductor device 20 in this way, the step of heating and curing the adhesive 24 is performed ((b) of fig. 56). Specifically, after the adhesive 24 such as the die attach paste is applied to the die pad 11 and the semiconductor element 21 is mounted on the die pad 11, the adhesive 24 is cured by heating. At this time, there is a possibility that the components such as the epoxy resin in the applied adhesive 24 ooze out due to capillary phenomenon of the front surface 11a of the chip carrier. Such a phenomenon is also called bleeding or epoxy bleeding.

In contrast, according to the present embodiment, the 1 st roughened surface R1 is formed on the die pad front surface 11a of the die pad 11. The roughness of the 1 st rough surface R1 is suppressed as compared with the roughness of the 2 nd rough surface R2. This can suppress a phenomenon (bleeding) of the epoxy resin or the like in the adhesive 24 due to capillary phenomenon caused by the irregularities of the front surface 11a of the die pad (see arrow E in fig. 57). On the other hand, it is also conceivable to make the front surface 11a of the die pad around the adhesive 24 a smooth surface. However, if the viscosity of the epoxy resin in the adhesive 24 is low, the epoxy resin tends to flow along the chip carrier front surface 11a as a smooth surface instead. Therefore, in the present embodiment, the roughness of the front surface 11a of the chip carrier is moderately roughened to such an extent that no capillary phenomenon occurs (the 1 st roughened surface R1). Thus, the epoxy resin can be suppressed from flowing along the chip carrier front surface 11a regardless of the viscosity of the epoxy resin in the adhesive 24.

In addition, if such a semiconductor device 20 is used for a long period of time, moisture and the like in the air may intrude from the side surface side or the back surface side of the semiconductor device 20. For example, it is conceivable that: moisture or the like intrudes through the interface between the sealing resin 23 and the chip carrier 11 or the lead portion 12.

In contrast, according to the present embodiment, the 2 nd roughened surface R2 is formed on the lead front surface 12a of the lead portion 12. Therefore, the distance of the moisture penetration path at the interface of the lead front face 12a and the sealing resin 23 becomes longer. This can suppress intrusion of moisture from the interface between the lead front surface 12a and the sealing resin 23 toward the semiconductor element 21 (see arrow F in fig. 57) _A ). As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

In addition, according to the present embodiment, the chip-holder side surface 11h of the chip holder 11 becomes the 3 rd roughened surface R3. The roughness of the 3 rd rough surface R3 is larger than that of the 1 st rough surface R1. Therefore, the distance of the moisture penetration path at the interface between the sealing resin 23 and the die pad 11 becomes longer on the back surface side of the semiconductor device 20. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the die pad 11 toward the semiconductor element 21 (see arrow F in fig. 57) _B ). As a result, the reliability of the semiconductor device 20 after long-term use can be improved. Further, the adhesion strength between the die pad 11 and the sealing resin 23 can be improved, and the die pad 11 and the sealing resin 23 can be prevented from being peeled off from each other.

In addition, according to the present embodiment, the inner lead back surface 51b of the lead portion 12 becomes the 4 th roughened surface R4. Further, the inner lead distal end surface 51c of the lead portion 12 becomes the 5 th roughened surface R5. The roughness of the 4 th rough surface R4 and the roughness of the 5 th rough surface R5 are respectively larger than the roughness of the 1 st rough surface R1. Therefore, the distance of the moisture penetration path at the interface between the sealing resin 23 and the lead portion 12 becomes longer on the back surface side of the semiconductor device 20. This can suppress the intrusion of moisture from the interface between the sealing resin 23 and the lead portion 12 toward the semiconductor element 21 (see arrow F in fig. 57) _c ). As a result, the reliability of the semiconductor device 20 after long-term use can be improved. Further, the adhesion strength between the lead portion 12 and the sealing resin 23 can be improved, and the lead portion 12 can be suppressedAnd the sealing resin 23.

(modification)

Next, a modification of the lead frame 10 of the present embodiment will be described with reference to fig. 58. Fig. 58 is a cross-sectional view of the lead frame 10 according to the modification. In fig. 58, the same reference numerals are given to the same parts as those shown in fig. 50 to 57, and detailed description thereof is omitted.

In fig. 58, a smooth surface region S and a 2 nd rough surface R2 are formed on the lead front surface 12a of the lead portion 12. In this case, the metal layer 25 is not provided in the smooth surface region S. Therefore, the smooth surface region S is exposed to the outside of the lead frame 10.

In the case of manufacturing the lead frame 10 shown in fig. 58, after the steps shown in (a) to (e) of fig. 54 and (a) to (g) of fig. 55 described above are performed, the step of forming the metal layer 25 is not performed ((h) of fig. 55). Thus, the lead frame 10 shown in fig. 58 can be obtained.

In this way, the metal layer 25 is not provided in the smooth surface region S, and thus the manufacturing process of the lead frame 10 can be reduced. In addition, the manufacturing cost of the lead frame 10 can be reduced by not providing the metal layer 25 composed of a plating layer of silver, silver alloy, gold alloy, platinum group, copper alloy, palladium, or the like. Further, it is more effective in the case where the semiconductor element 21 is connected to the lead portion 12 not by wire bonding but by flip-chip bonding.

The plurality of components disclosed in the above embodiments and modifications may be appropriately combined as necessary. Alternatively, some of the components may be deleted from all of the components shown in the above embodiments and modifications.

Claims

1. A lead frame, wherein,

the lead frame is provided with a plurality of lead parts,

at least a part of the upper surface of the lead portion and the side wall surface of the lead portion are roughened surfaces,

a of the rough surface in CIELab color space ^* A value of 12-19, b of the roughened surface in the CIELab color space ^* The value is in the range of 12 to 17.

2. A lead frame, wherein,

the lead frame is provided with a plurality of lead parts,

the arithmetic average curvature Spc of the peak and the peak point of the rough surface is 700mm ^-1 The above.

3. The leadframe of claim 2, wherein the conductive material is selected from the group consisting of,

the arithmetic mean height Sa of the roughened surface is 0.12 μm or more.

4. The lead frame according to claim 1 or 2, wherein,

a part of the upper surface of the lead portion and a side wall surface of the lead portion are the roughened surfaces,

a metal plating layer is provided on a face other than the roughened face in the upper face of the lead portion.

5. The leadframe of claim 4 wherein,

the metal plating layer comprises at least one of an Ag plating layer, a Ni plating layer, a Pd plating layer and an Au plating layer.

6. The lead frame according to claim 1 or 2, wherein,

the lead portion includes an inner lead portion thinned from a lower surface side of the lead portion,

the lower surface of the inner lead portion is the roughened surface.

7. The lead frame according to claim 1 or 2, wherein,

the lead frame further includes a chip carrier for mounting the semiconductor element,

the plurality of lead portions are arranged around the chip carrier portion,

the upper surface of the chip carrier part and the side wall surface of the chip carrier part are the rough surfaces.

8. The lead frame according to claim 1 or 2, wherein,

the lead frame is used for manufacturing a semiconductor device, the semiconductor device is provided with a sealing part for sealing at least the plurality of lead parts,

the upper surface of the lead portion and the side wall surface of the lead portion in contact with the sealing portion are roughened surfaces.

9. A method for manufacturing a lead frame, wherein,

the manufacturing method of the lead frame comprises the following steps:

a metal substrate preparation step of preparing a metal substrate having a 1 st surface and a 2 nd surface facing the 1 st surface;

a metal substrate processing step of forming a plurality of lead portions by processing the metal substrate; and

A roughened surface forming step of roughening at least a part of the upper surface of the lead portion and the side wall surface of the lead portion to form a roughened surface,

in the rough surface forming step, a of the rough surface in a CIELab color space ^* B in the CIELab color space with a value in the range of 12 to 19 ^* The roughening is performed so that the value falls within the range of 12 to 17.

10. A method for manufacturing a lead frame, wherein,

the manufacturing method of the lead frame comprises the following steps:

in the rough surface forming step, the arithmetic average curvature Spc of the peak-to-peak point of the rough surface is 700mm ^-1 Roughening is performed in the above manner.

11. A lead frame, wherein,

the lead frame includes:

a chip holder for mounting the semiconductor element; and

a lead portion located around the die pad,

a region having a smooth surface is formed on the front surface of the die pad or the front surface of the lead portion,

A rough surface region is present so as to surround the entire circumference of the smooth surface region.

12. A method for manufacturing a lead frame, wherein,

the method for manufacturing the lead frame comprises the following steps:

preparing a metal substrate;

a step of forming a die pad and a lead portion located around the die pad by etching the metal substrate;

a step of forming a plating layer on a part of the metal substrate;

a step of forming a roughened surface on a portion of the metal substrate that is not covered with the plating layer; and

a step of removing the plating layer,

the rough surface region is present so as to surround the entire circumference of the smooth surface region.

13. A method for manufacturing a lead frame, wherein,

the method for manufacturing the lead frame comprises the following steps:

a step of preparing a metal substrate having a die pad and a lead portion located around the die pad;

forming a plating layer on the outer periphery of the metal substrate except at least a part of the front surface;

a step of leaving a plating layer present on at least the back surface of the metal substrate and removing the other plating layer;

and removing the plating layer.

14. A lead frame, wherein,

the lead frame includes:

a chip holder for mounting the semiconductor element; and

a lead portion located around the die pad,

the lead portion has an inner lead thinned from the back side,

an inner lead front surface is formed on the front surface side of the inner lead, an inner lead back surface is formed on the back surface side of the inner lead, an inner lead end surface is formed on the surface facing the chip carrier in the inner lead,

an external terminal is formed at a portion of the rear surface of the lead portion which is not thinned,

at least a part of the front surface of the inner lead, the back surface of the inner lead, and the end surface of the inner lead are roughened,

the external terminal becomes a smooth surface.

15. A lead frame, wherein,

the lead frame includes:

a chip holder for mounting the semiconductor element; and

a lead portion located around the die pad,

a part of the lead portion is thinned from the back side,

the thinned portion of the back surface of the lead portion is roughened, and the portion not thinned is smoothed.

16. A method for manufacturing a lead frame, wherein,

the method for manufacturing the lead frame comprises the following steps:

preparing a metal substrate;

a step of forming a die pad and a lead portion located around the die pad by etching the metal substrate, wherein a part of the lead portion is thinned from a back surface side;

forming a plating layer around the metal substrate;

a step of removing a part of the plating layer existing in the rough surface forming region;

a step of removing the plating layer,

17. A lead frame, wherein,

the lead frame includes:

a chip holder for mounting the semiconductor element; and

a lead portion located around the die pad,

a 1 st rough surface is formed on at least a portion of the front surface of the chip carrier,

a 2 nd rough surface is formed on at least a part of the front surface of the lead portion,

the roughness of the 2 nd rough surface of the lead portion is greater than the roughness of the 1 st rough surface of the die pad.

18. A method for manufacturing a lead frame, wherein,

the method for manufacturing the lead frame comprises the following steps:

preparing a metal substrate;

forming a cover layer on the chip holder and the lead portion;

a step of removing the cover layer existing on at least a part of the front surface of the chip carrier;

forming a 1 st rough surface on a portion of the die pad not covered with the cover layer;

a step of removing the cover layer existing on at least a part of the front surface of the lead portion; and

a step of forming a 2 nd rough surface on a portion of the lead portion not covered with the cover layer,