CN116940140A - Laminated battery, battery assembly and photovoltaic system - Google Patents

Laminated battery, battery assembly and photovoltaic system Download PDF

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Publication number
CN116940140A
CN116940140A CN202310918986.XA CN202310918986A CN116940140A CN 116940140 A CN116940140 A CN 116940140A CN 202310918986 A CN202310918986 A CN 202310918986A CN 116940140 A CN116940140 A CN 116940140A
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layer
transport layer
silicon
polar
doped
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林文杰
邱开富
王永谦
陈刚
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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Priority to CN202310918986.XA priority Critical patent/CN116940140A/en
Publication of CN116940140A publication Critical patent/CN116940140A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/10—Organic photovoltaic [PV] modules; Arrays of single organic PV cells
    • H10K39/15—Organic photovoltaic [PV] modules; Arrays of single organic PV cells comprising both organic PV cells and inorganic PV cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • H01L31/02008—Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier for solar cells or solar cell modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/40—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising a p-i-n structure, e.g. having a perovskite absorber between p-type and n-type charge transport layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/50—Photovoltaic [PV] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K30/00—Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation
    • H10K30/80—Constructional details
    • H10K30/84—Layers having high charge carrier mobility
    • H10K30/85—Layers having high electron mobility, e.g. electron-transporting layers or hole-blocking layers

Abstract

The application is suitable for the technical field of solar cells, and provides a laminated cell, a cell assembly and a photovoltaic system. The laminated battery comprises a perovskite sub-battery and a crystalline silicon sub-battery, the perovskite sub-battery comprises a first polar transmission layer, a perovskite layer and a second polar transmission layer which are sequentially laminated along the direction from the perovskite sub-battery to the crystalline silicon sub-battery, the crystalline silicon sub-battery comprises a third polar transmission layer, a crystalline silicon layer and a fourth polar transmission layer which are sequentially laminated, the polarities of the second polar transmission layer and the third polar transmission layer are different, and the second polar transmission layer is connected with the third polar transmission layer. Therefore, a buffer layer is not required to be deposited between the second polar transmission layer and the third polar transmission layer, the second polar transmission layer and the third polar transmission layer can be in direct contact to realize conduction, and the deposition process of the buffer layer can be reduced, so that the cost is reduced, the parasitic absorption of the buffer layer can be reduced, and the photoelectric conversion efficiency of the laminated battery is improved.

Description

Laminated battery, battery assembly and photovoltaic system
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a laminated cell, a cell assembly and a photovoltaic system.
Background
Solar cell power generation is a sustainable clean energy source that uses the photovoltaic effect of semiconductor p-n junctions to convert sunlight into electrical energy. The two solar cells may be stacked to form a stacked cell.
In the related art, when a perovskite battery and a crystalline silicon battery are stacked, a buffer layer is generally deposited between the perovskite battery and the crystalline silicon battery, and conductive contacts of the perovskite battery and the crystalline silicon battery are formed through the buffer layer. However, the buffer layer deposition process increases the cost, and the buffer layer brings about parasitic absorption, resulting in lower photoelectric conversion efficiency.
Based on this, how to design a laminated battery to reduce the cost and improve the photoelectric conversion efficiency has become a problem to be solved.
Disclosure of Invention
The application provides a laminated battery, a battery assembly and a photovoltaic system, which aim to solve the problem of how to design the laminated battery to reduce the cost and improve the photoelectric conversion efficiency.
The laminated battery comprises a perovskite sub-battery and a crystalline silicon sub-battery, wherein the perovskite sub-battery comprises a first polar transmission layer, a perovskite layer and a second polar transmission layer which are sequentially laminated along the direction from the perovskite sub-battery to the crystalline silicon sub-battery, the crystalline silicon sub-battery comprises a third polar transmission layer, a crystalline silicon layer and a fourth polar transmission layer which are sequentially laminated, the polarities of the second polar transmission layer and the third polar transmission layer are different, and the second polar transmission layer is connected with the third polar transmission layer.
Optionally, the first polar transport layer is a first hole transport layer, the second polar transport layer is a first electron transport layer, the third polar transport layer is a second hole transport layer, and the fourth polar transport layer is a second electron transport layer;
or, the first polar transport layer is a first electron transport layer, the second polar transport layer is a first hole transport layer, the third polar transport layer is a second electron transport layer, and the fourth polar transport layer is a second hole transport layer.
Optionally, the first hole transport layer includes PEDOT: at least one of PSS, nickel oxide, spiro-oMeTad, copper phthalocyanine, cuprous thiocyanate and PTAA.
Optionally, the first electron transport layer comprises at least one of C60, PCBM, titanium oxide, zinc stannate, and tin oxide.
Optionally, the second hole transport layer includes: at least one of doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, PEDOT, PSS, vanadium oxide, molybdenum oxide, nickel oxide, chromium oxide, tungsten oxide, cuprous iodide and copper sulfide.
Optionally, the second electron transport layer includes: at least one of doped crystalline silicon layer, doped amorphous silicon, doped polycrystalline silicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, magnesium oxide, titanium oxide, zinc oxide, titanium nitride, titanium oxynitride, lithium fluoride, magnesium fluoride, cesium iodide, magnesium, lithium, cesium, and ytterbium.
Optionally, the perovskite subcell includes a first interface passivation layer located between the first polarity transport layer and the perovskite layer;
and/or the perovskite subcell includes a second interface passivation layer located between the second polar transport layer and the perovskite layer.
Optionally, the crystalline silicon subcell includes a third interface passivation layer located between the third polar transport layer and the crystalline silicon layer;
and/or the crystalline silicon subcell comprises a fourth interface passivation layer located between the fourth polar transport layer and the crystalline silicon layer.
The battery assembly provided by the application comprises the laminated battery.
The photovoltaic system provided by the application comprises the battery assembly.
According to the laminated battery, the battery assembly and the photovoltaic system, the second polar transmission layer of the perovskite sub-battery is different in polarity and is connected with the third polar transmission layer of the crystalline silicon sub-battery, so that a buffer layer is not required to be deposited between the second polar transmission layer and the third polar transmission layer, and the second polar transmission layer and the third polar transmission layer can be in direct contact to realize conduction. Therefore, the deposition process of the buffer layer can be reduced, so that the cost is reduced, the parasitic absorption of the buffer layer can be reduced, the short-circuit current is improved, the contact resistance is reduced, the filling factor is improved, and the photoelectric conversion efficiency of the laminated battery is improved.
Drawings
Fig. 1 is a schematic view of a structure of a laminate battery according to an embodiment of the present application;
fig. 2 is a schematic view of the structure of a laminate battery according to an embodiment of the present application;
description of main reference numerals:
the laminated cell 100, the perovskite subcell 10, the first polarity transport layer 11, the first interface passivation layer 12, the perovskite layer 13, the second interface passivation layer 14, the second polarity transport layer 15, the crystalline silicon subcell 20, the third polarity transport layer 21, the third interface passivation layer 22, the crystalline silicon layer 23, the fourth interface passivation layer 24, and the fourth polarity transport layer 25.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. Furthermore, it should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the present application.
In the description of the present application, it should be understood that the terms "length," "width," "upper," "lower," "left," "right," "horizontal," "top," "bottom," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different structures of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize applications of other processes and/or usage scenarios for other materials.
In the application, the second polar transmission layer of the perovskite subcell is different in polarity and connected with the third polar transmission layer of the crystalline silicon subcell, so that a buffer layer is not required to be deposited between the second polar transmission layer and the third polar transmission layer, and the second polar transmission layer and the third polar transmission layer can be in direct contact to realize conduction. Therefore, the deposition process of the buffer layer can be reduced, so that the cost is reduced, the parasitic absorption of the buffer layer can be reduced, the short-circuit current is improved, the contact resistance is reduced, the filling factor is improved, and the photoelectric conversion efficiency of the laminated battery is improved.
Example 1
Referring to fig. 1, a laminated battery 100 according to an embodiment of the present application includes a perovskite subcell 10 and a crystalline silicon subcell 20, wherein the perovskite subcell 10 includes a first polar transmission layer 11, a perovskite layer 13 and a second polar transmission layer 15 sequentially laminated along a direction from the perovskite subcell 10 to the crystalline silicon subcell 20, the crystalline silicon subcell 20 includes a third polar transmission layer 21, a crystalline silicon layer 23 and a fourth polar transmission layer 25 sequentially laminated, the polarities of the second polar transmission layer 15 and the third polar transmission layer 21 are different, and the second polar transmission layer 15 is connected with the third polar transmission layer 21.
In the laminated battery 100 according to the embodiment of the application, since the second polar transport layer 15 of the perovskite subcell 10 and the third polar transport layer 21 of the crystalline silicon subcell 20 have different polarities and are connected, a buffer layer is not required to be deposited between the second polar transport layer 15 and the third polar transport layer 21, and the second polar transport layer 15 and the third polar transport layer 21 can be in direct contact to realize conduction. In this way, the deposition process of the buffer layer can be reduced, thereby reducing the cost, reducing the parasitic absorption of the buffer layer, improving the short-circuit current, reducing the contact resistance, improving the filling factor, and being beneficial to improving the photoelectric conversion efficiency of the laminated battery 100.
In this embodiment, the perovskite subcell 10 is a top cell and the crystalline silicon subcell 20 is a bottom cell. It will be appreciated that in other embodiments, the crystalline silicon subcell 20 may be a top cell and the perovskite subcell 10 a bottom cell.
In particular, the perovskite subcell 10 may include a first electrode located on a side of the first polarity transport layer 11 facing away from the perovskite layer 13.
Further, the first electrode comprises a metal electrode and/or a transparent conductive oxide (Transparent Conductive Oxide, TCO). For example, the first electrode comprises a metal electrode, excluding TCO; as another example, the first electrode does not include a metal electrode, including TCO; for another example, the first electrode includes a metal electrode and a TCO.
It can be appreciated that the metal electrode has better conductivity, stronger corrosion resistance, and lower manufacturing cost, and the use of the metal electrode as the first electrode is advantageous in reducing the manufacturing cost of the laminated battery 100, and improving the reliability and photoelectric conversion efficiency of the laminated battery 100.
Further, the metal electrode may cover the entire area of the first polarity transfer layer 11, i.e., the metal electrode may be an entire metal electrode; the metal electrode may also cover a partial region of the first polarity transfer layer 11, for example, the metal electrode is a gate line.
Still further, the metal electrode may be made of at least one of silver, gold, aluminum, copper, nickel, chromium.
It can be appreciated that the TCO can effectively collect the current of the laminate battery 100, ensuring the normal operation of the laminate battery 100. Furthermore, TCOs are highly transmissive and can be antireflection, allowing for reduced solar losses. Thus, the photoelectric conversion efficiency is advantageously improved.
Still further, the TCO includes at least one of fluorine doped Tin Oxide (Fluorine doped Tin Oxide, FTO), tungsten doped Indium Oxide (In 2O3: W, IWO), cadmium doped Indium Oxide (ICO), indium Oxide (In 2O 3), indium zinc Oxide (Indium Zinc Oxide, IZO), indium Tin Oxide (ITO), aluminum doped zinc Oxide (Aluminum doped Zinc Oxide, AZO), aluminum doped Tin Oxide (Aluminum doped Tin Oxide, ATO), indium doped Tin Oxide (Indium doped Gallium Oxide, IGO).
Further, the TCO may cover the entire area of the first polarity transmission layer 11, or may cover a part of the area of the first polarity transmission layer 11.
Specifically, the polarities of the first and second polar transport layers 11 and 15 are opposite. In other words, in the case where the first polar transport layer 11 is the first hole transport layer, the second polar transport layer 15 is the first electron transport layer; in the case where the first polar transport layer 11 is a first electron transport layer, the second polar transport layer 15 is a first hole transport layer.
Specifically, the thickness of the first polar transport layer 11 is 10nm to 40nm. For example, 10nm, 15nm, 20nm, 30nm, 40nm. In this way, the thickness of the first polarity transfer layer 11 is made to be in a proper range, ensuring the effect of transferring one carrier and blocking the other carrier.
Specifically, the thickness of the second polar transport layer 15 is 10nm to 40nm. For example, 10nm, 15nm, 20nm, 30nm, 40nm. In this way, the thickness of the second polar transport layer 15 is made to be in a proper range, ensuring the effect of transporting one carrier and blocking the other carrier.
Specifically, the crystal structure of the material of the perovskite layer 13 is ABX 3 Type A is Cs + 、CH(NH 2 ) 2 + 、CH 3 NH 3 + 、C(NH 2 ) 3 + At least one of B is Pb 2+ 、Sn 2+ At least one of the X is Br - 、I - 、Cl - At least one of them. Thus, the perovskite layer 13 has better light absorption effect, and is beneficial to improving the photoelectric conversion efficiency.
Specifically, the perovskite layer 13 has a thickness of 300nm to 600nm. For example 300nm, 400nm, 500nm, 600nm. Therefore, the thickness of the perovskite layer 13 is in a proper range, so that the light absorption effect is good, and the photoelectric conversion efficiency is improved.
Specifically, the polarity of the third polar transport layer 21 and the fourth polar transport layer 25 are opposite. In other words, in the case where the third polar transport layer 21 is the third hole transport layer, the fourth polar transport layer 25 is the third electron transport layer; in the case where the third polar transport layer 21 is a third electron transport layer, the fourth polar transport layer 25 is a third hole transport layer.
Specifically, the thickness of the third polar transport layer 21 is 0.5nm to 2000nm. For example, 0.5nm, 1nm, 1.5nm, 10nm, 20nm, 100nm, 500nm, 1800nm, 2000nm. In this way, the thickness of the third polar transport layer 21 is made to be in a proper range, ensuring the effect of transporting one carrier and blocking the other carrier. In this way, parasitic absorption may be reduced while ensuring that one carrier is transported and the other carrier is blocked.
Preferably, the thickness of the third polar transport layer 21 is 0.5nm to 20nm. For example, 0.5nm, 1nm, 1.5nm, 8nm, 10nm, 15nm, 20nm. Thus, the effect of reducing parasitic absorption is better.
Specifically, the fourth polar transport layer 25 has a thickness of 0.5nm to 2000nm. For example, 0.5nm, 1nm, 1.5nm, 10nm, 20nm, 100nm, 500nm, 1800nm, 2000nm. In this way, the thickness of the fourth polar transport layer 25 is made to be in a proper range, ensuring the effect of transporting one carrier and blocking the other carrier. In this way, parasitic absorption may be reduced while ensuring that one carrier is transported and the other carrier is blocked.
Preferably, the fourth polar transport layer 25 has a thickness of 0.5nm to 20nm. For example, 0.5nm, 1nm, 1.5nm, 8nm, 10nm, 15nm, 20nm. Thus, the effect of reducing parasitic absorption is better.
Specifically, the crystalline silicon layer 23 may be a P-type silicon substrate, an N-type silicon substrate, a single crystal substrate, or a polycrystalline silicon substrate.
In particular, the crystalline silicon subcell 20 may include a second electrode located on a side of the fourth polar transport layer 25 facing away from the crystalline silicon layer 23.
Further, the second electrode comprises a metal electrode and/or a transparent conductive oxide (Transparent Conductive Oxide, TCO). For example, the second electrode comprises a metal electrode, excluding TCO; as another example, the second electrode does not include a metal electrode, including TCO; for another example, the second electrode includes a metal electrode and a TCO.
The explanation and explanation of the second electrode may refer to the explanation and explanation of the first electrode in the foregoing, and will not be repeated here to avoid redundancy.
It is noted that in the case where the first electrode and the second electrode are both metal electrodes, at least one of the first electrode and the second electrode is a gate line electrode. In this way, the first electrode and the second electrode are prevented from being covered with the polarity transmission layer over the entire surface, so that light cannot be incident to the battery.
Example two
In some alternative embodiments, the first polar transport layer 11 is a first hole transport layer, the second polar transport layer 15 is a first electron transport layer, the third polar transport layer 21 is a second hole transport layer, and the fourth polar transport layer 25 is a second electron transport layer.
In this way, along the direction from the perovskite subcell 10 to the crystalline silicon subcell 20, the four polarity transport layers are respectively a hole transport layer, an electron transport layer, a hole transport layer, and an electron transport layer, so that the polarities of the second polarity transport layer 15 and the third polarity transport layer 21 are different, serial connection and electrical conduction of the perovskite subcell 10 and the crystalline silicon subcell 20 can be realized, and normal operation of the laminated cell 100 is ensured.
In some alternative embodiments, the first polar transport layer 11 is a first electron transport layer, the second polar transport layer 15 is a first hole transport layer, the third polar transport layer 21 is a second electron transport layer, and the fourth polar transport layer 25 is a second hole transport layer.
In this way, along the direction from the perovskite subcell 10 to the crystalline silicon subcell 20, the four polarity transfer layers are respectively an electron transfer layer, a hole transfer layer, an electron transfer layer, and a hole transfer layer, so that the polarities of the second polarity transfer layer 15 and the third polarity transfer layer 21 are different, and the serial connection and electrical conduction of the perovskite subcell 10 and the crystalline silicon subcell 20 can be realized, thereby ensuring the normal operation of the laminated cell 100.
Example III
In some alternative embodiments, the first hole transport layer comprises PEDOT: at least one of PSS, nickel oxide (NiOx), spira-oMeTad, copper phthalocyanine (CuPc), copper thiocyanate (CuSCN), and PTAA. In other words, the first hole transport layer comprises PEDOT: one or more of PSS, nickel oxide (NiOx), spira-oMeTad, copper phthalocyanine (CuPc), copper thiocyanate (CuSCN), and PTAA.
For example, the first hole transport layer includes PEDOT: PSS, nickel oxide (NiOx), spiro-oMeTad, copper phthalocyanine (CuPc), copper thiocyanate (CuSCN), and PTAA; as another example, the first hole transport layer includes PEDOT: PSS; for another example, the first hole transport layer includes nickel oxide (NiOx) and PTAA. The specific form of the first hole transport layer is not limited herein.
Thus, holes excited by sunlight can be timely transmitted through the first hole transport layer, and the influence of hole accumulation on the service life of the laminated battery 100 is avoided. In addition, the hole transport layer can also block electrons, so that the recombination of holes and electrons is reduced, and the photoelectric conversion efficiency is improved. Furthermore, the first hole transport layer in various forms is provided, so that the method can adapt to more actual production scenes.
Example IV
In some alternative embodiments, the first electron transport layer comprises C60, PCBM, titanium oxide (TiO 2 ) Zinc oxide (ZnO), zinc stannate (ZnSnO) 4 ) And tin oxide (SnO) 2 ) At least one of them. In other words, the first electron transport layer comprises C60, PCBM, titanium oxide (TiO 2 ) Zinc oxide (ZnO), zinc stannate (ZnSnO) 4 ) And tin oxide (SnO) 2 ) One or more of the following.
For example, the first electron transport layer comprises C60, PCBM, titanium oxide (TiO 2 ) Zinc oxide (ZnO), zinc stannate (ZnSnO) 4 ) And tin oxide (SnO) 2 ) The method comprises the steps of carrying out a first treatment on the surface of the As another example, the first electron transport layer includes C60; for another example, the first electron transport layer includes zinc oxide (ZnO), zinc stannate (ZnSnO 4 ) And tin oxide (SnO) 2 ). The specific form of the first electron transport layer is not limited herein.
Thus, electrons excited by sunlight can be timely transmitted through the first electron transport layer, and the influence of electron accumulation on the service life of the laminated battery 100 is avoided. In addition, the electron transport layer can also block holes, so that the recombination of electrons and holes is reduced, and the photoelectric conversion efficiency is improved. Furthermore, the first electron transport layer in various forms is provided, so that the method can adapt to more actual production scenes.
Example five
In some alternative embodiments, the second hole transport layer comprises: at least one of doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, PEDOT, PSS, vanadium oxide, molybdenum oxide, nickel oxide, chromium oxide, tungsten oxide, cuprous iodide and copper sulfide.
In other words, the second hole transport layer includes: one or more of doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, PEDOT, PSS, vanadium oxide, molybdenum oxide, nickel oxide, chromium oxide, tungsten oxide, cuprous iodide and copper sulfide.
For example, the second hole transport layer includes a doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, PEDOT: PSS, vanadium oxide, molybdenum oxide, nickel oxide, chromium oxide, tungsten oxide, cuprous iodide, and copper sulfide; as another example, the second hole transport layer comprises a doped crystalline silicon layer; for another example, the second hole transport layer includes tungsten oxide, cuprous iodide, and cupric sulfide. The specific form of the second hole transport layer is not limited herein.
Thus, holes excited by sunlight can be timely transmitted through the second hole transport layer, and the influence of hole accumulation on the service life of the laminated battery 100 is avoided. In addition, the hole transport layer can also block electrons, so that the recombination of holes and electrons is reduced, and the photoelectric conversion efficiency is improved. Moreover, the second hole transport layer in various forms is provided, so that the method can adapt to more actual production scenes.
It is understood that the second hole transport layer may comprise a silicon material and/or a non-silicon material. For example, the second hole transport layer includes a silicon material and a non-silicon material; as another example, the second hole transport layer includes a silicon material and does not include a non-silicon material; for another example, the second hole transport layer includes a non-silicon material and does not include a silicon material. The silicon material is, for example, a doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride. Non-silicon materials are for example PEDOT PSS, vanadium oxide, molybdenum oxide, nickel oxide, chromium oxide, tungsten oxide, cuprous iodide and copper sulphide.
Preferably, the second hole transport layer comprises a non-silicon material. Therefore, the second hole transport layer is manufactured without using flammable and explosive reaction gas, so that the preparation safety is higher. In addition, the non-silicon material is prepared as the second hole transport layer, so that the instrument is cheaper, and the production cost is reduced. Meanwhile, parasitic absorption can be reduced, and photoelectric conversion efficiency is improved.
Example six
In some alternative embodiments, the second electron transport layer comprises: at least one of doped crystalline silicon layer, doped amorphous silicon, doped polycrystalline silicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, magnesium oxide (MgO), titanium oxide (TiO 2), zinc oxide (ZnO), titanium nitride (TiN), titanium oxynitride (lino), lithium fluoride (LiFx), magnesium fluoride (MgFx), cesium fluoride (CsF), cesium iodide (CsI), magnesium (Mg), lithium (Li), cesium (Sc), and ytterbium (Yb).
In other words, the second electron transport layer includes: doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, magnesium oxide (MgO), titanium oxide (TiO 2), zinc oxide (ZnO), titanium nitride (TiN), titanium oxynitride (lino), lithium fluoride (LiFx), magnesium fluoride (MgFx), cesium fluoride (CsF), cesium iodide (CsI), magnesium (Mg), lithium (Li), cesium (Sc), and ytterbium (Yb).
For example, the second electron transport layer includes: doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, magnesium oxide (MgO), titanium oxide (TiO 2), zinc oxide (ZnO), titanium nitride (TiN), titanium oxynitride (lino), lithium fluoride (LiFx), magnesium fluoride (MgFx), cesium fluoride (CsF), cesium iodide (CsI), magnesium (Mg), lithium (Li), cesium (Sc), and ytterbium (Yb); as another example, the second electron transport layer includes: doping the crystalline silicon layer; for another example, the second electron transport layer includes magnesium oxide (MgO), cesium (Sc), and ytterbium (Yb). The specific form of the second electron transport layer is not limited herein.
Thus, electrons excited by sunlight can be timely transmitted through the second electron transport layer, and the influence of electron accumulation on the life of the laminated battery 100 is avoided. In addition, the electron transport layer can also block holes, so that the recombination of electrons and holes is reduced, and the photoelectric conversion efficiency is improved. Moreover, the second electron transport layer in various forms is provided, so that the method can adapt to more actual production scenes.
It is understood that the second electron transport layer may comprise a silicon material and/or a non-silicon material. For example, the second electron transport layer includes a silicon material and a non-silicon material; as another example, the second electron transport layer comprises a silicon material and does not comprise a non-silicon material; for another example, the second electron transport layer includes a non-silicon material and does not include a silicon material. The silicon material is, for example, a doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride. Examples of the non-silicon material are magnesium oxide (MgO), titanium oxide (TiO 2), zinc oxide (ZnO), titanium nitride (TiN), titanium oxynitride (lino), lithium fluoride (LiFx), magnesium fluoride (MgFx), cesium fluoride (CsF), cesium iodide (CsI), magnesium (Mg), lithium (Li), cesium (Sc), and ytterbium (Yb).
Preferably, the second electron transport layer comprises a non-silicon material. Therefore, the second electron transport layer is manufactured without using flammable and explosive reaction gas, so that the preparation safety is higher. In addition, the non-silicon material is prepared as the second electron transport layer, so that the instrument is cheaper, and the production cost is reduced. Meanwhile, parasitic absorption can be reduced, and photoelectric conversion efficiency is improved.
Example seven
Referring to fig. 2, in some alternative embodiments, the perovskite subcell 10 includes a first interface passivation layer 12, the first interface passivation layer 12 being located between the first polarity transport layer 11 and the perovskite layer 13. And/or the perovskite subcell 10 includes a second interface passivation layer 14, the second interface passivation layer 14 being located between the second polar transport layer 15 and the perovskite layer 13.
Thus, the interface passivation between the polar transport layer and the perovskite layer 13 is realized through the interface passivation layer, so that recombination can be reduced, and the photoelectric conversion efficiency can be improved.
Specifically, in the example of fig. 2, the perovskite subcell 10 includes a first interface passivation layer 12 and a second interface passivation layer 14. It will be appreciated that in other embodiments, the perovskite subcell 10 may include the first interface passivation layer 12 without the second interface passivation layer 14; alternatively, the perovskite subcell 10 may include the second interface passivation layer 14 without the first interface passivation layer 12.
Specifically, one of the first interface passivation layer 12 and the second interface passivation layer 14 is an electronic interface passivation layer, and the other is a hole interface passivation layer.
Further, the electronic interface passivation layer comprises at least one of a polyurea layer, an amino molecule compound, an alkali metal halide, and an alkaline earth metal halide. Thus, various forms of the electronic interface passivation layer are provided, and the electronic interface passivation layer can adapt to more actual production scenes.
Further, the hole interface passivation layer comprises at least one of potassium benzoate, nickel oxide and PMMA. Thus, various forms of the hole interface passivation layer are provided, and the method can adapt to more actual production scenes.
Specifically, the thickness of the first interface passivation layer 12 is 0.2nm to 30nm. For example, 0.2nm, 1nm, 5nm, 8nm, 10nm, 20nm, 30nm. In this way, the thickness of the first interface passivation layer 12 is in a suitable range, so that poor passivation effect caused by too small thickness can be avoided, and too high resistivity caused by too large thickness can also be avoided.
Preferably, the thickness of the first interface passivation layer 12 is 0.2nm-15nm. For example, 0.2nm, 0.5nm, 0.8nm, 1nm, 8nm, 10nm, 15nm. Therefore, the passivation effect and the resistivity are considered, and the overall effect is better.
Specifically, the thickness of the second interface passivation layer 14 is 0.2nm to 30nm. For example, 0.2nm, 1nm, 5nm, 8nm, 10nm, 20nm, 30nm. In this way, the thickness of the second interface passivation layer 14 is in a suitable range, so that poor passivation effect caused by too small thickness can be avoided, and too high resistivity caused by too large thickness can also be avoided.
Preferably, the thickness of the second interface passivation layer 14 is 0.2nm-15nm. For example, 0.2nm, 0.5nm, 0.8nm, 1nm, 8nm, 10nm, 15nm. Therefore, the passivation effect and the resistivity are considered, and the overall effect is better.
Example eight
In some alternative embodiments, the crystalline silicon subcell 20 includes a third interface passivation layer 22, the third interface passivation layer 22 being located between the third polar transport layer 21 and the crystalline silicon layer 23; and/or the crystalline silicon subcell 20 includes a fourth interface passivation layer 24, the fourth interface passivation layer 24 being located between the fourth polar transport layer 25 and the crystalline silicon layer 23.
Thus, the interface passivation between the polar transport layer and the crystalline silicon layer 23 is realized by the interface passivation layer, so that the recombination can be reduced, and the photoelectric conversion efficiency can be improved.
Specifically, in the example of fig. 2, the perovskite subcell 10 includes a third interface passivation layer 22 and a fourth interface passivation layer 24. It will be appreciated that in other embodiments, the perovskite subcell 10 may include a third interface passivation layer 22, excluding a fourth interface passivation layer 24; alternatively, the perovskite subcell 10 may include a fourth interface passivation layer 24, excluding the third interface passivation layer 22.
Specifically, one of the third interface passivation layer 22 and the fourth interface passivation layer 24 is an electronic interface passivation layer, and the other is a hole interface passivation layer.
Specifically, the third interface passivation layer 22 includes one or more of silicon oxide, aluminum oxide, silicon nitride, intrinsic amorphous silicon, silicon oxynitride, silicon carbide. In this manner, multiple forms of the third interface passivation layer 22 are provided that can accommodate more practical production scenarios.
Specifically, the thickness of the third interface passivation layer 22 is 0.5nm to 15nm. For example, 0.5nm, 1nm, 5nm, 10nm, 13nm, 15nm. In this way, the thickness of the third interface passivation layer 22 is in a suitable range, so that poor passivation effect caused by too small thickness can be avoided, and too high resistivity caused by too large thickness can also be avoided.
Further, the third interface passivation layer 22 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the thickness of the third interface passivation layer 22 is 0.5nm to 2nm.
Further, the third interface passivation layer 22 comprises intrinsic amorphous silicon and has a thickness of 1nm to 15nm. For example, 1nm, 3nm, 10nm, 12nm, 15nm. Preferably, the intrinsic amorphous silicon has a thickness of 2nm to 8nm.
Specifically, the fourth interface passivation layer 24 comprises one or more of silicon oxide, aluminum oxide, silicon nitride, intrinsic amorphous silicon, silicon oxynitride, silicon carbide. In this manner, multiple forms of the fourth interface passivation layer 24 are provided that can accommodate more practical production scenarios.
Specifically, the thickness of the fourth interface passivation layer 24 is 0.5nm to 15nm. For example, 0.5nm, 1nm, 5nm, 10nm, 13nm, 15nm. In this way, the thickness of the fourth interface passivation layer 24 is in a suitable range, so that poor passivation effect caused by too small thickness can be avoided, and too high resistivity caused by too large thickness can be avoided.
Further, the fourth interface passivation layer 24 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, and the thickness of the fourth interface passivation layer 24 is 0.5nm to 2nm.
Further, the fourth interface passivation layer 24 comprises intrinsic amorphous silicon and has a thickness of 1nm to 15nm. For example, 1nm, 3nm, 10nm, 12nm, 15nm. Preferably, the intrinsic amorphous silicon has a thickness of 2nm to 8nm.
Example nine
The battery assembly of the embodiment of the application includes the laminated battery 100 of any one of embodiments one to eight.
In the battery assembly according to the embodiment of the application, since the second polar transport layer 15 of the perovskite subcell 10 and the third polar transport layer 21 of the crystalline silicon subcell 20 in the stacked battery 100 have different polarities and are connected, there is no need to deposit a buffer layer between the second polar transport layer 15 and the third polar transport layer 21, and the second polar transport layer 15 and the third polar transport layer 21 can be in direct contact to achieve electrical conduction. In this way, the deposition process of the buffer layer can be reduced, thereby reducing the cost, reducing the parasitic absorption of the buffer layer, improving the short-circuit current, reducing the contact resistance, improving the filling factor, and being beneficial to improving the photoelectric conversion efficiency of the laminated battery 100.
In this embodiment, a plurality of stacked batteries in the battery assembly may be sequentially connected in series to form a battery string, so as to realize serial bus output of current, for example, serial connection of battery pieces may be realized by providing a welding strip (bus bar, interconnection bar), a conductive back plate, and the like.
It will be appreciated that in such embodiments, the battery assembly may also include a metal frame, a back sheet, photovoltaic glass, and a glue film. The adhesive film can be filled between the front and back surfaces of the laminated battery and the photovoltaic glass, adjacent battery pieces and the like, and can be a transparent colloid with good light transmission performance and ageing resistance, for example, the adhesive film can be an EVA adhesive film or a POE adhesive film, and the adhesive film can be specifically selected according to actual conditions and is not limited.
The photovoltaic glass may be an ultra-white glass, which has high light transmittance, high transparency, and excellent physical, mechanical, and optical properties, for example, the ultra-white glass may have a light transmittance of 92% or more, which may protect the laminated battery without affecting the efficiency of the laminated battery as much as possible, and may be coated on the adhesive film on the front surface of the laminated battery. Meanwhile, the adhesive film can bond the photovoltaic glass and the laminated battery together, and the laminated battery can be sealed and insulated and waterproof and moistureproof by the adhesive film.
The back plate can be attached to the adhesive film on the back of the laminated battery, can protect and support the laminated battery, has reliable insulativity, water resistance and aging resistance, can be selected multiple times, can be toughened glass, organic glass, an aluminum alloy TPT composite adhesive film and the like, and can be specifically set according to specific conditions without limitation. The whole of backplate, laminate battery, glued membrane and photovoltaic glass constitution can set up on metal frame, and metal frame is as the main external support structure of whole battery module, and can carry out stable support and installation for the battery module, for example, can install the battery module in the position that needs the installation through metal frame.
Examples ten
The photovoltaic system of the embodiment of the application comprises the battery assembly of the ninth embodiment.
In the photovoltaic system according to the embodiment of the present application, since the second polar transport layer 15 of the perovskite subcell 10 and the third polar transport layer 21 of the crystalline silicon subcell 20 in the stacked cell 100 have different polarities and are connected, there is no need to deposit a buffer layer between the second polar transport layer 15 and the third polar transport layer 21, and the second polar transport layer 15 and the third polar transport layer 21 can be in direct contact to achieve electrical conduction. In this way, the deposition process of the buffer layer can be reduced, thereby reducing the cost, reducing the parasitic absorption of the buffer layer, improving the short-circuit current, reducing the contact resistance, improving the filling factor, and being beneficial to improving the photoelectric conversion efficiency of the laminated battery 100.
In this embodiment, the photovoltaic system may be applied to a photovoltaic power station, such as a ground power station, a roof power station, a water power station, or the like, and may also be applied to a device or apparatus that uses solar energy to generate power, such as a user solar power source, a solar street lamp, a solar car, a solar building, or the like. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system may be applied to all fields where solar energy is required to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system can comprise a photovoltaic array, a junction box and an inverter, wherein the photovoltaic array can be an array combination of a plurality of battery assemblies, for example, the plurality of battery assemblies can form a plurality of photovoltaic arrays, the photovoltaic array is connected with the junction box, the junction box can conduct junction on current generated by the photovoltaic array, and the junction box is connected with a commercial power network after the junction current flows through the inverter and is converted into alternating current required by the commercial power network so as to realize solar power supply.
In the description of the present specification, reference to the terms "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiments or examples is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the foregoing description of the preferred embodiment of the application is provided for the purpose of illustration only, and is not intended to limit the application to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application.

Claims (10)

1. The utility model provides a laminate battery, its characterized in that includes perovskite subcell and brilliant silicon subcell, along from perovskite subcell to the orientation of brilliant silicon subcell, perovskite subcell includes first polarity transmission layer, perovskite layer and the second polarity transmission layer of layering in proper order, brilliant silicon subcell includes the third polarity transmission layer, brilliant silicon layer and the fourth polarity transmission layer of layering in proper order, the second polarity transmission layer is different with the polarity of third polarity transmission layer, the second polarity transmission layer meets with third polarity transmission layer.
2. The laminate cell of claim 1, wherein the first polar transport layer is a first hole transport layer, the second polar transport layer is a first electron transport layer, the third polar transport layer is a second hole transport layer, and the fourth polar transport layer is a second electron transport layer;
or, the first polar transport layer is a first electron transport layer, the second polar transport layer is a first hole transport layer, the third polar transport layer is a second electron transport layer, and the fourth polar transport layer is a second hole transport layer.
3. The laminate cell of claim 2, wherein the first hole transport layer comprises PEDOT: at least one of PSS, nickel oxide, spiro-oMeTad, copper phthalocyanine, cuprous thiocyanate and PTAA.
4. The laminate cell of claim 2, wherein the first electron transport layer comprises at least one of C60, PCBM, titanium oxide, zinc stannate, and tin oxide.
5. The laminate cell of claim 2, wherein the second hole transport layer comprises: at least one of doped crystalline silicon layer, doped amorphous silicon, doped polysilicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, PEDOT, PSS, vanadium oxide, molybdenum oxide, nickel oxide, chromium oxide, tungsten oxide, cuprous iodide and copper sulfide.
6. The laminate cell of claim 2, wherein the second electron transport layer comprises: at least one of doped crystalline silicon layer, doped amorphous silicon, doped polycrystalline silicon, doped nanocrystalline silicon, doped silicon oxide, doped silicon carbide, doped silicon oxynitride, magnesium oxide, titanium oxide, zinc oxide, titanium nitride, titanium oxynitride, lithium fluoride, magnesium fluoride, cesium iodide, magnesium, lithium, cesium, and ytterbium.
7. The laminate cell of claim 1, wherein the perovskite subcell comprises a first interface passivation layer between the first polarity transport layer and the perovskite layer;
and/or the perovskite subcell includes a second interface passivation layer located between the second polar transport layer and the perovskite layer.
8. The laminate cell of claim 1, wherein the crystalline silicon subcell comprises a third interface passivation layer between the third polar transport layer and the crystalline silicon layer;
and/or the crystalline silicon subcell comprises a fourth interface passivation layer located between the fourth polar transport layer and the crystalline silicon layer.
9. A battery assembly comprising the laminated battery according to any one of claims 1 to 8.
10. A photovoltaic system comprising the cell assembly of claim 9.
CN202310918986.XA 2023-07-25 2023-07-25 Laminated battery, battery assembly and photovoltaic system Pending CN116940140A (en)

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